diff --git a/crates/cuda-device/src/generated/async_copy.rs b/crates/cuda-device/src/generated/async_copy.rs index 0d21301b61..fad1c972a3 100644 --- a/crates/cuda-device/src/generated/async_copy.rs +++ b/crates/cuda-device/src/generated/async_copy.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. // Included inside `cuda_device::async_copy` to keep existing paths stable. diff --git a/crates/cuda-device/src/generated/atomic.rs b/crates/cuda-device/src/generated/atomic.rs index 656a692bea..9d04143421 100644 --- a/crates/cuda-device/src/generated/atomic.rs +++ b/crates/cuda-device/src/generated/atomic.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. // Included inside `cuda_device::atomic` to keep existing paths stable. diff --git a/crates/cuda-device/src/generated/bf16.rs b/crates/cuda-device/src/generated/bf16.rs index 3afd619bb1..92ea51c470 100644 --- a/crates/cuda-device/src/generated/bf16.rs +++ b/crates/cuda-device/src/generated/bf16.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. // Included inside `cuda_device::bf16` to keep existing paths stable. diff --git a/crates/cuda-device/src/generated/bf16x2.rs b/crates/cuda-device/src/generated/bf16x2.rs index 5936c15cd9..fce51457fe 100644 --- a/crates/cuda-device/src/generated/bf16x2.rs +++ b/crates/cuda-device/src/generated/bf16x2.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. // Included inside `cuda_device::bf16x2` to keep existing paths stable. diff --git a/crates/cuda-device/src/generated/clc.rs b/crates/cuda-device/src/generated/clc.rs index 4b105d0639..456af9f612 100644 --- a/crates/cuda-device/src/generated/clc.rs +++ b/crates/cuda-device/src/generated/clc.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. // Included inside `cuda_device::clc` to keep its public API stable. diff --git a/crates/cuda-device/src/generated/cluster_barrier.rs b/crates/cuda-device/src/generated/cluster_barrier.rs index 01afe78999..6aad479db0 100644 --- a/crates/cuda-device/src/generated/cluster_barrier.rs +++ b/crates/cuda-device/src/generated/cluster_barrier.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. // Included inside `cuda_device::cluster` to keep public paths stable. diff --git a/crates/cuda-device/src/generated/cluster_memory.rs b/crates/cuda-device/src/generated/cluster_memory.rs index 469387222f..a23d3a3e00 100644 --- a/crates/cuda-device/src/generated/cluster_memory.rs +++ b/crates/cuda-device/src/generated/cluster_memory.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. // Included inside `cuda_device::cluster` to keep its public API stable. diff --git a/crates/cuda-device/src/generated/cluster_sreg.rs b/crates/cuda-device/src/generated/cluster_sreg.rs index ca853965ee..13a4529580 100644 --- a/crates/cuda-device/src/generated/cluster_sreg.rs +++ b/crates/cuda-device/src/generated/cluster_sreg.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. // This file is included inside `cuda_device::cluster`. diff --git a/crates/cuda-device/src/generated/convert.rs b/crates/cuda-device/src/generated/convert.rs index dffe770429..86aad7a0cf 100644 --- a/crates/cuda-device/src/generated/convert.rs +++ b/crates/cuda-device/src/generated/convert.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. // Included inside `cuda_device::convert`. diff --git a/crates/cuda-device/src/generated/counted_barrier.rs b/crates/cuda-device/src/generated/counted_barrier.rs index b1879d1b82..708a6dde6a 100644 --- a/crates/cuda-device/src/generated/counted_barrier.rs +++ b/crates/cuda-device/src/generated/counted_barrier.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. // Included inside `cuda_device::barrier` to keep its public API stable. diff --git a/crates/cuda-device/src/generated/debug_control.rs b/crates/cuda-device/src/generated/debug_control.rs index 906cf59a7a..58abb175a5 100644 --- a/crates/cuda-device/src/generated/debug_control.rs +++ b/crates/cuda-device/src/generated/debug_control.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. // Included inside `cuda_device::debug` to keep its public API stable. diff --git a/crates/cuda-device/src/generated/debug_sreg.rs b/crates/cuda-device/src/generated/debug_sreg.rs index 720b544db0..88bdb5210b 100644 --- a/crates/cuda-device/src/generated/debug_sreg.rs +++ b/crates/cuda-device/src/generated/debug_sreg.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. // Included inside `cuda_device::debug` to keep existing paths stable. diff --git a/crates/cuda-device/src/generated/dotprod.rs b/crates/cuda-device/src/generated/dotprod.rs index 7bd3249016..82b3d92af7 100644 --- a/crates/cuda-device/src/generated/dotprod.rs +++ b/crates/cuda-device/src/generated/dotprod.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. // Included inside `cuda_device::dotprod` to keep existing paths stable. diff --git a/crates/cuda-device/src/generated/f16.rs b/crates/cuda-device/src/generated/f16.rs index ba06a63dcc..3ad4bcce17 100644 --- a/crates/cuda-device/src/generated/f16.rs +++ b/crates/cuda-device/src/generated/f16.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. // Included inside `cuda_device::f16` to keep existing paths stable. diff --git a/crates/cuda-device/src/generated/f16x2.rs b/crates/cuda-device/src/generated/f16x2.rs index be2a7502f2..45f449330f 100644 --- a/crates/cuda-device/src/generated/f16x2.rs +++ b/crates/cuda-device/src/generated/f16x2.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. // Included inside `cuda_device::f16x2` to keep existing paths stable. diff --git a/crates/cuda-device/src/generated/f32x2.rs b/crates/cuda-device/src/generated/f32x2.rs index f2e1473057..72abfcfcea 100644 --- a/crates/cuda-device/src/generated/f32x2.rs +++ b/crates/cuda-device/src/generated/f32x2.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. // Included inside `cuda_device::f32x2` to keep existing paths stable. diff --git a/crates/cuda-device/src/generated/fence.rs b/crates/cuda-device/src/generated/fence.rs index 0efbec937a..df06d9f91e 100644 --- a/crates/cuda-device/src/generated/fence.rs +++ b/crates/cuda-device/src/generated/fence.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. // This file is included inside `cuda_device::fence` so existing paths stay stable. diff --git a/crates/cuda-device/src/generated/float.rs b/crates/cuda-device/src/generated/float.rs index 901fc0f6ff..575a42536a 100644 --- a/crates/cuda-device/src/generated/float.rs +++ b/crates/cuda-device/src/generated/float.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. // Included inside `cuda_device::float`. diff --git a/crates/cuda-device/src/generated/grid_dependency.rs b/crates/cuda-device/src/generated/grid_dependency.rs index 1f315de346..8af7873ec2 100644 --- a/crates/cuda-device/src/generated/grid_dependency.rs +++ b/crates/cuda-device/src/generated/grid_dependency.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. // Included inside `cuda_device::grid` to keep its public API stable. diff --git a/crates/cuda-device/src/generated/grid_sreg.rs b/crates/cuda-device/src/generated/grid_sreg.rs index a8fa7256bf..0e2dcf6b0f 100644 --- a/crates/cuda-device/src/generated/grid_sreg.rs +++ b/crates/cuda-device/src/generated/grid_sreg.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. // Included inside `cuda_device::grid` to keep existing paths stable. diff --git a/crates/cuda-device/src/generated/i16x2.rs b/crates/cuda-device/src/generated/i16x2.rs index 0206d501ab..c7164a3624 100644 --- a/crates/cuda-device/src/generated/i16x2.rs +++ b/crates/cuda-device/src/generated/i16x2.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. // Included inside `cuda_device::i16x2` to keep existing paths stable. diff --git a/crates/cuda-device/src/generated/int.rs b/crates/cuda-device/src/generated/int.rs index 95fbe4ba91..890bf63762 100644 --- a/crates/cuda-device/src/generated/int.rs +++ b/crates/cuda-device/src/generated/int.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. // Included inside `cuda_device::int` to keep existing paths stable. diff --git a/crates/cuda-device/src/generated/ldmatrix.rs b/crates/cuda-device/src/generated/ldmatrix.rs index fc62e3ca99..815b424c0a 100644 --- a/crates/cuda-device/src/generated/ldmatrix.rs +++ b/crates/cuda-device/src/generated/ldmatrix.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. // Included inside `cuda_device::wmma` to keep public paths stable. diff --git a/crates/cuda-device/src/generated/mbarrier_basic.rs b/crates/cuda-device/src/generated/mbarrier_basic.rs index ec38eb0344..f4d1e57c6a 100644 --- a/crates/cuda-device/src/generated/mbarrier_basic.rs +++ b/crates/cuda-device/src/generated/mbarrier_basic.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. // Included inside `cuda_device::barrier` to keep existing paths stable. diff --git a/crates/cuda-device/src/generated/mbarrier_extended.rs b/crates/cuda-device/src/generated/mbarrier_extended.rs index 5e55c21655..4269030c2a 100644 --- a/crates/cuda-device/src/generated/mbarrier_extended.rs +++ b/crates/cuda-device/src/generated/mbarrier_extended.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. // Included inside `cuda_device::barrier` to keep existing paths stable. diff --git a/crates/cuda-device/src/generated/movmatrix.rs b/crates/cuda-device/src/generated/movmatrix.rs index a70baa1b51..2b24130a41 100644 --- a/crates/cuda-device/src/generated/movmatrix.rs +++ b/crates/cuda-device/src/generated/movmatrix.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. // Included inside `cuda_device::wmma` to keep its public API stable. diff --git a/crates/cuda-device/src/generated/prmt.rs b/crates/cuda-device/src/generated/prmt.rs index 86e61b1f79..e5d41e47a5 100644 --- a/crates/cuda-device/src/generated/prmt.rs +++ b/crates/cuda-device/src/generated/prmt.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. // Included inside `cuda_device::prmt` to keep the public paths stable. diff --git a/crates/cuda-device/src/generated/register_control.rs b/crates/cuda-device/src/generated/register_control.rs index 9f5f8adfc3..d3d1f925e3 100644 --- a/crates/cuda-device/src/generated/register_control.rs +++ b/crates/cuda-device/src/generated/register_control.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. // Included inside `cuda_device::thread` to keep its public API stable. diff --git a/crates/cuda-device/src/generated/register_mma.rs b/crates/cuda-device/src/generated/register_mma.rs index d32c407f60..5fa99e877d 100644 --- a/crates/cuda-device/src/generated/register_mma.rs +++ b/crates/cuda-device/src/generated/register_mma.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. // Included inside `cuda_device::wmma` to keep public paths stable. diff --git a/crates/cuda-device/src/generated/shared_sreg.rs b/crates/cuda-device/src/generated/shared_sreg.rs index 6f33903181..a7761c7816 100644 --- a/crates/cuda-device/src/generated/shared_sreg.rs +++ b/crates/cuda-device/src/generated/shared_sreg.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. // Included inside `cuda_device::shared` to keep existing paths stable. diff --git a/crates/cuda-device/src/generated/sparse_mma.rs b/crates/cuda-device/src/generated/sparse_mma.rs index 212f96a7a3..8c6f522be0 100644 --- a/crates/cuda-device/src/generated/sparse_mma.rs +++ b/crates/cuda-device/src/generated/sparse_mma.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. // Included inside `cuda_device::wmma` to keep public paths stable. @@ -1017,6 +1017,174 @@ pub unsafe fn mma_sp_ordered_metadata_m16n8k128_s32_u4_satfinite( ) } +/// Multiplies warp-distributed ordered sparse f16 A and B fragments and adds a packed f16 accumulator. +/// Lowers to `mma.sp::ordered_metadata.sync.aligned.m16n8k16.row.col.f16.f16.f16.f16`. C, A, B, and metadata are this lane's PTX fragments. +/// Requires PTX 8.5 and `sm_80+`. +/// +/// # Safety +/// All 32 lanes must execute the same instruction with the same qualifiers, and no lane may have exited. +/// `c`, `a`, and `b` must contain this lane's 2-, 2-, and 2-register fragments; `metadata` must contain its sparse metadata. +/// Every 4-bit metadata group must be `0x4`, `0x8`, `0x9`, `0xc`, `0xd`, or `0xe`; any other value is undefined behavior. +/// `selector` must be the compile-time constant `0`, `1`, `2`, or `3`. +/// See the [PTX sparse MMA fragment layouts](https://docs.nvidia.com/cuda/parallel-thread-execution/#warp-level-matrix-instructions-mma-sp). +/// This register-only operation is not a memory fence. +#[must_use] +#[inline(never)] +pub unsafe fn mma_sp_ordered_metadata_m16n8k16_f16_f16( + c: [u32; 2], + a: [u32; 2], + b: [u32; 2], + metadata: u32, + selector: u32, +) -> [u32; 2] { + let _ = (c, a, b, metadata, selector); + unreachable!("mma_sp_ordered_metadata_m16n8k16_f16_f16 called outside CUDA kernel context") +} + +/// Multiplies warp-distributed ordered sparse bf16 A and B fragments and adds a f32 accumulator. +/// Lowers to `mma.sp::ordered_metadata.sync.aligned.m16n8k16.row.col.f32.bf16.bf16.f32`. C, A, B, and metadata are this lane's PTX fragments. +/// Requires PTX 8.5 and `sm_80+`. +/// +/// # Safety +/// All 32 lanes must execute the same instruction with the same qualifiers, and no lane may have exited. +/// `c`, `a`, and `b` must contain this lane's 4-, 2-, and 2-register fragments; `metadata` must contain its sparse metadata. +/// Every 4-bit metadata group must be `0x4`, `0x8`, `0x9`, `0xc`, `0xd`, or `0xe`; any other value is undefined behavior. +/// `selector` must be the compile-time constant `0`, `1`, `2`, or `3`. +/// See the [PTX sparse MMA fragment layouts](https://docs.nvidia.com/cuda/parallel-thread-execution/#warp-level-matrix-instructions-mma-sp). +/// This register-only operation is not a memory fence. +#[must_use] +#[inline(never)] +pub unsafe fn mma_sp_ordered_metadata_m16n8k16_f32_bf16( + c: [f32; 4], + a: [u32; 2], + b: [u32; 2], + metadata: u32, + selector: u32, +) -> [f32; 4] { + let _ = (c, a, b, metadata, selector); + unreachable!("mma_sp_ordered_metadata_m16n8k16_f32_bf16 called outside CUDA kernel context") +} + +/// Multiplies warp-distributed ordered sparse f16 A and B fragments and adds a f32 accumulator. +/// Lowers to `mma.sp::ordered_metadata.sync.aligned.m16n8k16.row.col.f32.f16.f16.f32`. C, A, B, and metadata are this lane's PTX fragments. +/// Requires PTX 8.5 and `sm_80+`. +/// +/// # Safety +/// All 32 lanes must execute the same instruction with the same qualifiers, and no lane may have exited. +/// `c`, `a`, and `b` must contain this lane's 4-, 2-, and 2-register fragments; `metadata` must contain its sparse metadata. +/// Every 4-bit metadata group must be `0x4`, `0x8`, `0x9`, `0xc`, `0xd`, or `0xe`; any other value is undefined behavior. +/// `selector` must be the compile-time constant `0`, `1`, `2`, or `3`. +/// See the [PTX sparse MMA fragment layouts](https://docs.nvidia.com/cuda/parallel-thread-execution/#warp-level-matrix-instructions-mma-sp). +/// This register-only operation is not a memory fence. +#[must_use] +#[inline(never)] +pub unsafe fn mma_sp_ordered_metadata_m16n8k16_f32_f16( + c: [f32; 4], + a: [u32; 2], + b: [u32; 2], + metadata: u32, + selector: u32, +) -> [f32; 4] { + let _ = (c, a, b, metadata, selector); + unreachable!("mma_sp_ordered_metadata_m16n8k16_f32_f16 called outside CUDA kernel context") +} + +/// Multiplies warp-distributed ordered sparse tf32 A and B fragments and adds a f32 accumulator. +/// Lowers to `mma.sp::ordered_metadata.sync.aligned.m16n8k16.row.col.f32.tf32.tf32.f32`. C, A, B, and metadata are this lane's PTX fragments. +/// Requires PTX 8.5 and `sm_80+`. +/// +/// # Safety +/// All 32 lanes must execute the same instruction with the same qualifiers, and no lane may have exited. +/// `c`, `a`, and `b` must contain this lane's 4-, 4-, and 4-register fragments; `metadata` must contain its sparse metadata. +/// Every 4-bit metadata group must be `0x4` or `0xe`; any other value is undefined behavior. +/// `selector` must be the compile-time constant `0` or `1`. +/// See the [PTX sparse MMA fragment layouts](https://docs.nvidia.com/cuda/parallel-thread-execution/#warp-level-matrix-instructions-mma-sp). +/// This register-only operation is not a memory fence. +#[must_use] +#[inline(never)] +pub unsafe fn mma_sp_ordered_metadata_m16n8k16_f32_tf32( + c: [f32; 4], + a: [u32; 4], + b: [u32; 4], + metadata: u32, + selector: u32, +) -> [f32; 4] { + let _ = (c, a, b, metadata, selector); + unreachable!("mma_sp_ordered_metadata_m16n8k16_f32_tf32 called outside CUDA kernel context") +} + +/// Multiplies warp-distributed ordered sparse f16 A and B fragments and adds a packed f16 accumulator. +/// Lowers to `mma.sp::ordered_metadata.sync.aligned.m16n8k32.row.col.f16.f16.f16.f16`. C, A, B, and metadata are this lane's PTX fragments. +/// Requires PTX 8.5 and `sm_80+`. +/// +/// # Safety +/// All 32 lanes must execute the same instruction with the same qualifiers, and no lane may have exited. +/// `c`, `a`, and `b` must contain this lane's 2-, 4-, and 4-register fragments; `metadata` must contain its sparse metadata. +/// Every 4-bit metadata group must be `0x4`, `0x8`, `0x9`, `0xc`, `0xd`, or `0xe`; any other value is undefined behavior. +/// `selector` must be the compile-time constant `0` or `1`. +/// See the [PTX sparse MMA fragment layouts](https://docs.nvidia.com/cuda/parallel-thread-execution/#warp-level-matrix-instructions-mma-sp). +/// This register-only operation is not a memory fence. +#[must_use] +#[inline(never)] +pub unsafe fn mma_sp_ordered_metadata_m16n8k32_f16_f16( + c: [u32; 2], + a: [u32; 4], + b: [u32; 4], + metadata: u32, + selector: u32, +) -> [u32; 2] { + let _ = (c, a, b, metadata, selector); + unreachable!("mma_sp_ordered_metadata_m16n8k32_f16_f16 called outside CUDA kernel context") +} + +/// Multiplies warp-distributed ordered sparse bf16 A and B fragments and adds a f32 accumulator. +/// Lowers to `mma.sp::ordered_metadata.sync.aligned.m16n8k32.row.col.f32.bf16.bf16.f32`. C, A, B, and metadata are this lane's PTX fragments. +/// Requires PTX 8.5 and `sm_80+`. +/// +/// # Safety +/// All 32 lanes must execute the same instruction with the same qualifiers, and no lane may have exited. +/// `c`, `a`, and `b` must contain this lane's 4-, 4-, and 4-register fragments; `metadata` must contain its sparse metadata. +/// Every 4-bit metadata group must be `0x4`, `0x8`, `0x9`, `0xc`, `0xd`, or `0xe`; any other value is undefined behavior. +/// `selector` must be the compile-time constant `0` or `1`. +/// See the [PTX sparse MMA fragment layouts](https://docs.nvidia.com/cuda/parallel-thread-execution/#warp-level-matrix-instructions-mma-sp). +/// This register-only operation is not a memory fence. +#[must_use] +#[inline(never)] +pub unsafe fn mma_sp_ordered_metadata_m16n8k32_f32_bf16( + c: [f32; 4], + a: [u32; 4], + b: [u32; 4], + metadata: u32, + selector: u32, +) -> [f32; 4] { + let _ = (c, a, b, metadata, selector); + unreachable!("mma_sp_ordered_metadata_m16n8k32_f32_bf16 called outside CUDA kernel context") +} + +/// Multiplies warp-distributed ordered sparse f16 A and B fragments and adds a f32 accumulator. +/// Lowers to `mma.sp::ordered_metadata.sync.aligned.m16n8k32.row.col.f32.f16.f16.f32`. C, A, B, and metadata are this lane's PTX fragments. +/// Requires PTX 8.5 and `sm_80+`. +/// +/// # Safety +/// All 32 lanes must execute the same instruction with the same qualifiers, and no lane may have exited. +/// `c`, `a`, and `b` must contain this lane's 4-, 4-, and 4-register fragments; `metadata` must contain its sparse metadata. +/// Every 4-bit metadata group must be `0x4`, `0x8`, `0x9`, `0xc`, `0xd`, or `0xe`; any other value is undefined behavior. +/// `selector` must be the compile-time constant `0` or `1`. +/// See the [PTX sparse MMA fragment layouts](https://docs.nvidia.com/cuda/parallel-thread-execution/#warp-level-matrix-instructions-mma-sp). +/// This register-only operation is not a memory fence. +#[must_use] +#[inline(never)] +pub unsafe fn mma_sp_ordered_metadata_m16n8k32_f32_f16( + c: [f32; 4], + a: [u32; 4], + b: [u32; 4], + metadata: u32, + selector: u32, +) -> [f32; 4] { + let _ = (c, a, b, metadata, selector); + unreachable!("mma_sp_ordered_metadata_m16n8k32_f32_f16 called outside CUDA kernel context") +} + /// Multiplies warp-distributed sparse signed A and signed B INT8 fragments with ordered sparsity metadata and adds a wrapping s32 accumulator. /// Lowers to `mma.sp::ordered_metadata.sync.aligned.m16n8k32.row.col.s32.s8.s8.s32`. C, A, B, and metadata are this lane's PTX fragments. /// Requires PTX 8.5 and `sm_80+`. @@ -2940,3 +3108,27 @@ pub unsafe fn mma_sp_ordered_metadata_m16n8k64_s32_u8_satfinite( "mma_sp_ordered_metadata_m16n8k64_s32_u8_satfinite called outside CUDA kernel context" ) } + +/// Multiplies warp-distributed ordered sparse tf32 A and B fragments and adds a f32 accumulator. +/// Lowers to `mma.sp::ordered_metadata.sync.aligned.m16n8k8.row.col.f32.tf32.tf32.f32`. C, A, B, and metadata are this lane's PTX fragments. +/// Requires PTX 8.5 and `sm_80+`. +/// +/// # Safety +/// All 32 lanes must execute the same instruction with the same qualifiers, and no lane may have exited. +/// `c`, `a`, and `b` must contain this lane's 4-, 2-, and 2-register fragments; `metadata` must contain its sparse metadata. +/// Every 4-bit metadata group must be `0x4` or `0xe`; any other value is undefined behavior. +/// `selector` must be the compile-time constant `0`, `1`, `2`, or `3`. +/// See the [PTX sparse MMA fragment layouts](https://docs.nvidia.com/cuda/parallel-thread-execution/#warp-level-matrix-instructions-mma-sp). +/// This register-only operation is not a memory fence. +#[must_use] +#[inline(never)] +pub unsafe fn mma_sp_ordered_metadata_m16n8k8_f32_tf32( + c: [f32; 4], + a: [u32; 2], + b: [u32; 2], + metadata: u32, + selector: u32, +) -> [f32; 4] { + let _ = (c, a, b, metadata, selector); + unreachable!("mma_sp_ordered_metadata_m16n8k8_f32_tf32 called outside CUDA kernel context") +} diff --git a/crates/cuda-device/src/generated/sreg.rs b/crates/cuda-device/src/generated/sreg.rs index bf69628a38..0f5678b5f7 100644 --- a/crates/cuda-device/src/generated/sreg.rs +++ b/crates/cuda-device/src/generated/sreg.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. // This file is included lexically inside `cuda_device::thread` so existing diff --git a/crates/cuda-device/src/generated/stmatrix.rs b/crates/cuda-device/src/generated/stmatrix.rs index 7e8161dfda..a694ef0e83 100644 --- a/crates/cuda-device/src/generated/stmatrix.rs +++ b/crates/cuda-device/src/generated/stmatrix.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. // Included inside `cuda_device::tcgen05` to keep public paths stable. diff --git a/crates/cuda-device/src/generated/tcgen05.rs b/crates/cuda-device/src/generated/tcgen05.rs index 87b873cc9d..6276d0add2 100644 --- a/crates/cuda-device/src/generated/tcgen05.rs +++ b/crates/cuda-device/src/generated/tcgen05.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. // Included inside `cuda_device::tcgen05` to keep its public API stable. diff --git a/crates/cuda-device/src/generated/tma.rs b/crates/cuda-device/src/generated/tma.rs index 835e8de428..86b3130c48 100644 --- a/crates/cuda-device/src/generated/tma.rs +++ b/crates/cuda-device/src/generated/tma.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. // Included inside `cuda_device::tma` to keep its public API stable. diff --git a/crates/cuda-device/src/generated/warp_sreg.rs b/crates/cuda-device/src/generated/warp_sreg.rs index f90d8680f1..47d9fff8c0 100644 --- a/crates/cuda-device/src/generated/warp_sreg.rs +++ b/crates/cuda-device/src/generated/warp_sreg.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. // Included inside `cuda_device::warp` to keep existing paths stable. diff --git a/crates/cuda-device/src/generated/wgmma_control.rs b/crates/cuda-device/src/generated/wgmma_control.rs index a71508c14b..e0a7e0e831 100644 --- a/crates/cuda-device/src/generated/wgmma_control.rs +++ b/crates/cuda-device/src/generated/wgmma_control.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. // Included inside `cuda_device::wgmma` to keep its public API stable. diff --git a/crates/cuda-intrinsics-gen/src/model/contracts/matrix.rs b/crates/cuda-intrinsics-gen/src/model/contracts/matrix.rs index d62f5562d1..52398b3382 100644 --- a/crates/cuda-intrinsics-gen/src/model/contracts/matrix.rs +++ b/crates/cuda-intrinsics-gen/src/model/contracts/matrix.rs @@ -296,6 +296,8 @@ pub struct SparseMma { #[derive(Debug, Clone, Copy, PartialEq, Eq, PartialOrd, Ord, Serialize, Deserialize)] #[serde(rename_all = "snake_case")] pub enum SparseMmaShape { + M16n8k8, + M16n8k16, M16n8k32, M16n8k64, M16n8k128, @@ -312,6 +314,9 @@ pub enum SparseMmaAccumulator { #[derive(Debug, Clone, Copy, PartialEq, Eq, PartialOrd, Ord, Serialize, Deserialize)] #[serde(rename_all = "snake_case")] pub enum SparseMmaElement { + F16, + Bf16, + Tf32, E2m1, E2m3, E3m2, @@ -347,7 +352,10 @@ pub enum SparseMmaMetadata { #[derive(Debug, Clone, Copy, PartialEq, Eq, PartialOrd, Ord, Serialize, Deserialize)] #[serde(rename_all = "snake_case")] +// The shared prefix makes each variant's accepted immediate range explicit in catalog data. +#[allow(clippy::enum_variant_names)] pub enum SparseMmaSelector { + ImmediateZeroThroughThree, ImmediateZeroOrOne, ImmediateZero, } @@ -362,7 +370,9 @@ pub enum SparseMmaParticipation { #[derive(Debug, Clone, Copy, PartialEq, Eq, PartialOrd, Ord, Serialize, Deserialize)] #[serde(rename_all = "snake_case")] pub enum SparseMmaAdapter { + C2U32A2U32B2U32MetadataU32SelectorU32ToD2U32, C2U32A4U32B4U32MetadataU32SelectorU32ToD2U32, + C4F32A2U32B2U32MetadataU32SelectorU32ToD4F32, C4F32A4U32B4U32MetadataU32SelectorU32ToD4F32, C4I32A2U32B2U32MetadataU32SelectorU32ToD4I32, C4I32A4U32B4U32MetadataU32SelectorU32ToD4I32, @@ -372,7 +382,13 @@ pub enum SparseMmaAdapter { #[derive(Debug, Clone, Copy, PartialEq, Eq, PartialOrd, Ord, Serialize, Deserialize)] #[serde(rename_all = "snake_case")] pub enum SparseMmaLlvmAdapter { + A2V2F16B2V2F16C2V2F16MetadataI32SelectorI32ToD2V2F16, + A4V2F16B4V2F16C2V2F16MetadataI32SelectorI32ToD2V2F16, + A2V2F16B2V2F16C4F32MetadataI32SelectorI32ToD4F32, + A4V2F16B4V2F16C4F32MetadataI32SelectorI32ToD4F32, + A2I32B2I32C2V2F16MetadataI32SelectorI32ToD2V2F16, A4I32B4I32C2V2F16MetadataI32SelectorI32ToD2V2F16, + A2I32B2I32C4F32MetadataI32SelectorI32ToD4F32, A4I32B4I32C4F32MetadataI32SelectorI32ToD4F32, A2I32B2I32C4I32MetadataI32SelectorI32ToD4I32, A4I32B4I32C4I32MetadataI32SelectorI32ToD4I32, diff --git a/crates/cuda-intrinsics-gen/src/model/overlay.rs b/crates/cuda-intrinsics-gen/src/model/overlay.rs index 60b1b6e351..b69c3e4885 100644 --- a/crates/cuda-intrinsics-gen/src/model/overlay.rs +++ b/crates/cuda-intrinsics-gen/src/model/overlay.rs @@ -16,12 +16,12 @@ use super::contracts::{ ScalarArithmetic, ScalarArithmeticFormat, ScalarArithmeticOperation, ScalarArithmeticRounding, ScalarArithmeticSaturation, ScalarArithmeticSubnormal, ScalarConversion, ScalarConversionRounding, ScalarConversionSaturation, ScalarMath, ScalarMathFormat, - ScalarMathOperation, ScalarMathPrecision, ScalarMathSubnormal, SparseMma, SparseMmaElement, - SparseMmaMetadata, SparseMmaOverflow, SparseMmaShape, SpecialRegister, SpecialRegisterKind, - StmatrixLayout, StmatrixMultiplicity, Tcgen05, Tcgen05CpGroup, Tcgen05CpMember, - Tcgen05LdMultiplicity, Tcgen05LdShape, Tcgen05MmaAlias, Tcgen05MmaForm, Tcgen05Operation, Tma, - TmaOperation, TmaReductionLoadMode, TmaReductionOperation, Vote, WarpBarrier, WarpMatch, - WarpShuffle, WgmmaControl, WgmmaControlMode, + ScalarMathOperation, ScalarMathPrecision, ScalarMathSubnormal, SparseMma, SparseMmaAccumulator, + SparseMmaElement, SparseMmaMetadata, SparseMmaOverflow, SparseMmaShape, SpecialRegister, + SpecialRegisterKind, StmatrixLayout, StmatrixMultiplicity, Tcgen05, Tcgen05CpGroup, + Tcgen05CpMember, Tcgen05LdMultiplicity, Tcgen05LdShape, Tcgen05MmaAlias, Tcgen05MmaForm, + Tcgen05Operation, Tma, TmaOperation, TmaReductionLoadMode, TmaReductionOperation, Vote, + WarpBarrier, WarpMatch, WarpShuffle, WgmmaControl, WgmmaControlMode, }; use super::core::{BackendLoweringMechanism, IntrinsicBackend, IntrinsicSource, RuntimeValidation}; use super::imported::ImportedAddressSpace; @@ -73,6 +73,8 @@ pub struct OverlayShardFile { #[serde(default)] pub sparse_mma_f8f6f4_f16: Option, #[serde(default)] + pub sparse_mma_ordered_ampere_float: Option, + #[serde(default)] pub prmt: Option, #[serde(default)] pub packed_conversion_fp8: Option, @@ -727,6 +729,26 @@ pub struct SparseMmaF8F6F4F16Admission { pub product_count: usize, } +/// Compact admission for the reviewed ordered-metadata Ampere floating sparse MMA forms. +#[derive(Debug, Clone, Deserialize)] +#[serde(deny_unknown_fields)] +pub struct SparseMmaOrderedAmpereFloatAdmission { + pub llvm_evidence_profile: String, + pub libnvvm_evidence_profile: String, + pub runtime_validation: RuntimeValidation, + #[serde(rename = "variant")] + pub variants: Vec, +} + +/// One reviewed ordered-metadata Ampere floating sparse MMA form. +#[derive(Debug, Clone, Copy, PartialEq, Eq, Deserialize)] +#[serde(deny_unknown_fields)] +pub struct SparseMmaOrderedAmpereFloatVariant { + pub shape: SparseMmaShape, + pub accumulator: SparseMmaAccumulator, + pub element: SparseMmaElement, +} + #[derive(Debug, Clone, Deserialize)] #[serde(deny_unknown_fields)] pub struct OverlayIntrinsic { diff --git a/crates/cuda-intrinsics-gen/src/probe.rs b/crates/cuda-intrinsics-gen/src/probe.rs index 7ab3ccab50..bda616c38d 100644 --- a/crates/cuda-intrinsics-gen/src/probe.rs +++ b/crates/cuda-intrinsics-gen/src/probe.rs @@ -884,6 +884,7 @@ fn validate_probe_instructions(record: &CatalogIntrinsic, ptx: &str) -> Result<( } if let Some(mma) = &record.sparse_mma { let selectors: &[u32] = match mma.selector { + SparseMmaSelector::ImmediateZeroThroughThree => &[0, 1, 2, 3], SparseMmaSelector::ImmediateZeroOrOne => &[0, 1], SparseMmaSelector::ImmediateZero => &[0], }; diff --git a/crates/cuda-intrinsics-gen/src/render/collector_targets.rs b/crates/cuda-intrinsics-gen/src/render/collector_targets.rs index de065ddffb..213bec7e94 100644 --- a/crates/cuda-intrinsics-gen/src/render/collector_targets.rs +++ b/crates/cuda-intrinsics-gen/src/render/collector_targets.rs @@ -233,6 +233,8 @@ pub(super) fn generated_intrinsic_variant(record: &CatalogIntrinsic) -> String { } if let Some(mma) = &record.sparse_mma { let shape = match mma.shape { + SparseMmaShape::M16n8k8 => "GeneratedSparseMmaShape::M16n8k8", + SparseMmaShape::M16n8k16 => "GeneratedSparseMmaShape::M16n8k16", SparseMmaShape::M16n8k32 => "GeneratedSparseMmaShape::M16n8k32", SparseMmaShape::M16n8k64 => "GeneratedSparseMmaShape::M16n8k64", SparseMmaShape::M16n8k128 => "GeneratedSparseMmaShape::M16n8k128", @@ -243,6 +245,9 @@ pub(super) fn generated_intrinsic_variant(record: &CatalogIntrinsic) -> String { SparseMmaAccumulator::S32 => "GeneratedSparseMmaAccumulator::S32", }; let element = |element| match element { + SparseMmaElement::F16 => "GeneratedSparseMmaElement::F16", + SparseMmaElement::Bf16 => "GeneratedSparseMmaElement::Bf16", + SparseMmaElement::Tf32 => "GeneratedSparseMmaElement::Tf32", SparseMmaElement::E2m1 => "GeneratedSparseMmaElement::E2m1", SparseMmaElement::E2m3 => "GeneratedSparseMmaElement::E2m3", SparseMmaElement::E3m2 => "GeneratedSparseMmaElement::E3m2", @@ -267,6 +272,9 @@ pub(super) fn generated_intrinsic_variant(record: &CatalogIntrinsic) -> String { SparseMmaMetadata::Ordered => "GeneratedSparseMmaMetadata::Ordered", }; let selector = match mma.selector { + SparseMmaSelector::ImmediateZeroThroughThree => { + "GeneratedSparseMmaSelector::ImmediateZeroThroughThree" + } SparseMmaSelector::ImmediateZeroOrOne => { "GeneratedSparseMmaSelector::ImmediateZeroOrOne" } @@ -573,7 +581,7 @@ impl GeneratedIntrinsicTarget { replace_exact_render_fragment( &mut output, "#[derive(Debug, Clone, Copy, PartialEq, Eq)]\npub enum GeneratedIntrinsicVariant {", - "#[derive(Debug, Clone, Copy, PartialEq, Eq)]\npub enum GeneratedSparseMmaShape { M16n8k32, M16n8k64, M16n8k128 }\n#[derive(Debug, Clone, Copy, PartialEq, Eq)]\npub enum GeneratedSparseMmaAccumulator { F16, F32, S32 }\n#[derive(Debug, Clone, Copy, PartialEq, Eq)]\npub enum GeneratedSparseMmaElement { E2m1, E2m3, E3m2, E4m3, E5m2, S4, U4, S8, U8 }\n#[derive(Debug, Clone, Copy, PartialEq, Eq)]\npub enum GeneratedSparseMmaLayout { Row, Col }\n#[derive(Debug, Clone, Copy, PartialEq, Eq)]\npub enum GeneratedSparseMmaOverflow { NotApplicable, Wrapping, Satfinite }\n#[derive(Debug, Clone, Copy, PartialEq, Eq)]\npub enum GeneratedSparseMmaMetadata { Standard, Ordered }\n#[derive(Debug, Clone, Copy, PartialEq, Eq)]\npub enum GeneratedSparseMmaSelector { ImmediateZeroOrOne, ImmediateZero }\n#[derive(Debug, Clone, Copy, PartialEq, Eq)]\npub enum GeneratedPrmtMode { Generic, F4e, B4e, Rc8, Ecl, Ecr, Rc16 }\n#[derive(Debug, Clone, Copy, PartialEq, Eq)]\npub enum GeneratedClusterBarrierMode { Arrive, ArriveAligned, ArriveRelaxed, ArriveRelaxedAligned, Wait, WaitAligned }\n#[derive(Debug, Clone, Copy, PartialEq, Eq)]\npub enum GeneratedScalarConversionRounding { NearestAway, NearestEven, TowardZero }\n#[derive(Debug, Clone, Copy, PartialEq, Eq)]\npub enum GeneratedScalarConversionSaturation { None, Relu, Satfinite, ReluSatfinite }\n#[derive(Debug, Clone, Copy, PartialEq, Eq)]\npub enum GeneratedIntrinsicVariant {", + "#[derive(Debug, Clone, Copy, PartialEq, Eq)]\npub enum GeneratedSparseMmaShape { M16n8k8, M16n8k16, M16n8k32, M16n8k64, M16n8k128 }\n#[derive(Debug, Clone, Copy, PartialEq, Eq)]\npub enum GeneratedSparseMmaAccumulator { F16, F32, S32 }\n#[derive(Debug, Clone, Copy, PartialEq, Eq)]\npub enum GeneratedSparseMmaElement { F16, Bf16, Tf32, E2m1, E2m3, E3m2, E4m3, E5m2, S4, U4, S8, U8 }\n#[derive(Debug, Clone, Copy, PartialEq, Eq)]\npub enum GeneratedSparseMmaLayout { Row, Col }\n#[derive(Debug, Clone, Copy, PartialEq, Eq)]\npub enum GeneratedSparseMmaOverflow { NotApplicable, Wrapping, Satfinite }\n#[derive(Debug, Clone, Copy, PartialEq, Eq)]\npub enum GeneratedSparseMmaMetadata { Standard, Ordered }\n#[derive(Debug, Clone, Copy, PartialEq, Eq)]\n#[allow(clippy::enum_variant_names)]\npub enum GeneratedSparseMmaSelector { ImmediateZeroThroughThree, ImmediateZeroOrOne, ImmediateZero }\n#[derive(Debug, Clone, Copy, PartialEq, Eq)]\npub enum GeneratedPrmtMode { Generic, F4e, B4e, Rc8, Ecl, Ecr, Rc16 }\n#[derive(Debug, Clone, Copy, PartialEq, Eq)]\npub enum GeneratedClusterBarrierMode { Arrive, ArriveAligned, ArriveRelaxed, ArriveRelaxedAligned, Wait, WaitAligned }\n#[derive(Debug, Clone, Copy, PartialEq, Eq)]\npub enum GeneratedScalarConversionRounding { NearestAway, NearestEven, TowardZero }\n#[derive(Debug, Clone, Copy, PartialEq, Eq)]\npub enum GeneratedScalarConversionSaturation { None, Relu, Satfinite, ReluSatfinite }\n#[derive(Debug, Clone, Copy, PartialEq, Eq)]\npub enum GeneratedIntrinsicVariant {", ); replace_exact_render_fragment( &mut output, @@ -784,12 +792,12 @@ impl GeneratedIntrinsicTarget { replace_exact_render_fragment( &mut output, " && overflow_matches\n }\n }\n}\n", - " && overflow_matches\n }\n GeneratedIntrinsicVariant::SparseMma { shape, accumulator, a_element, b_element, a_layout, b_layout, overflow, metadata, selector } => {\n let Some(op) = Operation::get_op::(operation, ctx) else { return false; };\n let element_matches = |expected, actual: Option<&SparseMmaElementAttr>| match expected {\n GeneratedSparseMmaElement::E2m1 => actual == Some(&SparseMmaElementAttr::E2m1),\n GeneratedSparseMmaElement::E2m3 => actual == Some(&SparseMmaElementAttr::E2m3),\n GeneratedSparseMmaElement::E3m2 => actual == Some(&SparseMmaElementAttr::E3m2),\n GeneratedSparseMmaElement::E4m3 => actual == Some(&SparseMmaElementAttr::E4m3),\n GeneratedSparseMmaElement::E5m2 => actual == Some(&SparseMmaElementAttr::E5m2),\n GeneratedSparseMmaElement::S4 => actual == Some(&SparseMmaElementAttr::S4),\n GeneratedSparseMmaElement::U4 => actual == Some(&SparseMmaElementAttr::U4),\n GeneratedSparseMmaElement::S8 => actual == Some(&SparseMmaElementAttr::S8),\n GeneratedSparseMmaElement::U8 => actual == Some(&SparseMmaElementAttr::U8),\n };\n let layout_matches = |expected, actual: Option<&SparseMmaLayoutAttr>| match expected {\n GeneratedSparseMmaLayout::Row => actual == Some(&SparseMmaLayoutAttr::Row),\n GeneratedSparseMmaLayout::Col => actual == Some(&SparseMmaLayoutAttr::Col),\n };\n let overflow_matches = match overflow {\n GeneratedSparseMmaOverflow::NotApplicable => op.get_attr_nvvm_sparse_mma_overflow(ctx).as_deref() == Some(&SparseMmaOverflowAttr::NotApplicable),\n GeneratedSparseMmaOverflow::Wrapping => op.get_attr_nvvm_sparse_mma_overflow(ctx).as_deref() == Some(&SparseMmaOverflowAttr::Wrapping),\n GeneratedSparseMmaOverflow::Satfinite => op.get_attr_nvvm_sparse_mma_overflow(ctx).as_deref() == Some(&SparseMmaOverflowAttr::Satfinite),\n };\n let metadata_matches = match metadata {\n GeneratedSparseMmaMetadata::Standard => op.get_attr_nvvm_sparse_mma_metadata(ctx).as_deref() == Some(&SparseMmaMetadataAttr::Standard),\n GeneratedSparseMmaMetadata::Ordered => op.get_attr_nvvm_sparse_mma_metadata(ctx).as_deref() == Some(&SparseMmaMetadataAttr::Ordered),\n };\n matches!(shape, GeneratedSparseMmaShape::M16n8k32)\n && op.get_attr_nvvm_sparse_mma_shape(ctx).as_deref() == Some(&SparseMmaShapeAttr::M16n8k32)\n && matches!(accumulator, GeneratedSparseMmaAccumulator::S32)\n && op.get_attr_nvvm_sparse_mma_accumulator(ctx).as_deref() == Some(&SparseMmaAccumulatorAttr::S32)\n && element_matches(a_element, op.get_attr_nvvm_sparse_mma_a_element(ctx).as_deref())\n && element_matches(b_element, op.get_attr_nvvm_sparse_mma_b_element(ctx).as_deref())\n && layout_matches(a_layout, op.get_attr_nvvm_sparse_mma_a_layout(ctx).as_deref())\n && layout_matches(b_layout, op.get_attr_nvvm_sparse_mma_b_layout(ctx).as_deref())\n && overflow_matches\n && metadata_matches\n && matches!(selector, GeneratedSparseMmaSelector::ImmediateZeroOrOne)\n && op.get_attr_nvvm_sparse_mma_selector(ctx).as_deref() == Some(&SparseMmaSelectorAttr::ImmediateZeroOrOne)\n }\n }\n}\n", + " && overflow_matches\n }\n GeneratedIntrinsicVariant::SparseMma { shape, accumulator, a_element, b_element, a_layout, b_layout, overflow, metadata, selector } => {\n let Some(op) = Operation::get_op::(operation, ctx) else { return false; };\n let element_matches = |expected, actual: Option<&SparseMmaElementAttr>| match expected {\n GeneratedSparseMmaElement::F16 => actual == Some(&SparseMmaElementAttr::F16),\n GeneratedSparseMmaElement::Bf16 => actual == Some(&SparseMmaElementAttr::Bf16),\n GeneratedSparseMmaElement::Tf32 => actual == Some(&SparseMmaElementAttr::Tf32),\n GeneratedSparseMmaElement::E2m1 => actual == Some(&SparseMmaElementAttr::E2m1),\n GeneratedSparseMmaElement::E2m3 => actual == Some(&SparseMmaElementAttr::E2m3),\n GeneratedSparseMmaElement::E3m2 => actual == Some(&SparseMmaElementAttr::E3m2),\n GeneratedSparseMmaElement::E4m3 => actual == Some(&SparseMmaElementAttr::E4m3),\n GeneratedSparseMmaElement::E5m2 => actual == Some(&SparseMmaElementAttr::E5m2),\n GeneratedSparseMmaElement::S4 => actual == Some(&SparseMmaElementAttr::S4),\n GeneratedSparseMmaElement::U4 => actual == Some(&SparseMmaElementAttr::U4),\n GeneratedSparseMmaElement::S8 => actual == Some(&SparseMmaElementAttr::S8),\n GeneratedSparseMmaElement::U8 => actual == Some(&SparseMmaElementAttr::U8),\n };\n let layout_matches = |expected, actual: Option<&SparseMmaLayoutAttr>| match expected {\n GeneratedSparseMmaLayout::Row => actual == Some(&SparseMmaLayoutAttr::Row),\n GeneratedSparseMmaLayout::Col => actual == Some(&SparseMmaLayoutAttr::Col),\n };\n let overflow_matches = match overflow {\n GeneratedSparseMmaOverflow::NotApplicable => op.get_attr_nvvm_sparse_mma_overflow(ctx).as_deref() == Some(&SparseMmaOverflowAttr::NotApplicable),\n GeneratedSparseMmaOverflow::Wrapping => op.get_attr_nvvm_sparse_mma_overflow(ctx).as_deref() == Some(&SparseMmaOverflowAttr::Wrapping),\n GeneratedSparseMmaOverflow::Satfinite => op.get_attr_nvvm_sparse_mma_overflow(ctx).as_deref() == Some(&SparseMmaOverflowAttr::Satfinite),\n };\n let metadata_matches = match metadata {\n GeneratedSparseMmaMetadata::Standard => op.get_attr_nvvm_sparse_mma_metadata(ctx).as_deref() == Some(&SparseMmaMetadataAttr::Standard),\n GeneratedSparseMmaMetadata::Ordered => op.get_attr_nvvm_sparse_mma_metadata(ctx).as_deref() == Some(&SparseMmaMetadataAttr::Ordered),\n };\n matches!(shape, GeneratedSparseMmaShape::M16n8k32)\n && op.get_attr_nvvm_sparse_mma_shape(ctx).as_deref() == Some(&SparseMmaShapeAttr::M16n8k32)\n && matches!(accumulator, GeneratedSparseMmaAccumulator::S32)\n && op.get_attr_nvvm_sparse_mma_accumulator(ctx).as_deref() == Some(&SparseMmaAccumulatorAttr::S32)\n && element_matches(a_element, op.get_attr_nvvm_sparse_mma_a_element(ctx).as_deref())\n && element_matches(b_element, op.get_attr_nvvm_sparse_mma_b_element(ctx).as_deref())\n && layout_matches(a_layout, op.get_attr_nvvm_sparse_mma_a_layout(ctx).as_deref())\n && layout_matches(b_layout, op.get_attr_nvvm_sparse_mma_b_layout(ctx).as_deref())\n && overflow_matches\n && metadata_matches\n && matches!(selector, GeneratedSparseMmaSelector::ImmediateZeroOrOne)\n && op.get_attr_nvvm_sparse_mma_selector(ctx).as_deref() == Some(&SparseMmaSelectorAttr::ImmediateZeroOrOne)\n }\n }\n}\n", ); replace_exact_render_fragment( &mut output, " matches!(shape, GeneratedSparseMmaShape::M16n8k32)\n && op.get_attr_nvvm_sparse_mma_shape(ctx).as_deref() == Some(&SparseMmaShapeAttr::M16n8k32)\n && matches!(accumulator, GeneratedSparseMmaAccumulator::S32)\n && op.get_attr_nvvm_sparse_mma_accumulator(ctx).as_deref() == Some(&SparseMmaAccumulatorAttr::S32)", - " let shape_matches = match shape {\n GeneratedSparseMmaShape::M16n8k32 => op.get_attr_nvvm_sparse_mma_shape(ctx).as_deref() == Some(&SparseMmaShapeAttr::M16n8k32),\n GeneratedSparseMmaShape::M16n8k64 => op.get_attr_nvvm_sparse_mma_shape(ctx).as_deref() == Some(&SparseMmaShapeAttr::M16n8k64),\n GeneratedSparseMmaShape::M16n8k128 => op.get_attr_nvvm_sparse_mma_shape(ctx).as_deref() == Some(&SparseMmaShapeAttr::M16n8k128),\n };\n let accumulator_matches = match accumulator {\n GeneratedSparseMmaAccumulator::F16 => op.get_attr_nvvm_sparse_mma_accumulator(ctx).as_deref() == Some(&SparseMmaAccumulatorAttr::F16),\n GeneratedSparseMmaAccumulator::F32 => op.get_attr_nvvm_sparse_mma_accumulator(ctx).as_deref() == Some(&SparseMmaAccumulatorAttr::F32),\n GeneratedSparseMmaAccumulator::S32 => op.get_attr_nvvm_sparse_mma_accumulator(ctx).as_deref() == Some(&SparseMmaAccumulatorAttr::S32),\n };\n let selector_matches = match selector {\n GeneratedSparseMmaSelector::ImmediateZeroOrOne => op.get_attr_nvvm_sparse_mma_selector(ctx).as_deref() == Some(&SparseMmaSelectorAttr::ImmediateZeroOrOne),\n GeneratedSparseMmaSelector::ImmediateZero => op.get_attr_nvvm_sparse_mma_selector(ctx).as_deref() == Some(&SparseMmaSelectorAttr::ImmediateZero),\n };\n shape_matches\n && accumulator_matches", + " let shape_matches = match shape {\n GeneratedSparseMmaShape::M16n8k8 => op.get_attr_nvvm_sparse_mma_shape(ctx).as_deref() == Some(&SparseMmaShapeAttr::M16n8k8),\n GeneratedSparseMmaShape::M16n8k16 => op.get_attr_nvvm_sparse_mma_shape(ctx).as_deref() == Some(&SparseMmaShapeAttr::M16n8k16),\n GeneratedSparseMmaShape::M16n8k32 => op.get_attr_nvvm_sparse_mma_shape(ctx).as_deref() == Some(&SparseMmaShapeAttr::M16n8k32),\n GeneratedSparseMmaShape::M16n8k64 => op.get_attr_nvvm_sparse_mma_shape(ctx).as_deref() == Some(&SparseMmaShapeAttr::M16n8k64),\n GeneratedSparseMmaShape::M16n8k128 => op.get_attr_nvvm_sparse_mma_shape(ctx).as_deref() == Some(&SparseMmaShapeAttr::M16n8k128),\n };\n let accumulator_matches = match accumulator {\n GeneratedSparseMmaAccumulator::F16 => op.get_attr_nvvm_sparse_mma_accumulator(ctx).as_deref() == Some(&SparseMmaAccumulatorAttr::F16),\n GeneratedSparseMmaAccumulator::F32 => op.get_attr_nvvm_sparse_mma_accumulator(ctx).as_deref() == Some(&SparseMmaAccumulatorAttr::F32),\n GeneratedSparseMmaAccumulator::S32 => op.get_attr_nvvm_sparse_mma_accumulator(ctx).as_deref() == Some(&SparseMmaAccumulatorAttr::S32),\n };\n let selector_matches = match selector {\n GeneratedSparseMmaSelector::ImmediateZeroThroughThree => op.get_attr_nvvm_sparse_mma_selector(ctx).as_deref() == Some(&SparseMmaSelectorAttr::ImmediateZeroThroughThree),\n GeneratedSparseMmaSelector::ImmediateZeroOrOne => op.get_attr_nvvm_sparse_mma_selector(ctx).as_deref() == Some(&SparseMmaSelectorAttr::ImmediateZeroOrOne),\n GeneratedSparseMmaSelector::ImmediateZero => op.get_attr_nvvm_sparse_mma_selector(ctx).as_deref() == Some(&SparseMmaSelectorAttr::ImmediateZero),\n };\n shape_matches\n && accumulator_matches", ); replace_exact_render_fragment( &mut output, diff --git a/crates/cuda-intrinsics-gen/src/render/compat.rs b/crates/cuda-intrinsics-gen/src/render/compat.rs index 1d6b967e72..ecc48feca7 100644 --- a/crates/cuda-intrinsics-gen/src/render/compat.rs +++ b/crates/cuda-intrinsics-gen/src/render/compat.rs @@ -205,7 +205,9 @@ pub(super) fn render_compat_sparse_mma(catalog: &CatalogFile, hash: &str) -> Str assert_eq!(path, &format!("cuda_device::wmma::{}", record.rust.name)); assert!(matches!( mma.adapter, - SparseMmaAdapter::C2U32A4U32B4U32MetadataU32SelectorU32ToD2U32 + SparseMmaAdapter::C2U32A2U32B2U32MetadataU32SelectorU32ToD2U32 + | SparseMmaAdapter::C2U32A4U32B4U32MetadataU32SelectorU32ToD2U32 + | SparseMmaAdapter::C4F32A2U32B2U32MetadataU32SelectorU32ToD4F32 | SparseMmaAdapter::C4F32A4U32B4U32MetadataU32SelectorU32ToD4F32 | SparseMmaAdapter::C4I32A2U32B2U32MetadataU32SelectorU32ToD4I32 | SparseMmaAdapter::C4I32A4U32B4U32MetadataU32SelectorU32ToD4I32 diff --git a/crates/cuda-intrinsics-gen/src/render/dialect/mma.rs b/crates/cuda-intrinsics-gen/src/render/dialect/mma.rs index bd793ae84d..e93f0300b8 100644 --- a/crates/cuda-intrinsics-gen/src/render/dialect/mma.rs +++ b/crates/cuda-intrinsics-gen/src/render/dialect/mma.rs @@ -776,7 +776,7 @@ use pliron_derive::{pliron_attr, pliron_op}; #[pliron_attr(name = "nvvm.sparse_mma_shape", format, verifier = "succ")] #[derive(PartialEq, Eq, Clone, Debug, Hash)] -pub enum SparseMmaShapeAttr { M16n8k32, M16n8k64, M16n8k128 } +pub enum SparseMmaShapeAttr { M16n8k8, M16n8k16, M16n8k32, M16n8k64, M16n8k128 } #[pliron_attr(name = "nvvm.sparse_mma_accumulator", format, verifier = "succ")] #[derive(PartialEq, Eq, Clone, Debug, Hash)] @@ -784,7 +784,7 @@ pub enum SparseMmaAccumulatorAttr { F16, F32, S32 } #[pliron_attr(name = "nvvm.sparse_mma_element", format, verifier = "succ")] #[derive(PartialEq, Eq, Clone, Debug, Hash)] -pub enum SparseMmaElementAttr { E2m1, E2m3, E3m2, E4m3, E5m2, S4, U4, S8, U8 } +pub enum SparseMmaElementAttr { F16, Bf16, Tf32, E2m1, E2m3, E3m2, E4m3, E5m2, S4, U4, S8, U8 } #[pliron_attr(name = "nvvm.sparse_mma_layout", format, verifier = "succ")] #[derive(PartialEq, Eq, Clone, Debug, Hash)] @@ -800,7 +800,8 @@ pub enum SparseMmaMetadataAttr { Standard, Ordered } #[pliron_attr(name = "nvvm.sparse_mma_selector", format, verifier = "succ")] #[derive(PartialEq, Eq, Clone, Debug, Hash)] -pub enum SparseMmaSelectorAttr { ImmediateZeroOrOne, ImmediateZero } +#[allow(clippy::enum_variant_names)] +pub enum SparseMmaSelectorAttr { ImmediateZeroThroughThree, ImmediateZeroOrOne, ImmediateZero } #[pliron_op( name = "nvvm.sparse_mma", diff --git a/crates/cuda-intrinsics-gen/src/render/families/mma.rs b/crates/cuda-intrinsics-gen/src/render/families/mma.rs index 42aebc76c0..f2de275c66 100644 --- a/crates/cuda-intrinsics-gen/src/render/families/mma.rs +++ b/crates/cuda-intrinsics-gen/src/render/families/mma.rs @@ -316,7 +316,9 @@ pub(in crate::render) fn sparse_mma_fragment_counts( record: &CatalogIntrinsic, ) -> (usize, usize, usize, usize) { match record.sparse_mma.as_ref().unwrap().adapter { + SparseMmaAdapter::C2U32A2U32B2U32MetadataU32SelectorU32ToD2U32 => (2, 2, 2, 2), SparseMmaAdapter::C2U32A4U32B4U32MetadataU32SelectorU32ToD2U32 => (2, 4, 4, 2), + SparseMmaAdapter::C4F32A2U32B2U32MetadataU32SelectorU32ToD4F32 => (4, 2, 2, 4), SparseMmaAdapter::C4F32A4U32B4U32MetadataU32SelectorU32ToD4F32 | SparseMmaAdapter::C4I32A4U32B4U32MetadataU32SelectorU32ToD4I32 => (4, 4, 4, 4), SparseMmaAdapter::C4I32A2U32B2U32MetadataU32SelectorU32ToD4I32 => (4, 2, 2, 4), @@ -325,6 +327,7 @@ pub(in crate::render) fn sparse_mma_fragment_counts( pub(in crate::render) fn sparse_mma_selector_values(record: &CatalogIntrinsic) -> &'static [u32] { match record.sparse_mma.as_ref().unwrap().selector { + SparseMmaSelector::ImmediateZeroThroughThree => &[0, 1, 2, 3], SparseMmaSelector::ImmediateZeroOrOne => &[0, 1], SparseMmaSelector::ImmediateZero => &[0], } @@ -334,6 +337,9 @@ pub(in crate::render) fn sparse_mma_selector_description( record: &CatalogIntrinsic, ) -> &'static str { match record.sparse_mma.as_ref().unwrap().selector { + SparseMmaSelector::ImmediateZeroThroughThree => { + "the compile-time constant `0`, `1`, `2`, or `3`" + } SparseMmaSelector::ImmediateZeroOrOne => "the compile-time constant `0` or `1`", SparseMmaSelector::ImmediateZero => "the compile-time constant `0`", } @@ -341,6 +347,9 @@ pub(in crate::render) fn sparse_mma_selector_description( pub(in crate::render) fn sparse_mma_selector_error(record: &CatalogIntrinsic) -> &'static str { match record.sparse_mma.as_ref().unwrap().selector { + SparseMmaSelector::ImmediateZeroThroughThree => { + "sparse MMA selector must be the compile-time constant 0, 1, 2, or 3" + } SparseMmaSelector::ImmediateZeroOrOne => { "sparse MMA selector must be the compile-time constant 0 or 1" } @@ -352,19 +361,30 @@ pub(in crate::render) fn sparse_mma_selector_error(record: &CatalogIntrinsic) -> pub(in crate::render) const SPARSE_MMA_STANDARD_METADATA_RULE: &str = "Every 4-bit metadata group must encode two distinct 2-bit indices; `0x0`, `0x5`, `0xa`, and `0xf` are undefined behavior."; pub(in crate::render) const SPARSE_MMA_ORDERED_METADATA_RULE: &str = "Every 4-bit metadata group must be `0x4`, `0x8`, `0x9`, `0xc`, `0xd`, or `0xe`; any other value is undefined behavior."; +pub(in crate::render) const SPARSE_MMA_ORDERED_TF32_METADATA_RULE: &str = + "Every 4-bit metadata group must be `0x4` or `0xe`; any other value is undefined behavior."; pub(in crate::render) fn sparse_mma_metadata_rule(mma: &SparseMma) -> &'static str { - match mma.metadata { - SparseMmaMetadata::Standard => SPARSE_MMA_STANDARD_METADATA_RULE, - SparseMmaMetadata::Ordered => SPARSE_MMA_ORDERED_METADATA_RULE, + match (mma.metadata, mma.a_element) { + (SparseMmaMetadata::Standard, _) => SPARSE_MMA_STANDARD_METADATA_RULE, + (SparseMmaMetadata::Ordered, SparseMmaElement::Tf32) => { + SPARSE_MMA_ORDERED_TF32_METADATA_RULE + } + (SparseMmaMetadata::Ordered, _) => SPARSE_MMA_ORDERED_METADATA_RULE, } } pub(in crate::render) fn sparse_mma_import_adapter(record: &CatalogIntrinsic) -> &'static str { match record.sparse_mma.as_ref().unwrap().adapter { + SparseMmaAdapter::C2U32A2U32B2U32MetadataU32SelectorU32ToD2U32 => { + "GeneratedMmaImportAdapter::C2U32A2U32B2U32ToD2U32" + } SparseMmaAdapter::C2U32A4U32B4U32MetadataU32SelectorU32ToD2U32 => { "GeneratedMmaImportAdapter::C2U32A4U32B4U32ToD2U32" } + SparseMmaAdapter::C4F32A2U32B2U32MetadataU32SelectorU32ToD4F32 => { + "GeneratedMmaImportAdapter::C4F32A2U32B2U32ToD4F32" + } SparseMmaAdapter::C4F32A4U32B4U32MetadataU32SelectorU32ToD4F32 => { "GeneratedMmaImportAdapter::C4F32A4U32B4U32ToD4F32" } @@ -392,6 +412,8 @@ pub(in crate::render) fn sparse_mma_attr_variants( ) { let mma = record.sparse_mma.as_ref().expect("sparse-MMA record"); let shape = match mma.shape { + SparseMmaShape::M16n8k8 => "SparseMmaShapeAttr::M16n8k8", + SparseMmaShape::M16n8k16 => "SparseMmaShapeAttr::M16n8k16", SparseMmaShape::M16n8k32 => "SparseMmaShapeAttr::M16n8k32", SparseMmaShape::M16n8k64 => "SparseMmaShapeAttr::M16n8k64", SparseMmaShape::M16n8k128 => "SparseMmaShapeAttr::M16n8k128", @@ -402,6 +424,9 @@ pub(in crate::render) fn sparse_mma_attr_variants( SparseMmaAccumulator::S32 => "SparseMmaAccumulatorAttr::S32", }; let element = |element| match element { + SparseMmaElement::F16 => "SparseMmaElementAttr::F16", + SparseMmaElement::Bf16 => "SparseMmaElementAttr::Bf16", + SparseMmaElement::Tf32 => "SparseMmaElementAttr::Tf32", SparseMmaElement::E2m1 => "SparseMmaElementAttr::E2m1", SparseMmaElement::E2m3 => "SparseMmaElementAttr::E2m3", SparseMmaElement::E3m2 => "SparseMmaElementAttr::E3m2", @@ -426,6 +451,9 @@ pub(in crate::render) fn sparse_mma_attr_variants( SparseMmaMetadata::Ordered => "SparseMmaMetadataAttr::Ordered", }; let selector = match mma.selector { + SparseMmaSelector::ImmediateZeroThroughThree => { + "SparseMmaSelectorAttr::ImmediateZeroThroughThree" + } SparseMmaSelector::ImmediateZeroOrOne => "SparseMmaSelectorAttr::ImmediateZeroOrOne", SparseMmaSelector::ImmediateZero => "SparseMmaSelectorAttr::ImmediateZero", }; diff --git a/crates/cuda-intrinsics-gen/src/render/importer.rs b/crates/cuda-intrinsics-gen/src/render/importer.rs index be90606a42..1fcc06c9c7 100644 --- a/crates/cuda-intrinsics-gen/src/render/importer.rs +++ b/crates/cuda-intrinsics-gen/src/render/importer.rs @@ -2623,9 +2623,11 @@ pub(super) fn import_generated_tcgen05_store_operands( #[derive(Clone, Copy)] pub(super) enum GeneratedMmaImportAdapter { C2U32A2U32B1U32ToD2U32, + C2U32A2U32B2U32ToD2U32, C2U32A4U32B2U32ToD2U32, C2U32A4U32B4U32ToD2U32, C4F32A2U32B1U32ToD4F32, + C4F32A2U32B2U32ToD4F32, C4F32A4U32B2U32ToD4F32, C4F32A4U32B4U32ToD4F32, C2F64A1F64B1F64ToD2F64, @@ -2702,12 +2704,16 @@ pub(super) fn import_generated_mma_operands( match adapter { GeneratedMmaImportAdapter::C2U32A2U32B1U32ToD2U32 => (u32_ty, 2, u32_ty, 2, true, u32_ty, 1, false, u32_ty, 2), + GeneratedMmaImportAdapter::C2U32A2U32B2U32ToD2U32 => + (u32_ty, 2, u32_ty, 2, true, u32_ty, 2, true, u32_ty, 2), GeneratedMmaImportAdapter::C2U32A4U32B2U32ToD2U32 => (u32_ty, 2, u32_ty, 4, true, u32_ty, 2, true, u32_ty, 2), GeneratedMmaImportAdapter::C2U32A4U32B4U32ToD2U32 => (u32_ty, 2, u32_ty, 4, true, u32_ty, 4, true, u32_ty, 2), GeneratedMmaImportAdapter::C4F32A2U32B1U32ToD4F32 => (f32_ty, 4, u32_ty, 2, true, u32_ty, 1, false, f32_ty, 4), + GeneratedMmaImportAdapter::C4F32A2U32B2U32ToD4F32 => + (f32_ty, 4, u32_ty, 2, true, u32_ty, 2, true, f32_ty, 4), GeneratedMmaImportAdapter::C4F32A4U32B2U32ToD4F32 => (f32_ty, 4, u32_ty, 4, true, u32_ty, 2, true, f32_ty, 4), GeneratedMmaImportAdapter::C4F32A4U32B4U32ToD4F32 => diff --git a/crates/cuda-intrinsics-gen/src/render/tests/mma.rs b/crates/cuda-intrinsics-gen/src/render/tests/mma.rs index d2704a6a72..7e96e179c9 100644 --- a/crates/cuda-intrinsics-gen/src/render/tests/mma.rs +++ b/crates/cuda-intrinsics-gen/src/render/tests/mma.rs @@ -13,9 +13,10 @@ use crate::render::collector_targets::generated_intrinsic_variant; use crate::render::common::intrinsic_marker; use crate::render::families::{ BLACKWELL_LDMATRIX_EFFECTIVE_FLOORS, SPARSE_MMA_ORDERED_METADATA_RULE, - SPARSE_MMA_STANDARD_METADATA_RULE, ldmatrix, register_mma_attr_variants, - register_mma_constraints, register_mma_template, register_mmas, sparse_mma_carriers, - sparse_mma_constraints, sparse_mma_fragment_counts, sparse_mma_selector_values, + SPARSE_MMA_ORDERED_TF32_METADATA_RULE, SPARSE_MMA_STANDARD_METADATA_RULE, ldmatrix, + register_mma_attr_variants, register_mma_constraints, register_mma_template, register_mmas, + sparse_mma_carriers, sparse_mma_constraints, sparse_mma_fragment_counts, + sparse_mma_metadata_rule, sparse_mma_selector_description, sparse_mma_selector_values, sparse_mma_template, sparse_mmas, }; use crate::util::read_json; @@ -344,7 +345,7 @@ fn register_mma_rendering_preserves_apis_order_convergence_and_variants() { let repo_root = Path::new(env!("CARGO_MANIFEST_DIR")).join("../.."); let catalog = crate::resolve::resolve(&repo_root).unwrap(); validate_renderable(&catalog).unwrap(); - assert_eq!(catalog.intrinsics.len(), 1017); + assert_eq!(catalog.intrinsics.len(), 1025); let records: Vec<_> = register_mmas(&catalog).collect(); assert_eq!(records.len(), 154); let generated_records = records @@ -808,7 +809,7 @@ fn sparse_mma_rendering_enforces_selector_and_keeps_family_distinct() { .iter() .filter(|record| record.sparse_mma.as_ref().unwrap().shape == SparseMmaShape::M16n8k128) .count(); - assert_eq!((records.len(), k32, k64, k128), (114, 16, 82, 16)); + assert_eq!((records.len(), k32, k64, k128), (122, 19, 82, 16)); let standard_k64 = records .iter() .copied() @@ -970,7 +971,7 @@ fn sparse_mma_rendering_enforces_selector_and_keeps_family_distinct() { } let compatibility = render_compat_sparse_mma(&catalog, "test-hash"); - assert_eq!(compatibility.matches("pub unsafe fn ").count(), 114); + assert_eq!(compatibility.matches("pub unsafe fn ").count(), 122); assert!( compatibility .contains("c: [i32; 4], a: [u32; 2], b: [u32; 2], metadata: u32, selector: u32") @@ -994,9 +995,13 @@ fn sparse_mma_rendering_enforces_selector_and_keeps_family_distinct() { assert!(dialect.contains("MmaCarrier::I32")); assert!(dialect.contains("MmaCarrier::U32")); assert!(dialect.contains("operands.len() != expected_operands")); - assert!(dialect.contains("SparseMmaShapeAttr { M16n8k32, M16n8k64, M16n8k128 }")); + assert!( + dialect.contains("SparseMmaShapeAttr { M16n8k8, M16n8k16, M16n8k32, M16n8k64, M16n8k128 }") + ); assert!(dialect.contains("SparseMmaAccumulatorAttr { F16, F32, S32 }")); - assert!(dialect.contains("SparseMmaSelectorAttr { ImmediateZeroOrOne, ImmediateZero }")); + assert!(dialect.contains( + "SparseMmaSelectorAttr { ImmediateZeroThroughThree, ImmediateZeroOrOne, ImmediateZero }" + )); assert!(dialect.contains("SparseMmaElementAttr::E2m1")); assert!(dialect.contains("SparseMmaElementAttr::E2m3")); assert!(dialect.contains("SparseMmaElementAttr::E3m2")); @@ -1068,7 +1073,11 @@ fn sparse_mma_rendering_enforces_selector_and_keeps_family_distinct() { assert!(targets.contains("GeneratedHardwareAlternative::ExactArchitecture(120)")); assert_eq!(raw.matches(SPARSE_MMA_STANDARD_METADATA_RULE).count(), 32); - assert_eq!(raw.matches(SPARSE_MMA_ORDERED_METADATA_RULE).count(), 82); + assert_eq!(raw.matches(SPARSE_MMA_ORDERED_METADATA_RULE).count(), 88); + assert_eq!( + raw.matches(SPARSE_MMA_ORDERED_TF32_METADATA_RULE).count(), + 2 + ); assert_eq!( compatibility .matches(SPARSE_MMA_STANDARD_METADATA_RULE) @@ -1079,7 +1088,13 @@ fn sparse_mma_rendering_enforces_selector_and_keeps_family_distinct() { compatibility .matches(SPARSE_MMA_ORDERED_METADATA_RULE) .count(), - 82 + 88 + ); + assert_eq!( + compatibility + .matches(SPARSE_MMA_ORDERED_TF32_METADATA_RULE) + .count(), + 2 ); assert!( lowering.contains("mma.sp::ordered_metadata.sync.aligned.m16n8k32.row.col.s32.s8.s8.s32") @@ -1135,7 +1150,37 @@ fn sparse_mma_rendering_enforces_selector_and_keeps_family_distinct() { ); assert_eq!( reference.matches(SPARSE_MMA_ORDERED_METADATA_RULE).count(), - 82 + 88 + ); + assert_eq!( + reference + .matches(SPARSE_MMA_ORDERED_TF32_METADATA_RULE) + .count(), + 2 + ); + let tf32_k8 = records + .iter() + .find(|record| record.id == "mma_sp_ordered_metadata_m16n8k8_f32_tf32") + .unwrap(); + let tf32_k16 = records + .iter() + .find(|record| record.id == "mma_sp_ordered_metadata_m16n8k16_f32_tf32") + .unwrap(); + assert_eq!( + sparse_mma_metadata_rule(tf32_k8.sparse_mma.as_ref().unwrap()), + SPARSE_MMA_ORDERED_TF32_METADATA_RULE + ); + assert_eq!( + sparse_mma_selector_description(tf32_k8), + "the compile-time constant `0`, `1`, `2`, or `3`" + ); + assert_eq!( + sparse_mma_metadata_rule(tf32_k16.sparse_mma.as_ref().unwrap()), + SPARSE_MMA_ORDERED_TF32_METADATA_RULE + ); + assert_eq!( + sparse_mma_selector_description(tf32_k16), + "the compile-time constant `0` or `1`" ); let sparse_reference = reference .split("## Sparse-MMA contracts") @@ -1147,7 +1192,11 @@ fn sparse_mma_rendering_enforces_selector_and_keeps_family_distinct() { assert!(sparse_reference.contains("Overflow mode is not applicable.")); assert!(!sparse_reference.contains("Integer overflow is not applicable")); for record in &records { - assert!(reference.contains(&format!("- `{}`: runtime `unexecuted`", record.id))); + let runtime = match record.sparse_mma.as_ref().unwrap().runtime_validation { + RuntimeValidation::Unexecuted => "unexecuted", + RuntimeValidation::Executed => "executed", + }; + assert!(reference.contains(&format!("- `{}`: runtime `{runtime}`", record.id))); } let outputs = all_outputs(&catalog, "{}\n".into(), "test-hash").unwrap(); diff --git a/crates/cuda-intrinsics-gen/src/resolve/families/mma/sparse.rs b/crates/cuda-intrinsics-gen/src/resolve/families/mma/sparse.rs index 4749642eb8..f7247af07f 100644 --- a/crates/cuda-intrinsics-gen/src/resolve/families/mma/sparse.rs +++ b/crates/cuda-intrinsics-gen/src/resolve/families/mma/sparse.rs @@ -8,8 +8,8 @@ use crate::model::{ OverlayIntrinsic, RuntimeValidation, SparseMma, SparseMmaAccumulator, SparseMmaAdapter, SparseMmaCompatibilitySource, SparseMmaElement, SparseMmaF8F6F4Admission, SparseMmaF8F6F4F16Admission, SparseMmaIntegerAdmission, SparseMmaLayout, SparseMmaLlvmAdapter, - SparseMmaMetadata, SparseMmaOverflow, SparseMmaParticipation, SparseMmaSelector, - SparseMmaShape, + SparseMmaMetadata, SparseMmaOrderedAmpereFloatAdmission, SparseMmaOrderedAmpereFloatVariant, + SparseMmaOverflow, SparseMmaParticipation, SparseMmaSelector, SparseMmaShape, }; use crate::ptx::{InstructionPattern, OperandPattern}; use anyhow::{Context, Result, ensure}; @@ -46,6 +46,7 @@ impl SparseMmaCarrierRecipe { fn selector_upper_exclusive(self) -> u8 { match self.selector { + SparseMmaSelector::ImmediateZeroThroughThree => 4, SparseMmaSelector::ImmediateZeroOrOne => 2, SparseMmaSelector::ImmediateZero => 1, } @@ -87,7 +88,20 @@ impl SparseMmaCarrierRecipe { SparseMmaAccumulator::F32 => "f32", SparseMmaAccumulator::S32 => "i32", }; - std::iter::repeat_n("i32".to_owned(), self.a_registers + self.b_registers) + // Ampere f16/bf16 forms carry their multiplicands as <2 x half> + // vectors in LLVM; every other family carries packed i32. + let multiplicand = if matches!( + self.llvm_adapter, + SparseMmaLlvmAdapter::A2V2F16B2V2F16C2V2F16MetadataI32SelectorI32ToD2V2F16 + | SparseMmaLlvmAdapter::A4V2F16B4V2F16C2V2F16MetadataI32SelectorI32ToD2V2F16 + | SparseMmaLlvmAdapter::A2V2F16B2V2F16C4F32MetadataI32SelectorI32ToD4F32 + | SparseMmaLlvmAdapter::A4V2F16B4V2F16C4F32MetadataI32SelectorI32ToD4F32 + ) { + "v2f16" + } else { + "i32" + }; + std::iter::repeat_n(multiplicand.to_owned(), self.a_registers + self.b_registers) .chain(std::iter::repeat_n( accumulator.to_owned(), self.accumulator_registers(), @@ -223,6 +237,63 @@ pub(in crate::resolve) fn sparse_mma_f8f6f4_f16_carrier_recipe( }) } +fn sparse_mma_ampere_float_carrier_recipe(mma: &SparseMma) -> Option { + use SparseMmaAccumulator::{F16 as AccF16, F32 as AccF32}; + use SparseMmaElement::{Bf16, F16, Tf32}; + use SparseMmaShape::{M16n8k8, M16n8k16, M16n8k32}; + + // Register width decides the selector domain (PTX 9.7.15.6.1): + // 2-reg forms (k8 tf32, k16 f16/bf16) -> one thread per quad, selector 0-3 + // 4-reg forms (k16 tf32, k32 f16/bf16) -> thread pair, selector 0-1 + let (a_registers, b_registers, selector) = match (mma.shape, (mma.a_element, mma.b_element)) { + (M16n8k8, (Tf32, Tf32)) => (2, 2, SparseMmaSelector::ImmediateZeroThroughThree), + (M16n8k16, (Tf32, Tf32)) => (4, 4, SparseMmaSelector::ImmediateZeroOrOne), + (M16n8k16, (Bf16, Bf16) | (F16, F16)) => { + (2, 2, SparseMmaSelector::ImmediateZeroThroughThree) + } + (M16n8k32, (Bf16, Bf16) | (F16, F16)) => (4, 4, SparseMmaSelector::ImmediateZeroOrOne), + _ => return None, + }; + let (adapter, llvm_adapter) = match (mma.accumulator, mma.a_element, a_registers) { + (AccF16, F16, 2) => ( + SparseMmaAdapter::C2U32A2U32B2U32MetadataU32SelectorU32ToD2U32, + SparseMmaLlvmAdapter::A2V2F16B2V2F16C2V2F16MetadataI32SelectorI32ToD2V2F16, + ), + (AccF16, F16, 4) => ( + SparseMmaAdapter::C2U32A4U32B4U32MetadataU32SelectorU32ToD2U32, + SparseMmaLlvmAdapter::A4V2F16B4V2F16C2V2F16MetadataI32SelectorI32ToD2V2F16, + ), + (AccF32, F16, 2) => ( + SparseMmaAdapter::C4F32A2U32B2U32MetadataU32SelectorU32ToD4F32, + SparseMmaLlvmAdapter::A2V2F16B2V2F16C4F32MetadataI32SelectorI32ToD4F32, + ), + (AccF32, F16, 4) => ( + SparseMmaAdapter::C4F32A4U32B4U32MetadataU32SelectorU32ToD4F32, + SparseMmaLlvmAdapter::A4V2F16B4V2F16C4F32MetadataI32SelectorI32ToD4F32, + ), + (AccF32, _, 2) => ( + SparseMmaAdapter::C4F32A2U32B2U32MetadataU32SelectorU32ToD4F32, + SparseMmaLlvmAdapter::A2I32B2I32C4F32MetadataI32SelectorI32ToD4F32, + ), + (AccF32, _, 4) => ( + SparseMmaAdapter::C4F32A4U32B4U32MetadataU32SelectorU32ToD4F32, + SparseMmaLlvmAdapter::A4I32B4I32C4F32MetadataI32SelectorI32ToD4F32, + ), + _ => return None, + }; + if mma.accumulator == AccF16 && mma.a_element != F16 { + return None; + } + Some(SparseMmaCarrierRecipe { + adapter, + llvm_adapter, + accumulator: mma.accumulator, + selector, + a_registers, + b_registers, + }) +} + pub(in crate::resolve) struct SparseMmaIdentity { pub(in crate::resolve) id: String, pub(in crate::resolve) operation_key: String, @@ -238,6 +309,8 @@ pub(in crate::resolve) struct SparseMmaRecipe { pub(in crate::resolve) fn sparse_mma_shape_name(shape: SparseMmaShape) -> &'static str { match shape { + SparseMmaShape::M16n8k8 => "m16n8k8", + SparseMmaShape::M16n8k16 => "m16n8k16", SparseMmaShape::M16n8k32 => "m16n8k32", SparseMmaShape::M16n8k64 => "m16n8k64", SparseMmaShape::M16n8k128 => "m16n8k128", @@ -246,6 +319,9 @@ pub(in crate::resolve) fn sparse_mma_shape_name(shape: SparseMmaShape) -> &'stat pub(in crate::resolve) fn sparse_mma_element_name(element: SparseMmaElement) -> &'static str { match element { + SparseMmaElement::F16 => "f16", + SparseMmaElement::Bf16 => "bf16", + SparseMmaElement::Tf32 => "tf32", SparseMmaElement::E2m1 => "e2m1", SparseMmaElement::E2m3 => "e2m3", SparseMmaElement::E3m2 => "e3m2", @@ -262,10 +338,20 @@ pub(in crate::resolve) fn sparse_mma_identity(mma: &SparseMma) -> SparseMmaIdent let shape = sparse_mma_shape_name(mma.shape); let a_element = sparse_mma_element_name(mma.a_element); let b_element = sparse_mma_element_name(mma.b_element); - if matches!( - mma.accumulator, - SparseMmaAccumulator::F16 | SparseMmaAccumulator::F32 - ) { + let f8f6f4 = matches!( + mma.a_element, + SparseMmaElement::E2m1 + | SparseMmaElement::E2m3 + | SparseMmaElement::E3m2 + | SparseMmaElement::E4m3 + | SparseMmaElement::E5m2 + ); + if f8f6f4 + && matches!( + mma.accumulator, + SparseMmaAccumulator::F16 | SparseMmaAccumulator::F32 + ) + { let scalar = match mma.accumulator { SparseMmaAccumulator::F16 => "f16", SparseMmaAccumulator::F32 => "f32", @@ -299,6 +385,48 @@ pub(in crate::resolve) fn sparse_mma_identity(mma: &SparseMma) -> SparseMmaIdent ], }; } + if matches!( + mma.a_element, + SparseMmaElement::F16 | SparseMmaElement::Bf16 | SparseMmaElement::Tf32 + ) { + let accumulator = match mma.accumulator { + SparseMmaAccumulator::F16 => "f16", + SparseMmaAccumulator::F32 => "f32", + SparseMmaAccumulator::S32 => unreachable!("Ampere float sparse MMA is not integer"), + }; + // LLVM's symbol tail differs per format family: + // f16 -> . pair (f16.f16 / f32.f32); bf16/tf32 -> bare element + let llvm_suffix = match (mma.accumulator, mma.a_element) { + (SparseMmaAccumulator::F16, SparseMmaElement::F16) => "f16.f16", + (SparseMmaAccumulator::F32, SparseMmaElement::F16) => "f32.f32", + (SparseMmaAccumulator::F32, SparseMmaElement::Bf16) => "bf16", + (SparseMmaAccumulator::F32, SparseMmaElement::Tf32) => "tf32", + _ => unreachable!("closed Ampere float recipe rejects this combination"), + }; + return SparseMmaIdentity { + id: format!("mma_sp_ordered_metadata_{shape}_{accumulator}_{a_element}"), + operation_key: format!( + "matrix.mma.sp.{shape}.row.col.{accumulator}.{a_element}.{b_element}.{accumulator}.not_applicable.ordered_metadata" + ), + source_record: format!( + "int_nvvm_mma_sp_ordered_metadata_{shape}_row_col_{}", + llvm_suffix.replace('.', "_") + ), + llvm_symbol: format!("llvm.nvvm.mma.sp.ordered.metadata.{shape}.row.col.{llvm_suffix}"), + ptx_modifiers: vec![ + "sp::ordered_metadata", + "sync", + "aligned", + shape, + "row", + "col", + accumulator, + a_element, + b_element, + accumulator, + ], + }; + } let compact_elements = if mma.a_element == mma.b_element { a_element.to_owned() } else { @@ -377,7 +505,13 @@ pub(in crate::resolve) fn sparse_mma_identity(mma: &SparseMma) -> SparseMmaIdent } pub(in crate::resolve) fn sparse_mma_recipe(mma: &SparseMma) -> Option { - let carrier = if mma.accumulator == SparseMmaAccumulator::F16 { + let ampere_float = matches!( + mma.a_element, + SparseMmaElement::F16 | SparseMmaElement::Bf16 | SparseMmaElement::Tf32 + ); + let carrier = if ampere_float { + sparse_mma_ampere_float_carrier_recipe(mma)? + } else if mma.accumulator == SparseMmaAccumulator::F16 { sparse_mma_f8f6f4_f16_carrier_recipe(mma.shape, mma.a_element, mma.b_element)? } else { sparse_mma_carrier_recipe(mma.shape, mma.a_element, mma.b_element)? @@ -417,6 +551,12 @@ pub(in crate::resolve) fn sparse_mma_recipe(mma: &SparseMma) -> Option &'static str { + if matches!( + mma.a_element, + SparseMmaElement::F16 | SparseMmaElement::Bf16 | SparseMmaElement::Tf32 + ) { + return "8.5"; + } if matches!( mma.accumulator, SparseMmaAccumulator::F16 | SparseMmaAccumulator::F32 @@ -432,6 +572,12 @@ pub(in crate::resolve) fn sparse_mma_minimum_ptx(mma: &SparseMma) -> &'static st pub(in crate::resolve) fn sparse_mma_hardware( mma: &SparseMma, ) -> (&'static str, Option<&'static str>) { + if matches!( + mma.a_element, + SparseMmaElement::F16 | SparseMmaElement::Bf16 | SparseMmaElement::Tf32 + ) { + return ("all", Some("sm_80")); + } match mma.accumulator { SparseMmaAccumulator::F16 | SparseMmaAccumulator::F32 => (SPARSE_MMA_F8F6F4_TARGETS, None), SparseMmaAccumulator::S32 => ("all", Some("sm_80")), @@ -442,6 +588,115 @@ pub(in crate::resolve) fn sparse_mma_ptx_section(_: SparseMmaMetadata) -> &'stat "9.7.15.6.3 Multiply-and-Accumulate Instruction: mma.sp" } +// The eight reviewed forms in ledger order (i1017..i1024). The admission +// must list exactly these, in this order, so ABI identity stays stable. +pub(in crate::resolve) const SPARSE_MMA_ORDERED_AMPERE_FLOAT_VARIANTS: + [SparseMmaOrderedAmpereFloatVariant; 8] = [ + SparseMmaOrderedAmpereFloatVariant { + shape: SparseMmaShape::M16n8k8, + accumulator: SparseMmaAccumulator::F32, + element: SparseMmaElement::Tf32, + }, + SparseMmaOrderedAmpereFloatVariant { + shape: SparseMmaShape::M16n8k16, + accumulator: SparseMmaAccumulator::F32, + element: SparseMmaElement::Tf32, + }, + SparseMmaOrderedAmpereFloatVariant { + shape: SparseMmaShape::M16n8k16, + accumulator: SparseMmaAccumulator::F32, + element: SparseMmaElement::Bf16, + }, + SparseMmaOrderedAmpereFloatVariant { + shape: SparseMmaShape::M16n8k16, + accumulator: SparseMmaAccumulator::F16, + element: SparseMmaElement::F16, + }, + SparseMmaOrderedAmpereFloatVariant { + shape: SparseMmaShape::M16n8k16, + accumulator: SparseMmaAccumulator::F32, + element: SparseMmaElement::F16, + }, + SparseMmaOrderedAmpereFloatVariant { + shape: SparseMmaShape::M16n8k32, + accumulator: SparseMmaAccumulator::F32, + element: SparseMmaElement::Bf16, + }, + SparseMmaOrderedAmpereFloatVariant { + shape: SparseMmaShape::M16n8k32, + accumulator: SparseMmaAccumulator::F16, + element: SparseMmaElement::F16, + }, + SparseMmaOrderedAmpereFloatVariant { + shape: SparseMmaShape::M16n8k32, + accumulator: SparseMmaAccumulator::F32, + element: SparseMmaElement::F16, + }, +]; + +pub(in crate::resolve) fn expand_sparse_mma_ordered_ampere_float_admission( + admission: &SparseMmaOrderedAmpereFloatAdmission, +) -> Result> { + ensure!( + !admission.llvm_evidence_profile.trim().is_empty() + && !admission.libnvvm_evidence_profile.trim().is_empty(), + "ordered Ampere floating sparse MMA admission requires both backend evidence profiles" + ); + ensure!( + admission.variants == SPARSE_MMA_ORDERED_AMPERE_FLOAT_VARIANTS, + "ordered Ampere floating sparse MMA admission must retain the eight reviewed variants in ABI order" + ); + + admission + .variants + .iter() + .map(|variant| { + let mut mma = SparseMma { + shape: variant.shape, + accumulator: variant.accumulator, + a_element: variant.element, + b_element: variant.element, + a_layout: SparseMmaLayout::Row, + b_layout: SparseMmaLayout::Col, + overflow: SparseMmaOverflow::NotApplicable, + metadata: SparseMmaMetadata::Ordered, + selector: SparseMmaSelector::ImmediateZero, + participation: + SparseMmaParticipation::AllWarpLanesSameInstructionAndQualifiersNoExitedLanes, + adapter: SparseMmaAdapter::C4F32A4U32B4U32MetadataU32SelectorU32ToD4F32, + llvm_adapter: SparseMmaLlvmAdapter::A4I32B4I32C4F32MetadataI32SelectorI32ToD4F32, + compatibility_source: SparseMmaCompatibilitySource::GeneratedStub, + runtime_validation: admission.runtime_validation, + }; + let carrier = sparse_mma_ampere_float_carrier_recipe(&mma).context( + "ordered Ampere floating sparse MMA admission uses an unsupported carrier", + )?; + mma.selector = carrier.selector; + mma.adapter = carrier.adapter; + mma.llvm_adapter = carrier.llvm_adapter; + let recipe = sparse_mma_recipe(&mma).context( + "ordered Ampere floating sparse MMA admission requests a variant outside the closed recipe set", + )?; + Ok(sparse_mma_overlay_record( + String::new(), + mma, + recipe, + &admission.llvm_evidence_profile, + &admission.libnvvm_evidence_profile, + format!( + "Multiplies warp-distributed ordered sparse {} A and B fragments and adds a {} accumulator.", + sparse_mma_element_name(variant.element), + match variant.accumulator { + SparseMmaAccumulator::F16 => "packed f16", + SparseMmaAccumulator::F32 => "f32", + SparseMmaAccumulator::S32 => unreachable!(), + }, + ), + )) + }) + .collect() +} + pub(in crate::resolve) fn expand_sparse_mma_integer_admission( admission: &SparseMmaIntegerAdmission, ) -> Result> { @@ -879,10 +1134,23 @@ pub(in crate::resolve) fn validate_sparse_mma_policy( declaration.classes == ["SDPatternOperator", "Intrinsic", "NVVM_MMA_SP"] && declaration.properties == recipe.carrier.imported_properties() && declaration.selections.len() == 1 - && (!matches!( + && (if matches!( + mma.a_element, + SparseMmaElement::F16 | SparseMmaElement::Bf16 | SparseMmaElement::Tf32 + ) { + declaration.selections[0].predicates + == [ + "Subtarget->getSmVersion() >= 80", + "Subtarget->getPTXVersion() >= 85", + ] + } else if matches!( mma.accumulator, SparseMmaAccumulator::F16 | SparseMmaAccumulator::F32 - ) || declaration.selections[0].predicates == ["Subtarget->hasMMABlockScale()"]) + ) { + declaration.selections[0].predicates == ["Subtarget->hasMMABlockScale()"] + } else { + true + }) && selection_matches_policy(policy, &declaration.selections[0])?, "{} imported sparse MMA declaration changed its class, immediate range, properties, or exact selection contract", policy.id diff --git a/crates/cuda-intrinsics-gen/src/resolve/overlay.rs b/crates/cuda-intrinsics-gen/src/resolve/overlay.rs index 88d9f637c7..f077a848fb 100644 --- a/crates/cuda-intrinsics-gen/src/resolve/overlay.rs +++ b/crates/cuda-intrinsics-gen/src/resolve/overlay.rs @@ -19,7 +19,7 @@ use super::guards::*; pub(super) const OVERLAY_SCHEMA: u32 = 44; pub(super) const MINIMUM_OVERLAY_SHARD_SCHEMA: u32 = 26; -pub(super) const OVERLAY_SHARD_SCHEMA: u32 = 62; +pub(super) const OVERLAY_SHARD_SCHEMA: u32 = 63; pub(super) const REGISTER_MMA_F8F6F4_SHARD_SCHEMA: u32 = 46; pub(super) const REGISTER_MMA_F8F6F4_F16_SHARD_SCHEMA: u32 = 47; pub(super) const REGISTER_MMA_MXF8F6F4_SHARD_SCHEMA: u32 = 60; @@ -27,6 +27,7 @@ pub(super) const REGISTER_MMA_FP8_SHARD_SCHEMA: u32 = 48; pub(super) const REGISTER_MMA_AMPERE_FLOAT_SHARD_SCHEMA: u32 = 49; pub(super) const SPARSE_MMA_F8F6F4_SHARD_SCHEMA: u32 = 27; pub(super) const SPARSE_MMA_F8F6F4_F16_SHARD_SCHEMA: u32 = 50; +pub(super) const SPARSE_MMA_AMPERE_FLOAT_SHARD_SCHEMA: u32 = 63; pub(super) const PRMT_SHARD_SCHEMA: u32 = 28; pub(super) const PACKED_CONVERSION_FP8_SHARD_SCHEMA: u32 = 29; pub(super) const PACKED_CONVERSION_FP8_F16X2_SHARD_SCHEMA: u32 = 59; @@ -108,6 +109,7 @@ pub(super) fn read_overlay( let sparse_mma_admission = shard.sparse_mma_integer.take(); let sparse_mma_f8f6f4_admission = shard.sparse_mma_f8f6f4_f32.take(); let sparse_mma_f8f6f4_f16_admission = shard.sparse_mma_f8f6f4_f16.take(); + let sparse_mma_ampere_float_admission = shard.sparse_mma_ordered_ampere_float.take(); let prmt_admission = shard.prmt.take(); let packed_conversion_fp8_admission = shard.packed_conversion_fp8.take(); let packed_conversion_fp8_f16x2_admission = shard.packed_conversion_fp8_f16x2.take(); @@ -137,7 +139,8 @@ pub(super) fn read_overlay( + usize::from(ampere_float_mma_admission.is_some()) + usize::from(sparse_mma_admission.is_some()) + usize::from(sparse_mma_f8f6f4_admission.is_some()) - + usize::from(sparse_mma_f8f6f4_f16_admission.is_some()); + + usize::from(sparse_mma_f8f6f4_f16_admission.is_some()) + + usize::from(sparse_mma_ampere_float_admission.is_some()); ensure!( compact_mma_count <= 1, "overlay shard {} contains more than one compact MMA admission", @@ -220,6 +223,13 @@ pub(super) fn read_overlay( ); shard.intrinsics = expand_sparse_mma_f8f6f4_f16_admission(&admission)?; } + if let Some(admission) = sparse_mma_ampere_float_admission { + ensure!( + shard.family == "sparse_mma" && shard.intrinsics.is_empty(), + "compact ordered Ampere floating sparse MMA admission must be the only content of a sparse_mma shard" + ); + shard.intrinsics = expand_sparse_mma_ordered_ampere_float_admission(&admission)?; + } if let Some(admission) = prmt_admission { ensure!( shard.family == "prmt" && shard.intrinsics.is_empty(), @@ -407,6 +417,12 @@ pub(super) fn validate_overlay_shard_schema_with_max( "compact sparse f8f6f4 F16 MMA admission requires overlay shard schema {}", SPARSE_MMA_F8F6F4_F16_SHARD_SCHEMA ); + ensure!( + shard.sparse_mma_ordered_ampere_float.is_none() + || shard.schema >= SPARSE_MMA_AMPERE_FLOAT_SHARD_SCHEMA, + "compact ordered Ampere floating sparse MMA admission requires overlay shard schema {}", + SPARSE_MMA_AMPERE_FLOAT_SHARD_SCHEMA + ); ensure!( shard.register_mma_f8f6f4_f32.is_none() || shard.schema >= REGISTER_MMA_F8F6F4_SHARD_SCHEMA, "compact dense f8f6f4 MMA admission requires overlay shard schema {}", diff --git a/crates/cuda-intrinsics-gen/src/resolve/tests/misc_families.rs b/crates/cuda-intrinsics-gen/src/resolve/tests/misc_families.rs index e3a3884b7e..27e6ea7e5f 100644 --- a/crates/cuda-intrinsics-gen/src/resolve/tests/misc_families.rs +++ b/crates/cuda-intrinsics-gen/src/resolve/tests/misc_families.rs @@ -187,6 +187,7 @@ fn debug_control_compact_schema_is_reserved_for_aggregation() { sparse_mma_integer: None, sparse_mma_f8f6f4_f32: None, sparse_mma_f8f6f4_f16: None, + sparse_mma_ordered_ampere_float: None, prmt: None, packed_conversion_fp8: None, packed_conversion_fp8_f16x2: None, @@ -454,6 +455,7 @@ fn wgmma_control_compact_schema_is_reserved_for_aggregation() { sparse_mma_integer: None, sparse_mma_f8f6f4_f32: None, sparse_mma_f8f6f4_f16: None, + sparse_mma_ordered_ampere_float: None, prmt: None, packed_conversion_fp8: None, packed_conversion_fp8_f16x2: None, diff --git a/crates/cuda-intrinsics-gen/src/resolve/tests/mma.rs b/crates/cuda-intrinsics-gen/src/resolve/tests/mma.rs index ae75b96be1..6488932c93 100644 --- a/crates/cuda-intrinsics-gen/src/resolve/tests/mma.rs +++ b/crates/cuda-intrinsics-gen/src/resolve/tests/mma.rs @@ -284,6 +284,105 @@ fn compact_sparse_f8f6f4_f16_admission_is_closed_and_ordered() { assert!(expand_sparse_mma_f8f6f4_f16_admission(&executed).is_err()); } +#[test] +fn compact_sparse_ordered_ampere_float_admission_is_closed_and_ledger_bound() { + let repo_root = Path::new(env!("CARGO_MANIFEST_DIR")).join("../.."); + let path = repo_root.join("intrinsics/overlay/sparse_mma_ordered_ampere_float.toml"); + let bytes = fs::read(&path).unwrap(); + let shard: OverlayShardFile = toml::from_slice(&bytes).unwrap(); + let admission = shard.sparse_mma_ordered_ampere_float.unwrap(); + + // Executed runtime validation is admitted for this family (GPU evidence backs it). + assert_eq!(admission.runtime_validation, RuntimeValidation::Executed); + let records = expand_sparse_mma_ordered_ampere_float_admission(&admission).unwrap(); + assert_eq!(records.len(), 8); + assert!(records.iter().all(|record| record.abi_id.is_empty())); + assert!(records.iter().all(|record| { + record + .sparse_mma + .as_ref() + .is_some_and(|mma| mma.runtime_validation == RuntimeValidation::Executed) + })); + + let mut bound = overlay_file(records.clone()); + bind_pinned_abi_ids(&repo_root, &mut bound); + assert_eq!( + bound + .intrinsics + .iter() + .map(|record| record.abi_id.clone()) + .collect::>(), + (1018..=1025) + .map(|id| format!("i{id:04}")) + .collect::>() + ); + + // First form: m16n8k8 tf32 (2-reg carrier, selector 0-3). + let first = &records[0]; + assert_eq!(first.id, "mma_sp_ordered_metadata_m16n8k8_f32_tf32"); + assert_eq!( + first.source_record.as_deref(), + Some("int_nvvm_mma_sp_ordered_metadata_m16n8k8_row_col_tf32") + ); + assert_eq!( + first.llvm_symbol.as_deref(), + Some("llvm.nvvm.mma.sp.ordered.metadata.m16n8k8.row.col.tf32") + ); + assert_eq!( + first.rust_arguments, + ["[f32; 4]", "[u32; 2]", "[u32; 2]", "u32", "u32"] + ); + assert_eq!(first.rust_result, "[f32; 4]"); + assert_eq!( + first.llvm_arguments, + [ + "i32", "i32", "i32", "i32", "f32", "f32", "f32", "f32", "i32", "i32" + ] + ); + assert_eq!(first.minimum_ptx, "8.5"); + assert_eq!(first.minimum_sm.as_deref(), Some("sm_80")); + assert_eq!(first.targets, "all"); + let mma = first.sparse_mma.as_ref().unwrap(); + assert_eq!(mma.selector, SparseMmaSelector::ImmediateZeroThroughThree); + assert_eq!( + mma.adapter, + SparseMmaAdapter::C4F32A2U32B2U32MetadataU32SelectorU32ToD4F32 + ); + assert_eq!( + mma.llvm_adapter, + SparseMmaLlvmAdapter::A2I32B2I32C4F32MetadataI32SelectorI32ToD4F32 + ); + + // f16 forms carry <2 x half> multiplicands; k32 pairs drop to selector 0-1. + let k32_f16 = &records[6]; + assert_eq!(k32_f16.id, "mma_sp_ordered_metadata_m16n8k32_f16_f16"); + assert_eq!( + k32_f16.llvm_arguments, + [ + "v2f16", "v2f16", "v2f16", "v2f16", "v2f16", "v2f16", "v2f16", "v2f16", "v2f16", + "v2f16", "i32", "i32" + ] + ); + let k32_mma = k32_f16.sparse_mma.as_ref().unwrap(); + assert_eq!(k32_mma.selector, SparseMmaSelector::ImmediateZeroOrOne); + assert_eq!( + k32_mma.adapter, + SparseMmaAdapter::C2U32A4U32B4U32MetadataU32SelectorU32ToD2U32 + ); + + let mut reordered = admission.clone(); + reordered.variants.swap(0, 1); + assert!(expand_sparse_mma_ordered_ampere_float_admission(&reordered).is_err()); + + let mut missing = admission.clone(); + missing.variants.pop(); + assert!(expand_sparse_mma_ordered_ampere_float_admission(&missing).is_err()); + + let mut missing_evidence = admission; + missing_evidence.llvm_evidence_profile.clear(); + assert!(expand_sparse_mma_ordered_ampere_float_admission(&missing_evidence).is_err()); +} + #[test] fn sparse_f8f6f4_f16_candidate_floor_uses_the_resolved_policy() { let policy = expand_sparse_mma_f8f6f4_f16_admission(&test_sparse_mma_f8f6f4_f16_admission()) @@ -1458,7 +1557,7 @@ fn pinned_sparse_mma_records_close_shape_specific_selectors_and_ranges() { .iter() .filter(|record| record.family == "sparse_mma") .collect::>(); - assert_eq!(records.len(), 114); + assert_eq!(records.len(), 122); assert_eq!( records .iter() @@ -1466,6 +1565,7 @@ fn pinned_sparse_mma_records_close_shape_specific_selectors_and_ranges() { .collect::>(), (163..=251) .chain(525..=549) + .chain(1018..=1025) .map(|id| format!("i{id:04}")) .collect::>() ); @@ -1494,10 +1594,10 @@ fn pinned_sparse_mma_records_close_shape_specific_selectors_and_ranges() { assert!(derived_source_records.insert(identity.source_record.clone())); assert!(derived_llvm_symbols.insert(identity.llvm_symbol.clone())); } - assert_eq!(derived_ids.len(), 114); - assert_eq!(derived_operation_keys.len(), 114); - assert_eq!(derived_source_records.len(), 114); - assert_eq!(derived_llvm_symbols.len(), 114); + assert_eq!(derived_ids.len(), 122); + assert_eq!(derived_operation_keys.len(), 122); + assert_eq!(derived_source_records.len(), 122); + assert_eq!(derived_llvm_symbols.len(), 122); let integer_records = records .iter() @@ -1511,7 +1611,16 @@ fn pinned_sparse_mma_records_close_shape_specific_selectors_and_ranges() { .iter() .copied() .filter(|record| { - record.sparse_mma.as_ref().unwrap().accumulator == SparseMmaAccumulator::F32 + let mma = record.sparse_mma.as_ref().unwrap(); + mma.accumulator == SparseMmaAccumulator::F32 + && matches!( + mma.a_element, + SparseMmaElement::E2m1 + | SparseMmaElement::E2m3 + | SparseMmaElement::E3m2 + | SparseMmaElement::E4m3 + | SparseMmaElement::E5m2 + ) }) .collect::>(); assert_eq!(f32_records.len(), 25); @@ -1519,7 +1628,16 @@ fn pinned_sparse_mma_records_close_shape_specific_selectors_and_ranges() { .iter() .copied() .filter(|record| { - record.sparse_mma.as_ref().unwrap().accumulator == SparseMmaAccumulator::F16 + let mma = record.sparse_mma.as_ref().unwrap(); + mma.accumulator == SparseMmaAccumulator::F16 + && matches!( + mma.a_element, + SparseMmaElement::E2m1 + | SparseMmaElement::E2m3 + | SparseMmaElement::E3m2 + | SparseMmaElement::E4m3 + | SparseMmaElement::E5m2 + ) }) .collect::>(); assert_eq!(f16_records.len(), 25); @@ -1566,6 +1684,9 @@ fn pinned_sparse_mma_records_close_shape_specific_selectors_and_ranges() { let mut expected_variants = BTreeSet::new(); for shape in [SparseMmaShape::M16n8k32, SparseMmaShape::M16n8k64] { let metadata = match shape { + SparseMmaShape::M16n8k8 | SparseMmaShape::M16n8k16 => { + unreachable!("integer sparse-MMA test does not enumerate float shapes") + } SparseMmaShape::M16n8k32 => [ Some(SparseMmaMetadata::Standard), Some(SparseMmaMetadata::Ordered), diff --git a/crates/cuda-intrinsics-gen/src/resolve/tests/overlay_schema.rs b/crates/cuda-intrinsics-gen/src/resolve/tests/overlay_schema.rs index 5932eadf3b..1e31bde935 100644 --- a/crates/cuda-intrinsics-gen/src/resolve/tests/overlay_schema.rs +++ b/crates/cuda-intrinsics-gen/src/resolve/tests/overlay_schema.rs @@ -48,8 +48,8 @@ fn overlay_manifest_loads_sorted_family_shards() { let (overlay, hash) = read_overlay(&repo_root, &repo_root.join("intrinsics/overlay.toml")).unwrap(); assert_eq!(overlay.schema, OVERLAY_SCHEMA); - assert_eq!(overlay.shards.len(), 64); - assert_eq!(overlay.intrinsics.len(), 1017); + assert_eq!(overlay.shards.len(), 65); + assert_eq!(overlay.intrinsics.len(), 1025); assert_eq!( overlay .intrinsics @@ -144,7 +144,7 @@ fn overlay_manifest_loads_sorted_family_shards() { .iter() .filter(|record| record.family == "sparse_mma") .count(), - 114 + 122 ); assert_eq!( overlay @@ -264,6 +264,7 @@ fn overlay_shard_schema_range_is_composable_and_new_fields_fail_closed() { sparse_mma_integer: None, sparse_mma_f8f6f4_f32, sparse_mma_f8f6f4_f16: None, + sparse_mma_ordered_ampere_float: None, prmt, packed_conversion_fp8: None, packed_conversion_fp8_f16x2: None, @@ -353,6 +354,29 @@ fn overlay_shard_schema_range_is_composable_and_new_fields_fail_closed() { .contains("requires overlay shard schema 50") ); + let repo_root = Path::new(env!("CARGO_MANIFEST_DIR")).join("../.."); + let ampere_float_bytes = + std::fs::read(repo_root.join("intrinsics/overlay/sparse_mma_ordered_ampere_float.toml")) + .unwrap(); + let mut sparse_ampere_float: OverlayShardFile = toml::from_slice(&ere_float_bytes).unwrap(); + assert!( + sparse_ampere_float + .sparse_mma_ordered_ampere_float + .is_some() + ); + assert_eq!( + sparse_ampere_float.schema, + SPARSE_MMA_AMPERE_FLOAT_SHARD_SCHEMA + ); + validate_overlay_shard_schema(&sparse_ampere_float, path).unwrap(); + sparse_ampere_float.schema -= 1; + assert!( + validate_overlay_shard_schema(&sparse_ampere_float, path) + .unwrap_err() + .to_string() + .contains("requires overlay shard schema 63") + ); + let mut standard_fp8_mma = shard(REGISTER_MMA_FP8_SHARD_SCHEMA, None, None); standard_fp8_mma.family = "register_mma".into(); standard_fp8_mma.register_mma_fp8 = Some(test_register_mma_fp8_admission()); @@ -380,6 +404,7 @@ fn overlay_shard_schema_range_is_composable_and_new_fields_fail_closed() { sparse_mma_integer: None, sparse_mma_f8f6f4_f32: None, sparse_mma_f8f6f4_f16: None, + sparse_mma_ordered_ampere_float: None, prmt: None, packed_conversion_fp8: Some(test_fp8_conversion_admission()), packed_conversion_fp8_f16x2: None, @@ -424,6 +449,7 @@ fn overlay_shard_schema_range_is_composable_and_new_fields_fail_closed() { sparse_mma_integer: None, sparse_mma_f8f6f4_f32: None, sparse_mma_f8f6f4_f16: None, + sparse_mma_ordered_ampere_float: None, prmt: None, packed_conversion_fp8: None, packed_conversion_fp8_f16x2: None, @@ -469,6 +495,7 @@ fn overlay_shard_schema_range_is_composable_and_new_fields_fail_closed() { sparse_mma_integer: None, sparse_mma_f8f6f4_f32: None, sparse_mma_f8f6f4_f16: None, + sparse_mma_ordered_ampere_float: None, prmt: None, packed_conversion_fp8: None, packed_conversion_fp8_f16x2: None, diff --git a/crates/cuda-intrinsics-gen/src/resolve/tests/sreg_threadfence.rs b/crates/cuda-intrinsics-gen/src/resolve/tests/sreg_threadfence.rs index 083dc8992e..4b7395a66c 100644 --- a/crates/cuda-intrinsics-gen/src/resolve/tests/sreg_threadfence.rs +++ b/crates/cuda-intrinsics-gen/src/resolve/tests/sreg_threadfence.rs @@ -112,6 +112,7 @@ fn special_register_admission_is_closed_and_schema_gated() { sparse_mma_integer: None, sparse_mma_f8f6f4_f32: None, sparse_mma_f8f6f4_f16: None, + sparse_mma_ordered_ampere_float: None, prmt: None, packed_conversion_fp8: None, packed_conversion_fp8_f16x2: None, diff --git a/crates/cuda-intrinsics-gen/src/resolve/tests/tcgen05.rs b/crates/cuda-intrinsics-gen/src/resolve/tests/tcgen05.rs index 811c6abfea..94b14d1877 100644 --- a/crates/cuda-intrinsics-gen/src/resolve/tests/tcgen05.rs +++ b/crates/cuda-intrinsics-gen/src/resolve/tests/tcgen05.rs @@ -1184,6 +1184,7 @@ fn tcgen05_compact_schema_is_reserved_for_aggregation() { sparse_mma_integer: None, sparse_mma_f8f6f4_f32: None, sparse_mma_f8f6f4_f16: None, + sparse_mma_ordered_ampere_float: None, prmt: None, packed_conversion_fp8: None, packed_conversion_fp8_f16x2: None, diff --git a/crates/cuda-intrinsics-gen/src/resolve/tests/tma_clc_cluster.rs b/crates/cuda-intrinsics-gen/src/resolve/tests/tma_clc_cluster.rs index d009b8c020..3ee6c335b2 100644 --- a/crates/cuda-intrinsics-gen/src/resolve/tests/tma_clc_cluster.rs +++ b/crates/cuda-intrinsics-gen/src/resolve/tests/tma_clc_cluster.rs @@ -112,6 +112,7 @@ fn clc_compact_schema_is_reserved_for_aggregation() { sparse_mma_integer: None, sparse_mma_f8f6f4_f32: None, sparse_mma_f8f6f4_f16: None, + sparse_mma_ordered_ampere_float: None, prmt: None, packed_conversion_fp8: None, packed_conversion_fp8_f16x2: None, @@ -343,6 +344,7 @@ fn tma_compact_schema_is_reserved_for_aggregation() { sparse_mma_integer: None, sparse_mma_f8f6f4_f32: None, sparse_mma_f8f6f4_f16: None, + sparse_mma_ordered_ampere_float: None, prmt: None, packed_conversion_fp8: None, packed_conversion_fp8_f16x2: None, @@ -418,6 +420,7 @@ fn cluster_memory_compact_schema_is_reserved_and_fail_closed() { sparse_mma_integer: None, sparse_mma_f8f6f4_f32: None, sparse_mma_f8f6f4_f16: None, + sparse_mma_ordered_ampere_float: None, prmt: None, packed_conversion_fp8: None, packed_conversion_fp8_f16x2: None, diff --git a/crates/cuda-intrinsics/src/generated/abi_v1.rs b/crates/cuda-intrinsics/src/generated/abi_v1.rs index 3e053363d2..8937c89e8a 100644 --- a/crates/cuda-intrinsics/src/generated/abi_v1.rs +++ b/crates/cuda-intrinsics/src/generated/abi_v1.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. //! Raw ABI functions recognized by cuda-oxide. @@ -9886,6 +9886,188 @@ pub unsafe fn i0209( ) } +/// Multiplies warp-distributed ordered sparse f16 A and B fragments and adds a packed f16 accumulator. +/// +/// Catalog ID: `mma_sp_ordered_metadata_m16n8k16_f16_f16`. Source: LLVM `llvm.nvvm.mma.sp.ordered.metadata.m16n8k16.row.col.f16.f16` from `int_nvvm_mma_sp_ordered_metadata_m16n8k16_row_col_f16_f16`; expects PTX `mma.sp::ordered_metadata.sync.aligned.m16n8k16.row.col.f16.f16.f16.f16 , , , , , ;`. +/// Available on `sm_80+` targets from PTX 8.5. +/// +/// # Safety +/// All 32 warp lanes must execute the same sparse MMA instruction with the same qualifiers, and no lane may have exited. +/// `_arg0`, `_arg1`, and `_arg2` hold this lane's 2-register C, 2-register A, and 2-register B fragments; `_arg3` holds its sparse metadata. +/// `_arg4` must be the compile-time constant `0`, `1`, `2`, or `3`. +/// The operation is register-only and is not a memory fence. +/// Every 4-bit metadata group must be `0x4`, `0x8`, `0x9`, `0xc`, `0xd`, or `0xe`; any other value is undefined behavior. +/// See the [PTX sparse MMA fragment layouts](https://docs.nvidia.com/cuda/parallel-thread-execution/#warp-level-matrix-instructions-mma-sp). +#[must_use] +#[inline(never)] +pub unsafe fn i1021( + _arg0: [u32; 2], + _arg1: [u32; 2], + _arg2: [u32; 2], + _arg3: u32, + _arg4: u32, +) -> [u32; 2] { + unreachable!( + "generated CUDA intrinsic `cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i1021` executed outside device compilation" + ) +} + +/// Multiplies warp-distributed ordered sparse bf16 A and B fragments and adds a f32 accumulator. +/// +/// Catalog ID: `mma_sp_ordered_metadata_m16n8k16_f32_bf16`. Source: LLVM `llvm.nvvm.mma.sp.ordered.metadata.m16n8k16.row.col.bf16` from `int_nvvm_mma_sp_ordered_metadata_m16n8k16_row_col_bf16`; expects PTX `mma.sp::ordered_metadata.sync.aligned.m16n8k16.row.col.f32.bf16.bf16.f32 , , , , , ;`. +/// Available on `sm_80+` targets from PTX 8.5. +/// +/// # Safety +/// All 32 warp lanes must execute the same sparse MMA instruction with the same qualifiers, and no lane may have exited. +/// `_arg0`, `_arg1`, and `_arg2` hold this lane's 4-register C, 2-register A, and 2-register B fragments; `_arg3` holds its sparse metadata. +/// `_arg4` must be the compile-time constant `0`, `1`, `2`, or `3`. +/// The operation is register-only and is not a memory fence. +/// Every 4-bit metadata group must be `0x4`, `0x8`, `0x9`, `0xc`, `0xd`, or `0xe`; any other value is undefined behavior. +/// See the [PTX sparse MMA fragment layouts](https://docs.nvidia.com/cuda/parallel-thread-execution/#warp-level-matrix-instructions-mma-sp). +#[must_use] +#[inline(never)] +pub unsafe fn i1020( + _arg0: [f32; 4], + _arg1: [u32; 2], + _arg2: [u32; 2], + _arg3: u32, + _arg4: u32, +) -> [f32; 4] { + unreachable!( + "generated CUDA intrinsic `cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i1020` executed outside device compilation" + ) +} + +/// Multiplies warp-distributed ordered sparse f16 A and B fragments and adds a f32 accumulator. +/// +/// Catalog ID: `mma_sp_ordered_metadata_m16n8k16_f32_f16`. Source: LLVM `llvm.nvvm.mma.sp.ordered.metadata.m16n8k16.row.col.f32.f32` from `int_nvvm_mma_sp_ordered_metadata_m16n8k16_row_col_f32_f32`; expects PTX `mma.sp::ordered_metadata.sync.aligned.m16n8k16.row.col.f32.f16.f16.f32 , , , , , ;`. +/// Available on `sm_80+` targets from PTX 8.5. +/// +/// # Safety +/// All 32 warp lanes must execute the same sparse MMA instruction with the same qualifiers, and no lane may have exited. +/// `_arg0`, `_arg1`, and `_arg2` hold this lane's 4-register C, 2-register A, and 2-register B fragments; `_arg3` holds its sparse metadata. +/// `_arg4` must be the compile-time constant `0`, `1`, `2`, or `3`. +/// The operation is register-only and is not a memory fence. +/// Every 4-bit metadata group must be `0x4`, `0x8`, `0x9`, `0xc`, `0xd`, or `0xe`; any other value is undefined behavior. +/// See the [PTX sparse MMA fragment layouts](https://docs.nvidia.com/cuda/parallel-thread-execution/#warp-level-matrix-instructions-mma-sp). +#[must_use] +#[inline(never)] +pub unsafe fn i1022( + _arg0: [f32; 4], + _arg1: [u32; 2], + _arg2: [u32; 2], + _arg3: u32, + _arg4: u32, +) -> [f32; 4] { + unreachable!( + "generated CUDA intrinsic `cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i1022` executed outside device compilation" + ) +} + +/// Multiplies warp-distributed ordered sparse tf32 A and B fragments and adds a f32 accumulator. +/// +/// Catalog ID: `mma_sp_ordered_metadata_m16n8k16_f32_tf32`. Source: LLVM `llvm.nvvm.mma.sp.ordered.metadata.m16n8k16.row.col.tf32` from `int_nvvm_mma_sp_ordered_metadata_m16n8k16_row_col_tf32`; expects PTX `mma.sp::ordered_metadata.sync.aligned.m16n8k16.row.col.f32.tf32.tf32.f32 , , , , , ;`. +/// Available on `sm_80+` targets from PTX 8.5. +/// +/// # Safety +/// All 32 warp lanes must execute the same sparse MMA instruction with the same qualifiers, and no lane may have exited. +/// `_arg0`, `_arg1`, and `_arg2` hold this lane's 4-register C, 4-register A, and 4-register B fragments; `_arg3` holds its sparse metadata. +/// `_arg4` must be the compile-time constant `0` or `1`. +/// The operation is register-only and is not a memory fence. +/// Every 4-bit metadata group must be `0x4` or `0xe`; any other value is undefined behavior. +/// See the [PTX sparse MMA fragment layouts](https://docs.nvidia.com/cuda/parallel-thread-execution/#warp-level-matrix-instructions-mma-sp). +#[must_use] +#[inline(never)] +pub unsafe fn i1019( + _arg0: [f32; 4], + _arg1: [u32; 4], + _arg2: [u32; 4], + _arg3: u32, + _arg4: u32, +) -> [f32; 4] { + unreachable!( + "generated CUDA intrinsic `cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i1019` executed outside device compilation" + ) +} + +/// Multiplies warp-distributed ordered sparse f16 A and B fragments and adds a packed f16 accumulator. +/// +/// Catalog ID: `mma_sp_ordered_metadata_m16n8k32_f16_f16`. Source: LLVM `llvm.nvvm.mma.sp.ordered.metadata.m16n8k32.row.col.f16.f16` from `int_nvvm_mma_sp_ordered_metadata_m16n8k32_row_col_f16_f16`; expects PTX `mma.sp::ordered_metadata.sync.aligned.m16n8k32.row.col.f16.f16.f16.f16 , , , , , ;`. +/// Available on `sm_80+` targets from PTX 8.5. +/// +/// # Safety +/// All 32 warp lanes must execute the same sparse MMA instruction with the same qualifiers, and no lane may have exited. +/// `_arg0`, `_arg1`, and `_arg2` hold this lane's 2-register C, 4-register A, and 4-register B fragments; `_arg3` holds its sparse metadata. +/// `_arg4` must be the compile-time constant `0` or `1`. +/// The operation is register-only and is not a memory fence. +/// Every 4-bit metadata group must be `0x4`, `0x8`, `0x9`, `0xc`, `0xd`, or `0xe`; any other value is undefined behavior. +/// See the [PTX sparse MMA fragment layouts](https://docs.nvidia.com/cuda/parallel-thread-execution/#warp-level-matrix-instructions-mma-sp). +#[must_use] +#[inline(never)] +pub unsafe fn i1024( + _arg0: [u32; 2], + _arg1: [u32; 4], + _arg2: [u32; 4], + _arg3: u32, + _arg4: u32, +) -> [u32; 2] { + unreachable!( + "generated CUDA intrinsic `cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i1024` executed outside device compilation" + ) +} + +/// Multiplies warp-distributed ordered sparse bf16 A and B fragments and adds a f32 accumulator. +/// +/// Catalog ID: `mma_sp_ordered_metadata_m16n8k32_f32_bf16`. Source: LLVM `llvm.nvvm.mma.sp.ordered.metadata.m16n8k32.row.col.bf16` from `int_nvvm_mma_sp_ordered_metadata_m16n8k32_row_col_bf16`; expects PTX `mma.sp::ordered_metadata.sync.aligned.m16n8k32.row.col.f32.bf16.bf16.f32 , , , , , ;`. +/// Available on `sm_80+` targets from PTX 8.5. +/// +/// # Safety +/// All 32 warp lanes must execute the same sparse MMA instruction with the same qualifiers, and no lane may have exited. +/// `_arg0`, `_arg1`, and `_arg2` hold this lane's 4-register C, 4-register A, and 4-register B fragments; `_arg3` holds its sparse metadata. +/// `_arg4` must be the compile-time constant `0` or `1`. +/// The operation is register-only and is not a memory fence. +/// Every 4-bit metadata group must be `0x4`, `0x8`, `0x9`, `0xc`, `0xd`, or `0xe`; any other value is undefined behavior. +/// See the [PTX sparse MMA fragment layouts](https://docs.nvidia.com/cuda/parallel-thread-execution/#warp-level-matrix-instructions-mma-sp). +#[must_use] +#[inline(never)] +pub unsafe fn i1023( + _arg0: [f32; 4], + _arg1: [u32; 4], + _arg2: [u32; 4], + _arg3: u32, + _arg4: u32, +) -> [f32; 4] { + unreachable!( + "generated CUDA intrinsic `cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i1023` executed outside device compilation" + ) +} + +/// Multiplies warp-distributed ordered sparse f16 A and B fragments and adds a f32 accumulator. +/// +/// Catalog ID: `mma_sp_ordered_metadata_m16n8k32_f32_f16`. Source: LLVM `llvm.nvvm.mma.sp.ordered.metadata.m16n8k32.row.col.f32.f32` from `int_nvvm_mma_sp_ordered_metadata_m16n8k32_row_col_f32_f32`; expects PTX `mma.sp::ordered_metadata.sync.aligned.m16n8k32.row.col.f32.f16.f16.f32 , , , , , ;`. +/// Available on `sm_80+` targets from PTX 8.5. +/// +/// # Safety +/// All 32 warp lanes must execute the same sparse MMA instruction with the same qualifiers, and no lane may have exited. +/// `_arg0`, `_arg1`, and `_arg2` hold this lane's 4-register C, 4-register A, and 4-register B fragments; `_arg3` holds its sparse metadata. +/// `_arg4` must be the compile-time constant `0` or `1`. +/// The operation is register-only and is not a memory fence. +/// Every 4-bit metadata group must be `0x4`, `0x8`, `0x9`, `0xc`, `0xd`, or `0xe`; any other value is undefined behavior. +/// See the [PTX sparse MMA fragment layouts](https://docs.nvidia.com/cuda/parallel-thread-execution/#warp-level-matrix-instructions-mma-sp). +#[must_use] +#[inline(never)] +pub unsafe fn i1025( + _arg0: [f32; 4], + _arg1: [u32; 4], + _arg2: [u32; 4], + _arg3: u32, + _arg4: u32, +) -> [f32; 4] { + unreachable!( + "generated CUDA intrinsic `cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i1025` executed outside device compilation" + ) +} + /// Multiplies warp-distributed sparse signed A and signed B INT8 fragments with ordered sparsity metadata and adds a wrapping s32 accumulator. /// /// Catalog ID: `mma_sp_ordered_metadata_m16n8k32_s32_s8`. Source: LLVM `llvm.nvvm.mma.sp.ordered.metadata.m16n8k32.row.col.s8` from `int_nvvm_mma_sp_ordered_metadata_m16n8k32_row_col_s8`; expects PTX `mma.sp::ordered_metadata.sync.aligned.m16n8k32.row.col.s32.s8.s8.s32 , , , , , ;`. @@ -11834,6 +12016,32 @@ pub unsafe fn i0185( ) } +/// Multiplies warp-distributed ordered sparse tf32 A and B fragments and adds a f32 accumulator. +/// +/// Catalog ID: `mma_sp_ordered_metadata_m16n8k8_f32_tf32`. Source: LLVM `llvm.nvvm.mma.sp.ordered.metadata.m16n8k8.row.col.tf32` from `int_nvvm_mma_sp_ordered_metadata_m16n8k8_row_col_tf32`; expects PTX `mma.sp::ordered_metadata.sync.aligned.m16n8k8.row.col.f32.tf32.tf32.f32 , , , , , ;`. +/// Available on `sm_80+` targets from PTX 8.5. +/// +/// # Safety +/// All 32 warp lanes must execute the same sparse MMA instruction with the same qualifiers, and no lane may have exited. +/// `_arg0`, `_arg1`, and `_arg2` hold this lane's 4-register C, 2-register A, and 2-register B fragments; `_arg3` holds its sparse metadata. +/// `_arg4` must be the compile-time constant `0`, `1`, `2`, or `3`. +/// The operation is register-only and is not a memory fence. +/// Every 4-bit metadata group must be `0x4` or `0xe`; any other value is undefined behavior. +/// See the [PTX sparse MMA fragment layouts](https://docs.nvidia.com/cuda/parallel-thread-execution/#warp-level-matrix-instructions-mma-sp). +#[must_use] +#[inline(never)] +pub unsafe fn i1018( + _arg0: [f32; 4], + _arg1: [u32; 2], + _arg2: [u32; 2], + _arg3: u32, + _arg4: u32, +) -> [f32; 4] { + unreachable!( + "generated CUDA intrinsic `cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i1018` executed outside device compilation" + ) +} + /// Transposes one packed b16 matrix fragment across a warp. /// /// Catalog ID: `movmatrix_trans_b16`. Source: PTX-native `movmatrix.sync.aligned.m8n8.trans.b16`; expects PTX `movmatrix.sync.aligned.m8n8.trans.b16 , ;`. diff --git a/crates/cuda-intrinsics/src/generated/mod.rs b/crates/cuda-intrinsics/src/generated/mod.rs index 5e87012eaa..82a16eb7ea 100644 --- a/crates/cuda-intrinsics/src/generated/mod.rs +++ b/crates/cuda-intrinsics/src/generated/mod.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. #[doc(hidden)] @@ -667,6 +667,14 @@ pub mod matrix { pub use crate::__cuda_oxide_intrinsic_abi_v1::i0880 as mma_m16n8k32_mxf8f6f4_f32_e5m2_e3m2; pub use crate::__cuda_oxide_intrinsic_abi_v1::i0881 as mma_m16n8k32_mxf8f6f4_f32_e5m2_e4m3; pub use crate::__cuda_oxide_intrinsic_abi_v1::i0882 as mma_m16n8k32_mxf8f6f4_f32_e5m2_e5m2; + pub use crate::__cuda_oxide_intrinsic_abi_v1::i1018 as mma_sp_ordered_metadata_m16n8k8_f32_tf32; + pub use crate::__cuda_oxide_intrinsic_abi_v1::i1019 as mma_sp_ordered_metadata_m16n8k16_f32_tf32; + pub use crate::__cuda_oxide_intrinsic_abi_v1::i1020 as mma_sp_ordered_metadata_m16n8k16_f32_bf16; + pub use crate::__cuda_oxide_intrinsic_abi_v1::i1021 as mma_sp_ordered_metadata_m16n8k16_f16_f16; + pub use crate::__cuda_oxide_intrinsic_abi_v1::i1022 as mma_sp_ordered_metadata_m16n8k16_f32_f16; + pub use crate::__cuda_oxide_intrinsic_abi_v1::i1023 as mma_sp_ordered_metadata_m16n8k32_f32_bf16; + pub use crate::__cuda_oxide_intrinsic_abi_v1::i1024 as mma_sp_ordered_metadata_m16n8k32_f16_f16; + pub use crate::__cuda_oxide_intrinsic_abi_v1::i1025 as mma_sp_ordered_metadata_m16n8k32_f32_f16; } /// Generated `prmt` intrinsic source API. @@ -5672,6 +5680,62 @@ mod tests { assert_eq!(public as usize, canonical as usize); } #[test] + fn public_mma_sp_ordered_metadata_m16n8k16_f16_f16_reexports_abi_i1021() { + let public: unsafe fn([u32; 2], [u32; 2], [u32; 2], u32, u32) -> [u32; 2] = + super::matrix::mma_sp_ordered_metadata_m16n8k16_f16_f16; + let canonical: unsafe fn([u32; 2], [u32; 2], [u32; 2], u32, u32) -> [u32; 2] = + super::__cuda_oxide_intrinsic_abi_v1::i1021; + assert_eq!(public as usize, canonical as usize); + } + #[test] + fn public_mma_sp_ordered_metadata_m16n8k16_f32_bf16_reexports_abi_i1020() { + let public: unsafe fn([f32; 4], [u32; 2], [u32; 2], u32, u32) -> [f32; 4] = + super::matrix::mma_sp_ordered_metadata_m16n8k16_f32_bf16; + let canonical: unsafe fn([f32; 4], [u32; 2], [u32; 2], u32, u32) -> [f32; 4] = + super::__cuda_oxide_intrinsic_abi_v1::i1020; + assert_eq!(public as usize, canonical as usize); + } + #[test] + fn public_mma_sp_ordered_metadata_m16n8k16_f32_f16_reexports_abi_i1022() { + let public: unsafe fn([f32; 4], [u32; 2], [u32; 2], u32, u32) -> [f32; 4] = + super::matrix::mma_sp_ordered_metadata_m16n8k16_f32_f16; + let canonical: unsafe fn([f32; 4], [u32; 2], [u32; 2], u32, u32) -> [f32; 4] = + super::__cuda_oxide_intrinsic_abi_v1::i1022; + assert_eq!(public as usize, canonical as usize); + } + #[test] + fn public_mma_sp_ordered_metadata_m16n8k16_f32_tf32_reexports_abi_i1019() { + let public: unsafe fn([f32; 4], [u32; 4], [u32; 4], u32, u32) -> [f32; 4] = + super::matrix::mma_sp_ordered_metadata_m16n8k16_f32_tf32; + let canonical: unsafe fn([f32; 4], [u32; 4], [u32; 4], u32, u32) -> [f32; 4] = + super::__cuda_oxide_intrinsic_abi_v1::i1019; + assert_eq!(public as usize, canonical as usize); + } + #[test] + fn public_mma_sp_ordered_metadata_m16n8k32_f16_f16_reexports_abi_i1024() { + let public: unsafe fn([u32; 2], [u32; 4], [u32; 4], u32, u32) -> [u32; 2] = + super::matrix::mma_sp_ordered_metadata_m16n8k32_f16_f16; + let canonical: unsafe fn([u32; 2], [u32; 4], [u32; 4], u32, u32) -> [u32; 2] = + super::__cuda_oxide_intrinsic_abi_v1::i1024; + assert_eq!(public as usize, canonical as usize); + } + #[test] + fn public_mma_sp_ordered_metadata_m16n8k32_f32_bf16_reexports_abi_i1023() { + let public: unsafe fn([f32; 4], [u32; 4], [u32; 4], u32, u32) -> [f32; 4] = + super::matrix::mma_sp_ordered_metadata_m16n8k32_f32_bf16; + let canonical: unsafe fn([f32; 4], [u32; 4], [u32; 4], u32, u32) -> [f32; 4] = + super::__cuda_oxide_intrinsic_abi_v1::i1023; + assert_eq!(public as usize, canonical as usize); + } + #[test] + fn public_mma_sp_ordered_metadata_m16n8k32_f32_f16_reexports_abi_i1025() { + let public: unsafe fn([f32; 4], [u32; 4], [u32; 4], u32, u32) -> [f32; 4] = + super::matrix::mma_sp_ordered_metadata_m16n8k32_f32_f16; + let canonical: unsafe fn([f32; 4], [u32; 4], [u32; 4], u32, u32) -> [f32; 4] = + super::__cuda_oxide_intrinsic_abi_v1::i1025; + assert_eq!(public as usize, canonical as usize); + } + #[test] fn public_mma_sp_ordered_metadata_m16n8k32_s32_s8_reexports_abi_i0171() { let public: unsafe fn([i32; 4], [u32; 2], [u32; 2], u32, u32) -> [i32; 4] = super::matrix::mma_sp_ordered_metadata_m16n8k32_s32_s8; @@ -6264,6 +6328,14 @@ mod tests { assert_eq!(public as usize, canonical as usize); } #[test] + fn public_mma_sp_ordered_metadata_m16n8k8_f32_tf32_reexports_abi_i1018() { + let public: unsafe fn([f32; 4], [u32; 2], [u32; 2], u32, u32) -> [f32; 4] = + super::matrix::mma_sp_ordered_metadata_m16n8k8_f32_tf32; + let canonical: unsafe fn([f32; 4], [u32; 2], [u32; 2], u32, u32) -> [f32; 4] = + super::__cuda_oxide_intrinsic_abi_v1::i1018; + assert_eq!(public as usize, canonical as usize); + } + #[test] fn public_movmatrix_trans_b16_reexports_abi_i0305() { let public: unsafe fn(u32) -> u32 = super::matrix::movmatrix_trans_b16; let canonical: unsafe fn(u32) -> u32 = super::__cuda_oxide_intrinsic_abi_v1::i0305; diff --git a/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/active_mask.rs b/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/active_mask.rs index 2ef9234f71..ec73562e97 100644 --- a/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/active_mask.rs +++ b/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/active_mask.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. //! Generated intrinsic target records: `active_mask` intrinsics. diff --git a/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/clc.rs b/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/clc.rs index 2111019e4c..354ed5f8f6 100644 --- a/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/clc.rs +++ b/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/clc.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. //! Generated intrinsic target records: `clc` intrinsics. diff --git a/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/cluster_barrier.rs b/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/cluster_barrier.rs index b8b48454bc..fe591dd61e 100644 --- a/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/cluster_barrier.rs +++ b/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/cluster_barrier.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. //! Generated intrinsic target records: `cluster_barrier` intrinsics. diff --git a/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/cluster_memory.rs b/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/cluster_memory.rs index 95a1ef3b49..66c9bf9718 100644 --- a/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/cluster_memory.rs +++ b/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/cluster_memory.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. //! Generated intrinsic target records: `cluster_memory` intrinsics. diff --git a/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/cp_async.rs b/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/cp_async.rs index 833dd32a30..d8049440fb 100644 --- a/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/cp_async.rs +++ b/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/cp_async.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. //! Generated intrinsic target records: `cp_async` intrinsics. diff --git a/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/debug_control.rs b/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/debug_control.rs index 6f13b9bd69..a46ebe6a98 100644 --- a/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/debug_control.rs +++ b/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/debug_control.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. //! Generated intrinsic target records: `debug_control` intrinsics. diff --git a/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/dotprod.rs b/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/dotprod.rs index 94b2847fad..f439e4d0b4 100644 --- a/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/dotprod.rs +++ b/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/dotprod.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. //! Generated intrinsic target records: `dotprod` intrinsics. diff --git a/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/elect.rs b/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/elect.rs index 4ab347386e..d7bd3a6167 100644 --- a/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/elect.rs +++ b/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/elect.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. //! Generated intrinsic target records: `elect` intrinsics. diff --git a/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/execution_control.rs b/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/execution_control.rs index 9aa33b064f..f4716b0db4 100644 --- a/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/execution_control.rs +++ b/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/execution_control.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. //! Generated intrinsic target records: `execution_control` intrinsics. diff --git a/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/extended_minmax.rs b/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/extended_minmax.rs index c49de834ae..d1d4f67d70 100644 --- a/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/extended_minmax.rs +++ b/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/extended_minmax.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. //! Generated intrinsic target records: `extended_minmax` intrinsics. diff --git a/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/integer_minmax.rs b/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/integer_minmax.rs index f65134bdbb..5f7f560cea 100644 --- a/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/integer_minmax.rs +++ b/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/integer_minmax.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. //! Generated intrinsic target records: `integer_minmax` intrinsics. diff --git a/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/ldmatrix.rs b/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/ldmatrix.rs index c3098b10b1..c6d5c0e70f 100644 --- a/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/ldmatrix.rs +++ b/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/ldmatrix.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. //! Generated intrinsic target records: `ldmatrix` intrinsics. diff --git a/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/mbarrier_basic.rs b/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/mbarrier_basic.rs index a0428ea366..1725acc764 100644 --- a/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/mbarrier_basic.rs +++ b/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/mbarrier_basic.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. //! Generated intrinsic target records: `mbarrier_basic` intrinsics. diff --git a/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/mbarrier_extended.rs b/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/mbarrier_extended.rs index 01a80c2873..3b5e3dfd8a 100644 --- a/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/mbarrier_extended.rs +++ b/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/mbarrier_extended.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. //! Generated intrinsic target records: `mbarrier_extended` intrinsics. diff --git a/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/mod.rs b/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/mod.rs index 777b637733..036bfc31cd 100644 --- a/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/mod.rs +++ b/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/mod.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. //! Generated target requirements and separately imported LLVM/selection facts. @@ -200,6 +200,8 @@ pub enum GeneratedRegisterMmaOverflow { } #[derive(Debug, Clone, Copy, PartialEq, Eq)] pub enum GeneratedSparseMmaShape { + M16n8k8, + M16n8k16, M16n8k32, M16n8k64, M16n8k128, @@ -212,6 +214,9 @@ pub enum GeneratedSparseMmaAccumulator { } #[derive(Debug, Clone, Copy, PartialEq, Eq)] pub enum GeneratedSparseMmaElement { + F16, + Bf16, + Tf32, E2m1, E2m3, E3m2, @@ -239,7 +244,9 @@ pub enum GeneratedSparseMmaMetadata { Ordered, } #[derive(Debug, Clone, Copy, PartialEq, Eq)] +#[allow(clippy::enum_variant_names)] pub enum GeneratedSparseMmaSelector { + ImmediateZeroThroughThree, ImmediateZeroOrOne, ImmediateZero, } @@ -951,6 +958,9 @@ pub fn generated_intrinsic_operation_matches( return false; }; let element_matches = |expected, actual: Option<&SparseMmaElementAttr>| match expected { + GeneratedSparseMmaElement::F16 => actual == Some(&SparseMmaElementAttr::F16), + GeneratedSparseMmaElement::Bf16 => actual == Some(&SparseMmaElementAttr::Bf16), + GeneratedSparseMmaElement::Tf32 => actual == Some(&SparseMmaElementAttr::Tf32), GeneratedSparseMmaElement::E2m1 => actual == Some(&SparseMmaElementAttr::E2m1), GeneratedSparseMmaElement::E2m3 => actual == Some(&SparseMmaElementAttr::E2m3), GeneratedSparseMmaElement::E3m2 => actual == Some(&SparseMmaElementAttr::E3m2), @@ -990,6 +1000,14 @@ pub fn generated_intrinsic_operation_matches( } }; let shape_matches = match shape { + GeneratedSparseMmaShape::M16n8k8 => { + op.get_attr_nvvm_sparse_mma_shape(ctx).as_deref() + == Some(&SparseMmaShapeAttr::M16n8k8) + } + GeneratedSparseMmaShape::M16n8k16 => { + op.get_attr_nvvm_sparse_mma_shape(ctx).as_deref() + == Some(&SparseMmaShapeAttr::M16n8k16) + } GeneratedSparseMmaShape::M16n8k32 => { op.get_attr_nvvm_sparse_mma_shape(ctx).as_deref() == Some(&SparseMmaShapeAttr::M16n8k32) @@ -1018,6 +1036,10 @@ pub fn generated_intrinsic_operation_matches( } }; let selector_matches = match selector { + GeneratedSparseMmaSelector::ImmediateZeroThroughThree => { + op.get_attr_nvvm_sparse_mma_selector(ctx).as_deref() + == Some(&SparseMmaSelectorAttr::ImmediateZeroThroughThree) + } GeneratedSparseMmaSelector::ImmediateZeroOrOne => { op.get_attr_nvvm_sparse_mma_selector(ctx).as_deref() == Some(&SparseMmaSelectorAttr::ImmediateZeroOrOne) diff --git a/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/movmatrix.rs b/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/movmatrix.rs index 59490927da..a78ee2d4b4 100644 --- a/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/movmatrix.rs +++ b/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/movmatrix.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. //! Generated intrinsic target records: `movmatrix` intrinsics. diff --git a/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/packed_alu.rs b/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/packed_alu.rs index a1a4d87335..11f4e9c0e8 100644 --- a/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/packed_alu.rs +++ b/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/packed_alu.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. //! Generated intrinsic target records: `packed_alu` intrinsics. diff --git a/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/packed_atomic.rs b/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/packed_atomic.rs index da48ade2a5..a82bb6bc7a 100644 --- a/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/packed_atomic.rs +++ b/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/packed_atomic.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. //! Generated intrinsic target records: `packed_atomic` intrinsics. diff --git a/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/packed_conversion.rs b/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/packed_conversion.rs index 2173271a0c..bdb4e7aeaa 100644 --- a/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/packed_conversion.rs +++ b/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/packed_conversion.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. //! Generated intrinsic target records: `packed_conversion` intrinsics. diff --git a/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/prmt.rs b/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/prmt.rs index 632f71e1ea..58512155c0 100644 --- a/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/prmt.rs +++ b/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/prmt.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. //! Generated intrinsic target records: `prmt` intrinsics. diff --git a/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/redux.rs b/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/redux.rs index 65c8719f7a..112f54acd7 100644 --- a/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/redux.rs +++ b/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/redux.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. //! Generated intrinsic target records: `redux` intrinsics. diff --git a/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/register_mma.rs b/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/register_mma.rs index ea3985c2c5..6115af3f86 100644 --- a/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/register_mma.rs +++ b/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/register_mma.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. //! Generated intrinsic target records: `register_mma` intrinsics. diff --git a/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/scalar_arithmetic.rs b/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/scalar_arithmetic.rs index 6d62b494dd..bc5ba16309 100644 --- a/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/scalar_arithmetic.rs +++ b/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/scalar_arithmetic.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. //! Generated intrinsic target records: `scalar_arithmetic` intrinsics. diff --git a/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/scalar_conversion.rs b/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/scalar_conversion.rs index d063134443..43e01afa46 100644 --- a/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/scalar_conversion.rs +++ b/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/scalar_conversion.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. //! Generated intrinsic target records: `scalar_conversion` intrinsics. diff --git a/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/scalar_math.rs b/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/scalar_math.rs index 7b9f1b5ba7..46813a75fe 100644 --- a/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/scalar_math.rs +++ b/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/scalar_math.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. //! Generated intrinsic target records: `scalar_math` intrinsics. diff --git a/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/sparse_mma.rs b/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/sparse_mma.rs index 3bc606543f..6e6a1ff7ec 100644 --- a/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/sparse_mma.rs +++ b/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/sparse_mma.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. //! Generated intrinsic target records: `sparse_mma` intrinsics. @@ -7729,4 +7729,524 @@ pub(super) const TARGETS: &[GeneratedIntrinsicTarget] = &[ result_range: None, }), }, + GeneratedIntrinsicTarget { + marker: "v1:i1018", + id: "mma_sp_ordered_metadata_m16n8k8_f32_tf32", + abi_id: "i1018", + dialect_op: "nvvm.sparse_mma", + variant: GeneratedIntrinsicVariant::SparseMma { + shape: GeneratedSparseMmaShape::M16n8k8, + accumulator: GeneratedSparseMmaAccumulator::F32, + a_element: GeneratedSparseMmaElement::Tf32, + b_element: GeneratedSparseMmaElement::Tf32, + a_layout: GeneratedSparseMmaLayout::Row, + b_layout: GeneratedSparseMmaLayout::Col, + overflow: GeneratedSparseMmaOverflow::NotApplicable, + metadata: GeneratedSparseMmaMetadata::Ordered, + selector: GeneratedSparseMmaSelector::ImmediateZeroThroughThree, + }, + requirement: GeneratedTargetRequirement { + minimum_ptx: GeneratedPtxVersion::from_encoded(85), + hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm( + 80, + )]), + }, + backend_requirements: &[ + GeneratedBackendRequirement { + backend: GeneratedIntrinsicBackend::LlvmNvptx, + requirement: GeneratedTargetRequirement { + minimum_ptx: GeneratedPtxVersion::from_encoded(85), + hardware: GeneratedHardwareTarget::AnyOf(&[ + GeneratedHardwareAlternative::MinimumSm(80), + ]), + }, + }, + GeneratedBackendRequirement { + backend: GeneratedIntrinsicBackend::LibNvvm, + requirement: GeneratedTargetRequirement { + minimum_ptx: GeneratedPtxVersion::from_encoded(85), + hardware: GeneratedHardwareTarget::AnyOf(&[ + GeneratedHardwareAlternative::MinimumSm(80), + ]), + }, + }, + ], + selections: &[GeneratedSelectionAlternative { + source_record: "anonymous_19540", + asm: "mma.sp::ordered_metadata.sync.aligned.m16n8k8.row.col.f32.tf32.tf32.f32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1}},\n\t\t{{$rb0, $rb1}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}},\n\t\t$metadata,\n\t\t$selector;", + predicates: &[ + "Subtarget->getSmVersion() >= 80", + "Subtarget->getPTXVersion() >= 85", + ], + constraints: GeneratedSelectionConstraints { + address_space: None, + immediate_bindings: &[], + }, + }], + llvm: Some(GeneratedLlvmFacts { + properties: &[ + "ImmArg", + "IntrNoCallback", + "IntrNoMem", + "Range", + ], + result_no_undef: false, + result_range: None, + }), + }, + GeneratedIntrinsicTarget { + marker: "v1:i1019", + id: "mma_sp_ordered_metadata_m16n8k16_f32_tf32", + abi_id: "i1019", + dialect_op: "nvvm.sparse_mma", + variant: GeneratedIntrinsicVariant::SparseMma { + shape: GeneratedSparseMmaShape::M16n8k16, + accumulator: GeneratedSparseMmaAccumulator::F32, + a_element: GeneratedSparseMmaElement::Tf32, + b_element: GeneratedSparseMmaElement::Tf32, + a_layout: GeneratedSparseMmaLayout::Row, + b_layout: GeneratedSparseMmaLayout::Col, + overflow: GeneratedSparseMmaOverflow::NotApplicable, + metadata: GeneratedSparseMmaMetadata::Ordered, + selector: GeneratedSparseMmaSelector::ImmediateZeroOrOne, + }, + requirement: GeneratedTargetRequirement { + minimum_ptx: GeneratedPtxVersion::from_encoded(85), + hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm( + 80, + )]), + }, + backend_requirements: &[ + GeneratedBackendRequirement { + backend: GeneratedIntrinsicBackend::LlvmNvptx, + requirement: GeneratedTargetRequirement { + minimum_ptx: GeneratedPtxVersion::from_encoded(85), + hardware: GeneratedHardwareTarget::AnyOf(&[ + GeneratedHardwareAlternative::MinimumSm(80), + ]), + }, + }, + GeneratedBackendRequirement { + backend: GeneratedIntrinsicBackend::LibNvvm, + requirement: GeneratedTargetRequirement { + minimum_ptx: GeneratedPtxVersion::from_encoded(85), + hardware: GeneratedHardwareTarget::AnyOf(&[ + GeneratedHardwareAlternative::MinimumSm(80), + ]), + }, + }, + ], + selections: &[GeneratedSelectionAlternative { + source_record: "anonymous_19546", + asm: "mma.sp::ordered_metadata.sync.aligned.m16n8k16.row.col.f32.tf32.tf32.f32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1, $rb2, $rb3}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}},\n\t\t$metadata,\n\t\t$selector;", + predicates: &[ + "Subtarget->getSmVersion() >= 80", + "Subtarget->getPTXVersion() >= 85", + ], + constraints: GeneratedSelectionConstraints { + address_space: None, + immediate_bindings: &[], + }, + }], + llvm: Some(GeneratedLlvmFacts { + properties: &[ + "ImmArg", + "IntrNoCallback", + "IntrNoMem", + "Range", + ], + result_no_undef: false, + result_range: None, + }), + }, + GeneratedIntrinsicTarget { + marker: "v1:i1020", + id: "mma_sp_ordered_metadata_m16n8k16_f32_bf16", + abi_id: "i1020", + dialect_op: "nvvm.sparse_mma", + variant: GeneratedIntrinsicVariant::SparseMma { + shape: GeneratedSparseMmaShape::M16n8k16, + accumulator: GeneratedSparseMmaAccumulator::F32, + a_element: GeneratedSparseMmaElement::Bf16, + b_element: GeneratedSparseMmaElement::Bf16, + a_layout: GeneratedSparseMmaLayout::Row, + b_layout: GeneratedSparseMmaLayout::Col, + overflow: GeneratedSparseMmaOverflow::NotApplicable, + metadata: GeneratedSparseMmaMetadata::Ordered, + selector: GeneratedSparseMmaSelector::ImmediateZeroThroughThree, + }, + requirement: GeneratedTargetRequirement { + minimum_ptx: GeneratedPtxVersion::from_encoded(85), + hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm( + 80, + )]), + }, + backend_requirements: &[ + GeneratedBackendRequirement { + backend: GeneratedIntrinsicBackend::LlvmNvptx, + requirement: GeneratedTargetRequirement { + minimum_ptx: GeneratedPtxVersion::from_encoded(85), + hardware: GeneratedHardwareTarget::AnyOf(&[ + GeneratedHardwareAlternative::MinimumSm(80), + ]), + }, + }, + GeneratedBackendRequirement { + backend: GeneratedIntrinsicBackend::LibNvvm, + requirement: GeneratedTargetRequirement { + minimum_ptx: GeneratedPtxVersion::from_encoded(85), + hardware: GeneratedHardwareTarget::AnyOf(&[ + GeneratedHardwareAlternative::MinimumSm(80), + ]), + }, + }, + ], + selections: &[GeneratedSelectionAlternative { + source_record: "anonymous_19524", + asm: "mma.sp::ordered_metadata.sync.aligned.m16n8k16.row.col.f32.bf16.bf16.f32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1}},\n\t\t{{$rb0, $rb1}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}},\n\t\t$metadata,\n\t\t$selector;", + predicates: &[ + "Subtarget->getSmVersion() >= 80", + "Subtarget->getPTXVersion() >= 85", + ], + constraints: GeneratedSelectionConstraints { + address_space: None, + immediate_bindings: &[], + }, + }], + llvm: Some(GeneratedLlvmFacts { + properties: &[ + "ImmArg", + "IntrNoCallback", + "IntrNoMem", + "Range", + ], + result_no_undef: false, + result_range: None, + }), + }, + GeneratedIntrinsicTarget { + marker: "v1:i1021", + id: "mma_sp_ordered_metadata_m16n8k16_f16_f16", + abi_id: "i1021", + dialect_op: "nvvm.sparse_mma", + variant: GeneratedIntrinsicVariant::SparseMma { + shape: GeneratedSparseMmaShape::M16n8k16, + accumulator: GeneratedSparseMmaAccumulator::F16, + a_element: GeneratedSparseMmaElement::F16, + b_element: GeneratedSparseMmaElement::F16, + a_layout: GeneratedSparseMmaLayout::Row, + b_layout: GeneratedSparseMmaLayout::Col, + overflow: GeneratedSparseMmaOverflow::NotApplicable, + metadata: GeneratedSparseMmaMetadata::Ordered, + selector: GeneratedSparseMmaSelector::ImmediateZeroThroughThree, + }, + requirement: GeneratedTargetRequirement { + minimum_ptx: GeneratedPtxVersion::from_encoded(85), + hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm( + 80, + )]), + }, + backend_requirements: &[ + GeneratedBackendRequirement { + backend: GeneratedIntrinsicBackend::LlvmNvptx, + requirement: GeneratedTargetRequirement { + minimum_ptx: GeneratedPtxVersion::from_encoded(85), + hardware: GeneratedHardwareTarget::AnyOf(&[ + GeneratedHardwareAlternative::MinimumSm(80), + ]), + }, + }, + GeneratedBackendRequirement { + backend: GeneratedIntrinsicBackend::LibNvvm, + requirement: GeneratedTargetRequirement { + minimum_ptx: GeneratedPtxVersion::from_encoded(85), + hardware: GeneratedHardwareTarget::AnyOf(&[ + GeneratedHardwareAlternative::MinimumSm(80), + ]), + }, + }, + ], + selections: &[GeneratedSelectionAlternative { + source_record: "anonymous_19554", + asm: "mma.sp::ordered_metadata.sync.aligned.m16n8k16.row.col.f16.f16.f16.f16\n\t\t{{$rd0, $rd1}},\n\t\t{{$ra0, $ra1}},\n\t\t{{$rb0, $rb1}},\n\t\t{{$rc0, $rc1}},\n\t\t$metadata,\n\t\t$selector;", + predicates: &[ + "Subtarget->getSmVersion() >= 80", + "Subtarget->getPTXVersion() >= 85", + ], + constraints: GeneratedSelectionConstraints { + address_space: None, + immediate_bindings: &[], + }, + }], + llvm: Some(GeneratedLlvmFacts { + properties: &[ + "ImmArg", + "IntrNoCallback", + "IntrNoMem", + "Range", + ], + result_no_undef: false, + result_range: None, + }), + }, + GeneratedIntrinsicTarget { + marker: "v1:i1022", + id: "mma_sp_ordered_metadata_m16n8k16_f32_f16", + abi_id: "i1022", + dialect_op: "nvvm.sparse_mma", + variant: GeneratedIntrinsicVariant::SparseMma { + shape: GeneratedSparseMmaShape::M16n8k16, + accumulator: GeneratedSparseMmaAccumulator::F32, + a_element: GeneratedSparseMmaElement::F16, + b_element: GeneratedSparseMmaElement::F16, + a_layout: GeneratedSparseMmaLayout::Row, + b_layout: GeneratedSparseMmaLayout::Col, + overflow: GeneratedSparseMmaOverflow::NotApplicable, + metadata: GeneratedSparseMmaMetadata::Ordered, + selector: GeneratedSparseMmaSelector::ImmediateZeroThroughThree, + }, + requirement: GeneratedTargetRequirement { + minimum_ptx: GeneratedPtxVersion::from_encoded(85), + hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm( + 80, + )]), + }, + backend_requirements: &[ + GeneratedBackendRequirement { + backend: GeneratedIntrinsicBackend::LlvmNvptx, + requirement: GeneratedTargetRequirement { + minimum_ptx: GeneratedPtxVersion::from_encoded(85), + hardware: GeneratedHardwareTarget::AnyOf(&[ + GeneratedHardwareAlternative::MinimumSm(80), + ]), + }, + }, + GeneratedBackendRequirement { + backend: GeneratedIntrinsicBackend::LibNvvm, + requirement: GeneratedTargetRequirement { + minimum_ptx: GeneratedPtxVersion::from_encoded(85), + hardware: GeneratedHardwareTarget::AnyOf(&[ + GeneratedHardwareAlternative::MinimumSm(80), + ]), + }, + }, + ], + selections: &[GeneratedSelectionAlternative { + source_record: "anonymous_19558", + asm: "mma.sp::ordered_metadata.sync.aligned.m16n8k16.row.col.f32.f16.f16.f32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1}},\n\t\t{{$rb0, $rb1}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}},\n\t\t$metadata,\n\t\t$selector;", + predicates: &[ + "Subtarget->getSmVersion() >= 80", + "Subtarget->getPTXVersion() >= 85", + ], + constraints: GeneratedSelectionConstraints { + address_space: None, + immediate_bindings: &[], + }, + }], + llvm: Some(GeneratedLlvmFacts { + properties: &[ + "ImmArg", + "IntrNoCallback", + "IntrNoMem", + "Range", + ], + result_no_undef: false, + result_range: None, + }), + }, + GeneratedIntrinsicTarget { + marker: "v1:i1023", + id: "mma_sp_ordered_metadata_m16n8k32_f32_bf16", + abi_id: "i1023", + dialect_op: "nvvm.sparse_mma", + variant: GeneratedIntrinsicVariant::SparseMma { + shape: GeneratedSparseMmaShape::M16n8k32, + accumulator: GeneratedSparseMmaAccumulator::F32, + a_element: GeneratedSparseMmaElement::Bf16, + b_element: GeneratedSparseMmaElement::Bf16, + a_layout: GeneratedSparseMmaLayout::Row, + b_layout: GeneratedSparseMmaLayout::Col, + overflow: GeneratedSparseMmaOverflow::NotApplicable, + metadata: GeneratedSparseMmaMetadata::Ordered, + selector: GeneratedSparseMmaSelector::ImmediateZeroOrOne, + }, + requirement: GeneratedTargetRequirement { + minimum_ptx: GeneratedPtxVersion::from_encoded(85), + hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm( + 80, + )]), + }, + backend_requirements: &[ + GeneratedBackendRequirement { + backend: GeneratedIntrinsicBackend::LlvmNvptx, + requirement: GeneratedTargetRequirement { + minimum_ptx: GeneratedPtxVersion::from_encoded(85), + hardware: GeneratedHardwareTarget::AnyOf(&[ + GeneratedHardwareAlternative::MinimumSm(80), + ]), + }, + }, + GeneratedBackendRequirement { + backend: GeneratedIntrinsicBackend::LibNvvm, + requirement: GeneratedTargetRequirement { + minimum_ptx: GeneratedPtxVersion::from_encoded(85), + hardware: GeneratedHardwareTarget::AnyOf(&[ + GeneratedHardwareAlternative::MinimumSm(80), + ]), + }, + }, + ], + selections: &[GeneratedSelectionAlternative { + source_record: "anonymous_19532", + asm: "mma.sp::ordered_metadata.sync.aligned.m16n8k32.row.col.f32.bf16.bf16.f32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1, $rb2, $rb3}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}},\n\t\t$metadata,\n\t\t$selector;", + predicates: &[ + "Subtarget->getSmVersion() >= 80", + "Subtarget->getPTXVersion() >= 85", + ], + constraints: GeneratedSelectionConstraints { + address_space: None, + immediate_bindings: &[], + }, + }], + llvm: Some(GeneratedLlvmFacts { + properties: &[ + "ImmArg", + "IntrNoCallback", + "IntrNoMem", + "Range", + ], + result_no_undef: false, + result_range: None, + }), + }, + GeneratedIntrinsicTarget { + marker: "v1:i1024", + id: "mma_sp_ordered_metadata_m16n8k32_f16_f16", + abi_id: "i1024", + dialect_op: "nvvm.sparse_mma", + variant: GeneratedIntrinsicVariant::SparseMma { + shape: GeneratedSparseMmaShape::M16n8k32, + accumulator: GeneratedSparseMmaAccumulator::F16, + a_element: GeneratedSparseMmaElement::F16, + b_element: GeneratedSparseMmaElement::F16, + a_layout: GeneratedSparseMmaLayout::Row, + b_layout: GeneratedSparseMmaLayout::Col, + overflow: GeneratedSparseMmaOverflow::NotApplicable, + metadata: GeneratedSparseMmaMetadata::Ordered, + selector: GeneratedSparseMmaSelector::ImmediateZeroOrOne, + }, + requirement: GeneratedTargetRequirement { + minimum_ptx: GeneratedPtxVersion::from_encoded(85), + hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm( + 80, + )]), + }, + backend_requirements: &[ + GeneratedBackendRequirement { + backend: GeneratedIntrinsicBackend::LlvmNvptx, + requirement: GeneratedTargetRequirement { + minimum_ptx: GeneratedPtxVersion::from_encoded(85), + hardware: GeneratedHardwareTarget::AnyOf(&[ + GeneratedHardwareAlternative::MinimumSm(80), + ]), + }, + }, + GeneratedBackendRequirement { + backend: GeneratedIntrinsicBackend::LibNvvm, + requirement: GeneratedTargetRequirement { + minimum_ptx: GeneratedPtxVersion::from_encoded(85), + hardware: GeneratedHardwareTarget::AnyOf(&[ + GeneratedHardwareAlternative::MinimumSm(80), + ]), + }, + }, + ], + selections: &[GeneratedSelectionAlternative { + source_record: "anonymous_19566", + asm: "mma.sp::ordered_metadata.sync.aligned.m16n8k32.row.col.f16.f16.f16.f16\n\t\t{{$rd0, $rd1}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1, $rb2, $rb3}},\n\t\t{{$rc0, $rc1}},\n\t\t$metadata,\n\t\t$selector;", + predicates: &[ + "Subtarget->getSmVersion() >= 80", + "Subtarget->getPTXVersion() >= 85", + ], + constraints: GeneratedSelectionConstraints { + address_space: None, + immediate_bindings: &[], + }, + }], + llvm: Some(GeneratedLlvmFacts { + properties: &[ + "ImmArg", + "IntrNoCallback", + "IntrNoMem", + "Range", + ], + result_no_undef: false, + result_range: None, + }), + }, + GeneratedIntrinsicTarget { + marker: "v1:i1025", + id: "mma_sp_ordered_metadata_m16n8k32_f32_f16", + abi_id: "i1025", + dialect_op: "nvvm.sparse_mma", + variant: GeneratedIntrinsicVariant::SparseMma { + shape: GeneratedSparseMmaShape::M16n8k32, + accumulator: GeneratedSparseMmaAccumulator::F32, + a_element: GeneratedSparseMmaElement::F16, + b_element: GeneratedSparseMmaElement::F16, + a_layout: GeneratedSparseMmaLayout::Row, + b_layout: GeneratedSparseMmaLayout::Col, + overflow: GeneratedSparseMmaOverflow::NotApplicable, + metadata: GeneratedSparseMmaMetadata::Ordered, + selector: GeneratedSparseMmaSelector::ImmediateZeroOrOne, + }, + requirement: GeneratedTargetRequirement { + minimum_ptx: GeneratedPtxVersion::from_encoded(85), + hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm( + 80, + )]), + }, + backend_requirements: &[ + GeneratedBackendRequirement { + backend: GeneratedIntrinsicBackend::LlvmNvptx, + requirement: GeneratedTargetRequirement { + minimum_ptx: GeneratedPtxVersion::from_encoded(85), + hardware: GeneratedHardwareTarget::AnyOf(&[ + GeneratedHardwareAlternative::MinimumSm(80), + ]), + }, + }, + GeneratedBackendRequirement { + backend: GeneratedIntrinsicBackend::LibNvvm, + requirement: GeneratedTargetRequirement { + minimum_ptx: GeneratedPtxVersion::from_encoded(85), + hardware: GeneratedHardwareTarget::AnyOf(&[ + GeneratedHardwareAlternative::MinimumSm(80), + ]), + }, + }, + ], + selections: &[GeneratedSelectionAlternative { + source_record: "anonymous_19570", + asm: "mma.sp::ordered_metadata.sync.aligned.m16n8k32.row.col.f32.f16.f16.f32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1, $rb2, $rb3}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}},\n\t\t$metadata,\n\t\t$selector;", + predicates: &[ + "Subtarget->getSmVersion() >= 80", + "Subtarget->getPTXVersion() >= 85", + ], + constraints: GeneratedSelectionConstraints { + address_space: None, + immediate_bindings: &[], + }, + }], + llvm: Some(GeneratedLlvmFacts { + properties: &[ + "ImmArg", + "IntrNoCallback", + "IntrNoMem", + "Range", + ], + result_no_undef: false, + result_range: None, + }), + }, ]; diff --git a/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/sreg.rs b/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/sreg.rs index cd79d74d45..b0d6781a7b 100644 --- a/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/sreg.rs +++ b/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/sreg.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. //! Generated intrinsic target records: `sreg` intrinsics. diff --git a/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/stmatrix.rs b/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/stmatrix.rs index 6d164c1470..91bde465a2 100644 --- a/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/stmatrix.rs +++ b/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/stmatrix.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. //! Generated intrinsic target records: `stmatrix` intrinsics. diff --git a/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/sync.rs b/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/sync.rs index b975d25205..62b9020d72 100644 --- a/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/sync.rs +++ b/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/sync.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. //! Generated intrinsic target records: `sync` intrinsics. diff --git a/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/tcgen05_cp.rs b/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/tcgen05_cp.rs index 9ef56eac96..975eb188f2 100644 --- a/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/tcgen05_cp.rs +++ b/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/tcgen05_cp.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. //! Generated intrinsic target records: `tcgen05_cp` intrinsics. diff --git a/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/tcgen05_ld.rs b/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/tcgen05_ld.rs index 3ea8086bd3..734b676879 100644 --- a/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/tcgen05_ld.rs +++ b/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/tcgen05_ld.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. //! Generated intrinsic target records: `tcgen05_ld` intrinsics. diff --git a/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/tcgen05_mma.rs b/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/tcgen05_mma.rs index f272f5698d..16033307b1 100644 --- a/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/tcgen05_mma.rs +++ b/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/tcgen05_mma.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. //! Generated intrinsic target records: `tcgen05_mma` intrinsics. diff --git a/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/tcgen05_mma_ws.rs b/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/tcgen05_mma_ws.rs index d69f2f08fb..a1fa79185b 100644 --- a/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/tcgen05_mma_ws.rs +++ b/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/tcgen05_mma_ws.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. //! Generated intrinsic target records: `tcgen05_mma_ws` intrinsics. diff --git a/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/tcgen05_other.rs b/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/tcgen05_other.rs index da3c031c19..f98bb4fdc8 100644 --- a/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/tcgen05_other.rs +++ b/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/tcgen05_other.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. //! Generated intrinsic target records: `tcgen05_other` intrinsics. diff --git a/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/tcgen05_st.rs b/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/tcgen05_st.rs index c167650a16..36171df3a3 100644 --- a/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/tcgen05_st.rs +++ b/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/tcgen05_st.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. //! Generated intrinsic target records: `tcgen05_st` intrinsics. diff --git a/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/tests/active_mask.rs b/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/tests/active_mask.rs index fe70233f45..497448b5aa 100644 --- a/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/tests/active_mask.rs +++ b/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/tests/active_mask.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. //! Generated intrinsic target tests: `active_mask` intrinsics. diff --git a/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/tests/clc.rs b/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/tests/clc.rs index 77345611d1..09aefc73dc 100644 --- a/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/tests/clc.rs +++ b/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/tests/clc.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. //! Generated intrinsic target tests: `clc` intrinsics. diff --git a/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/tests/cluster_barrier.rs b/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/tests/cluster_barrier.rs index 02aa2e4efc..ae5b18bc3e 100644 --- a/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/tests/cluster_barrier.rs +++ b/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/tests/cluster_barrier.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. //! Generated intrinsic target tests: `cluster_barrier` intrinsics. diff --git a/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/tests/cluster_memory.rs b/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/tests/cluster_memory.rs index 484a30a88d..1b2ee4a8f0 100644 --- a/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/tests/cluster_memory.rs +++ b/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/tests/cluster_memory.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. //! Generated intrinsic target tests: `cluster_memory` intrinsics. diff --git a/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/tests/cp_async.rs b/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/tests/cp_async.rs index 4602722703..bc1b3504c3 100644 --- a/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/tests/cp_async.rs +++ b/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/tests/cp_async.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. //! Generated intrinsic target tests: `cp_async` intrinsics. diff --git a/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/tests/debug_control.rs b/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/tests/debug_control.rs index ce4eec9b42..889b3f6847 100644 --- a/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/tests/debug_control.rs +++ b/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/tests/debug_control.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. //! Generated intrinsic target tests: `debug_control` intrinsics. diff --git a/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/tests/dotprod.rs b/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/tests/dotprod.rs index 54e9369a57..4a3915bd64 100644 --- a/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/tests/dotprod.rs +++ b/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/tests/dotprod.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. //! Generated intrinsic target tests: `dotprod` intrinsics. diff --git a/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/tests/elect.rs b/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/tests/elect.rs index 69ae7a3898..a6238f49bc 100644 --- a/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/tests/elect.rs +++ b/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/tests/elect.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. //! Generated intrinsic target tests: `elect` intrinsics. diff --git a/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/tests/execution_control.rs b/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/tests/execution_control.rs index b5d0e0bd5a..eba36daf92 100644 --- a/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/tests/execution_control.rs +++ b/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/tests/execution_control.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. //! Generated intrinsic target tests: `execution_control` intrinsics. diff --git a/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/tests/extended_minmax.rs b/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/tests/extended_minmax.rs index 1d1102ef54..476ea24cfa 100644 --- a/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/tests/extended_minmax.rs +++ b/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/tests/extended_minmax.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. //! Generated intrinsic target tests: `extended_minmax` intrinsics. diff --git a/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/tests/integer_minmax.rs b/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/tests/integer_minmax.rs index de89a0f95d..2d44a4d0d7 100644 --- a/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/tests/integer_minmax.rs +++ b/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/tests/integer_minmax.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. //! Generated intrinsic target tests: `integer_minmax` intrinsics. diff --git a/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/tests/ldmatrix.rs b/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/tests/ldmatrix.rs index 19840f39fb..da38217c63 100644 --- a/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/tests/ldmatrix.rs +++ b/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/tests/ldmatrix.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. //! Generated intrinsic target tests: `ldmatrix` intrinsics. diff --git a/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/tests/mbarrier_basic.rs b/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/tests/mbarrier_basic.rs index a62e887c34..bd3445de5a 100644 --- a/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/tests/mbarrier_basic.rs +++ b/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/tests/mbarrier_basic.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. //! Generated intrinsic target tests: `mbarrier_basic` intrinsics. diff --git a/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/tests/mbarrier_extended.rs b/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/tests/mbarrier_extended.rs index 362d556a8f..0dc250c691 100644 --- a/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/tests/mbarrier_extended.rs +++ b/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/tests/mbarrier_extended.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. //! Generated intrinsic target tests: `mbarrier_extended` intrinsics. diff --git a/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/tests/mod.rs b/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/tests/mod.rs index b498490d9c..09774ed313 100644 --- a/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/tests/mod.rs +++ b/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/tests/mod.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. //! Generated intrinsic target tests, grouped per family shard. diff --git a/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/tests/movmatrix.rs b/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/tests/movmatrix.rs index da10454fc1..afca446525 100644 --- a/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/tests/movmatrix.rs +++ b/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/tests/movmatrix.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. //! Generated intrinsic target tests: `movmatrix` intrinsics. diff --git a/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/tests/packed_alu.rs b/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/tests/packed_alu.rs index c5bc500488..4685cbacb5 100644 --- a/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/tests/packed_alu.rs +++ b/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/tests/packed_alu.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. //! Generated intrinsic target tests: `packed_alu` intrinsics. diff --git a/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/tests/packed_atomic.rs b/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/tests/packed_atomic.rs index 5dc511cf54..201b8669a6 100644 --- a/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/tests/packed_atomic.rs +++ b/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/tests/packed_atomic.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. //! Generated intrinsic target tests: `packed_atomic` intrinsics. diff --git a/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/tests/packed_conversion.rs b/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/tests/packed_conversion.rs index ce392b5f02..ac8d341c1a 100644 --- a/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/tests/packed_conversion.rs +++ b/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/tests/packed_conversion.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. //! Generated intrinsic target tests: `packed_conversion` intrinsics. diff --git a/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/tests/prmt.rs b/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/tests/prmt.rs index 274ba66e96..19ae1183aa 100644 --- a/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/tests/prmt.rs +++ b/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/tests/prmt.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. //! Generated intrinsic target tests: `prmt` intrinsics. diff --git a/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/tests/redux.rs b/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/tests/redux.rs index 3d096b2d69..26bb8b0c23 100644 --- a/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/tests/redux.rs +++ b/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/tests/redux.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. //! Generated intrinsic target tests: `redux` intrinsics. diff --git a/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/tests/register_mma_float.rs b/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/tests/register_mma_float.rs index 5e0cf7ab89..f7a700f649 100644 --- a/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/tests/register_mma_float.rs +++ b/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/tests/register_mma_float.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. //! Generated intrinsic target tests: `register_mma_float` intrinsics. diff --git a/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/tests/register_mma_s32.rs b/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/tests/register_mma_s32.rs index 11d5af4c0c..adf6d73295 100644 --- a/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/tests/register_mma_s32.rs +++ b/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/tests/register_mma_s32.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. //! Generated intrinsic target tests: `register_mma_s32` intrinsics. diff --git a/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/tests/scalar_arithmetic.rs b/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/tests/scalar_arithmetic.rs index d98b8f47c2..36e82aa4b3 100644 --- a/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/tests/scalar_arithmetic.rs +++ b/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/tests/scalar_arithmetic.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. //! Generated intrinsic target tests: `scalar_arithmetic` intrinsics. diff --git a/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/tests/scalar_conversion.rs b/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/tests/scalar_conversion.rs index e8032ea7f2..8e9dc0e2c7 100644 --- a/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/tests/scalar_conversion.rs +++ b/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/tests/scalar_conversion.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. //! Generated intrinsic target tests: `scalar_conversion` intrinsics. diff --git a/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/tests/scalar_math.rs b/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/tests/scalar_math.rs index 27f1f6cfe8..808ddfea01 100644 --- a/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/tests/scalar_math.rs +++ b/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/tests/scalar_math.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. //! Generated intrinsic target tests: `scalar_math` intrinsics. diff --git a/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/tests/sparse_mma.rs b/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/tests/sparse_mma.rs index 81cd8eabac..4e30a9b56f 100644 --- a/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/tests/sparse_mma.rs +++ b/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/tests/sparse_mma.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. //! Generated intrinsic target tests: `sparse_mma` intrinsics. @@ -9372,3 +9372,611 @@ fn mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e5m2_e5m2_f16_target_matches ] as &[&str] ); } + +#[test] +fn mma_sp_ordered_metadata_m16n8k8_f32_tf32_target_matches_the_catalog() { + let target = generated_intrinsic_target_by_marker("v1:i1018").unwrap(); + assert_eq!(target.id, "mma_sp_ordered_metadata_m16n8k8_f32_tf32"); + assert_eq!(target.abi_id, "i1018"); + assert_eq!(target.dialect_op, "nvvm.sparse_mma"); + assert_eq!( + target.variant, + GeneratedIntrinsicVariant::SparseMma { + shape: GeneratedSparseMmaShape::M16n8k8, + accumulator: GeneratedSparseMmaAccumulator::F32, + a_element: GeneratedSparseMmaElement::Tf32, + b_element: GeneratedSparseMmaElement::Tf32, + a_layout: GeneratedSparseMmaLayout::Row, + b_layout: GeneratedSparseMmaLayout::Col, + overflow: GeneratedSparseMmaOverflow::NotApplicable, + metadata: GeneratedSparseMmaMetadata::Ordered, + selector: GeneratedSparseMmaSelector::ImmediateZeroThroughThree + } + ); + assert_eq!(target.requirement.minimum_ptx.encoded(), 85); + assert_eq!( + target.requirement.hardware, + const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(80)]) } + ); + assert_eq!( + target.backend_requirements, + const { + &[ + GeneratedBackendRequirement { + backend: GeneratedIntrinsicBackend::LlvmNvptx, + requirement: GeneratedTargetRequirement { + minimum_ptx: GeneratedPtxVersion::from_encoded(85), + hardware: GeneratedHardwareTarget::AnyOf(&[ + GeneratedHardwareAlternative::MinimumSm(80), + ]), + }, + }, + GeneratedBackendRequirement { + backend: GeneratedIntrinsicBackend::LibNvvm, + requirement: GeneratedTargetRequirement { + minimum_ptx: GeneratedPtxVersion::from_encoded(85), + hardware: GeneratedHardwareTarget::AnyOf(&[ + GeneratedHardwareAlternative::MinimumSm(80), + ]), + }, + }, + ] + } + ); + assert_eq!( + target.selections, + &[GeneratedSelectionAlternative { + source_record: "anonymous_19540", + asm: "mma.sp::ordered_metadata.sync.aligned.m16n8k8.row.col.f32.tf32.tf32.f32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1}},\n\t\t{{$rb0, $rb1}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}},\n\t\t$metadata,\n\t\t$selector;", + predicates: &[ + "Subtarget->getSmVersion() >= 80", + "Subtarget->getPTXVersion() >= 85" + ], + constraints: GeneratedSelectionConstraints { + address_space: None, + immediate_bindings: &[] + } + },] + ); + assert_eq!( + target.llvm.unwrap().properties, + &[ + "ImmArg", + "IntrNoCallback", + "IntrNoMem", + "Range" + ] as &[&str] + ); +} + +#[test] +fn mma_sp_ordered_metadata_m16n8k16_f32_tf32_target_matches_the_catalog() { + let target = generated_intrinsic_target_by_marker("v1:i1019").unwrap(); + assert_eq!(target.id, "mma_sp_ordered_metadata_m16n8k16_f32_tf32"); + assert_eq!(target.abi_id, "i1019"); + assert_eq!(target.dialect_op, "nvvm.sparse_mma"); + assert_eq!( + target.variant, + GeneratedIntrinsicVariant::SparseMma { + shape: GeneratedSparseMmaShape::M16n8k16, + accumulator: GeneratedSparseMmaAccumulator::F32, + a_element: GeneratedSparseMmaElement::Tf32, + b_element: GeneratedSparseMmaElement::Tf32, + a_layout: GeneratedSparseMmaLayout::Row, + b_layout: GeneratedSparseMmaLayout::Col, + overflow: GeneratedSparseMmaOverflow::NotApplicable, + metadata: GeneratedSparseMmaMetadata::Ordered, + selector: GeneratedSparseMmaSelector::ImmediateZeroOrOne + } + ); + assert_eq!(target.requirement.minimum_ptx.encoded(), 85); + assert_eq!( + target.requirement.hardware, + const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(80)]) } + ); + assert_eq!( + target.backend_requirements, + const { + &[ + GeneratedBackendRequirement { + backend: GeneratedIntrinsicBackend::LlvmNvptx, + requirement: GeneratedTargetRequirement { + minimum_ptx: GeneratedPtxVersion::from_encoded(85), + hardware: GeneratedHardwareTarget::AnyOf(&[ + GeneratedHardwareAlternative::MinimumSm(80), + ]), + }, + }, + GeneratedBackendRequirement { + backend: GeneratedIntrinsicBackend::LibNvvm, + requirement: GeneratedTargetRequirement { + minimum_ptx: GeneratedPtxVersion::from_encoded(85), + hardware: GeneratedHardwareTarget::AnyOf(&[ + GeneratedHardwareAlternative::MinimumSm(80), + ]), + }, + }, + ] + } + ); + assert_eq!( + target.selections, + &[GeneratedSelectionAlternative { + source_record: "anonymous_19546", + asm: "mma.sp::ordered_metadata.sync.aligned.m16n8k16.row.col.f32.tf32.tf32.f32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1, $rb2, $rb3}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}},\n\t\t$metadata,\n\t\t$selector;", + predicates: &[ + "Subtarget->getSmVersion() >= 80", + "Subtarget->getPTXVersion() >= 85" + ], + constraints: GeneratedSelectionConstraints { + address_space: None, + immediate_bindings: &[] + } + },] + ); + assert_eq!( + target.llvm.unwrap().properties, + &[ + "ImmArg", + "IntrNoCallback", + "IntrNoMem", + "Range" + ] as &[&str] + ); +} + +#[test] +fn mma_sp_ordered_metadata_m16n8k16_f32_bf16_target_matches_the_catalog() { + let target = generated_intrinsic_target_by_marker("v1:i1020").unwrap(); + assert_eq!(target.id, "mma_sp_ordered_metadata_m16n8k16_f32_bf16"); + assert_eq!(target.abi_id, "i1020"); + assert_eq!(target.dialect_op, "nvvm.sparse_mma"); + assert_eq!( + target.variant, + GeneratedIntrinsicVariant::SparseMma { + shape: GeneratedSparseMmaShape::M16n8k16, + accumulator: GeneratedSparseMmaAccumulator::F32, + a_element: GeneratedSparseMmaElement::Bf16, + b_element: GeneratedSparseMmaElement::Bf16, + a_layout: GeneratedSparseMmaLayout::Row, + b_layout: GeneratedSparseMmaLayout::Col, + overflow: GeneratedSparseMmaOverflow::NotApplicable, + metadata: GeneratedSparseMmaMetadata::Ordered, + selector: GeneratedSparseMmaSelector::ImmediateZeroThroughThree + } + ); + assert_eq!(target.requirement.minimum_ptx.encoded(), 85); + assert_eq!( + target.requirement.hardware, + const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(80)]) } + ); + assert_eq!( + target.backend_requirements, + const { + &[ + GeneratedBackendRequirement { + backend: GeneratedIntrinsicBackend::LlvmNvptx, + requirement: GeneratedTargetRequirement { + minimum_ptx: GeneratedPtxVersion::from_encoded(85), + hardware: GeneratedHardwareTarget::AnyOf(&[ + GeneratedHardwareAlternative::MinimumSm(80), + ]), + }, + }, + GeneratedBackendRequirement { + backend: GeneratedIntrinsicBackend::LibNvvm, + requirement: GeneratedTargetRequirement { + minimum_ptx: GeneratedPtxVersion::from_encoded(85), + hardware: GeneratedHardwareTarget::AnyOf(&[ + GeneratedHardwareAlternative::MinimumSm(80), + ]), + }, + }, + ] + } + ); + assert_eq!( + target.selections, + &[GeneratedSelectionAlternative { + source_record: "anonymous_19524", + asm: "mma.sp::ordered_metadata.sync.aligned.m16n8k16.row.col.f32.bf16.bf16.f32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1}},\n\t\t{{$rb0, $rb1}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}},\n\t\t$metadata,\n\t\t$selector;", + predicates: &[ + "Subtarget->getSmVersion() >= 80", + "Subtarget->getPTXVersion() >= 85" + ], + constraints: GeneratedSelectionConstraints { + address_space: None, + immediate_bindings: &[] + } + },] + ); + assert_eq!( + target.llvm.unwrap().properties, + &[ + "ImmArg", + "IntrNoCallback", + "IntrNoMem", + "Range" + ] as &[&str] + ); +} + +#[test] +fn mma_sp_ordered_metadata_m16n8k16_f16_f16_target_matches_the_catalog() { + let target = generated_intrinsic_target_by_marker("v1:i1021").unwrap(); + assert_eq!(target.id, "mma_sp_ordered_metadata_m16n8k16_f16_f16"); + assert_eq!(target.abi_id, "i1021"); + assert_eq!(target.dialect_op, "nvvm.sparse_mma"); + assert_eq!( + target.variant, + GeneratedIntrinsicVariant::SparseMma { + shape: GeneratedSparseMmaShape::M16n8k16, + accumulator: GeneratedSparseMmaAccumulator::F16, + a_element: GeneratedSparseMmaElement::F16, + b_element: GeneratedSparseMmaElement::F16, + a_layout: GeneratedSparseMmaLayout::Row, + b_layout: GeneratedSparseMmaLayout::Col, + overflow: GeneratedSparseMmaOverflow::NotApplicable, + metadata: GeneratedSparseMmaMetadata::Ordered, + selector: GeneratedSparseMmaSelector::ImmediateZeroThroughThree + } + ); + assert_eq!(target.requirement.minimum_ptx.encoded(), 85); + assert_eq!( + target.requirement.hardware, + const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(80)]) } + ); + assert_eq!( + target.backend_requirements, + const { + &[ + GeneratedBackendRequirement { + backend: GeneratedIntrinsicBackend::LlvmNvptx, + requirement: GeneratedTargetRequirement { + minimum_ptx: GeneratedPtxVersion::from_encoded(85), + hardware: GeneratedHardwareTarget::AnyOf(&[ + GeneratedHardwareAlternative::MinimumSm(80), + ]), + }, + }, + GeneratedBackendRequirement { + backend: GeneratedIntrinsicBackend::LibNvvm, + requirement: GeneratedTargetRequirement { + minimum_ptx: GeneratedPtxVersion::from_encoded(85), + hardware: GeneratedHardwareTarget::AnyOf(&[ + GeneratedHardwareAlternative::MinimumSm(80), + ]), + }, + }, + ] + } + ); + assert_eq!( + target.selections, + &[GeneratedSelectionAlternative { + source_record: "anonymous_19554", + asm: "mma.sp::ordered_metadata.sync.aligned.m16n8k16.row.col.f16.f16.f16.f16\n\t\t{{$rd0, $rd1}},\n\t\t{{$ra0, $ra1}},\n\t\t{{$rb0, $rb1}},\n\t\t{{$rc0, $rc1}},\n\t\t$metadata,\n\t\t$selector;", + predicates: &[ + "Subtarget->getSmVersion() >= 80", + "Subtarget->getPTXVersion() >= 85" + ], + constraints: GeneratedSelectionConstraints { + address_space: None, + immediate_bindings: &[] + } + },] + ); + assert_eq!( + target.llvm.unwrap().properties, + &[ + "ImmArg", + "IntrNoCallback", + "IntrNoMem", + "Range" + ] as &[&str] + ); +} + +#[test] +fn mma_sp_ordered_metadata_m16n8k16_f32_f16_target_matches_the_catalog() { + let target = generated_intrinsic_target_by_marker("v1:i1022").unwrap(); + assert_eq!(target.id, "mma_sp_ordered_metadata_m16n8k16_f32_f16"); + assert_eq!(target.abi_id, "i1022"); + assert_eq!(target.dialect_op, "nvvm.sparse_mma"); + assert_eq!( + target.variant, + GeneratedIntrinsicVariant::SparseMma { + shape: GeneratedSparseMmaShape::M16n8k16, + accumulator: GeneratedSparseMmaAccumulator::F32, + a_element: GeneratedSparseMmaElement::F16, + b_element: GeneratedSparseMmaElement::F16, + a_layout: GeneratedSparseMmaLayout::Row, + b_layout: GeneratedSparseMmaLayout::Col, + overflow: GeneratedSparseMmaOverflow::NotApplicable, + metadata: GeneratedSparseMmaMetadata::Ordered, + selector: GeneratedSparseMmaSelector::ImmediateZeroThroughThree + } + ); + assert_eq!(target.requirement.minimum_ptx.encoded(), 85); + assert_eq!( + target.requirement.hardware, + const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(80)]) } + ); + assert_eq!( + target.backend_requirements, + const { + &[ + GeneratedBackendRequirement { + backend: GeneratedIntrinsicBackend::LlvmNvptx, + requirement: GeneratedTargetRequirement { + minimum_ptx: GeneratedPtxVersion::from_encoded(85), + hardware: GeneratedHardwareTarget::AnyOf(&[ + GeneratedHardwareAlternative::MinimumSm(80), + ]), + }, + }, + GeneratedBackendRequirement { + backend: GeneratedIntrinsicBackend::LibNvvm, + requirement: GeneratedTargetRequirement { + minimum_ptx: GeneratedPtxVersion::from_encoded(85), + hardware: GeneratedHardwareTarget::AnyOf(&[ + GeneratedHardwareAlternative::MinimumSm(80), + ]), + }, + }, + ] + } + ); + assert_eq!( + target.selections, + &[GeneratedSelectionAlternative { + source_record: "anonymous_19558", + asm: "mma.sp::ordered_metadata.sync.aligned.m16n8k16.row.col.f32.f16.f16.f32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1}},\n\t\t{{$rb0, $rb1}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}},\n\t\t$metadata,\n\t\t$selector;", + predicates: &[ + "Subtarget->getSmVersion() >= 80", + "Subtarget->getPTXVersion() >= 85" + ], + constraints: GeneratedSelectionConstraints { + address_space: None, + immediate_bindings: &[] + } + },] + ); + assert_eq!( + target.llvm.unwrap().properties, + &[ + "ImmArg", + "IntrNoCallback", + "IntrNoMem", + "Range" + ] as &[&str] + ); +} + +#[test] +fn mma_sp_ordered_metadata_m16n8k32_f32_bf16_target_matches_the_catalog() { + let target = generated_intrinsic_target_by_marker("v1:i1023").unwrap(); + assert_eq!(target.id, "mma_sp_ordered_metadata_m16n8k32_f32_bf16"); + assert_eq!(target.abi_id, "i1023"); + assert_eq!(target.dialect_op, "nvvm.sparse_mma"); + assert_eq!( + target.variant, + GeneratedIntrinsicVariant::SparseMma { + shape: GeneratedSparseMmaShape::M16n8k32, + accumulator: GeneratedSparseMmaAccumulator::F32, + a_element: GeneratedSparseMmaElement::Bf16, + b_element: GeneratedSparseMmaElement::Bf16, + a_layout: GeneratedSparseMmaLayout::Row, + b_layout: GeneratedSparseMmaLayout::Col, + overflow: GeneratedSparseMmaOverflow::NotApplicable, + metadata: GeneratedSparseMmaMetadata::Ordered, + selector: GeneratedSparseMmaSelector::ImmediateZeroOrOne + } + ); + assert_eq!(target.requirement.minimum_ptx.encoded(), 85); + assert_eq!( + target.requirement.hardware, + const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(80)]) } + ); + assert_eq!( + target.backend_requirements, + const { + &[ + GeneratedBackendRequirement { + backend: GeneratedIntrinsicBackend::LlvmNvptx, + requirement: GeneratedTargetRequirement { + minimum_ptx: GeneratedPtxVersion::from_encoded(85), + hardware: GeneratedHardwareTarget::AnyOf(&[ + GeneratedHardwareAlternative::MinimumSm(80), + ]), + }, + }, + GeneratedBackendRequirement { + backend: GeneratedIntrinsicBackend::LibNvvm, + requirement: GeneratedTargetRequirement { + minimum_ptx: GeneratedPtxVersion::from_encoded(85), + hardware: GeneratedHardwareTarget::AnyOf(&[ + GeneratedHardwareAlternative::MinimumSm(80), + ]), + }, + }, + ] + } + ); + assert_eq!( + target.selections, + &[GeneratedSelectionAlternative { + source_record: "anonymous_19532", + asm: "mma.sp::ordered_metadata.sync.aligned.m16n8k32.row.col.f32.bf16.bf16.f32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1, $rb2, $rb3}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}},\n\t\t$metadata,\n\t\t$selector;", + predicates: &[ + "Subtarget->getSmVersion() >= 80", + "Subtarget->getPTXVersion() >= 85" + ], + constraints: GeneratedSelectionConstraints { + address_space: None, + immediate_bindings: &[] + } + },] + ); + assert_eq!( + target.llvm.unwrap().properties, + &[ + "ImmArg", + "IntrNoCallback", + "IntrNoMem", + "Range" + ] as &[&str] + ); +} + +#[test] +fn mma_sp_ordered_metadata_m16n8k32_f16_f16_target_matches_the_catalog() { + let target = generated_intrinsic_target_by_marker("v1:i1024").unwrap(); + assert_eq!(target.id, "mma_sp_ordered_metadata_m16n8k32_f16_f16"); + assert_eq!(target.abi_id, "i1024"); + assert_eq!(target.dialect_op, "nvvm.sparse_mma"); + assert_eq!( + target.variant, + GeneratedIntrinsicVariant::SparseMma { + shape: GeneratedSparseMmaShape::M16n8k32, + accumulator: GeneratedSparseMmaAccumulator::F16, + a_element: GeneratedSparseMmaElement::F16, + b_element: GeneratedSparseMmaElement::F16, + a_layout: GeneratedSparseMmaLayout::Row, + b_layout: GeneratedSparseMmaLayout::Col, + overflow: GeneratedSparseMmaOverflow::NotApplicable, + metadata: GeneratedSparseMmaMetadata::Ordered, + selector: GeneratedSparseMmaSelector::ImmediateZeroOrOne + } + ); + assert_eq!(target.requirement.minimum_ptx.encoded(), 85); + assert_eq!( + target.requirement.hardware, + const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(80)]) } + ); + assert_eq!( + target.backend_requirements, + const { + &[ + GeneratedBackendRequirement { + backend: GeneratedIntrinsicBackend::LlvmNvptx, + requirement: GeneratedTargetRequirement { + minimum_ptx: GeneratedPtxVersion::from_encoded(85), + hardware: GeneratedHardwareTarget::AnyOf(&[ + GeneratedHardwareAlternative::MinimumSm(80), + ]), + }, + }, + GeneratedBackendRequirement { + backend: GeneratedIntrinsicBackend::LibNvvm, + requirement: GeneratedTargetRequirement { + minimum_ptx: GeneratedPtxVersion::from_encoded(85), + hardware: GeneratedHardwareTarget::AnyOf(&[ + GeneratedHardwareAlternative::MinimumSm(80), + ]), + }, + }, + ] + } + ); + assert_eq!( + target.selections, + &[GeneratedSelectionAlternative { + source_record: "anonymous_19566", + asm: "mma.sp::ordered_metadata.sync.aligned.m16n8k32.row.col.f16.f16.f16.f16\n\t\t{{$rd0, $rd1}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1, $rb2, $rb3}},\n\t\t{{$rc0, $rc1}},\n\t\t$metadata,\n\t\t$selector;", + predicates: &[ + "Subtarget->getSmVersion() >= 80", + "Subtarget->getPTXVersion() >= 85" + ], + constraints: GeneratedSelectionConstraints { + address_space: None, + immediate_bindings: &[] + } + },] + ); + assert_eq!( + target.llvm.unwrap().properties, + &[ + "ImmArg", + "IntrNoCallback", + "IntrNoMem", + "Range" + ] as &[&str] + ); +} + +#[test] +fn mma_sp_ordered_metadata_m16n8k32_f32_f16_target_matches_the_catalog() { + let target = generated_intrinsic_target_by_marker("v1:i1025").unwrap(); + assert_eq!(target.id, "mma_sp_ordered_metadata_m16n8k32_f32_f16"); + assert_eq!(target.abi_id, "i1025"); + assert_eq!(target.dialect_op, "nvvm.sparse_mma"); + assert_eq!( + target.variant, + GeneratedIntrinsicVariant::SparseMma { + shape: GeneratedSparseMmaShape::M16n8k32, + accumulator: GeneratedSparseMmaAccumulator::F32, + a_element: GeneratedSparseMmaElement::F16, + b_element: GeneratedSparseMmaElement::F16, + a_layout: GeneratedSparseMmaLayout::Row, + b_layout: GeneratedSparseMmaLayout::Col, + overflow: GeneratedSparseMmaOverflow::NotApplicable, + metadata: GeneratedSparseMmaMetadata::Ordered, + selector: GeneratedSparseMmaSelector::ImmediateZeroOrOne + } + ); + assert_eq!(target.requirement.minimum_ptx.encoded(), 85); + assert_eq!( + target.requirement.hardware, + const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(80)]) } + ); + assert_eq!( + target.backend_requirements, + const { + &[ + GeneratedBackendRequirement { + backend: GeneratedIntrinsicBackend::LlvmNvptx, + requirement: GeneratedTargetRequirement { + minimum_ptx: GeneratedPtxVersion::from_encoded(85), + hardware: GeneratedHardwareTarget::AnyOf(&[ + GeneratedHardwareAlternative::MinimumSm(80), + ]), + }, + }, + GeneratedBackendRequirement { + backend: GeneratedIntrinsicBackend::LibNvvm, + requirement: GeneratedTargetRequirement { + minimum_ptx: GeneratedPtxVersion::from_encoded(85), + hardware: GeneratedHardwareTarget::AnyOf(&[ + GeneratedHardwareAlternative::MinimumSm(80), + ]), + }, + }, + ] + } + ); + assert_eq!( + target.selections, + &[GeneratedSelectionAlternative { + source_record: "anonymous_19570", + asm: "mma.sp::ordered_metadata.sync.aligned.m16n8k32.row.col.f32.f16.f16.f32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1, $rb2, $rb3}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}},\n\t\t$metadata,\n\t\t$selector;", + predicates: &[ + "Subtarget->getSmVersion() >= 80", + "Subtarget->getPTXVersion() >= 85" + ], + constraints: GeneratedSelectionConstraints { + address_space: None, + immediate_bindings: &[] + } + },] + ); + assert_eq!( + target.llvm.unwrap().properties, + &[ + "ImmArg", + "IntrNoCallback", + "IntrNoMem", + "Range" + ] as &[&str] + ); +} diff --git a/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/tests/sreg.rs b/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/tests/sreg.rs index 9b2cc82b77..5d31d8e34e 100644 --- a/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/tests/sreg.rs +++ b/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/tests/sreg.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. //! Generated intrinsic target tests: `sreg` intrinsics. diff --git a/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/tests/stmatrix.rs b/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/tests/stmatrix.rs index 53d860a8fd..787d115ba5 100644 --- a/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/tests/stmatrix.rs +++ b/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/tests/stmatrix.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. //! Generated intrinsic target tests: `stmatrix` intrinsics. diff --git a/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/tests/sync.rs b/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/tests/sync.rs index d11ee40123..f3bcf80c39 100644 --- a/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/tests/sync.rs +++ b/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/tests/sync.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. //! Generated intrinsic target tests: `sync` intrinsics. diff --git a/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/tests/tcgen05_cp.rs b/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/tests/tcgen05_cp.rs index b619091f16..3503c59bca 100644 --- a/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/tests/tcgen05_cp.rs +++ b/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/tests/tcgen05_cp.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. //! Generated intrinsic target tests: `tcgen05_cp` intrinsics. diff --git a/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/tests/tcgen05_ld.rs b/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/tests/tcgen05_ld.rs index 15d04bb4b5..8d0a4b43f2 100644 --- a/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/tests/tcgen05_ld.rs +++ b/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/tests/tcgen05_ld.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. //! Generated intrinsic target tests: `tcgen05_ld` intrinsics. diff --git a/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/tests/tcgen05_mma.rs b/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/tests/tcgen05_mma.rs index 22534aa05c..0afb9a2b09 100644 --- a/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/tests/tcgen05_mma.rs +++ b/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/tests/tcgen05_mma.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. //! Generated intrinsic target tests: `tcgen05_mma` intrinsics. diff --git a/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/tests/tcgen05_mma_ws.rs b/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/tests/tcgen05_mma_ws.rs index c82fc49167..16f0e56e39 100644 --- a/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/tests/tcgen05_mma_ws.rs +++ b/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/tests/tcgen05_mma_ws.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. //! Generated intrinsic target tests: `tcgen05_mma_ws` intrinsics. diff --git a/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/tests/tcgen05_other.rs b/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/tests/tcgen05_other.rs index bd28656aa3..58594ab388 100644 --- a/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/tests/tcgen05_other.rs +++ b/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/tests/tcgen05_other.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. //! Generated intrinsic target tests: `tcgen05_other` intrinsics. diff --git a/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/tests/tcgen05_st.rs b/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/tests/tcgen05_st.rs index d6d3607d8e..a66483b4f6 100644 --- a/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/tests/tcgen05_st.rs +++ b/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/tests/tcgen05_st.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. //! Generated intrinsic target tests: `tcgen05_st` intrinsics. diff --git a/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/tests/tma.rs b/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/tests/tma.rs index d33374744d..5991cade11 100644 --- a/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/tests/tma.rs +++ b/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/tests/tma.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. //! Generated intrinsic target tests: `tma` intrinsics. diff --git a/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/tests/vote.rs b/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/tests/vote.rs index dad5f2307e..ddf7051009 100644 --- a/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/tests/vote.rs +++ b/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/tests/vote.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. //! Generated intrinsic target tests: `vote` intrinsics. diff --git a/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/tests/warp_barrier.rs b/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/tests/warp_barrier.rs index f5693c9606..842093bb03 100644 --- a/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/tests/warp_barrier.rs +++ b/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/tests/warp_barrier.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. //! Generated intrinsic target tests: `warp_barrier` intrinsics. diff --git a/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/tests/warp_match.rs b/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/tests/warp_match.rs index 992f067881..c4de4eb5bc 100644 --- a/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/tests/warp_match.rs +++ b/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/tests/warp_match.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. //! Generated intrinsic target tests: `warp_match` intrinsics. diff --git a/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/tests/warp_shuffle.rs b/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/tests/warp_shuffle.rs index a484f7f540..dfcaa6dccc 100644 --- a/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/tests/warp_shuffle.rs +++ b/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/tests/warp_shuffle.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. //! Generated intrinsic target tests: `warp_shuffle` intrinsics. diff --git a/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/tests/wgmma_control.rs b/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/tests/wgmma_control.rs index 2932f7086b..54fee0d73d 100644 --- a/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/tests/wgmma_control.rs +++ b/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/tests/wgmma_control.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. //! Generated intrinsic target tests: `wgmma_control` intrinsics. diff --git a/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/tma.rs b/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/tma.rs index 27dfb98ae6..33aff22dc2 100644 --- a/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/tma.rs +++ b/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/tma.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. //! Generated intrinsic target records: `tma` intrinsics. diff --git a/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/vote.rs b/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/vote.rs index daecd90947..9d8a12ddbe 100644 --- a/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/vote.rs +++ b/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/vote.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. //! Generated intrinsic target records: `vote` intrinsics. diff --git a/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/warp_barrier.rs b/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/warp_barrier.rs index f4900f4233..9cd16903ef 100644 --- a/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/warp_barrier.rs +++ b/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/warp_barrier.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. //! Generated intrinsic target records: `warp_barrier` intrinsics. diff --git a/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/warp_match.rs b/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/warp_match.rs index b4f1513349..c2cc875f8d 100644 --- a/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/warp_match.rs +++ b/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/warp_match.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. //! Generated intrinsic target records: `warp_match` intrinsics. diff --git a/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/warp_shuffle.rs b/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/warp_shuffle.rs index 021b54df30..b21964fd8b 100644 --- a/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/warp_shuffle.rs +++ b/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/warp_shuffle.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. //! Generated intrinsic target records: `warp_shuffle` intrinsics. diff --git a/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/wgmma_control.rs b/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/wgmma_control.rs index 1c4f4ab6f1..7fdb800976 100644 --- a/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/wgmma_control.rs +++ b/crates/cuda-oxide-codegen/src/generated_intrinsic_targets/wgmma_control.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. //! Generated intrinsic target records: `wgmma_control` intrinsics. diff --git a/crates/dialect-nvvm/src/ops/generated/active_mask.rs b/crates/dialect-nvvm/src/ops/generated/active_mask.rs index 5cf207ac55..b1352980ef 100644 --- a/crates/dialect-nvvm/src/ops/generated/active_mask.rs +++ b/crates/dialect-nvvm/src/ops/generated/active_mask.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. //! Structural operation for the generated active warp mask. diff --git a/crates/dialect-nvvm/src/ops/generated/clc.rs b/crates/dialect-nvvm/src/ops/generated/clc.rs index 994e7ab199..11142925b7 100644 --- a/crates/dialect-nvvm/src/ops/generated/clc.rs +++ b/crates/dialect-nvvm/src/ops/generated/clc.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. //! Generated Cluster Launch Control operations. diff --git a/crates/dialect-nvvm/src/ops/generated/cluster_barrier.rs b/crates/dialect-nvvm/src/ops/generated/cluster_barrier.rs index 633884475c..731acf5f1b 100644 --- a/crates/dialect-nvvm/src/ops/generated/cluster_barrier.rs +++ b/crates/dialect-nvvm/src/ops/generated/cluster_barrier.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. //! Generated operations for the closed cluster-barrier family. diff --git a/crates/dialect-nvvm/src/ops/generated/cluster_memory.rs b/crates/dialect-nvvm/src/ops/generated/cluster_memory.rs index 78e0701237..0a434b43a6 100644 --- a/crates/dialect-nvvm/src/ops/generated/cluster_memory.rs +++ b/crates/dialect-nvvm/src/ops/generated/cluster_memory.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. //! Structural operations for cluster address mapping and remote shared reads. diff --git a/crates/dialect-nvvm/src/ops/generated/cp_async.rs b/crates/dialect-nvvm/src/ops/generated/cp_async.rs index 2c23432c94..de211e6799 100644 --- a/crates/dialect-nvvm/src/ops/generated/cp_async.rs +++ b/crates/dialect-nvvm/src/ops/generated/cp_async.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. //! Structural operations for classic `cp.async` instructions. diff --git a/crates/dialect-nvvm/src/ops/generated/debug_control.rs b/crates/dialect-nvvm/src/ops/generated/debug_control.rs index 268063e6c3..30c29f6348 100644 --- a/crates/dialect-nvvm/src/ops/generated/debug_control.rs +++ b/crates/dialect-nvvm/src/ops/generated/debug_control.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. //! Structural operations for generated PTX debug controls. diff --git a/crates/dialect-nvvm/src/ops/generated/dotprod.rs b/crates/dialect-nvvm/src/ops/generated/dotprod.rs index 57f4256938..20eb60a931 100644 --- a/crates/dialect-nvvm/src/ops/generated/dotprod.rs +++ b/crates/dialect-nvvm/src/ops/generated/dotprod.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. //! Structural operations for generated packed integer dot products. diff --git a/crates/dialect-nvvm/src/ops/generated/elect.rs b/crates/dialect-nvvm/src/ops/generated/elect.rs index 1897de702c..4051a3a087 100644 --- a/crates/dialect-nvvm/src/ops/generated/elect.rs +++ b/crates/dialect-nvvm/src/ops/generated/elect.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. //! Generated warp leader-election operation. diff --git a/crates/dialect-nvvm/src/ops/generated/execution_control.rs b/crates/dialect-nvvm/src/ops/generated/execution_control.rs index 9acc8e905a..8253bb1764 100644 --- a/crates/dialect-nvvm/src/ops/generated/execution_control.rs +++ b/crates/dialect-nvvm/src/ops/generated/execution_control.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. //! Generated counted-barrier, grid-dependency, and register-control operations. diff --git a/crates/dialect-nvvm/src/ops/generated/extended_minmax.rs b/crates/dialect-nvvm/src/ops/generated/extended_minmax.rs index 58321963c7..380d603c36 100644 --- a/crates/dialect-nvvm/src/ops/generated/extended_minmax.rs +++ b/crates/dialect-nvvm/src/ops/generated/extended_minmax.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. //! One structural operation for extended floating-point min/max. diff --git a/crates/dialect-nvvm/src/ops/generated/integer_minmax.rs b/crates/dialect-nvvm/src/ops/generated/integer_minmax.rs index 66820b6f33..38eefde618 100644 --- a/crates/dialect-nvvm/src/ops/generated/integer_minmax.rs +++ b/crates/dialect-nvvm/src/ops/generated/integer_minmax.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. //! Structural operations for generated extended integer min/max. diff --git a/crates/dialect-nvvm/src/ops/generated/ldmatrix.rs b/crates/dialect-nvvm/src/ops/generated/ldmatrix.rs index 3cbce7a3f3..d31095c805 100644 --- a/crates/dialect-nvvm/src/ops/generated/ldmatrix.rs +++ b/crates/dialect-nvvm/src/ops/generated/ldmatrix.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. //! Structural operation and compatibility carriers for generated `ldmatrix`. diff --git a/crates/dialect-nvvm/src/ops/generated/mbarrier_basic.rs b/crates/dialect-nvvm/src/ops/generated/mbarrier_basic.rs index 861fada5cb..ff9d7372ce 100644 --- a/crates/dialect-nvvm/src/ops/generated/mbarrier_basic.rs +++ b/crates/dialect-nvvm/src/ops/generated/mbarrier_basic.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. //! Structural operations for the basic shared-memory mbarrier lifecycle. diff --git a/crates/dialect-nvvm/src/ops/generated/mbarrier_extended.rs b/crates/dialect-nvvm/src/ops/generated/mbarrier_extended.rs index 074c74f0ba..ed4f59c72c 100644 --- a/crates/dialect-nvvm/src/ops/generated/mbarrier_extended.rs +++ b/crates/dialect-nvvm/src/ops/generated/mbarrier_extended.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. //! Structural operations for extended mbarrier and async-proxy instructions. diff --git a/crates/dialect-nvvm/src/ops/generated/mod.rs b/crates/dialect-nvvm/src/ops/generated/mod.rs index e42d9026ed..a6a8ba99ce 100644 --- a/crates/dialect-nvvm/src/ops/generated/mod.rs +++ b/crates/dialect-nvvm/src/ops/generated/mod.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. mod active_mask; diff --git a/crates/dialect-nvvm/src/ops/generated/movmatrix.rs b/crates/dialect-nvvm/src/ops/generated/movmatrix.rs index c5f55cf30d..09dc0a2dcb 100644 --- a/crates/dialect-nvvm/src/ops/generated/movmatrix.rs +++ b/crates/dialect-nvvm/src/ops/generated/movmatrix.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. //! Structural operation for generated in-register matrix transpose. diff --git a/crates/dialect-nvvm/src/ops/generated/packed_alu.rs b/crates/dialect-nvvm/src/ops/generated/packed_alu.rs index 4d72f1098e..49dabb7e40 100644 --- a/crates/dialect-nvvm/src/ops/generated/packed_alu.rs +++ b/crates/dialect-nvvm/src/ops/generated/packed_alu.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. //! Structural operations for generated packed floating-point arithmetic. diff --git a/crates/dialect-nvvm/src/ops/generated/packed_atomic.rs b/crates/dialect-nvvm/src/ops/generated/packed_atomic.rs index f5249e8e13..ec056b9278 100644 --- a/crates/dialect-nvvm/src/ops/generated/packed_atomic.rs +++ b/crates/dialect-nvvm/src/ops/generated/packed_atomic.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. //! One structural operation for the closed generated packed-atomic family. diff --git a/crates/dialect-nvvm/src/ops/generated/packed_conversion.rs b/crates/dialect-nvvm/src/ops/generated/packed_conversion.rs index c6a531f4ae..dea3bf5f66 100644 --- a/crates/dialect-nvvm/src/ops/generated/packed_conversion.rs +++ b/crates/dialect-nvvm/src/ops/generated/packed_conversion.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. //! Structural operation for generated packed conversion. diff --git a/crates/dialect-nvvm/src/ops/generated/prmt.rs b/crates/dialect-nvvm/src/ops/generated/prmt.rs index 33d10c9c66..97924ef5c1 100644 --- a/crates/dialect-nvvm/src/ops/generated/prmt.rs +++ b/crates/dialect-nvvm/src/ops/generated/prmt.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. //! One structural operation for the closed generated `prmt` family. diff --git a/crates/dialect-nvvm/src/ops/generated/redux.rs b/crates/dialect-nvvm/src/ops/generated/redux.rs index 10628978f0..34751311c8 100644 --- a/crates/dialect-nvvm/src/ops/generated/redux.rs +++ b/crates/dialect-nvvm/src/ops/generated/redux.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. //! Structural NVVM operations for the closed generated `redux.sync` family. diff --git a/crates/dialect-nvvm/src/ops/generated/register_mma.rs b/crates/dialect-nvvm/src/ops/generated/register_mma.rs index f125651dc7..2a3ac72f48 100644 --- a/crates/dialect-nvvm/src/ops/generated/register_mma.rs +++ b/crates/dialect-nvvm/src/ops/generated/register_mma.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. //! One structural operation for generated register-only `mma.sync` variants. diff --git a/crates/dialect-nvvm/src/ops/generated/scalar_arithmetic.rs b/crates/dialect-nvvm/src/ops/generated/scalar_arithmetic.rs index 6b2e1442f5..aae15b119c 100644 --- a/crates/dialect-nvvm/src/ops/generated/scalar_arithmetic.rs +++ b/crates/dialect-nvvm/src/ops/generated/scalar_arithmetic.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. //! One structural operation for generated scalar arithmetic. diff --git a/crates/dialect-nvvm/src/ops/generated/scalar_conversion.rs b/crates/dialect-nvvm/src/ops/generated/scalar_conversion.rs index 9b3b384250..28c3c29632 100644 --- a/crates/dialect-nvvm/src/ops/generated/scalar_conversion.rs +++ b/crates/dialect-nvvm/src/ops/generated/scalar_conversion.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. //! One structural operation for generated `f32` to TF32 conversions. diff --git a/crates/dialect-nvvm/src/ops/generated/scalar_math.rs b/crates/dialect-nvvm/src/ops/generated/scalar_math.rs index 3ce7f0b810..7440089e98 100644 --- a/crates/dialect-nvvm/src/ops/generated/scalar_math.rs +++ b/crates/dialect-nvvm/src/ops/generated/scalar_math.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. //! One structural operation for generated scalar math. diff --git a/crates/dialect-nvvm/src/ops/generated/sparse_mma.rs b/crates/dialect-nvvm/src/ops/generated/sparse_mma.rs index 1cd9638817..761dd5a461 100644 --- a/crates/dialect-nvvm/src/ops/generated/sparse_mma.rs +++ b/crates/dialect-nvvm/src/ops/generated/sparse_mma.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. //! One structural operation for generated sparse MMA variants. @@ -32,6 +32,8 @@ use pliron_derive::{pliron_attr, pliron_op}; #[pliron_attr(name = "nvvm.sparse_mma_shape", format, verifier = "succ")] #[derive(PartialEq, Eq, Clone, Debug, Hash)] pub enum SparseMmaShapeAttr { + M16n8k8, + M16n8k16, M16n8k32, M16n8k64, M16n8k128, @@ -48,6 +50,9 @@ pub enum SparseMmaAccumulatorAttr { #[pliron_attr(name = "nvvm.sparse_mma_element", format, verifier = "succ")] #[derive(PartialEq, Eq, Clone, Debug, Hash)] pub enum SparseMmaElementAttr { + F16, + Bf16, + Tf32, E2m1, E2m3, E3m2, @@ -83,7 +88,9 @@ pub enum SparseMmaMetadataAttr { #[pliron_attr(name = "nvvm.sparse_mma_selector", format, verifier = "succ")] #[derive(PartialEq, Eq, Clone, Debug, Hash)] +#[allow(clippy::enum_variant_names)] pub enum SparseMmaSelectorAttr { + ImmediateZeroThroughThree, ImmediateZeroOrOne, ImmediateZero, } @@ -1502,6 +1509,225 @@ impl Verify for SparseMmaOp { ], 1, ), + ( + Some(&SparseMmaShapeAttr::M16n8k16), + Some(&SparseMmaAccumulatorAttr::F16), + Some(&SparseMmaElementAttr::F16), + Some(&SparseMmaElementAttr::F16), + Some(&SparseMmaLayoutAttr::Row), + Some(&SparseMmaLayoutAttr::Col), + Some(&SparseMmaOverflowAttr::NotApplicable), + Some(&SparseMmaMetadataAttr::Ordered), + Some(&SparseMmaSelectorAttr::ImmediateZeroThroughThree), + ) => ( + &[ + MmaCarrier::U32, + MmaCarrier::U32, + MmaCarrier::U32, + MmaCarrier::U32, + MmaCarrier::U32, + MmaCarrier::U32, + MmaCarrier::U32, + MmaCarrier::U32, + ], + &[MmaCarrier::U32, MmaCarrier::U32], + 4, + ), + ( + Some(&SparseMmaShapeAttr::M16n8k16), + Some(&SparseMmaAccumulatorAttr::F32), + Some(&SparseMmaElementAttr::Bf16), + Some(&SparseMmaElementAttr::Bf16), + Some(&SparseMmaLayoutAttr::Row), + Some(&SparseMmaLayoutAttr::Col), + Some(&SparseMmaOverflowAttr::NotApplicable), + Some(&SparseMmaMetadataAttr::Ordered), + Some(&SparseMmaSelectorAttr::ImmediateZeroThroughThree), + ) => ( + &[ + MmaCarrier::F32, + MmaCarrier::F32, + MmaCarrier::F32, + MmaCarrier::F32, + MmaCarrier::U32, + MmaCarrier::U32, + MmaCarrier::U32, + MmaCarrier::U32, + MmaCarrier::U32, + MmaCarrier::U32, + ], + &[ + MmaCarrier::F32, + MmaCarrier::F32, + MmaCarrier::F32, + MmaCarrier::F32, + ], + 4, + ), + ( + Some(&SparseMmaShapeAttr::M16n8k16), + Some(&SparseMmaAccumulatorAttr::F32), + Some(&SparseMmaElementAttr::F16), + Some(&SparseMmaElementAttr::F16), + Some(&SparseMmaLayoutAttr::Row), + Some(&SparseMmaLayoutAttr::Col), + Some(&SparseMmaOverflowAttr::NotApplicable), + Some(&SparseMmaMetadataAttr::Ordered), + Some(&SparseMmaSelectorAttr::ImmediateZeroThroughThree), + ) => ( + &[ + MmaCarrier::F32, + MmaCarrier::F32, + MmaCarrier::F32, + MmaCarrier::F32, + MmaCarrier::U32, + MmaCarrier::U32, + MmaCarrier::U32, + MmaCarrier::U32, + MmaCarrier::U32, + MmaCarrier::U32, + ], + &[ + MmaCarrier::F32, + MmaCarrier::F32, + MmaCarrier::F32, + MmaCarrier::F32, + ], + 4, + ), + ( + Some(&SparseMmaShapeAttr::M16n8k16), + Some(&SparseMmaAccumulatorAttr::F32), + Some(&SparseMmaElementAttr::Tf32), + Some(&SparseMmaElementAttr::Tf32), + Some(&SparseMmaLayoutAttr::Row), + Some(&SparseMmaLayoutAttr::Col), + Some(&SparseMmaOverflowAttr::NotApplicable), + Some(&SparseMmaMetadataAttr::Ordered), + Some(&SparseMmaSelectorAttr::ImmediateZeroOrOne), + ) => ( + &[ + MmaCarrier::F32, + MmaCarrier::F32, + MmaCarrier::F32, + MmaCarrier::F32, + MmaCarrier::U32, + MmaCarrier::U32, + MmaCarrier::U32, + MmaCarrier::U32, + MmaCarrier::U32, + MmaCarrier::U32, + MmaCarrier::U32, + MmaCarrier::U32, + MmaCarrier::U32, + MmaCarrier::U32, + ], + &[ + MmaCarrier::F32, + MmaCarrier::F32, + MmaCarrier::F32, + MmaCarrier::F32, + ], + 2, + ), + ( + Some(&SparseMmaShapeAttr::M16n8k32), + Some(&SparseMmaAccumulatorAttr::F16), + Some(&SparseMmaElementAttr::F16), + Some(&SparseMmaElementAttr::F16), + Some(&SparseMmaLayoutAttr::Row), + Some(&SparseMmaLayoutAttr::Col), + Some(&SparseMmaOverflowAttr::NotApplicable), + Some(&SparseMmaMetadataAttr::Ordered), + Some(&SparseMmaSelectorAttr::ImmediateZeroOrOne), + ) => ( + &[ + MmaCarrier::U32, + MmaCarrier::U32, + MmaCarrier::U32, + MmaCarrier::U32, + MmaCarrier::U32, + MmaCarrier::U32, + MmaCarrier::U32, + MmaCarrier::U32, + MmaCarrier::U32, + MmaCarrier::U32, + MmaCarrier::U32, + MmaCarrier::U32, + ], + &[MmaCarrier::U32, MmaCarrier::U32], + 2, + ), + ( + Some(&SparseMmaShapeAttr::M16n8k32), + Some(&SparseMmaAccumulatorAttr::F32), + Some(&SparseMmaElementAttr::Bf16), + Some(&SparseMmaElementAttr::Bf16), + Some(&SparseMmaLayoutAttr::Row), + Some(&SparseMmaLayoutAttr::Col), + Some(&SparseMmaOverflowAttr::NotApplicable), + Some(&SparseMmaMetadataAttr::Ordered), + Some(&SparseMmaSelectorAttr::ImmediateZeroOrOne), + ) => ( + &[ + MmaCarrier::F32, + MmaCarrier::F32, + MmaCarrier::F32, + MmaCarrier::F32, + MmaCarrier::U32, + MmaCarrier::U32, + MmaCarrier::U32, + MmaCarrier::U32, + MmaCarrier::U32, + MmaCarrier::U32, + MmaCarrier::U32, + MmaCarrier::U32, + MmaCarrier::U32, + MmaCarrier::U32, + ], + &[ + MmaCarrier::F32, + MmaCarrier::F32, + MmaCarrier::F32, + MmaCarrier::F32, + ], + 2, + ), + ( + Some(&SparseMmaShapeAttr::M16n8k32), + Some(&SparseMmaAccumulatorAttr::F32), + Some(&SparseMmaElementAttr::F16), + Some(&SparseMmaElementAttr::F16), + Some(&SparseMmaLayoutAttr::Row), + Some(&SparseMmaLayoutAttr::Col), + Some(&SparseMmaOverflowAttr::NotApplicable), + Some(&SparseMmaMetadataAttr::Ordered), + Some(&SparseMmaSelectorAttr::ImmediateZeroOrOne), + ) => ( + &[ + MmaCarrier::F32, + MmaCarrier::F32, + MmaCarrier::F32, + MmaCarrier::F32, + MmaCarrier::U32, + MmaCarrier::U32, + MmaCarrier::U32, + MmaCarrier::U32, + MmaCarrier::U32, + MmaCarrier::U32, + MmaCarrier::U32, + MmaCarrier::U32, + MmaCarrier::U32, + MmaCarrier::U32, + ], + &[ + MmaCarrier::F32, + MmaCarrier::F32, + MmaCarrier::F32, + MmaCarrier::F32, + ], + 2, + ), ( Some(&SparseMmaShapeAttr::M16n8k32), Some(&SparseMmaAccumulatorAttr::S32), @@ -3853,6 +4079,37 @@ impl Verify for SparseMmaOp { ], 1, ), + ( + Some(&SparseMmaShapeAttr::M16n8k8), + Some(&SparseMmaAccumulatorAttr::F32), + Some(&SparseMmaElementAttr::Tf32), + Some(&SparseMmaElementAttr::Tf32), + Some(&SparseMmaLayoutAttr::Row), + Some(&SparseMmaLayoutAttr::Col), + Some(&SparseMmaOverflowAttr::NotApplicable), + Some(&SparseMmaMetadataAttr::Ordered), + Some(&SparseMmaSelectorAttr::ImmediateZeroThroughThree), + ) => ( + &[ + MmaCarrier::F32, + MmaCarrier::F32, + MmaCarrier::F32, + MmaCarrier::F32, + MmaCarrier::U32, + MmaCarrier::U32, + MmaCarrier::U32, + MmaCarrier::U32, + MmaCarrier::U32, + MmaCarrier::U32, + ], + &[ + MmaCarrier::F32, + MmaCarrier::F32, + MmaCarrier::F32, + MmaCarrier::F32, + ], + 4, + ), _ => { return verify_err!( op.loc(), diff --git a/crates/dialect-nvvm/src/ops/generated/sreg.rs b/crates/dialect-nvvm/src/ops/generated/sreg.rs index 793b96f0eb..b68617a48f 100644 --- a/crates/dialect-nvvm/src/ops/generated/sreg.rs +++ b/crates/dialect-nvvm/src/ops/generated/sreg.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. //! Structural NVVM operations for generated special-register reads. diff --git a/crates/dialect-nvvm/src/ops/generated/stmatrix.rs b/crates/dialect-nvvm/src/ops/generated/stmatrix.rs index 7b6e0e34fa..5ca338f3ea 100644 --- a/crates/dialect-nvvm/src/ops/generated/stmatrix.rs +++ b/crates/dialect-nvvm/src/ops/generated/stmatrix.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. //! Structural operations for the four generated `stmatrix` stores. diff --git a/crates/dialect-nvvm/src/ops/generated/sync.rs b/crates/dialect-nvvm/src/ops/generated/sync.rs index 59a159d2c1..fb001334ab 100644 --- a/crates/dialect-nvvm/src/ops/generated/sync.rs +++ b/crates/dialect-nvvm/src/ops/generated/sync.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. //! Structural operation for generated CTA synchronization. diff --git a/crates/dialect-nvvm/src/ops/generated/tcgen05.rs b/crates/dialect-nvvm/src/ops/generated/tcgen05.rs index e5a44a0389..57e5f6f024 100644 --- a/crates/dialect-nvvm/src/ops/generated/tcgen05.rs +++ b/crates/dialect-nvvm/src/ops/generated/tcgen05.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. //! Generated Tensor Core Generation 5 operations. diff --git a/crates/dialect-nvvm/src/ops/generated/tma.rs b/crates/dialect-nvvm/src/ops/generated/tma.rs index 11c8de69e3..4a93cf7a23 100644 --- a/crates/dialect-nvvm/src/ops/generated/tma.rs +++ b/crates/dialect-nvvm/src/ops/generated/tma.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. //! Generated Tensor Memory Accelerator operations. diff --git a/crates/dialect-nvvm/src/ops/generated/vote.rs b/crates/dialect-nvvm/src/ops/generated/vote.rs index a128ed5182..1d003190a1 100644 --- a/crates/dialect-nvvm/src/ops/generated/vote.rs +++ b/crates/dialect-nvvm/src/ops/generated/vote.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. //! Structural operations for the generated `vote.sync` family. diff --git a/crates/dialect-nvvm/src/ops/generated/warp_barrier.rs b/crates/dialect-nvvm/src/ops/generated/warp_barrier.rs index 873bbec90e..a7e4169d16 100644 --- a/crates/dialect-nvvm/src/ops/generated/warp_barrier.rs +++ b/crates/dialect-nvvm/src/ops/generated/warp_barrier.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. //! Structural operation for generated warp synchronization. diff --git a/crates/dialect-nvvm/src/ops/generated/warp_match.rs b/crates/dialect-nvvm/src/ops/generated/warp_match.rs index 21b2f33144..3551d80c49 100644 --- a/crates/dialect-nvvm/src/ops/generated/warp_match.rs +++ b/crates/dialect-nvvm/src/ops/generated/warp_match.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. //! Structural operations for the generated `match.sync` family. diff --git a/crates/dialect-nvvm/src/ops/generated/warp_shuffle.rs b/crates/dialect-nvvm/src/ops/generated/warp_shuffle.rs index 0e965adb10..d87f6f5fcd 100644 --- a/crates/dialect-nvvm/src/ops/generated/warp_shuffle.rs +++ b/crates/dialect-nvvm/src/ops/generated/warp_shuffle.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. //! Structural operations for the generated `shfl.sync` family. diff --git a/crates/dialect-nvvm/src/ops/generated/wgmma_control.rs b/crates/dialect-nvvm/src/ops/generated/wgmma_control.rs index dabeb18ab7..a4b1df4869 100644 --- a/crates/dialect-nvvm/src/ops/generated/wgmma_control.rs +++ b/crates/dialect-nvvm/src/ops/generated/wgmma_control.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. //! Structural operations for generated WGMMA controls. diff --git a/crates/mir-importer/src/translator/terminator/intrinsics/generated/active_mask.rs b/crates/mir-importer/src/translator/terminator/intrinsics/generated/active_mask.rs index 81b188fb5e..521f4ee605 100644 --- a/crates/mir-importer/src/translator/terminator/intrinsics/generated/active_mask.rs +++ b/crates/mir-importer/src/translator/terminator/intrinsics/generated/active_mask.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. //! Generated raw/compatibility dispatch arms: `active_mask` intrinsics. diff --git a/crates/mir-importer/src/translator/terminator/intrinsics/generated/clc.rs b/crates/mir-importer/src/translator/terminator/intrinsics/generated/clc.rs index 24b2e81587..0b258f101d 100644 --- a/crates/mir-importer/src/translator/terminator/intrinsics/generated/clc.rs +++ b/crates/mir-importer/src/translator/terminator/intrinsics/generated/clc.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. //! Generated raw/compatibility dispatch arms: `clc` intrinsics. diff --git a/crates/mir-importer/src/translator/terminator/intrinsics/generated/cluster_barrier.rs b/crates/mir-importer/src/translator/terminator/intrinsics/generated/cluster_barrier.rs index 322a44b852..62be37edad 100644 --- a/crates/mir-importer/src/translator/terminator/intrinsics/generated/cluster_barrier.rs +++ b/crates/mir-importer/src/translator/terminator/intrinsics/generated/cluster_barrier.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. //! Generated raw/compatibility dispatch arms: `cluster_barrier` intrinsics. diff --git a/crates/mir-importer/src/translator/terminator/intrinsics/generated/cluster_memory.rs b/crates/mir-importer/src/translator/terminator/intrinsics/generated/cluster_memory.rs index d7039946ec..77a67a0bd6 100644 --- a/crates/mir-importer/src/translator/terminator/intrinsics/generated/cluster_memory.rs +++ b/crates/mir-importer/src/translator/terminator/intrinsics/generated/cluster_memory.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. //! Generated raw/compatibility dispatch arms: `cluster_memory` intrinsics. diff --git a/crates/mir-importer/src/translator/terminator/intrinsics/generated/cp_async.rs b/crates/mir-importer/src/translator/terminator/intrinsics/generated/cp_async.rs index e74ad12196..98e00ade0c 100644 --- a/crates/mir-importer/src/translator/terminator/intrinsics/generated/cp_async.rs +++ b/crates/mir-importer/src/translator/terminator/intrinsics/generated/cp_async.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. //! Generated raw/compatibility dispatch arms: `cp_async` intrinsics. diff --git a/crates/mir-importer/src/translator/terminator/intrinsics/generated/debug_control.rs b/crates/mir-importer/src/translator/terminator/intrinsics/generated/debug_control.rs index 81a1a19074..38a9b93732 100644 --- a/crates/mir-importer/src/translator/terminator/intrinsics/generated/debug_control.rs +++ b/crates/mir-importer/src/translator/terminator/intrinsics/generated/debug_control.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. //! Generated raw/compatibility dispatch arms: `debug_control` intrinsics. diff --git a/crates/mir-importer/src/translator/terminator/intrinsics/generated/dotprod.rs b/crates/mir-importer/src/translator/terminator/intrinsics/generated/dotprod.rs index 6714783295..cf20bc1f09 100644 --- a/crates/mir-importer/src/translator/terminator/intrinsics/generated/dotprod.rs +++ b/crates/mir-importer/src/translator/terminator/intrinsics/generated/dotprod.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. //! Generated raw/compatibility dispatch arms: `dotprod` intrinsics. diff --git a/crates/mir-importer/src/translator/terminator/intrinsics/generated/elect.rs b/crates/mir-importer/src/translator/terminator/intrinsics/generated/elect.rs index fc2c33000e..3b0a6e2440 100644 --- a/crates/mir-importer/src/translator/terminator/intrinsics/generated/elect.rs +++ b/crates/mir-importer/src/translator/terminator/intrinsics/generated/elect.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. //! Generated raw/compatibility dispatch arms: `elect` intrinsics. diff --git a/crates/mir-importer/src/translator/terminator/intrinsics/generated/execution_control.rs b/crates/mir-importer/src/translator/terminator/intrinsics/generated/execution_control.rs index 13742e48d3..bd106ff960 100644 --- a/crates/mir-importer/src/translator/terminator/intrinsics/generated/execution_control.rs +++ b/crates/mir-importer/src/translator/terminator/intrinsics/generated/execution_control.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. //! Generated raw/compatibility dispatch arms: `execution_control` intrinsics. diff --git a/crates/mir-importer/src/translator/terminator/intrinsics/generated/extended_minmax.rs b/crates/mir-importer/src/translator/terminator/intrinsics/generated/extended_minmax.rs index 9d02b9455f..d4866b198f 100644 --- a/crates/mir-importer/src/translator/terminator/intrinsics/generated/extended_minmax.rs +++ b/crates/mir-importer/src/translator/terminator/intrinsics/generated/extended_minmax.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. //! Generated raw/compatibility dispatch arms: `extended_minmax` intrinsics. diff --git a/crates/mir-importer/src/translator/terminator/intrinsics/generated/helpers.rs b/crates/mir-importer/src/translator/terminator/intrinsics/generated/helpers.rs index ffa40376d8..2d5556235f 100644 --- a/crates/mir-importer/src/translator/terminator/intrinsics/generated/helpers.rs +++ b/crates/mir-importer/src/translator/terminator/intrinsics/generated/helpers.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. //! Shared glue for the generated intrinsic dispatch shards. @@ -215,9 +215,11 @@ pub(super) fn import_generated_tcgen05_store_operands( #[derive(Clone, Copy)] pub(super) enum GeneratedMmaImportAdapter { C2U32A2U32B1U32ToD2U32, + C2U32A2U32B2U32ToD2U32, C2U32A4U32B2U32ToD2U32, C2U32A4U32B4U32ToD2U32, C4F32A2U32B1U32ToD4F32, + C4F32A2U32B2U32ToD4F32, C4F32A4U32B2U32ToD4F32, C4F32A4U32B4U32ToD4F32, C2F64A1F64B1F64ToD2F64, @@ -297,6 +299,9 @@ pub(super) fn import_generated_mma_operands( GeneratedMmaImportAdapter::C2U32A2U32B1U32ToD2U32 => { (u32_ty, 2, u32_ty, 2, true, u32_ty, 1, false, u32_ty, 2) } + GeneratedMmaImportAdapter::C2U32A2U32B2U32ToD2U32 => { + (u32_ty, 2, u32_ty, 2, true, u32_ty, 2, true, u32_ty, 2) + } GeneratedMmaImportAdapter::C2U32A4U32B2U32ToD2U32 => { (u32_ty, 2, u32_ty, 4, true, u32_ty, 2, true, u32_ty, 2) } @@ -306,6 +311,9 @@ pub(super) fn import_generated_mma_operands( GeneratedMmaImportAdapter::C4F32A2U32B1U32ToD4F32 => { (f32_ty, 4, u32_ty, 2, true, u32_ty, 1, false, f32_ty, 4) } + GeneratedMmaImportAdapter::C4F32A2U32B2U32ToD4F32 => { + (f32_ty, 4, u32_ty, 2, true, u32_ty, 2, true, f32_ty, 4) + } GeneratedMmaImportAdapter::C4F32A4U32B2U32ToD4F32 => { (f32_ty, 4, u32_ty, 4, true, u32_ty, 2, true, f32_ty, 4) } diff --git a/crates/mir-importer/src/translator/terminator/intrinsics/generated/integer_minmax.rs b/crates/mir-importer/src/translator/terminator/intrinsics/generated/integer_minmax.rs index 388f2683a5..061df42a98 100644 --- a/crates/mir-importer/src/translator/terminator/intrinsics/generated/integer_minmax.rs +++ b/crates/mir-importer/src/translator/terminator/intrinsics/generated/integer_minmax.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. //! Generated raw/compatibility dispatch arms: `integer_minmax` intrinsics. diff --git a/crates/mir-importer/src/translator/terminator/intrinsics/generated/ldmatrix.rs b/crates/mir-importer/src/translator/terminator/intrinsics/generated/ldmatrix.rs index 4343a2135c..c65eb69ee4 100644 --- a/crates/mir-importer/src/translator/terminator/intrinsics/generated/ldmatrix.rs +++ b/crates/mir-importer/src/translator/terminator/intrinsics/generated/ldmatrix.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. //! Generated raw/compatibility dispatch arms: `ldmatrix` intrinsics. diff --git a/crates/mir-importer/src/translator/terminator/intrinsics/generated/mbarrier_basic.rs b/crates/mir-importer/src/translator/terminator/intrinsics/generated/mbarrier_basic.rs index 15d3e3aaff..4ce8cf0a78 100644 --- a/crates/mir-importer/src/translator/terminator/intrinsics/generated/mbarrier_basic.rs +++ b/crates/mir-importer/src/translator/terminator/intrinsics/generated/mbarrier_basic.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. //! Generated raw/compatibility dispatch arms: `mbarrier_basic` intrinsics. diff --git a/crates/mir-importer/src/translator/terminator/intrinsics/generated/mbarrier_extended.rs b/crates/mir-importer/src/translator/terminator/intrinsics/generated/mbarrier_extended.rs index 9d6562a64f..08c23edb33 100644 --- a/crates/mir-importer/src/translator/terminator/intrinsics/generated/mbarrier_extended.rs +++ b/crates/mir-importer/src/translator/terminator/intrinsics/generated/mbarrier_extended.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. //! Generated raw/compatibility dispatch arms: `mbarrier_extended` intrinsics. diff --git a/crates/mir-importer/src/translator/terminator/intrinsics/generated/mod.rs b/crates/mir-importer/src/translator/terminator/intrinsics/generated/mod.rs index 828dc7c5e4..86bbcc0417 100644 --- a/crates/mir-importer/src/translator/terminator/intrinsics/generated/mod.rs +++ b/crates/mir-importer/src/translator/terminator/intrinsics/generated/mod.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. //! Generated raw/compatibility path dispatch for CUDA intrinsics. @@ -1294,6 +1294,20 @@ pub fn is_generated_intrinsic_path(name: &str) -> bool { | "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k128_s32_u4_s4_satfinite" | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0209" | "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k128_s32_u4_satfinite" + | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i1021" + | "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k16_f16_f16" + | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i1020" + | "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k16_f32_bf16" + | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i1022" + | "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k16_f32_f16" + | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i1019" + | "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k16_f32_tf32" + | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i1024" + | "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k32_f16_f16" + | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i1023" + | "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k32_f32_bf16" + | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i1025" + | "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k32_f32_f16" | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0171" | "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k32_s32_s8" | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0175" @@ -1442,6 +1456,8 @@ pub fn is_generated_intrinsic_path(name: &str) -> bool { | "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_s32_u8_s8_satfinite" | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0185" | "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_s32_u8_satfinite" + | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i1018" + | "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k8_f32_tf32" | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0305" | "cuda_device::wmma::movmatrix_trans_b16" | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0066" @@ -2764,6 +2780,13 @@ pub fn is_raw_generated_intrinsic_path(name: &str) -> bool { | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0206" | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0210" | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0209" + | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i1021" + | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i1020" + | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i1022" + | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i1019" + | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i1024" + | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i1023" + | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i1025" | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0171" | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0175" | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0172" @@ -2838,6 +2861,7 @@ pub fn is_raw_generated_intrinsic_path(name: &str) -> bool { | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0182" | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0186" | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0185" + | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i1018" | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0305" | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0066" | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0076" @@ -4389,6 +4413,20 @@ pub fn generated_intrinsic_marker(name: &str) -> Option<&'static str> { | "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k128_s32_u4_satfinite" => { Some("v1:i0209") } + "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i1021" + | "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k16_f16_f16" => Some("v1:i1021"), + "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i1020" + | "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k16_f32_bf16" => Some("v1:i1020"), + "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i1022" + | "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k16_f32_f16" => Some("v1:i1022"), + "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i1019" + | "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k16_f32_tf32" => Some("v1:i1019"), + "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i1024" + | "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k32_f16_f16" => Some("v1:i1024"), + "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i1023" + | "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k32_f32_bf16" => Some("v1:i1023"), + "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i1025" + | "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k32_f32_f16" => Some("v1:i1025"), "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0171" | "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k32_s32_s8" => Some("v1:i0171"), "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0175" @@ -4661,6 +4699,8 @@ pub fn generated_intrinsic_marker(name: &str) -> Option<&'static str> { | "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_s32_u8_satfinite" => { Some("v1:i0185") } + "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i1018" + | "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k8_f32_tf32" => Some("v1:i1018"), "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0305" | "cuda_device::wmma::movmatrix_trans_b16" => Some("v1:i0305"), "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0066" diff --git a/crates/mir-importer/src/translator/terminator/intrinsics/generated/movmatrix.rs b/crates/mir-importer/src/translator/terminator/intrinsics/generated/movmatrix.rs index 5dc53db45a..c6547fda02 100644 --- a/crates/mir-importer/src/translator/terminator/intrinsics/generated/movmatrix.rs +++ b/crates/mir-importer/src/translator/terminator/intrinsics/generated/movmatrix.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. //! Generated raw/compatibility dispatch arms: `movmatrix` intrinsics. diff --git a/crates/mir-importer/src/translator/terminator/intrinsics/generated/packed_alu.rs b/crates/mir-importer/src/translator/terminator/intrinsics/generated/packed_alu.rs index ae4c125784..b4970b1e69 100644 --- a/crates/mir-importer/src/translator/terminator/intrinsics/generated/packed_alu.rs +++ b/crates/mir-importer/src/translator/terminator/intrinsics/generated/packed_alu.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. //! Generated raw/compatibility dispatch arms: `packed_alu` intrinsics. diff --git a/crates/mir-importer/src/translator/terminator/intrinsics/generated/packed_atomic.rs b/crates/mir-importer/src/translator/terminator/intrinsics/generated/packed_atomic.rs index 7ff58494bf..2d11bcb6b8 100644 --- a/crates/mir-importer/src/translator/terminator/intrinsics/generated/packed_atomic.rs +++ b/crates/mir-importer/src/translator/terminator/intrinsics/generated/packed_atomic.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. //! Generated raw/compatibility dispatch arms: `packed_atomic` intrinsics. diff --git a/crates/mir-importer/src/translator/terminator/intrinsics/generated/packed_conversion.rs b/crates/mir-importer/src/translator/terminator/intrinsics/generated/packed_conversion.rs index 9b66bc3b07..d4d87efabf 100644 --- a/crates/mir-importer/src/translator/terminator/intrinsics/generated/packed_conversion.rs +++ b/crates/mir-importer/src/translator/terminator/intrinsics/generated/packed_conversion.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. //! Generated raw/compatibility dispatch arms: `packed_conversion` intrinsics. diff --git a/crates/mir-importer/src/translator/terminator/intrinsics/generated/prmt.rs b/crates/mir-importer/src/translator/terminator/intrinsics/generated/prmt.rs index 6d8f7066fd..d1b9e3e03d 100644 --- a/crates/mir-importer/src/translator/terminator/intrinsics/generated/prmt.rs +++ b/crates/mir-importer/src/translator/terminator/intrinsics/generated/prmt.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. //! Generated raw/compatibility dispatch arms: `prmt` intrinsics. diff --git a/crates/mir-importer/src/translator/terminator/intrinsics/generated/redux.rs b/crates/mir-importer/src/translator/terminator/intrinsics/generated/redux.rs index 73ff1098aa..771031a6c4 100644 --- a/crates/mir-importer/src/translator/terminator/intrinsics/generated/redux.rs +++ b/crates/mir-importer/src/translator/terminator/intrinsics/generated/redux.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. //! Generated raw/compatibility dispatch arms: `redux` intrinsics. diff --git a/crates/mir-importer/src/translator/terminator/intrinsics/generated/register_mma.rs b/crates/mir-importer/src/translator/terminator/intrinsics/generated/register_mma.rs index 088b43da86..fee6bbecf5 100644 --- a/crates/mir-importer/src/translator/terminator/intrinsics/generated/register_mma.rs +++ b/crates/mir-importer/src/translator/terminator/intrinsics/generated/register_mma.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. //! Generated raw/compatibility dispatch arms: `register_mma` intrinsics. diff --git a/crates/mir-importer/src/translator/terminator/intrinsics/generated/scalar_arithmetic.rs b/crates/mir-importer/src/translator/terminator/intrinsics/generated/scalar_arithmetic.rs index f650d2f9fd..b0cde6adfa 100644 --- a/crates/mir-importer/src/translator/terminator/intrinsics/generated/scalar_arithmetic.rs +++ b/crates/mir-importer/src/translator/terminator/intrinsics/generated/scalar_arithmetic.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. //! Generated raw/compatibility dispatch arms: `scalar_arithmetic` intrinsics. diff --git a/crates/mir-importer/src/translator/terminator/intrinsics/generated/scalar_conversion.rs b/crates/mir-importer/src/translator/terminator/intrinsics/generated/scalar_conversion.rs index 5bd1e63537..c9de33c3ff 100644 --- a/crates/mir-importer/src/translator/terminator/intrinsics/generated/scalar_conversion.rs +++ b/crates/mir-importer/src/translator/terminator/intrinsics/generated/scalar_conversion.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. //! Generated raw/compatibility dispatch arms: `scalar_conversion` intrinsics. diff --git a/crates/mir-importer/src/translator/terminator/intrinsics/generated/scalar_math.rs b/crates/mir-importer/src/translator/terminator/intrinsics/generated/scalar_math.rs index 242fae11de..170a7a2e49 100644 --- a/crates/mir-importer/src/translator/terminator/intrinsics/generated/scalar_math.rs +++ b/crates/mir-importer/src/translator/terminator/intrinsics/generated/scalar_math.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. //! Generated raw/compatibility dispatch arms: `scalar_math` intrinsics. diff --git a/crates/mir-importer/src/translator/terminator/intrinsics/generated/sparse_mma.rs b/crates/mir-importer/src/translator/terminator/intrinsics/generated/sparse_mma.rs index 2ef72ecd88..6597e8a997 100644 --- a/crates/mir-importer/src/translator/terminator/intrinsics/generated/sparse_mma.rs +++ b/crates/mir-importer/src/translator/terminator/intrinsics/generated/sparse_mma.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. //! Generated raw/compatibility dispatch arms: `sparse_mma` intrinsics. @@ -3162,6 +3162,564 @@ pub(super) fn try_dispatch( "mma_sp_ordered_metadata_m16n8k128_s32_u4_satfinite call without target block", )?)) } + "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i1021" + | "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k16_f16_f16" => { + require_arity(name, args.len(), 5, &loc)?; + if !matches!(&args[4], mir::Operand::Constant(_)) { + return input_err!( + loc, + TranslationErr::unsupported( + "sparse MMA selector must be the compile-time constant 0, 1, 2, or 3" + .to_owned() + ) + ); + } + let (mut operands, last_op, result_ty, result_count) = import_generated_mma_operands( + ctx, + body, + args, + block_ptr, + prev_op, + value_map, + loc.clone(), + GeneratedMmaImportAdapter::C2U32A2U32B2U32ToD2U32, + )?; + let (metadata, last_op) = rvalue::translate_operand( + ctx, + body, + &args[3], + value_map, + block_ptr, + Some(last_op), + loc.clone(), + )?; + operands.push(metadata); + let (selector_value, last_op) = rvalue::translate_operand( + ctx, + body, + &args[4], + value_map, + block_ptr, + last_op, + loc.clone(), + )?; + operands.push(selector_value); + let mma = Operation::new( + ctx, + SparseMmaOp::get_concrete_op_info(), + vec![result_ty; result_count], + operands, + vec![], + 0, + ); + mma.deref_mut(ctx).set_loc(loc.clone()); + let mma = SparseMmaOp::new(mma); + mma.set_attr_nvvm_sparse_mma_shape(ctx, SparseMmaShapeAttr::M16n8k16); + mma.set_attr_nvvm_sparse_mma_accumulator(ctx, SparseMmaAccumulatorAttr::F16); + mma.set_attr_nvvm_sparse_mma_a_element(ctx, SparseMmaElementAttr::F16); + mma.set_attr_nvvm_sparse_mma_b_element(ctx, SparseMmaElementAttr::F16); + mma.set_attr_nvvm_sparse_mma_a_layout(ctx, SparseMmaLayoutAttr::Row); + mma.set_attr_nvvm_sparse_mma_b_layout(ctx, SparseMmaLayoutAttr::Col); + mma.set_attr_nvvm_sparse_mma_overflow(ctx, SparseMmaOverflowAttr::NotApplicable); + mma.set_attr_nvvm_sparse_mma_metadata(ctx, SparseMmaMetadataAttr::Ordered); + mma.set_attr_nvvm_sparse_mma_selector( + ctx, + SparseMmaSelectorAttr::ImmediateZeroThroughThree, + ); + let mma = mma.get_operation(); + helpers::set_generated_intrinsic_marker(ctx, mma, "v1:i1021"); + helpers::insert_op(ctx, mma, block_ptr, last_op); + let (result, last_op) = + bundle_generated_mma_results(ctx, mma, result_ty, result_count, loc.clone()); + Ok(Some(helpers::emit_store_result_and_goto( + ctx, + destination, + result, + target, + block_ptr, + last_op, + value_map, + block_map, + loc, + "mma_sp_ordered_metadata_m16n8k16_f16_f16 call without target block", + )?)) + } + "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i1020" + | "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k16_f32_bf16" => { + require_arity(name, args.len(), 5, &loc)?; + if !matches!(&args[4], mir::Operand::Constant(_)) { + return input_err!( + loc, + TranslationErr::unsupported( + "sparse MMA selector must be the compile-time constant 0, 1, 2, or 3" + .to_owned() + ) + ); + } + let (mut operands, last_op, result_ty, result_count) = import_generated_mma_operands( + ctx, + body, + args, + block_ptr, + prev_op, + value_map, + loc.clone(), + GeneratedMmaImportAdapter::C4F32A2U32B2U32ToD4F32, + )?; + let (metadata, last_op) = rvalue::translate_operand( + ctx, + body, + &args[3], + value_map, + block_ptr, + Some(last_op), + loc.clone(), + )?; + operands.push(metadata); + let (selector_value, last_op) = rvalue::translate_operand( + ctx, + body, + &args[4], + value_map, + block_ptr, + last_op, + loc.clone(), + )?; + operands.push(selector_value); + let mma = Operation::new( + ctx, + SparseMmaOp::get_concrete_op_info(), + vec![result_ty; result_count], + operands, + vec![], + 0, + ); + mma.deref_mut(ctx).set_loc(loc.clone()); + let mma = SparseMmaOp::new(mma); + mma.set_attr_nvvm_sparse_mma_shape(ctx, SparseMmaShapeAttr::M16n8k16); + mma.set_attr_nvvm_sparse_mma_accumulator(ctx, SparseMmaAccumulatorAttr::F32); + mma.set_attr_nvvm_sparse_mma_a_element(ctx, SparseMmaElementAttr::Bf16); + mma.set_attr_nvvm_sparse_mma_b_element(ctx, SparseMmaElementAttr::Bf16); + mma.set_attr_nvvm_sparse_mma_a_layout(ctx, SparseMmaLayoutAttr::Row); + mma.set_attr_nvvm_sparse_mma_b_layout(ctx, SparseMmaLayoutAttr::Col); + mma.set_attr_nvvm_sparse_mma_overflow(ctx, SparseMmaOverflowAttr::NotApplicable); + mma.set_attr_nvvm_sparse_mma_metadata(ctx, SparseMmaMetadataAttr::Ordered); + mma.set_attr_nvvm_sparse_mma_selector( + ctx, + SparseMmaSelectorAttr::ImmediateZeroThroughThree, + ); + let mma = mma.get_operation(); + helpers::set_generated_intrinsic_marker(ctx, mma, "v1:i1020"); + helpers::insert_op(ctx, mma, block_ptr, last_op); + let (result, last_op) = + bundle_generated_mma_results(ctx, mma, result_ty, result_count, loc.clone()); + Ok(Some(helpers::emit_store_result_and_goto( + ctx, + destination, + result, + target, + block_ptr, + last_op, + value_map, + block_map, + loc, + "mma_sp_ordered_metadata_m16n8k16_f32_bf16 call without target block", + )?)) + } + "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i1022" + | "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k16_f32_f16" => { + require_arity(name, args.len(), 5, &loc)?; + if !matches!(&args[4], mir::Operand::Constant(_)) { + return input_err!( + loc, + TranslationErr::unsupported( + "sparse MMA selector must be the compile-time constant 0, 1, 2, or 3" + .to_owned() + ) + ); + } + let (mut operands, last_op, result_ty, result_count) = import_generated_mma_operands( + ctx, + body, + args, + block_ptr, + prev_op, + value_map, + loc.clone(), + GeneratedMmaImportAdapter::C4F32A2U32B2U32ToD4F32, + )?; + let (metadata, last_op) = rvalue::translate_operand( + ctx, + body, + &args[3], + value_map, + block_ptr, + Some(last_op), + loc.clone(), + )?; + operands.push(metadata); + let (selector_value, last_op) = rvalue::translate_operand( + ctx, + body, + &args[4], + value_map, + block_ptr, + last_op, + loc.clone(), + )?; + operands.push(selector_value); + let mma = Operation::new( + ctx, + SparseMmaOp::get_concrete_op_info(), + vec![result_ty; result_count], + operands, + vec![], + 0, + ); + mma.deref_mut(ctx).set_loc(loc.clone()); + let mma = SparseMmaOp::new(mma); + mma.set_attr_nvvm_sparse_mma_shape(ctx, SparseMmaShapeAttr::M16n8k16); + mma.set_attr_nvvm_sparse_mma_accumulator(ctx, SparseMmaAccumulatorAttr::F32); + mma.set_attr_nvvm_sparse_mma_a_element(ctx, SparseMmaElementAttr::F16); + mma.set_attr_nvvm_sparse_mma_b_element(ctx, SparseMmaElementAttr::F16); + mma.set_attr_nvvm_sparse_mma_a_layout(ctx, SparseMmaLayoutAttr::Row); + mma.set_attr_nvvm_sparse_mma_b_layout(ctx, SparseMmaLayoutAttr::Col); + mma.set_attr_nvvm_sparse_mma_overflow(ctx, SparseMmaOverflowAttr::NotApplicable); + mma.set_attr_nvvm_sparse_mma_metadata(ctx, SparseMmaMetadataAttr::Ordered); + mma.set_attr_nvvm_sparse_mma_selector( + ctx, + SparseMmaSelectorAttr::ImmediateZeroThroughThree, + ); + let mma = mma.get_operation(); + helpers::set_generated_intrinsic_marker(ctx, mma, "v1:i1022"); + helpers::insert_op(ctx, mma, block_ptr, last_op); + let (result, last_op) = + bundle_generated_mma_results(ctx, mma, result_ty, result_count, loc.clone()); + Ok(Some(helpers::emit_store_result_and_goto( + ctx, + destination, + result, + target, + block_ptr, + last_op, + value_map, + block_map, + loc, + "mma_sp_ordered_metadata_m16n8k16_f32_f16 call without target block", + )?)) + } + "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i1019" + | "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k16_f32_tf32" => { + require_arity(name, args.len(), 5, &loc)?; + if !matches!(&args[4], mir::Operand::Constant(_)) { + return input_err!( + loc, + TranslationErr::unsupported( + "sparse MMA selector must be the compile-time constant 0 or 1".to_owned() + ) + ); + } + let (mut operands, last_op, result_ty, result_count) = import_generated_mma_operands( + ctx, + body, + args, + block_ptr, + prev_op, + value_map, + loc.clone(), + GeneratedMmaImportAdapter::C4F32A4U32B4U32ToD4F32, + )?; + let (metadata, last_op) = rvalue::translate_operand( + ctx, + body, + &args[3], + value_map, + block_ptr, + Some(last_op), + loc.clone(), + )?; + operands.push(metadata); + let (selector_value, last_op) = rvalue::translate_operand( + ctx, + body, + &args[4], + value_map, + block_ptr, + last_op, + loc.clone(), + )?; + operands.push(selector_value); + let mma = Operation::new( + ctx, + SparseMmaOp::get_concrete_op_info(), + vec![result_ty; result_count], + operands, + vec![], + 0, + ); + mma.deref_mut(ctx).set_loc(loc.clone()); + let mma = SparseMmaOp::new(mma); + mma.set_attr_nvvm_sparse_mma_shape(ctx, SparseMmaShapeAttr::M16n8k16); + mma.set_attr_nvvm_sparse_mma_accumulator(ctx, SparseMmaAccumulatorAttr::F32); + mma.set_attr_nvvm_sparse_mma_a_element(ctx, SparseMmaElementAttr::Tf32); + mma.set_attr_nvvm_sparse_mma_b_element(ctx, SparseMmaElementAttr::Tf32); + mma.set_attr_nvvm_sparse_mma_a_layout(ctx, SparseMmaLayoutAttr::Row); + mma.set_attr_nvvm_sparse_mma_b_layout(ctx, SparseMmaLayoutAttr::Col); + mma.set_attr_nvvm_sparse_mma_overflow(ctx, SparseMmaOverflowAttr::NotApplicable); + mma.set_attr_nvvm_sparse_mma_metadata(ctx, SparseMmaMetadataAttr::Ordered); + mma.set_attr_nvvm_sparse_mma_selector(ctx, SparseMmaSelectorAttr::ImmediateZeroOrOne); + let mma = mma.get_operation(); + helpers::set_generated_intrinsic_marker(ctx, mma, "v1:i1019"); + helpers::insert_op(ctx, mma, block_ptr, last_op); + let (result, last_op) = + bundle_generated_mma_results(ctx, mma, result_ty, result_count, loc.clone()); + Ok(Some(helpers::emit_store_result_and_goto( + ctx, + destination, + result, + target, + block_ptr, + last_op, + value_map, + block_map, + loc, + "mma_sp_ordered_metadata_m16n8k16_f32_tf32 call without target block", + )?)) + } + "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i1024" + | "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k32_f16_f16" => { + require_arity(name, args.len(), 5, &loc)?; + if !matches!(&args[4], mir::Operand::Constant(_)) { + return input_err!( + loc, + TranslationErr::unsupported( + "sparse MMA selector must be the compile-time constant 0 or 1".to_owned() + ) + ); + } + let (mut operands, last_op, result_ty, result_count) = import_generated_mma_operands( + ctx, + body, + args, + block_ptr, + prev_op, + value_map, + loc.clone(), + GeneratedMmaImportAdapter::C2U32A4U32B4U32ToD2U32, + )?; + let (metadata, last_op) = rvalue::translate_operand( + ctx, + body, + &args[3], + value_map, + block_ptr, + Some(last_op), + loc.clone(), + )?; + operands.push(metadata); + let (selector_value, last_op) = rvalue::translate_operand( + ctx, + body, + &args[4], + value_map, + block_ptr, + last_op, + loc.clone(), + )?; + operands.push(selector_value); + let mma = Operation::new( + ctx, + SparseMmaOp::get_concrete_op_info(), + vec![result_ty; result_count], + operands, + vec![], + 0, + ); + mma.deref_mut(ctx).set_loc(loc.clone()); + let mma = SparseMmaOp::new(mma); + mma.set_attr_nvvm_sparse_mma_shape(ctx, SparseMmaShapeAttr::M16n8k32); + mma.set_attr_nvvm_sparse_mma_accumulator(ctx, SparseMmaAccumulatorAttr::F16); + mma.set_attr_nvvm_sparse_mma_a_element(ctx, SparseMmaElementAttr::F16); + mma.set_attr_nvvm_sparse_mma_b_element(ctx, SparseMmaElementAttr::F16); + mma.set_attr_nvvm_sparse_mma_a_layout(ctx, SparseMmaLayoutAttr::Row); + mma.set_attr_nvvm_sparse_mma_b_layout(ctx, SparseMmaLayoutAttr::Col); + mma.set_attr_nvvm_sparse_mma_overflow(ctx, SparseMmaOverflowAttr::NotApplicable); + mma.set_attr_nvvm_sparse_mma_metadata(ctx, SparseMmaMetadataAttr::Ordered); + mma.set_attr_nvvm_sparse_mma_selector(ctx, SparseMmaSelectorAttr::ImmediateZeroOrOne); + let mma = mma.get_operation(); + helpers::set_generated_intrinsic_marker(ctx, mma, "v1:i1024"); + helpers::insert_op(ctx, mma, block_ptr, last_op); + let (result, last_op) = + bundle_generated_mma_results(ctx, mma, result_ty, result_count, loc.clone()); + Ok(Some(helpers::emit_store_result_and_goto( + ctx, + destination, + result, + target, + block_ptr, + last_op, + value_map, + block_map, + loc, + "mma_sp_ordered_metadata_m16n8k32_f16_f16 call without target block", + )?)) + } + "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i1023" + | "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k32_f32_bf16" => { + require_arity(name, args.len(), 5, &loc)?; + if !matches!(&args[4], mir::Operand::Constant(_)) { + return input_err!( + loc, + TranslationErr::unsupported( + "sparse MMA selector must be the compile-time constant 0 or 1".to_owned() + ) + ); + } + let (mut operands, last_op, result_ty, result_count) = import_generated_mma_operands( + ctx, + body, + args, + block_ptr, + prev_op, + value_map, + loc.clone(), + GeneratedMmaImportAdapter::C4F32A4U32B4U32ToD4F32, + )?; + let (metadata, last_op) = rvalue::translate_operand( + ctx, + body, + &args[3], + value_map, + block_ptr, + Some(last_op), + loc.clone(), + )?; + operands.push(metadata); + let (selector_value, last_op) = rvalue::translate_operand( + ctx, + body, + &args[4], + value_map, + block_ptr, + last_op, + loc.clone(), + )?; + operands.push(selector_value); + let mma = Operation::new( + ctx, + SparseMmaOp::get_concrete_op_info(), + vec![result_ty; result_count], + operands, + vec![], + 0, + ); + mma.deref_mut(ctx).set_loc(loc.clone()); + let mma = SparseMmaOp::new(mma); + mma.set_attr_nvvm_sparse_mma_shape(ctx, SparseMmaShapeAttr::M16n8k32); + mma.set_attr_nvvm_sparse_mma_accumulator(ctx, SparseMmaAccumulatorAttr::F32); + mma.set_attr_nvvm_sparse_mma_a_element(ctx, SparseMmaElementAttr::Bf16); + mma.set_attr_nvvm_sparse_mma_b_element(ctx, SparseMmaElementAttr::Bf16); + mma.set_attr_nvvm_sparse_mma_a_layout(ctx, SparseMmaLayoutAttr::Row); + mma.set_attr_nvvm_sparse_mma_b_layout(ctx, SparseMmaLayoutAttr::Col); + mma.set_attr_nvvm_sparse_mma_overflow(ctx, SparseMmaOverflowAttr::NotApplicable); + mma.set_attr_nvvm_sparse_mma_metadata(ctx, SparseMmaMetadataAttr::Ordered); + mma.set_attr_nvvm_sparse_mma_selector(ctx, SparseMmaSelectorAttr::ImmediateZeroOrOne); + let mma = mma.get_operation(); + helpers::set_generated_intrinsic_marker(ctx, mma, "v1:i1023"); + helpers::insert_op(ctx, mma, block_ptr, last_op); + let (result, last_op) = + bundle_generated_mma_results(ctx, mma, result_ty, result_count, loc.clone()); + Ok(Some(helpers::emit_store_result_and_goto( + ctx, + destination, + result, + target, + block_ptr, + last_op, + value_map, + block_map, + loc, + "mma_sp_ordered_metadata_m16n8k32_f32_bf16 call without target block", + )?)) + } + "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i1025" + | "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k32_f32_f16" => { + require_arity(name, args.len(), 5, &loc)?; + if !matches!(&args[4], mir::Operand::Constant(_)) { + return input_err!( + loc, + TranslationErr::unsupported( + "sparse MMA selector must be the compile-time constant 0 or 1".to_owned() + ) + ); + } + let (mut operands, last_op, result_ty, result_count) = import_generated_mma_operands( + ctx, + body, + args, + block_ptr, + prev_op, + value_map, + loc.clone(), + GeneratedMmaImportAdapter::C4F32A4U32B4U32ToD4F32, + )?; + let (metadata, last_op) = rvalue::translate_operand( + ctx, + body, + &args[3], + value_map, + block_ptr, + Some(last_op), + loc.clone(), + )?; + operands.push(metadata); + let (selector_value, last_op) = rvalue::translate_operand( + ctx, + body, + &args[4], + value_map, + block_ptr, + last_op, + loc.clone(), + )?; + operands.push(selector_value); + let mma = Operation::new( + ctx, + SparseMmaOp::get_concrete_op_info(), + vec![result_ty; result_count], + operands, + vec![], + 0, + ); + mma.deref_mut(ctx).set_loc(loc.clone()); + let mma = SparseMmaOp::new(mma); + mma.set_attr_nvvm_sparse_mma_shape(ctx, SparseMmaShapeAttr::M16n8k32); + mma.set_attr_nvvm_sparse_mma_accumulator(ctx, SparseMmaAccumulatorAttr::F32); + mma.set_attr_nvvm_sparse_mma_a_element(ctx, SparseMmaElementAttr::F16); + mma.set_attr_nvvm_sparse_mma_b_element(ctx, SparseMmaElementAttr::F16); + mma.set_attr_nvvm_sparse_mma_a_layout(ctx, SparseMmaLayoutAttr::Row); + mma.set_attr_nvvm_sparse_mma_b_layout(ctx, SparseMmaLayoutAttr::Col); + mma.set_attr_nvvm_sparse_mma_overflow(ctx, SparseMmaOverflowAttr::NotApplicable); + mma.set_attr_nvvm_sparse_mma_metadata(ctx, SparseMmaMetadataAttr::Ordered); + mma.set_attr_nvvm_sparse_mma_selector(ctx, SparseMmaSelectorAttr::ImmediateZeroOrOne); + let mma = mma.get_operation(); + helpers::set_generated_intrinsic_marker(ctx, mma, "v1:i1025"); + helpers::insert_op(ctx, mma, block_ptr, last_op); + let (result, last_op) = + bundle_generated_mma_results(ctx, mma, result_ty, result_count, loc.clone()); + Ok(Some(helpers::emit_store_result_and_goto( + ctx, + destination, + result, + target, + block_ptr, + last_op, + value_map, + block_map, + loc, + "mma_sp_ordered_metadata_m16n8k32_f32_f16 call without target block", + )?)) + } "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0171" | "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k32_s32_s8" => { require_arity(name, args.len(), 5, &loc)?; @@ -8934,6 +9492,88 @@ pub(super) fn try_dispatch( "mma_sp_ordered_metadata_m16n8k64_s32_u8_satfinite call without target block", )?)) } + "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i1018" + | "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k8_f32_tf32" => { + require_arity(name, args.len(), 5, &loc)?; + if !matches!(&args[4], mir::Operand::Constant(_)) { + return input_err!( + loc, + TranslationErr::unsupported( + "sparse MMA selector must be the compile-time constant 0, 1, 2, or 3" + .to_owned() + ) + ); + } + let (mut operands, last_op, result_ty, result_count) = import_generated_mma_operands( + ctx, + body, + args, + block_ptr, + prev_op, + value_map, + loc.clone(), + GeneratedMmaImportAdapter::C4F32A2U32B2U32ToD4F32, + )?; + let (metadata, last_op) = rvalue::translate_operand( + ctx, + body, + &args[3], + value_map, + block_ptr, + Some(last_op), + loc.clone(), + )?; + operands.push(metadata); + let (selector_value, last_op) = rvalue::translate_operand( + ctx, + body, + &args[4], + value_map, + block_ptr, + last_op, + loc.clone(), + )?; + operands.push(selector_value); + let mma = Operation::new( + ctx, + SparseMmaOp::get_concrete_op_info(), + vec![result_ty; result_count], + operands, + vec![], + 0, + ); + mma.deref_mut(ctx).set_loc(loc.clone()); + let mma = SparseMmaOp::new(mma); + mma.set_attr_nvvm_sparse_mma_shape(ctx, SparseMmaShapeAttr::M16n8k8); + mma.set_attr_nvvm_sparse_mma_accumulator(ctx, SparseMmaAccumulatorAttr::F32); + mma.set_attr_nvvm_sparse_mma_a_element(ctx, SparseMmaElementAttr::Tf32); + mma.set_attr_nvvm_sparse_mma_b_element(ctx, SparseMmaElementAttr::Tf32); + mma.set_attr_nvvm_sparse_mma_a_layout(ctx, SparseMmaLayoutAttr::Row); + mma.set_attr_nvvm_sparse_mma_b_layout(ctx, SparseMmaLayoutAttr::Col); + mma.set_attr_nvvm_sparse_mma_overflow(ctx, SparseMmaOverflowAttr::NotApplicable); + mma.set_attr_nvvm_sparse_mma_metadata(ctx, SparseMmaMetadataAttr::Ordered); + mma.set_attr_nvvm_sparse_mma_selector( + ctx, + SparseMmaSelectorAttr::ImmediateZeroThroughThree, + ); + let mma = mma.get_operation(); + helpers::set_generated_intrinsic_marker(ctx, mma, "v1:i1018"); + helpers::insert_op(ctx, mma, block_ptr, last_op); + let (result, last_op) = + bundle_generated_mma_results(ctx, mma, result_ty, result_count, loc.clone()); + Ok(Some(helpers::emit_store_result_and_goto( + ctx, + destination, + result, + target, + block_ptr, + last_op, + value_map, + block_map, + loc, + "mma_sp_ordered_metadata_m16n8k8_f32_tf32 call without target block", + )?)) + } _ => Ok(None), } } diff --git a/crates/mir-importer/src/translator/terminator/intrinsics/generated/sreg.rs b/crates/mir-importer/src/translator/terminator/intrinsics/generated/sreg.rs index 4812c84ace..b3ec374991 100644 --- a/crates/mir-importer/src/translator/terminator/intrinsics/generated/sreg.rs +++ b/crates/mir-importer/src/translator/terminator/intrinsics/generated/sreg.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. //! Generated raw/compatibility dispatch arms: `sreg` intrinsics. diff --git a/crates/mir-importer/src/translator/terminator/intrinsics/generated/stmatrix.rs b/crates/mir-importer/src/translator/terminator/intrinsics/generated/stmatrix.rs index bc1695a4cb..350d60e432 100644 --- a/crates/mir-importer/src/translator/terminator/intrinsics/generated/stmatrix.rs +++ b/crates/mir-importer/src/translator/terminator/intrinsics/generated/stmatrix.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. //! Generated raw/compatibility dispatch arms: `stmatrix` intrinsics. diff --git a/crates/mir-importer/src/translator/terminator/intrinsics/generated/sync.rs b/crates/mir-importer/src/translator/terminator/intrinsics/generated/sync.rs index 4fda59ebb4..34a0290e70 100644 --- a/crates/mir-importer/src/translator/terminator/intrinsics/generated/sync.rs +++ b/crates/mir-importer/src/translator/terminator/intrinsics/generated/sync.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. //! Generated raw/compatibility dispatch arms: `sync` intrinsics. diff --git a/crates/mir-importer/src/translator/terminator/intrinsics/generated/tcgen05_cp.rs b/crates/mir-importer/src/translator/terminator/intrinsics/generated/tcgen05_cp.rs index ee331e42f1..bef2d66c32 100644 --- a/crates/mir-importer/src/translator/terminator/intrinsics/generated/tcgen05_cp.rs +++ b/crates/mir-importer/src/translator/terminator/intrinsics/generated/tcgen05_cp.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. //! Generated raw/compatibility dispatch arms: `tcgen05_cp` intrinsics. diff --git a/crates/mir-importer/src/translator/terminator/intrinsics/generated/tcgen05_ld.rs b/crates/mir-importer/src/translator/terminator/intrinsics/generated/tcgen05_ld.rs index ae44646bf3..e313340cab 100644 --- a/crates/mir-importer/src/translator/terminator/intrinsics/generated/tcgen05_ld.rs +++ b/crates/mir-importer/src/translator/terminator/intrinsics/generated/tcgen05_ld.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. //! Generated raw/compatibility dispatch arms: `tcgen05_ld` intrinsics. diff --git a/crates/mir-importer/src/translator/terminator/intrinsics/generated/tcgen05_mma.rs b/crates/mir-importer/src/translator/terminator/intrinsics/generated/tcgen05_mma.rs index 2e3af271d5..18d9f86aa9 100644 --- a/crates/mir-importer/src/translator/terminator/intrinsics/generated/tcgen05_mma.rs +++ b/crates/mir-importer/src/translator/terminator/intrinsics/generated/tcgen05_mma.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. //! Generated raw/compatibility dispatch arms: `tcgen05_mma` intrinsics. diff --git a/crates/mir-importer/src/translator/terminator/intrinsics/generated/tcgen05_other.rs b/crates/mir-importer/src/translator/terminator/intrinsics/generated/tcgen05_other.rs index 9ccbf7e532..0d64190fb9 100644 --- a/crates/mir-importer/src/translator/terminator/intrinsics/generated/tcgen05_other.rs +++ b/crates/mir-importer/src/translator/terminator/intrinsics/generated/tcgen05_other.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. //! Generated raw/compatibility dispatch arms: `tcgen05_other` intrinsics. diff --git a/crates/mir-importer/src/translator/terminator/intrinsics/generated/tcgen05_st.rs b/crates/mir-importer/src/translator/terminator/intrinsics/generated/tcgen05_st.rs index be8eead2d0..f061f7f78e 100644 --- a/crates/mir-importer/src/translator/terminator/intrinsics/generated/tcgen05_st.rs +++ b/crates/mir-importer/src/translator/terminator/intrinsics/generated/tcgen05_st.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. //! Generated raw/compatibility dispatch arms: `tcgen05_st` intrinsics. diff --git a/crates/mir-importer/src/translator/terminator/intrinsics/generated/tests/active_mask.rs b/crates/mir-importer/src/translator/terminator/intrinsics/generated/tests/active_mask.rs index d0409c46ce..6eba436ad1 100644 --- a/crates/mir-importer/src/translator/terminator/intrinsics/generated/tests/active_mask.rs +++ b/crates/mir-importer/src/translator/terminator/intrinsics/generated/tests/active_mask.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. //! Generated dispatch-path tests: `active_mask` intrinsics. diff --git a/crates/mir-importer/src/translator/terminator/intrinsics/generated/tests/clc.rs b/crates/mir-importer/src/translator/terminator/intrinsics/generated/tests/clc.rs index 46fa631c4e..a9f051add7 100644 --- a/crates/mir-importer/src/translator/terminator/intrinsics/generated/tests/clc.rs +++ b/crates/mir-importer/src/translator/terminator/intrinsics/generated/tests/clc.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. //! Generated dispatch-path tests: `clc` intrinsics. diff --git a/crates/mir-importer/src/translator/terminator/intrinsics/generated/tests/cluster_barrier.rs b/crates/mir-importer/src/translator/terminator/intrinsics/generated/tests/cluster_barrier.rs index d758321ba5..46e853ad28 100644 --- a/crates/mir-importer/src/translator/terminator/intrinsics/generated/tests/cluster_barrier.rs +++ b/crates/mir-importer/src/translator/terminator/intrinsics/generated/tests/cluster_barrier.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. //! Generated dispatch-path tests: `cluster_barrier` intrinsics. diff --git a/crates/mir-importer/src/translator/terminator/intrinsics/generated/tests/cluster_memory.rs b/crates/mir-importer/src/translator/terminator/intrinsics/generated/tests/cluster_memory.rs index 10e4061042..dc632dedf3 100644 --- a/crates/mir-importer/src/translator/terminator/intrinsics/generated/tests/cluster_memory.rs +++ b/crates/mir-importer/src/translator/terminator/intrinsics/generated/tests/cluster_memory.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. //! Generated dispatch-path tests: `cluster_memory` intrinsics. diff --git a/crates/mir-importer/src/translator/terminator/intrinsics/generated/tests/cp_async.rs b/crates/mir-importer/src/translator/terminator/intrinsics/generated/tests/cp_async.rs index 27973b2888..1423a01bfc 100644 --- a/crates/mir-importer/src/translator/terminator/intrinsics/generated/tests/cp_async.rs +++ b/crates/mir-importer/src/translator/terminator/intrinsics/generated/tests/cp_async.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. //! Generated dispatch-path tests: `cp_async` intrinsics. diff --git a/crates/mir-importer/src/translator/terminator/intrinsics/generated/tests/debug_control.rs b/crates/mir-importer/src/translator/terminator/intrinsics/generated/tests/debug_control.rs index ccd5a8a89a..8f2443bdc1 100644 --- a/crates/mir-importer/src/translator/terminator/intrinsics/generated/tests/debug_control.rs +++ b/crates/mir-importer/src/translator/terminator/intrinsics/generated/tests/debug_control.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. //! Generated dispatch-path tests: `debug_control` intrinsics. diff --git a/crates/mir-importer/src/translator/terminator/intrinsics/generated/tests/dotprod.rs b/crates/mir-importer/src/translator/terminator/intrinsics/generated/tests/dotprod.rs index b31a7c3606..0a4b81a23e 100644 --- a/crates/mir-importer/src/translator/terminator/intrinsics/generated/tests/dotprod.rs +++ b/crates/mir-importer/src/translator/terminator/intrinsics/generated/tests/dotprod.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. //! Generated dispatch-path tests: `dotprod` intrinsics. diff --git a/crates/mir-importer/src/translator/terminator/intrinsics/generated/tests/elect.rs b/crates/mir-importer/src/translator/terminator/intrinsics/generated/tests/elect.rs index 6e3a8b5422..384fb990a5 100644 --- a/crates/mir-importer/src/translator/terminator/intrinsics/generated/tests/elect.rs +++ b/crates/mir-importer/src/translator/terminator/intrinsics/generated/tests/elect.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. //! Generated dispatch-path tests: `elect` intrinsics. diff --git a/crates/mir-importer/src/translator/terminator/intrinsics/generated/tests/execution_control.rs b/crates/mir-importer/src/translator/terminator/intrinsics/generated/tests/execution_control.rs index cbba264543..af1665cd68 100644 --- a/crates/mir-importer/src/translator/terminator/intrinsics/generated/tests/execution_control.rs +++ b/crates/mir-importer/src/translator/terminator/intrinsics/generated/tests/execution_control.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. //! Generated dispatch-path tests: `execution_control` intrinsics. diff --git a/crates/mir-importer/src/translator/terminator/intrinsics/generated/tests/extended_minmax.rs b/crates/mir-importer/src/translator/terminator/intrinsics/generated/tests/extended_minmax.rs index 775ab522c6..2cd87f5467 100644 --- a/crates/mir-importer/src/translator/terminator/intrinsics/generated/tests/extended_minmax.rs +++ b/crates/mir-importer/src/translator/terminator/intrinsics/generated/tests/extended_minmax.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. //! Generated dispatch-path tests: `extended_minmax` intrinsics. diff --git a/crates/mir-importer/src/translator/terminator/intrinsics/generated/tests/integer_minmax.rs b/crates/mir-importer/src/translator/terminator/intrinsics/generated/tests/integer_minmax.rs index 4ab0c8d2cb..c65e22ddf1 100644 --- a/crates/mir-importer/src/translator/terminator/intrinsics/generated/tests/integer_minmax.rs +++ b/crates/mir-importer/src/translator/terminator/intrinsics/generated/tests/integer_minmax.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. //! Generated dispatch-path tests: `integer_minmax` intrinsics. diff --git a/crates/mir-importer/src/translator/terminator/intrinsics/generated/tests/ldmatrix.rs b/crates/mir-importer/src/translator/terminator/intrinsics/generated/tests/ldmatrix.rs index 40071d6c95..f6637c989c 100644 --- a/crates/mir-importer/src/translator/terminator/intrinsics/generated/tests/ldmatrix.rs +++ b/crates/mir-importer/src/translator/terminator/intrinsics/generated/tests/ldmatrix.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. //! Generated dispatch-path tests: `ldmatrix` intrinsics. diff --git a/crates/mir-importer/src/translator/terminator/intrinsics/generated/tests/mbarrier_basic.rs b/crates/mir-importer/src/translator/terminator/intrinsics/generated/tests/mbarrier_basic.rs index ae2896d98d..174de5f729 100644 --- a/crates/mir-importer/src/translator/terminator/intrinsics/generated/tests/mbarrier_basic.rs +++ b/crates/mir-importer/src/translator/terminator/intrinsics/generated/tests/mbarrier_basic.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. //! Generated dispatch-path tests: `mbarrier_basic` intrinsics. diff --git a/crates/mir-importer/src/translator/terminator/intrinsics/generated/tests/mbarrier_extended.rs b/crates/mir-importer/src/translator/terminator/intrinsics/generated/tests/mbarrier_extended.rs index 0bfc6832b7..83c5378967 100644 --- a/crates/mir-importer/src/translator/terminator/intrinsics/generated/tests/mbarrier_extended.rs +++ b/crates/mir-importer/src/translator/terminator/intrinsics/generated/tests/mbarrier_extended.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. //! Generated dispatch-path tests: `mbarrier_extended` intrinsics. diff --git a/crates/mir-importer/src/translator/terminator/intrinsics/generated/tests/mod.rs b/crates/mir-importer/src/translator/terminator/intrinsics/generated/tests/mod.rs index 7a8b6e12b9..e2a1af66ee 100644 --- a/crates/mir-importer/src/translator/terminator/intrinsics/generated/tests/mod.rs +++ b/crates/mir-importer/src/translator/terminator/intrinsics/generated/tests/mod.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. //! Generated dispatch-path tests, grouped per intrinsic family. diff --git a/crates/mir-importer/src/translator/terminator/intrinsics/generated/tests/movmatrix.rs b/crates/mir-importer/src/translator/terminator/intrinsics/generated/tests/movmatrix.rs index 05a046dd51..b60d7ac1bc 100644 --- a/crates/mir-importer/src/translator/terminator/intrinsics/generated/tests/movmatrix.rs +++ b/crates/mir-importer/src/translator/terminator/intrinsics/generated/tests/movmatrix.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. //! Generated dispatch-path tests: `movmatrix` intrinsics. diff --git a/crates/mir-importer/src/translator/terminator/intrinsics/generated/tests/packed_alu.rs b/crates/mir-importer/src/translator/terminator/intrinsics/generated/tests/packed_alu.rs index 9a2e5236aa..ae7834badd 100644 --- a/crates/mir-importer/src/translator/terminator/intrinsics/generated/tests/packed_alu.rs +++ b/crates/mir-importer/src/translator/terminator/intrinsics/generated/tests/packed_alu.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. //! Generated dispatch-path tests: `packed_alu` intrinsics. diff --git a/crates/mir-importer/src/translator/terminator/intrinsics/generated/tests/packed_atomic.rs b/crates/mir-importer/src/translator/terminator/intrinsics/generated/tests/packed_atomic.rs index 0d56d27ad0..71b0a6d45a 100644 --- a/crates/mir-importer/src/translator/terminator/intrinsics/generated/tests/packed_atomic.rs +++ b/crates/mir-importer/src/translator/terminator/intrinsics/generated/tests/packed_atomic.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. //! Generated dispatch-path tests: `packed_atomic` intrinsics. diff --git a/crates/mir-importer/src/translator/terminator/intrinsics/generated/tests/packed_conversion.rs b/crates/mir-importer/src/translator/terminator/intrinsics/generated/tests/packed_conversion.rs index af6f6546aa..34e4a80724 100644 --- a/crates/mir-importer/src/translator/terminator/intrinsics/generated/tests/packed_conversion.rs +++ b/crates/mir-importer/src/translator/terminator/intrinsics/generated/tests/packed_conversion.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. //! Generated dispatch-path tests: `packed_conversion` intrinsics. diff --git a/crates/mir-importer/src/translator/terminator/intrinsics/generated/tests/prmt.rs b/crates/mir-importer/src/translator/terminator/intrinsics/generated/tests/prmt.rs index ac16dd3e23..308a2a0217 100644 --- a/crates/mir-importer/src/translator/terminator/intrinsics/generated/tests/prmt.rs +++ b/crates/mir-importer/src/translator/terminator/intrinsics/generated/tests/prmt.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. //! Generated dispatch-path tests: `prmt` intrinsics. diff --git a/crates/mir-importer/src/translator/terminator/intrinsics/generated/tests/redux.rs b/crates/mir-importer/src/translator/terminator/intrinsics/generated/tests/redux.rs index 7bacb1f1d8..5e9c280c2f 100644 --- a/crates/mir-importer/src/translator/terminator/intrinsics/generated/tests/redux.rs +++ b/crates/mir-importer/src/translator/terminator/intrinsics/generated/tests/redux.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. //! Generated dispatch-path tests: `redux` intrinsics. diff --git a/crates/mir-importer/src/translator/terminator/intrinsics/generated/tests/register_mma.rs b/crates/mir-importer/src/translator/terminator/intrinsics/generated/tests/register_mma.rs index fcbcd92700..59ded28ba0 100644 --- a/crates/mir-importer/src/translator/terminator/intrinsics/generated/tests/register_mma.rs +++ b/crates/mir-importer/src/translator/terminator/intrinsics/generated/tests/register_mma.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. //! Generated dispatch-path tests: `register_mma` intrinsics. diff --git a/crates/mir-importer/src/translator/terminator/intrinsics/generated/tests/scalar_arithmetic.rs b/crates/mir-importer/src/translator/terminator/intrinsics/generated/tests/scalar_arithmetic.rs index 3ad5f3bc00..4352b82e98 100644 --- a/crates/mir-importer/src/translator/terminator/intrinsics/generated/tests/scalar_arithmetic.rs +++ b/crates/mir-importer/src/translator/terminator/intrinsics/generated/tests/scalar_arithmetic.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. //! Generated dispatch-path tests: `scalar_arithmetic` intrinsics. diff --git a/crates/mir-importer/src/translator/terminator/intrinsics/generated/tests/scalar_conversion.rs b/crates/mir-importer/src/translator/terminator/intrinsics/generated/tests/scalar_conversion.rs index cf4178f938..dda9b15cfa 100644 --- a/crates/mir-importer/src/translator/terminator/intrinsics/generated/tests/scalar_conversion.rs +++ b/crates/mir-importer/src/translator/terminator/intrinsics/generated/tests/scalar_conversion.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. //! Generated dispatch-path tests: `scalar_conversion` intrinsics. diff --git a/crates/mir-importer/src/translator/terminator/intrinsics/generated/tests/scalar_math.rs b/crates/mir-importer/src/translator/terminator/intrinsics/generated/tests/scalar_math.rs index e88f37dd81..0628c12ab4 100644 --- a/crates/mir-importer/src/translator/terminator/intrinsics/generated/tests/scalar_math.rs +++ b/crates/mir-importer/src/translator/terminator/intrinsics/generated/tests/scalar_math.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. //! Generated dispatch-path tests: `scalar_math` intrinsics. diff --git a/crates/mir-importer/src/translator/terminator/intrinsics/generated/tests/sparse_mma.rs b/crates/mir-importer/src/translator/terminator/intrinsics/generated/tests/sparse_mma.rs index c41136dfdf..bd5eb64375 100644 --- a/crates/mir-importer/src/translator/terminator/intrinsics/generated/tests/sparse_mma.rs +++ b/crates/mir-importer/src/translator/terminator/intrinsics/generated/tests/sparse_mma.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. //! Generated dispatch-path tests: `sparse_mma` intrinsics. @@ -1468,6 +1468,258 @@ fn mma_sp_ordered_metadata_m16n8k128_s32_u4_satfinite_uses_only_canonical_or_com )); } #[test] +fn mma_sp_ordered_metadata_m16n8k16_f16_f16_uses_only_canonical_or_compatibility_defpaths() { + assert!(is_generated_intrinsic_path( + "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i1021" + )); + assert!(is_raw_generated_intrinsic_path( + "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i1021" + )); + assert_eq!( + generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i1021"), + Some("v1:i1021") + ); + assert!(matches!( + classify_raw_intrinsic_path( + "cuda_intrinsics", + "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i1021".into() + ), + RawIntrinsicIdentity::Known(_) + )); + assert!(!is_generated_intrinsic_path( + "cuda_intrinsics::matrix::mma_sp_ordered_metadata_m16n8k16_f16_f16" + )); + assert!(is_generated_intrinsic_path( + "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k16_f16_f16" + )); + assert!(!is_raw_generated_intrinsic_path( + "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k16_f16_f16" + )); + assert_eq!( + generated_intrinsic_marker("cuda_device::wmma::mma_sp_ordered_metadata_m16n8k16_f16_f16"), + Some("v1:i1021") + ); + assert!(!is_generated_intrinsic_path( + "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i1021" + )); +} +#[test] +fn mma_sp_ordered_metadata_m16n8k16_f32_bf16_uses_only_canonical_or_compatibility_defpaths() { + assert!(is_generated_intrinsic_path( + "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i1020" + )); + assert!(is_raw_generated_intrinsic_path( + "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i1020" + )); + assert_eq!( + generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i1020"), + Some("v1:i1020") + ); + assert!(matches!( + classify_raw_intrinsic_path( + "cuda_intrinsics", + "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i1020".into() + ), + RawIntrinsicIdentity::Known(_) + )); + assert!(!is_generated_intrinsic_path( + "cuda_intrinsics::matrix::mma_sp_ordered_metadata_m16n8k16_f32_bf16" + )); + assert!(is_generated_intrinsic_path( + "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k16_f32_bf16" + )); + assert!(!is_raw_generated_intrinsic_path( + "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k16_f32_bf16" + )); + assert_eq!( + generated_intrinsic_marker("cuda_device::wmma::mma_sp_ordered_metadata_m16n8k16_f32_bf16"), + Some("v1:i1020") + ); + assert!(!is_generated_intrinsic_path( + "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i1020" + )); +} +#[test] +fn mma_sp_ordered_metadata_m16n8k16_f32_f16_uses_only_canonical_or_compatibility_defpaths() { + assert!(is_generated_intrinsic_path( + "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i1022" + )); + assert!(is_raw_generated_intrinsic_path( + "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i1022" + )); + assert_eq!( + generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i1022"), + Some("v1:i1022") + ); + assert!(matches!( + classify_raw_intrinsic_path( + "cuda_intrinsics", + "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i1022".into() + ), + RawIntrinsicIdentity::Known(_) + )); + assert!(!is_generated_intrinsic_path( + "cuda_intrinsics::matrix::mma_sp_ordered_metadata_m16n8k16_f32_f16" + )); + assert!(is_generated_intrinsic_path( + "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k16_f32_f16" + )); + assert!(!is_raw_generated_intrinsic_path( + "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k16_f32_f16" + )); + assert_eq!( + generated_intrinsic_marker("cuda_device::wmma::mma_sp_ordered_metadata_m16n8k16_f32_f16"), + Some("v1:i1022") + ); + assert!(!is_generated_intrinsic_path( + "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i1022" + )); +} +#[test] +fn mma_sp_ordered_metadata_m16n8k16_f32_tf32_uses_only_canonical_or_compatibility_defpaths() { + assert!(is_generated_intrinsic_path( + "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i1019" + )); + assert!(is_raw_generated_intrinsic_path( + "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i1019" + )); + assert_eq!( + generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i1019"), + Some("v1:i1019") + ); + assert!(matches!( + classify_raw_intrinsic_path( + "cuda_intrinsics", + "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i1019".into() + ), + RawIntrinsicIdentity::Known(_) + )); + assert!(!is_generated_intrinsic_path( + "cuda_intrinsics::matrix::mma_sp_ordered_metadata_m16n8k16_f32_tf32" + )); + assert!(is_generated_intrinsic_path( + "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k16_f32_tf32" + )); + assert!(!is_raw_generated_intrinsic_path( + "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k16_f32_tf32" + )); + assert_eq!( + generated_intrinsic_marker("cuda_device::wmma::mma_sp_ordered_metadata_m16n8k16_f32_tf32"), + Some("v1:i1019") + ); + assert!(!is_generated_intrinsic_path( + "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i1019" + )); +} +#[test] +fn mma_sp_ordered_metadata_m16n8k32_f16_f16_uses_only_canonical_or_compatibility_defpaths() { + assert!(is_generated_intrinsic_path( + "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i1024" + )); + assert!(is_raw_generated_intrinsic_path( + "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i1024" + )); + assert_eq!( + generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i1024"), + Some("v1:i1024") + ); + assert!(matches!( + classify_raw_intrinsic_path( + "cuda_intrinsics", + "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i1024".into() + ), + RawIntrinsicIdentity::Known(_) + )); + assert!(!is_generated_intrinsic_path( + "cuda_intrinsics::matrix::mma_sp_ordered_metadata_m16n8k32_f16_f16" + )); + assert!(is_generated_intrinsic_path( + "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k32_f16_f16" + )); + assert!(!is_raw_generated_intrinsic_path( + "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k32_f16_f16" + )); + assert_eq!( + generated_intrinsic_marker("cuda_device::wmma::mma_sp_ordered_metadata_m16n8k32_f16_f16"), + Some("v1:i1024") + ); + assert!(!is_generated_intrinsic_path( + "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i1024" + )); +} +#[test] +fn mma_sp_ordered_metadata_m16n8k32_f32_bf16_uses_only_canonical_or_compatibility_defpaths() { + assert!(is_generated_intrinsic_path( + "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i1023" + )); + assert!(is_raw_generated_intrinsic_path( + "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i1023" + )); + assert_eq!( + generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i1023"), + Some("v1:i1023") + ); + assert!(matches!( + classify_raw_intrinsic_path( + "cuda_intrinsics", + "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i1023".into() + ), + RawIntrinsicIdentity::Known(_) + )); + assert!(!is_generated_intrinsic_path( + "cuda_intrinsics::matrix::mma_sp_ordered_metadata_m16n8k32_f32_bf16" + )); + assert!(is_generated_intrinsic_path( + "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k32_f32_bf16" + )); + assert!(!is_raw_generated_intrinsic_path( + "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k32_f32_bf16" + )); + assert_eq!( + generated_intrinsic_marker("cuda_device::wmma::mma_sp_ordered_metadata_m16n8k32_f32_bf16"), + Some("v1:i1023") + ); + assert!(!is_generated_intrinsic_path( + "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i1023" + )); +} +#[test] +fn mma_sp_ordered_metadata_m16n8k32_f32_f16_uses_only_canonical_or_compatibility_defpaths() { + assert!(is_generated_intrinsic_path( + "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i1025" + )); + assert!(is_raw_generated_intrinsic_path( + "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i1025" + )); + assert_eq!( + generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i1025"), + Some("v1:i1025") + ); + assert!(matches!( + classify_raw_intrinsic_path( + "cuda_intrinsics", + "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i1025".into() + ), + RawIntrinsicIdentity::Known(_) + )); + assert!(!is_generated_intrinsic_path( + "cuda_intrinsics::matrix::mma_sp_ordered_metadata_m16n8k32_f32_f16" + )); + assert!(is_generated_intrinsic_path( + "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k32_f32_f16" + )); + assert!(!is_raw_generated_intrinsic_path( + "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k32_f32_f16" + )); + assert_eq!( + generated_intrinsic_marker("cuda_device::wmma::mma_sp_ordered_metadata_m16n8k32_f32_f16"), + Some("v1:i1025") + ); + assert!(!is_generated_intrinsic_path( + "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i1025" + )); +} +#[test] fn mma_sp_ordered_metadata_m16n8k32_s32_s8_uses_only_canonical_or_compatibility_defpaths() { assert!(is_generated_intrinsic_path( "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0171" @@ -4317,3 +4569,39 @@ fn mma_sp_ordered_metadata_m16n8k64_s32_u8_satfinite_uses_only_canonical_or_comp "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i0185" )); } +#[test] +fn mma_sp_ordered_metadata_m16n8k8_f32_tf32_uses_only_canonical_or_compatibility_defpaths() { + assert!(is_generated_intrinsic_path( + "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i1018" + )); + assert!(is_raw_generated_intrinsic_path( + "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i1018" + )); + assert_eq!( + generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i1018"), + Some("v1:i1018") + ); + assert!(matches!( + classify_raw_intrinsic_path( + "cuda_intrinsics", + "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i1018".into() + ), + RawIntrinsicIdentity::Known(_) + )); + assert!(!is_generated_intrinsic_path( + "cuda_intrinsics::matrix::mma_sp_ordered_metadata_m16n8k8_f32_tf32" + )); + assert!(is_generated_intrinsic_path( + "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k8_f32_tf32" + )); + assert!(!is_raw_generated_intrinsic_path( + "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k8_f32_tf32" + )); + assert_eq!( + generated_intrinsic_marker("cuda_device::wmma::mma_sp_ordered_metadata_m16n8k8_f32_tf32"), + Some("v1:i1018") + ); + assert!(!is_generated_intrinsic_path( + "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i1018" + )); +} diff --git a/crates/mir-importer/src/translator/terminator/intrinsics/generated/tests/sreg.rs b/crates/mir-importer/src/translator/terminator/intrinsics/generated/tests/sreg.rs index c52d0cba71..7cebcbef4f 100644 --- a/crates/mir-importer/src/translator/terminator/intrinsics/generated/tests/sreg.rs +++ b/crates/mir-importer/src/translator/terminator/intrinsics/generated/tests/sreg.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. //! Generated dispatch-path tests: `sreg` intrinsics. diff --git a/crates/mir-importer/src/translator/terminator/intrinsics/generated/tests/stmatrix.rs b/crates/mir-importer/src/translator/terminator/intrinsics/generated/tests/stmatrix.rs index 603902cb59..89649aa4fd 100644 --- a/crates/mir-importer/src/translator/terminator/intrinsics/generated/tests/stmatrix.rs +++ b/crates/mir-importer/src/translator/terminator/intrinsics/generated/tests/stmatrix.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. //! Generated dispatch-path tests: `stmatrix` intrinsics. diff --git a/crates/mir-importer/src/translator/terminator/intrinsics/generated/tests/sync.rs b/crates/mir-importer/src/translator/terminator/intrinsics/generated/tests/sync.rs index 3ce973c04d..b1c95d1492 100644 --- a/crates/mir-importer/src/translator/terminator/intrinsics/generated/tests/sync.rs +++ b/crates/mir-importer/src/translator/terminator/intrinsics/generated/tests/sync.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. //! Generated dispatch-path tests: `sync` intrinsics. diff --git a/crates/mir-importer/src/translator/terminator/intrinsics/generated/tests/tcgen05.rs b/crates/mir-importer/src/translator/terminator/intrinsics/generated/tests/tcgen05.rs index b49c1605e3..3aeced866b 100644 --- a/crates/mir-importer/src/translator/terminator/intrinsics/generated/tests/tcgen05.rs +++ b/crates/mir-importer/src/translator/terminator/intrinsics/generated/tests/tcgen05.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. //! Generated dispatch-path tests: `tcgen05` intrinsics. diff --git a/crates/mir-importer/src/translator/terminator/intrinsics/generated/tests/tma.rs b/crates/mir-importer/src/translator/terminator/intrinsics/generated/tests/tma.rs index 30f8783aee..512d0b312e 100644 --- a/crates/mir-importer/src/translator/terminator/intrinsics/generated/tests/tma.rs +++ b/crates/mir-importer/src/translator/terminator/intrinsics/generated/tests/tma.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. //! Generated dispatch-path tests: `tma` intrinsics. diff --git a/crates/mir-importer/src/translator/terminator/intrinsics/generated/tests/vote.rs b/crates/mir-importer/src/translator/terminator/intrinsics/generated/tests/vote.rs index cd4ebfa124..1098ca86ce 100644 --- a/crates/mir-importer/src/translator/terminator/intrinsics/generated/tests/vote.rs +++ b/crates/mir-importer/src/translator/terminator/intrinsics/generated/tests/vote.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. //! Generated dispatch-path tests: `vote` intrinsics. diff --git a/crates/mir-importer/src/translator/terminator/intrinsics/generated/tests/warp_barrier.rs b/crates/mir-importer/src/translator/terminator/intrinsics/generated/tests/warp_barrier.rs index 28be01624f..7d01ed9ad0 100644 --- a/crates/mir-importer/src/translator/terminator/intrinsics/generated/tests/warp_barrier.rs +++ b/crates/mir-importer/src/translator/terminator/intrinsics/generated/tests/warp_barrier.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. //! Generated dispatch-path tests: `warp_barrier` intrinsics. diff --git a/crates/mir-importer/src/translator/terminator/intrinsics/generated/tests/warp_match.rs b/crates/mir-importer/src/translator/terminator/intrinsics/generated/tests/warp_match.rs index 6433c45670..f182d47088 100644 --- a/crates/mir-importer/src/translator/terminator/intrinsics/generated/tests/warp_match.rs +++ b/crates/mir-importer/src/translator/terminator/intrinsics/generated/tests/warp_match.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. //! Generated dispatch-path tests: `warp_match` intrinsics. diff --git a/crates/mir-importer/src/translator/terminator/intrinsics/generated/tests/warp_shuffle.rs b/crates/mir-importer/src/translator/terminator/intrinsics/generated/tests/warp_shuffle.rs index 30eb34cdbe..52b31c7e4b 100644 --- a/crates/mir-importer/src/translator/terminator/intrinsics/generated/tests/warp_shuffle.rs +++ b/crates/mir-importer/src/translator/terminator/intrinsics/generated/tests/warp_shuffle.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. //! Generated dispatch-path tests: `warp_shuffle` intrinsics. diff --git a/crates/mir-importer/src/translator/terminator/intrinsics/generated/tests/wgmma_control.rs b/crates/mir-importer/src/translator/terminator/intrinsics/generated/tests/wgmma_control.rs index 8569e18359..ba0b51912f 100644 --- a/crates/mir-importer/src/translator/terminator/intrinsics/generated/tests/wgmma_control.rs +++ b/crates/mir-importer/src/translator/terminator/intrinsics/generated/tests/wgmma_control.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. //! Generated dispatch-path tests: `wgmma_control` intrinsics. diff --git a/crates/mir-importer/src/translator/terminator/intrinsics/generated/tma.rs b/crates/mir-importer/src/translator/terminator/intrinsics/generated/tma.rs index 091bf952af..3b0f1a3037 100644 --- a/crates/mir-importer/src/translator/terminator/intrinsics/generated/tma.rs +++ b/crates/mir-importer/src/translator/terminator/intrinsics/generated/tma.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. //! Generated raw/compatibility dispatch arms: `tma` intrinsics. diff --git a/crates/mir-importer/src/translator/terminator/intrinsics/generated/vote.rs b/crates/mir-importer/src/translator/terminator/intrinsics/generated/vote.rs index 16ae581e9a..a9795b56c8 100644 --- a/crates/mir-importer/src/translator/terminator/intrinsics/generated/vote.rs +++ b/crates/mir-importer/src/translator/terminator/intrinsics/generated/vote.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. //! Generated raw/compatibility dispatch arms: `vote` intrinsics. diff --git a/crates/mir-importer/src/translator/terminator/intrinsics/generated/warp_barrier.rs b/crates/mir-importer/src/translator/terminator/intrinsics/generated/warp_barrier.rs index e528999d90..72b2006d8c 100644 --- a/crates/mir-importer/src/translator/terminator/intrinsics/generated/warp_barrier.rs +++ b/crates/mir-importer/src/translator/terminator/intrinsics/generated/warp_barrier.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. //! Generated raw/compatibility dispatch arms: `warp_barrier` intrinsics. diff --git a/crates/mir-importer/src/translator/terminator/intrinsics/generated/warp_match.rs b/crates/mir-importer/src/translator/terminator/intrinsics/generated/warp_match.rs index 6eb7a7745c..8e3c3b471e 100644 --- a/crates/mir-importer/src/translator/terminator/intrinsics/generated/warp_match.rs +++ b/crates/mir-importer/src/translator/terminator/intrinsics/generated/warp_match.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. //! Generated raw/compatibility dispatch arms: `warp_match` intrinsics. diff --git a/crates/mir-importer/src/translator/terminator/intrinsics/generated/warp_shuffle.rs b/crates/mir-importer/src/translator/terminator/intrinsics/generated/warp_shuffle.rs index 7381f20d75..f1810e7a84 100644 --- a/crates/mir-importer/src/translator/terminator/intrinsics/generated/warp_shuffle.rs +++ b/crates/mir-importer/src/translator/terminator/intrinsics/generated/warp_shuffle.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. //! Generated raw/compatibility dispatch arms: `warp_shuffle` intrinsics. diff --git a/crates/mir-importer/src/translator/terminator/intrinsics/generated/wgmma_control.rs b/crates/mir-importer/src/translator/terminator/intrinsics/generated/wgmma_control.rs index 15d21ac5a0..c19ff6274a 100644 --- a/crates/mir-importer/src/translator/terminator/intrinsics/generated/wgmma_control.rs +++ b/crates/mir-importer/src/translator/terminator/intrinsics/generated/wgmma_control.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. //! Generated raw/compatibility dispatch arms: `wgmma_control` intrinsics. diff --git a/crates/mir-lower/src/convert/generated_intrinsics/active_mask.rs b/crates/mir-lower/src/convert/generated_intrinsics/active_mask.rs index 4df2365edb..2eda8e7f0c 100644 --- a/crates/mir-lower/src/convert/generated_intrinsics/active_mask.rs +++ b/crates/mir-lower/src/convert/generated_intrinsics/active_mask.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. //! Generated conversion interfaces: `active_mask` intrinsics. diff --git a/crates/mir-lower/src/convert/generated_intrinsics/clc.rs b/crates/mir-lower/src/convert/generated_intrinsics/clc.rs index edaeba79ad..1de5b128cf 100644 --- a/crates/mir-lower/src/convert/generated_intrinsics/clc.rs +++ b/crates/mir-lower/src/convert/generated_intrinsics/clc.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. //! Generated conversion interfaces: `clc` intrinsics. diff --git a/crates/mir-lower/src/convert/generated_intrinsics/cluster_barrier.rs b/crates/mir-lower/src/convert/generated_intrinsics/cluster_barrier.rs index af248aad90..611faee60b 100644 --- a/crates/mir-lower/src/convert/generated_intrinsics/cluster_barrier.rs +++ b/crates/mir-lower/src/convert/generated_intrinsics/cluster_barrier.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. //! Generated conversion interfaces: `cluster_barrier` intrinsics. diff --git a/crates/mir-lower/src/convert/generated_intrinsics/cluster_memory.rs b/crates/mir-lower/src/convert/generated_intrinsics/cluster_memory.rs index 86cee24dfc..0c917d9f35 100644 --- a/crates/mir-lower/src/convert/generated_intrinsics/cluster_memory.rs +++ b/crates/mir-lower/src/convert/generated_intrinsics/cluster_memory.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. //! Generated conversion interfaces: `cluster_memory` intrinsics. diff --git a/crates/mir-lower/src/convert/generated_intrinsics/cp_async.rs b/crates/mir-lower/src/convert/generated_intrinsics/cp_async.rs index 0bdef0e01c..2c94c876dd 100644 --- a/crates/mir-lower/src/convert/generated_intrinsics/cp_async.rs +++ b/crates/mir-lower/src/convert/generated_intrinsics/cp_async.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. //! Generated conversion interfaces: `cp_async` intrinsics. diff --git a/crates/mir-lower/src/convert/generated_intrinsics/debug_control.rs b/crates/mir-lower/src/convert/generated_intrinsics/debug_control.rs index d84e07c037..c4e3eb607a 100644 --- a/crates/mir-lower/src/convert/generated_intrinsics/debug_control.rs +++ b/crates/mir-lower/src/convert/generated_intrinsics/debug_control.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. //! Generated conversion interfaces: `debug_control` intrinsics. diff --git a/crates/mir-lower/src/convert/generated_intrinsics/dotprod.rs b/crates/mir-lower/src/convert/generated_intrinsics/dotprod.rs index 2b85892e8c..fd1ad83ca1 100644 --- a/crates/mir-lower/src/convert/generated_intrinsics/dotprod.rs +++ b/crates/mir-lower/src/convert/generated_intrinsics/dotprod.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. //! Generated conversion interfaces: `dotprod` intrinsics. diff --git a/crates/mir-lower/src/convert/generated_intrinsics/elect.rs b/crates/mir-lower/src/convert/generated_intrinsics/elect.rs index 35594169a5..cdb0a8d07d 100644 --- a/crates/mir-lower/src/convert/generated_intrinsics/elect.rs +++ b/crates/mir-lower/src/convert/generated_intrinsics/elect.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. //! Generated conversion interfaces: `elect` intrinsics. diff --git a/crates/mir-lower/src/convert/generated_intrinsics/execution_control.rs b/crates/mir-lower/src/convert/generated_intrinsics/execution_control.rs index cd8202445b..1b7053f9d1 100644 --- a/crates/mir-lower/src/convert/generated_intrinsics/execution_control.rs +++ b/crates/mir-lower/src/convert/generated_intrinsics/execution_control.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. //! Generated conversion interfaces: `execution_control` intrinsics. diff --git a/crates/mir-lower/src/convert/generated_intrinsics/extended_minmax.rs b/crates/mir-lower/src/convert/generated_intrinsics/extended_minmax.rs index c2918ce4f4..991e5e4f19 100644 --- a/crates/mir-lower/src/convert/generated_intrinsics/extended_minmax.rs +++ b/crates/mir-lower/src/convert/generated_intrinsics/extended_minmax.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. //! Generated conversion interfaces: `extended_minmax` intrinsics. diff --git a/crates/mir-lower/src/convert/generated_intrinsics/integer_minmax.rs b/crates/mir-lower/src/convert/generated_intrinsics/integer_minmax.rs index 085bd30c5f..6dbe08aa52 100644 --- a/crates/mir-lower/src/convert/generated_intrinsics/integer_minmax.rs +++ b/crates/mir-lower/src/convert/generated_intrinsics/integer_minmax.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. //! Generated conversion interfaces: `integer_minmax` intrinsics. diff --git a/crates/mir-lower/src/convert/generated_intrinsics/ldmatrix.rs b/crates/mir-lower/src/convert/generated_intrinsics/ldmatrix.rs index 57f16b5a63..60904e7b71 100644 --- a/crates/mir-lower/src/convert/generated_intrinsics/ldmatrix.rs +++ b/crates/mir-lower/src/convert/generated_intrinsics/ldmatrix.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. //! Generated conversion interfaces: `ldmatrix` intrinsics. diff --git a/crates/mir-lower/src/convert/generated_intrinsics/mbarrier_basic.rs b/crates/mir-lower/src/convert/generated_intrinsics/mbarrier_basic.rs index b0cf4aa568..57da0a72a7 100644 --- a/crates/mir-lower/src/convert/generated_intrinsics/mbarrier_basic.rs +++ b/crates/mir-lower/src/convert/generated_intrinsics/mbarrier_basic.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. //! Generated conversion interfaces: `mbarrier_basic` intrinsics. diff --git a/crates/mir-lower/src/convert/generated_intrinsics/mbarrier_extended.rs b/crates/mir-lower/src/convert/generated_intrinsics/mbarrier_extended.rs index af9b91bac7..b454ebedfb 100644 --- a/crates/mir-lower/src/convert/generated_intrinsics/mbarrier_extended.rs +++ b/crates/mir-lower/src/convert/generated_intrinsics/mbarrier_extended.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. //! Generated conversion interfaces: `mbarrier_extended` intrinsics. diff --git a/crates/mir-lower/src/convert/generated_intrinsics/mod.rs b/crates/mir-lower/src/convert/generated_intrinsics/mod.rs index 77a22ea639..4aaa41a8ab 100644 --- a/crates/mir-lower/src/convert/generated_intrinsics/mod.rs +++ b/crates/mir-lower/src/convert/generated_intrinsics/mod.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. //! Generated conversion interfaces for admitted CUDA intrinsic families. diff --git a/crates/mir-lower/src/convert/generated_intrinsics/movmatrix.rs b/crates/mir-lower/src/convert/generated_intrinsics/movmatrix.rs index ccec7ad477..54dad4f80e 100644 --- a/crates/mir-lower/src/convert/generated_intrinsics/movmatrix.rs +++ b/crates/mir-lower/src/convert/generated_intrinsics/movmatrix.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. //! Generated conversion interfaces: `movmatrix` intrinsics. diff --git a/crates/mir-lower/src/convert/generated_intrinsics/packed_alu.rs b/crates/mir-lower/src/convert/generated_intrinsics/packed_alu.rs index 3f5852a074..8e3f0920c3 100644 --- a/crates/mir-lower/src/convert/generated_intrinsics/packed_alu.rs +++ b/crates/mir-lower/src/convert/generated_intrinsics/packed_alu.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. //! Generated conversion interfaces: `packed_alu` intrinsics. diff --git a/crates/mir-lower/src/convert/generated_intrinsics/packed_atomic.rs b/crates/mir-lower/src/convert/generated_intrinsics/packed_atomic.rs index 3edd9ea0d2..92fbc8c4b7 100644 --- a/crates/mir-lower/src/convert/generated_intrinsics/packed_atomic.rs +++ b/crates/mir-lower/src/convert/generated_intrinsics/packed_atomic.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. //! Generated conversion interfaces: `packed_atomic` intrinsics. diff --git a/crates/mir-lower/src/convert/generated_intrinsics/packed_conversion.rs b/crates/mir-lower/src/convert/generated_intrinsics/packed_conversion.rs index 81da7ba81b..a6786e12d4 100644 --- a/crates/mir-lower/src/convert/generated_intrinsics/packed_conversion.rs +++ b/crates/mir-lower/src/convert/generated_intrinsics/packed_conversion.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. //! Generated conversion interfaces: `packed_conversion` intrinsics. diff --git a/crates/mir-lower/src/convert/generated_intrinsics/prmt.rs b/crates/mir-lower/src/convert/generated_intrinsics/prmt.rs index 2d828e3e18..cebd21a026 100644 --- a/crates/mir-lower/src/convert/generated_intrinsics/prmt.rs +++ b/crates/mir-lower/src/convert/generated_intrinsics/prmt.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. //! Generated conversion interfaces: `prmt` intrinsics. diff --git a/crates/mir-lower/src/convert/generated_intrinsics/redux.rs b/crates/mir-lower/src/convert/generated_intrinsics/redux.rs index 3b4404a4d2..2222992016 100644 --- a/crates/mir-lower/src/convert/generated_intrinsics/redux.rs +++ b/crates/mir-lower/src/convert/generated_intrinsics/redux.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. //! Generated conversion interfaces: `redux` intrinsics. diff --git a/crates/mir-lower/src/convert/generated_intrinsics/register_mma.rs b/crates/mir-lower/src/convert/generated_intrinsics/register_mma.rs index 646b4afaf4..82378b8754 100644 --- a/crates/mir-lower/src/convert/generated_intrinsics/register_mma.rs +++ b/crates/mir-lower/src/convert/generated_intrinsics/register_mma.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. //! Generated conversion interfaces: `register_mma` intrinsics. diff --git a/crates/mir-lower/src/convert/generated_intrinsics/scalar_arithmetic.rs b/crates/mir-lower/src/convert/generated_intrinsics/scalar_arithmetic.rs index b8069ed352..f8a79afa7f 100644 --- a/crates/mir-lower/src/convert/generated_intrinsics/scalar_arithmetic.rs +++ b/crates/mir-lower/src/convert/generated_intrinsics/scalar_arithmetic.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. //! Generated conversion interfaces: `scalar_arithmetic` intrinsics. diff --git a/crates/mir-lower/src/convert/generated_intrinsics/scalar_conversion.rs b/crates/mir-lower/src/convert/generated_intrinsics/scalar_conversion.rs index 8e753029d5..6fb57d78cf 100644 --- a/crates/mir-lower/src/convert/generated_intrinsics/scalar_conversion.rs +++ b/crates/mir-lower/src/convert/generated_intrinsics/scalar_conversion.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. //! Generated conversion interfaces: `scalar_conversion` intrinsics. diff --git a/crates/mir-lower/src/convert/generated_intrinsics/scalar_math.rs b/crates/mir-lower/src/convert/generated_intrinsics/scalar_math.rs index 89f8c3b35a..976951a76d 100644 --- a/crates/mir-lower/src/convert/generated_intrinsics/scalar_math.rs +++ b/crates/mir-lower/src/convert/generated_intrinsics/scalar_math.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. //! Generated conversion interfaces: `scalar_math` intrinsics. diff --git a/crates/mir-lower/src/convert/generated_intrinsics/sparse_mma.rs b/crates/mir-lower/src/convert/generated_intrinsics/sparse_mma.rs index 8bcbb87e52..6719d49abe 100644 --- a/crates/mir-lower/src/convert/generated_intrinsics/sparse_mma.rs +++ b/crates/mir-lower/src/convert/generated_intrinsics/sparse_mma.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. //! Generated conversion interfaces: `sparse_mma` intrinsics. @@ -723,6 +723,125 @@ impl MirToLlvmConversion for SparseMmaOp { "mma.sp::ordered_metadata.sync.aligned.m16n8k128.row.col.satfinite.s32.u4.u4.s32 {$0, $1, $2, $3}, {$8, $9, $10, $11}, {$12, $13, $14, $15}, {$4, $5, $6, $7}, $16, $17;", "=r,=r,=r,=r,r,r,r,r,r,r,r,r,r,r,r,r,r,n", ), + ( + Some(&SparseMmaShapeAttr::M16n8k16), + Some(&SparseMmaAccumulatorAttr::F16), + Some(&SparseMmaElementAttr::F16), + Some(&SparseMmaElementAttr::F16), + Some(&SparseMmaLayoutAttr::Row), + Some(&SparseMmaLayoutAttr::Col), + Some(&SparseMmaOverflowAttr::NotApplicable), + Some(&SparseMmaMetadataAttr::Ordered), + Some(&SparseMmaSelectorAttr::ImmediateZeroThroughThree), + ) => ( + GeneratedMmaResultType::I32, + 2, + 8, + "mma.sp::ordered_metadata.sync.aligned.m16n8k16.row.col.f16.f16.f16.f16 {$0, $1}, {$4, $5}, {$6, $7}, {$2, $3}, $8, $9;", + "=r,=r,r,r,r,r,r,r,r,n", + ), + ( + Some(&SparseMmaShapeAttr::M16n8k16), + Some(&SparseMmaAccumulatorAttr::F32), + Some(&SparseMmaElementAttr::Bf16), + Some(&SparseMmaElementAttr::Bf16), + Some(&SparseMmaLayoutAttr::Row), + Some(&SparseMmaLayoutAttr::Col), + Some(&SparseMmaOverflowAttr::NotApplicable), + Some(&SparseMmaMetadataAttr::Ordered), + Some(&SparseMmaSelectorAttr::ImmediateZeroThroughThree), + ) => ( + GeneratedMmaResultType::F32, + 4, + 10, + "mma.sp::ordered_metadata.sync.aligned.m16n8k16.row.col.f32.bf16.bf16.f32 {$0, $1, $2, $3}, {$8, $9}, {$10, $11}, {$4, $5, $6, $7}, $12, $13;", + "=f,=f,=f,=f,f,f,f,f,r,r,r,r,r,n", + ), + ( + Some(&SparseMmaShapeAttr::M16n8k16), + Some(&SparseMmaAccumulatorAttr::F32), + Some(&SparseMmaElementAttr::F16), + Some(&SparseMmaElementAttr::F16), + Some(&SparseMmaLayoutAttr::Row), + Some(&SparseMmaLayoutAttr::Col), + Some(&SparseMmaOverflowAttr::NotApplicable), + Some(&SparseMmaMetadataAttr::Ordered), + Some(&SparseMmaSelectorAttr::ImmediateZeroThroughThree), + ) => ( + GeneratedMmaResultType::F32, + 4, + 10, + "mma.sp::ordered_metadata.sync.aligned.m16n8k16.row.col.f32.f16.f16.f32 {$0, $1, $2, $3}, {$8, $9}, {$10, $11}, {$4, $5, $6, $7}, $12, $13;", + "=f,=f,=f,=f,f,f,f,f,r,r,r,r,r,n", + ), + ( + Some(&SparseMmaShapeAttr::M16n8k16), + Some(&SparseMmaAccumulatorAttr::F32), + Some(&SparseMmaElementAttr::Tf32), + Some(&SparseMmaElementAttr::Tf32), + Some(&SparseMmaLayoutAttr::Row), + Some(&SparseMmaLayoutAttr::Col), + Some(&SparseMmaOverflowAttr::NotApplicable), + Some(&SparseMmaMetadataAttr::Ordered), + Some(&SparseMmaSelectorAttr::ImmediateZeroOrOne), + ) => ( + GeneratedMmaResultType::F32, + 4, + 14, + "mma.sp::ordered_metadata.sync.aligned.m16n8k16.row.col.f32.tf32.tf32.f32 {$0, $1, $2, $3}, {$8, $9, $10, $11}, {$12, $13, $14, $15}, {$4, $5, $6, $7}, $16, $17;", + "=f,=f,=f,=f,f,f,f,f,r,r,r,r,r,r,r,r,r,n", + ), + ( + Some(&SparseMmaShapeAttr::M16n8k32), + Some(&SparseMmaAccumulatorAttr::F16), + Some(&SparseMmaElementAttr::F16), + Some(&SparseMmaElementAttr::F16), + Some(&SparseMmaLayoutAttr::Row), + Some(&SparseMmaLayoutAttr::Col), + Some(&SparseMmaOverflowAttr::NotApplicable), + Some(&SparseMmaMetadataAttr::Ordered), + Some(&SparseMmaSelectorAttr::ImmediateZeroOrOne), + ) => ( + GeneratedMmaResultType::I32, + 2, + 12, + "mma.sp::ordered_metadata.sync.aligned.m16n8k32.row.col.f16.f16.f16.f16 {$0, $1}, {$4, $5, $6, $7}, {$8, $9, $10, $11}, {$2, $3}, $12, $13;", + "=r,=r,r,r,r,r,r,r,r,r,r,r,r,n", + ), + ( + Some(&SparseMmaShapeAttr::M16n8k32), + Some(&SparseMmaAccumulatorAttr::F32), + Some(&SparseMmaElementAttr::Bf16), + Some(&SparseMmaElementAttr::Bf16), + Some(&SparseMmaLayoutAttr::Row), + Some(&SparseMmaLayoutAttr::Col), + Some(&SparseMmaOverflowAttr::NotApplicable), + Some(&SparseMmaMetadataAttr::Ordered), + Some(&SparseMmaSelectorAttr::ImmediateZeroOrOne), + ) => ( + GeneratedMmaResultType::F32, + 4, + 14, + "mma.sp::ordered_metadata.sync.aligned.m16n8k32.row.col.f32.bf16.bf16.f32 {$0, $1, $2, $3}, {$8, $9, $10, $11}, {$12, $13, $14, $15}, {$4, $5, $6, $7}, $16, $17;", + "=f,=f,=f,=f,f,f,f,f,r,r,r,r,r,r,r,r,r,n", + ), + ( + Some(&SparseMmaShapeAttr::M16n8k32), + Some(&SparseMmaAccumulatorAttr::F32), + Some(&SparseMmaElementAttr::F16), + Some(&SparseMmaElementAttr::F16), + Some(&SparseMmaLayoutAttr::Row), + Some(&SparseMmaLayoutAttr::Col), + Some(&SparseMmaOverflowAttr::NotApplicable), + Some(&SparseMmaMetadataAttr::Ordered), + Some(&SparseMmaSelectorAttr::ImmediateZeroOrOne), + ) => ( + GeneratedMmaResultType::F32, + 4, + 14, + "mma.sp::ordered_metadata.sync.aligned.m16n8k32.row.col.f32.f16.f16.f32 {$0, $1, $2, $3}, {$8, $9, $10, $11}, {$12, $13, $14, $15}, {$4, $5, $6, $7}, $16, $17;", + "=f,=f,=f,=f,f,f,f,f,r,r,r,r,r,r,r,r,r,n", + ), ( Some(&SparseMmaShapeAttr::M16n8k32), Some(&SparseMmaAccumulatorAttr::S32), @@ -1981,6 +2100,23 @@ impl MirToLlvmConversion for SparseMmaOp { "mma.sp::ordered_metadata.sync.aligned.m16n8k64.row.col.satfinite.s32.u8.u8.s32 {$0, $1, $2, $3}, {$8, $9, $10, $11}, {$12, $13, $14, $15}, {$4, $5, $6, $7}, $16, $17;", "=r,=r,=r,=r,r,r,r,r,r,r,r,r,r,r,r,r,r,n", ), + ( + Some(&SparseMmaShapeAttr::M16n8k8), + Some(&SparseMmaAccumulatorAttr::F32), + Some(&SparseMmaElementAttr::Tf32), + Some(&SparseMmaElementAttr::Tf32), + Some(&SparseMmaLayoutAttr::Row), + Some(&SparseMmaLayoutAttr::Col), + Some(&SparseMmaOverflowAttr::NotApplicable), + Some(&SparseMmaMetadataAttr::Ordered), + Some(&SparseMmaSelectorAttr::ImmediateZeroThroughThree), + ) => ( + GeneratedMmaResultType::F32, + 4, + 10, + "mma.sp::ordered_metadata.sync.aligned.m16n8k8.row.col.f32.tf32.tf32.f32 {$0, $1, $2, $3}, {$8, $9}, {$10, $11}, {$4, $5, $6, $7}, $12, $13;", + "=f,=f,=f,=f,f,f,f,f,r,r,r,r,r,n", + ), _ => { return pliron::input_err!( self.get_operation().deref(ctx).loc(), diff --git a/crates/mir-lower/src/convert/generated_intrinsics/sreg.rs b/crates/mir-lower/src/convert/generated_intrinsics/sreg.rs index d36148e7b7..49ddff7317 100644 --- a/crates/mir-lower/src/convert/generated_intrinsics/sreg.rs +++ b/crates/mir-lower/src/convert/generated_intrinsics/sreg.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. //! Generated conversion interfaces: `sreg` intrinsics. diff --git a/crates/mir-lower/src/convert/generated_intrinsics/stmatrix.rs b/crates/mir-lower/src/convert/generated_intrinsics/stmatrix.rs index ae4b41a915..a167653808 100644 --- a/crates/mir-lower/src/convert/generated_intrinsics/stmatrix.rs +++ b/crates/mir-lower/src/convert/generated_intrinsics/stmatrix.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. //! Generated conversion interfaces: `stmatrix` intrinsics. diff --git a/crates/mir-lower/src/convert/generated_intrinsics/sync.rs b/crates/mir-lower/src/convert/generated_intrinsics/sync.rs index f6f1fe1611..27285e8185 100644 --- a/crates/mir-lower/src/convert/generated_intrinsics/sync.rs +++ b/crates/mir-lower/src/convert/generated_intrinsics/sync.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. //! Generated conversion interfaces: `sync` intrinsics. diff --git a/crates/mir-lower/src/convert/generated_intrinsics/tcgen05.rs b/crates/mir-lower/src/convert/generated_intrinsics/tcgen05.rs index 6502dcbd57..b8d0b4560d 100644 --- a/crates/mir-lower/src/convert/generated_intrinsics/tcgen05.rs +++ b/crates/mir-lower/src/convert/generated_intrinsics/tcgen05.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. //! Generated conversion interfaces: `tcgen05` intrinsics. diff --git a/crates/mir-lower/src/convert/generated_intrinsics/tma.rs b/crates/mir-lower/src/convert/generated_intrinsics/tma.rs index b1b217b0d5..fa1afb7ff3 100644 --- a/crates/mir-lower/src/convert/generated_intrinsics/tma.rs +++ b/crates/mir-lower/src/convert/generated_intrinsics/tma.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. //! Generated conversion interfaces: `tma` intrinsics. diff --git a/crates/mir-lower/src/convert/generated_intrinsics/vote.rs b/crates/mir-lower/src/convert/generated_intrinsics/vote.rs index 8d65992489..04e4eec15b 100644 --- a/crates/mir-lower/src/convert/generated_intrinsics/vote.rs +++ b/crates/mir-lower/src/convert/generated_intrinsics/vote.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. //! Generated conversion interfaces: `vote` intrinsics. diff --git a/crates/mir-lower/src/convert/generated_intrinsics/warp_barrier.rs b/crates/mir-lower/src/convert/generated_intrinsics/warp_barrier.rs index 31cfb8b7b6..29f44b88b3 100644 --- a/crates/mir-lower/src/convert/generated_intrinsics/warp_barrier.rs +++ b/crates/mir-lower/src/convert/generated_intrinsics/warp_barrier.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. //! Generated conversion interfaces: `warp_barrier` intrinsics. diff --git a/crates/mir-lower/src/convert/generated_intrinsics/warp_match.rs b/crates/mir-lower/src/convert/generated_intrinsics/warp_match.rs index 348016b9f6..eacb6710b7 100644 --- a/crates/mir-lower/src/convert/generated_intrinsics/warp_match.rs +++ b/crates/mir-lower/src/convert/generated_intrinsics/warp_match.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. //! Generated conversion interfaces: `warp_match` intrinsics. diff --git a/crates/mir-lower/src/convert/generated_intrinsics/warp_shuffle.rs b/crates/mir-lower/src/convert/generated_intrinsics/warp_shuffle.rs index c52c196802..507077c9e6 100644 --- a/crates/mir-lower/src/convert/generated_intrinsics/warp_shuffle.rs +++ b/crates/mir-lower/src/convert/generated_intrinsics/warp_shuffle.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. //! Generated conversion interfaces: `warp_shuffle` intrinsics. diff --git a/crates/mir-lower/src/convert/generated_intrinsics/wgmma_control.rs b/crates/mir-lower/src/convert/generated_intrinsics/wgmma_control.rs index 1de6f6d52c..ec0582db76 100644 --- a/crates/mir-lower/src/convert/generated_intrinsics/wgmma_control.rs +++ b/crates/mir-lower/src/convert/generated_intrinsics/wgmma_control.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. //! 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All rights reserved. +# SPDX-License-Identifier: Apache-2.0 + +[package] +name = "sparse_mma_ordered_float" +version = "0.1.0" +edition = "2024" +authors = ["NVIDIA Corporation"] +license = "Apache-2.0" + +[workspace] + +[dependencies] +cuda-device = { path = "../../../cuda-device" } +cuda-host = { path = "../../../cuda-host" } +cuda-core = { path = "../../../cuda-core" } diff --git a/crates/rustc-codegen-cuda/examples/sparse_mma_ordered_float/src/main.rs b/crates/rustc-codegen-cuda/examples/sparse_mma_ordered_float/src/main.rs new file mode 100644 index 0000000000..68086277eb --- /dev/null +++ b/crates/rustc-codegen-cuda/examples/sparse_mma_ordered_float/src/main.rs @@ -0,0 +1,351 @@ +/* SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: Apache-2.0 */ +//! GPU oracle for all eight ordered sparse floating MMA forms. +//! +//! Why the inputs look the way they do: +//! - the first cut of this oracle used val(x,y) = 1 + ((x+y) & 1); that +//! parity pattern made the A and B fragments bitwise IDENTICAL in every +//! lane, so an a<->b swap in the lowering still passed: +//! +//! ```text +//! old: A[r][q] = f(r+q) B[k][c] = f(k+c) -> same lane bytes +//! new: A[r][j] = 1+(3r+5j)%7, B[k][c] = 1+(2k+3c)%8 -> distinct +//! ``` +//! +//! - metadata is no longer the single code 0x4: every valid ordered code +//! (0x4 0x8 0x9 0xc 0xd 0xe; tf32: 0x4 0xe) cycles by (row+chunk), so a +//! metadata misroute picks different B rows and the sum changes; +//! - each selector domain runs a NONZERO selector (2/1/3 for the 0-3 forms, +//! 1 for the 0-1 forms), and non-selected lanes carry a valid DECOY +//! pattern (every code bumped one table slot), so reading the wrong +//! lane's metadata register also changes the result; +//! - values stay small (A<=7, B<=8, C<=31, sums < 1024) so f16, bf16, and +//! tf32 all accumulate exactly and the host reference is integer math. +use cuda_core::{CudaContext, DeviceBuffer, LaunchConfig}; +use cuda_device::{DisjointSlice, cuda_module, kernel, thread, wmma}; + +// Positionally distinct inputs: A over compressed (row, j), B over (k, col). +const fn a_val(r: u32, j: u32) -> u32 { + 1 + ((3 * r + 5 * j) % 7) +} +const fn b_val(k: u32, c: u32) -> u32 { + 1 + ((2 * k + 3 * c) % 8) +} +const fn c_val(r: u32, c: u32) -> u32 { + (5 * r + 7 * c) % 32 +} + +// Ordered metadata code for (row, chunk); bump=1 yields the decoy pattern +// (next code in the table) handed to non-selected lanes. +// tf=0: f16/bf16 6-code table; tf=1: tf32 2-code table. +// The tf32 index mixes r/8 and g/3 so no wrong (lane, nibble) -> (row, chunk) +// reading can reproduce the true pattern by periodicity (rows 8 apart and +// chunks 4 apart would otherwise alias under a plain (r+g) parity). +const fn meta_code(r: u32, g: u32, bump: u32, tf: u32) -> u32 { + if tf == 1 { + if (r + r / 8 + g + g / 3 + bump) & 1 == 0 { + 0x4 + } else { + 0xe + } + } else { + match (r + g + bump) % 6 { + 0 => 0x4, + 1 => 0x8, + 2 => 0x9, + 3 => 0xc, + 4 => 0xd, + _ => 0xe, + } + } +} + +// Exact bit patterns for small integers (all values here fit losslessly). +const fn f32_bits(x: u32) -> u32 { + if x == 0 { + return 0; + } + let mut e = 0; + while (x >> e) > 1 { + e += 1; + } + ((127 + e) << 23) | ((x << (23 - e)) & 0x007f_ffff) +} +const fn f16_bits(x: u32) -> u32 { + if x == 0 { + return 0; + } + let mut e = 0; + while (x >> e) > 1 { + e += 1; + } + ((15 + e) << 10) | ((x << (10 - e)) & 0x03ff) +} +const fn bf16_bits(x: u32) -> u32 { + f32_bits(x) >> 16 +} +const fn pack(lo: u32, hi: u32) -> u32 { + lo | (hi << 16) +} + +#[cuda_module] +mod kernels { + use super::*; + + // f16/bf16 A fragment register n: row l/4 (+8 for odd n), + // compressed cols (l%4)*2 + 8*(n/2) and +1, packed lo/hi. + fn af(l: u32, n: u32, bf: u32) -> u32 { + let r = l / 4 + 8 * (n & 1); + let j = (l & 3) * 2 + 8 * (n / 2); + if bf == 1 { + pack(bf16_bits(a_val(r, j)), bf16_bits(a_val(r, j + 1))) + } else { + pack(f16_bits(a_val(r, j)), f16_bits(a_val(r, j + 1))) + } + } + // f16/bf16 B fragment register n: col l/4, rows (l%4)*2 + 8n and +1. + fn bf(l: u32, n: u32, b16: u32) -> u32 { + let c = l / 4; + let k = (l & 3) * 2 + 8 * n; + if b16 == 1 { + pack(bf16_bits(b_val(k, c)), bf16_bits(b_val(k + 1, c))) + } else { + pack(f16_bits(b_val(k, c)), f16_bits(b_val(k + 1, c))) + } + } + // tf32 A fragment register n: row l/4 (+8 odd n), compressed col (l%4)+4*(n/2). + fn at(l: u32, n: u32) -> u32 { + f32_bits(a_val(l / 4 + 8 * (n & 1), (l & 3) + 4 * (n / 2))) + } + // tf32 B fragment register n: row (l%4)+4n, col l/4. + fn bt(l: u32, n: u32) -> u32 { + f32_bits(b_val((l & 3) + 4 * n, l / 4)) + } + // f32 accumulator quad: rows l/4, l/4+8; cols (l%4)*2, +1. + fn cf(l: u32) -> [f32; 4] { + let r = l / 4; + let c = (l & 3) * 2; + [ + c_val(r, c) as f32, + c_val(r, c + 1) as f32, + c_val(r + 8, c) as f32, + c_val(r + 8, c + 1) as f32, + ] + } + // packed f16 accumulator register n: row l/4+8n, cols (l%4)*2, +1. + fn cp(l: u32, n: u32) -> u32 { + let r = l / 4 + 8 * n; + let c = (l & 3) * 2; + pack(f16_bits(c_val(r, c)), f16_bits(c_val(r, c + 1))) + } + // One metadata thread per quad (k16 f16/bf16, k8 tf32; 4 chunks/row): + // bits [15:0] row g, bits [31:16] row g+8, nibble j = chunk j. + // Only lane l%4 == sel carries the real pattern; the rest carry the decoy. + fn meta_one(l: u32, sel: u32, tf: u32) -> u32 { + let g = l / 4; + let bump = if l % 4 == sel { 0 } else { 1 }; + let mut m = 0; + let mut j = 0; + while j < 4 { + m |= meta_code(g, j, bump, tf) << (4 * j); + m |= meta_code(g + 8, j, bump, tf) << (16 + 4 * j); + j += 1; + } + m + } + // Metadata thread pair per quad (k32 f16/bf16, k16 tf32; 8 chunks/row): + // selector s picks lanes {2s, 2s+1} of the quad, and the pair splits + // the K dimension, keeping the one-thread [row g | row g+8] register + // split (verified against sm_120 hardware; a row-per-thread split + // fails the oracle): + // + // lane 2s+t: bits [15:0] row g chunks 4t..4t+3 + // bits [31:16] row g+8 chunks 4t..4t+3 + fn meta_pair(l: u32, sel: u32, tf: u32) -> u32 { + let g = l / 4; + let t = (l & 3) % 2; + let bump = if (l & 3) / 2 == sel { 0 } else { 1 }; + let mut m = 0; + let mut j = 0; + while j < 4 { + m |= meta_code(g, 4 * t + j, bump, tf) << (4 * j); + m |= meta_code(g + 8, 4 * t + j, bump, tf) << (16 + 4 * j); + j += 1; + } + m + } + + #[kernel] + pub fn oracle(mut po: DisjointSlice, mut fo: DisjointSlice) { + let l = thread::threadIdx_x(); + let c = [cp(l, 0), cp(l, 1)]; + let f = cf(l); + let (h16, h32, x16, x32, y16, y32, z8, z16) = unsafe { + ( + // selector domains: k16 f16/bf16 and k8 tf32 accept 0-3, + // k32 and k16 tf32 accept 0-1; every domain runs a nonzero one. + wmma::mma_sp_ordered_metadata_m16n8k16_f16_f16( + c, + [af(l, 0, 0), af(l, 1, 0)], + [bf(l, 0, 0), bf(l, 1, 0)], + meta_one(l, 2, 0), + 2, + ), + wmma::mma_sp_ordered_metadata_m16n8k32_f16_f16( + c, + [af(l, 0, 0), af(l, 1, 0), af(l, 2, 0), af(l, 3, 0)], + [bf(l, 0, 0), bf(l, 1, 0), bf(l, 2, 0), bf(l, 3, 0)], + meta_pair(l, 0, 0), + 0, + ), + wmma::mma_sp_ordered_metadata_m16n8k16_f32_f16( + f, + [af(l, 0, 0), af(l, 1, 0)], + [bf(l, 0, 0), bf(l, 1, 0)], + meta_one(l, 1, 0), + 1, + ), + wmma::mma_sp_ordered_metadata_m16n8k32_f32_f16( + f, + [af(l, 0, 0), af(l, 1, 0), af(l, 2, 0), af(l, 3, 0)], + [bf(l, 0, 0), bf(l, 1, 0), bf(l, 2, 0), bf(l, 3, 0)], + meta_pair(l, 1, 0), + 1, + ), + wmma::mma_sp_ordered_metadata_m16n8k16_f32_bf16( + f, + [af(l, 0, 1), af(l, 1, 1)], + [bf(l, 0, 1), bf(l, 1, 1)], + meta_one(l, 3, 0), + 3, + ), + wmma::mma_sp_ordered_metadata_m16n8k32_f32_bf16( + f, + [af(l, 0, 1), af(l, 1, 1), af(l, 2, 1), af(l, 3, 1)], + [bf(l, 0, 1), bf(l, 1, 1), bf(l, 2, 1), bf(l, 3, 1)], + meta_pair(l, 0, 0), + 0, + ), + wmma::mma_sp_ordered_metadata_m16n8k8_f32_tf32( + f, + [at(l, 0), at(l, 1)], + [bt(l, 0), bt(l, 1)], + meta_one(l, 3, 1), + 3, + ), + wmma::mma_sp_ordered_metadata_m16n8k16_f32_tf32( + f, + [at(l, 0), at(l, 1), at(l, 2), at(l, 3)], + [bt(l, 0), bt(l, 1), bt(l, 2), bt(l, 3)], + meta_pair(l, 1, 1), + 1, + ), + ) + }; + let p = l as usize * 4; + for (i, v) in h16.into_iter().chain(h32).enumerate() { + unsafe { *po.get_unchecked_mut(p + i) = v } + } + let p = l as usize * 24; + for (i, v) in x16 + .into_iter() + .chain(x32) + .chain(y16) + .chain(y32) + .chain(z8) + .chain(z16) + .enumerate() + { + unsafe { *fo.get_unchecked_mut(p + i) = v } + } + } +} + +/// Register slot -> (row, col) for one lane's four logical accumulators. +fn rc(l: usize, r: usize) -> (usize, usize) { + (l / 4 + 8 * (r / 2), (l % 4) * 2 + r % 2) +} + +/// Host GEMM for the f16/bf16 forms: per 4-wide chunk g the ordered code +/// (r,g) keeps columns 4g+i0 and 4g+i1 of logical A. +fn expect_h(r: usize, c: usize, kdim: usize) -> u32 { + let (r, c) = (r as u32, c as u32); + let mut s = c_val(r, c); + for g in 0..(kdim as u32) / 4 { + let m = meta_code(r, g, 0, 0); + let (i0, i1) = (m & 3, (m >> 2) & 3); + s += a_val(r, 2 * g) * b_val(4 * g + i0, c); + s += a_val(r, 2 * g + 1) * b_val(4 * g + i1, c); + } + s +} + +/// Host GEMM for the tf32 forms: per 2-wide chunk g, 0x4 keeps column 2g +/// and 0xe keeps column 2g+1. +fn expect_t(r: usize, c: usize, kdim: usize) -> u32 { + let (r, c) = (r as u32, c as u32); + let mut s = c_val(r, c); + for g in 0..(kdim as u32) / 2 { + let e = if meta_code(r, g, 0, 1) == 0x4 { 0 } else { 1 }; + s += a_val(r, g) * b_val(2 * g + e, c); + } + s +} + +fn main() { + let ctx = CudaContext::new(0).expect("CUDA context"); + let (major, minor) = ctx.compute_capability().unwrap(); + if major < 8 { + println!("skipping: ordered sparse MMA requires sm_80+, found sm_{major}{minor}"); + return; + } + let s = ctx.default_stream(); + let m = kernels::load(&ctx).expect("module"); + let mut pd = DeviceBuffer::::zeroed(&s, 128).unwrap(); + let mut fd = DeviceBuffer::::zeroed(&s, 768).unwrap(); + let cfg = LaunchConfig { + block_dim: (32, 1, 1), + grid_dim: (1, 1, 1), + shared_mem_bytes: 0, + }; + unsafe { m.oracle(&s, cfg, &mut pd, &mut fd) }.unwrap(); + let p = pd.to_host_vec(&s).unwrap(); + let f = fd.to_host_vec(&s).unwrap(); + let mut bad = 0; + for l in 0..32 { + // packed-f16 accumulators: [k16_f16_f16, k32_f16_f16] + for v in 0..2 { + for r in 0..4 { + let w = p[l * 4 + v * 2 + r / 2]; + let got = if r % 2 == 0 { w & 0xffff } else { w >> 16 }; + let (x, y) = rc(l, r); + let want = f16_bits(expect_h(x, y, [16, 32][v])); + if got != want { + eprintln!("f16 variant {v} lane {l} reg {r}: {got:#x} != {want:#x}"); + bad += 1 + } + } + } + // f32 accumulators: [k16_f32_f16, k32_f32_f16, k16_f32_bf16, + // k32_f32_bf16, k8_f32_tf32, k16_f32_tf32] + for v in 0..6 { + for r in 0..4 { + let got = f[l * 24 + v * 4 + r]; + let (x, y) = rc(l, r); + let want = if v < 4 { + expect_h(x, y, [16, 32, 16, 32][v]) + } else { + expect_t(x, y, [8, 16][v - 4]) + } as f32; + if got != want { + eprintln!("f32 variant {v} lane {l} reg {r}: {got} != {want}"); + bad += 1 + } + } + } + } + assert_eq!(bad, 0, "accumulator mismatches"); + println!( + "SUCCESS: all 8 variants; all 32 lanes and 4 logical accumulators/lane match host GEMM" + ) +} diff --git a/crates/rustc-codegen-cuda/src/generated_intrinsics.rs b/crates/rustc-codegen-cuda/src/generated_intrinsics.rs index d387bb69f0..d81ea49143 100644 --- a/crates/rustc-codegen-cuda/src/generated_intrinsics.rs +++ b/crates/rustc-codegen-cuda/src/generated_intrinsics.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. // LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. //! Generated collector predicates for intrinsic placeholder functions. @@ -592,6 +592,13 @@ pub(crate) const GENERATED_INTRINSIC_CANONICAL_PATHS: &[&str] = &[ "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0206", "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0210", "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0209", + "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i1021", + "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i1020", + "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i1022", + "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i1019", + "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i1024", + "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i1023", + "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i1025", "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0171", "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0175", "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0172", @@ -666,6 +673,7 @@ pub(crate) const GENERATED_INTRINSIC_CANONICAL_PATHS: &[&str] = &[ "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0182", "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0186", "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0185", + "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i1018", "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0305", "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0066", "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0076", @@ -1612,6 +1620,13 @@ pub(crate) const GENERATED_INTRINSIC_PUBLIC_PATHS: &[&str] = &[ "cuda_intrinsics::matrix::mma_sp_ordered_metadata_m16n8k128_s32_u4_s4", "cuda_intrinsics::matrix::mma_sp_ordered_metadata_m16n8k128_s32_u4_s4_satfinite", "cuda_intrinsics::matrix::mma_sp_ordered_metadata_m16n8k128_s32_u4_satfinite", + "cuda_intrinsics::matrix::mma_sp_ordered_metadata_m16n8k16_f16_f16", + "cuda_intrinsics::matrix::mma_sp_ordered_metadata_m16n8k16_f32_bf16", + "cuda_intrinsics::matrix::mma_sp_ordered_metadata_m16n8k16_f32_f16", + "cuda_intrinsics::matrix::mma_sp_ordered_metadata_m16n8k16_f32_tf32", + "cuda_intrinsics::matrix::mma_sp_ordered_metadata_m16n8k32_f16_f16", + "cuda_intrinsics::matrix::mma_sp_ordered_metadata_m16n8k32_f32_bf16", + "cuda_intrinsics::matrix::mma_sp_ordered_metadata_m16n8k32_f32_f16", "cuda_intrinsics::matrix::mma_sp_ordered_metadata_m16n8k32_s32_s8", "cuda_intrinsics::matrix::mma_sp_ordered_metadata_m16n8k32_s32_s8_satfinite", "cuda_intrinsics::matrix::mma_sp_ordered_metadata_m16n8k32_s32_s8_u8", @@ -1686,6 +1701,7 @@ pub(crate) const GENERATED_INTRINSIC_PUBLIC_PATHS: &[&str] = &[ "cuda_intrinsics::matrix::mma_sp_ordered_metadata_m16n8k64_s32_u8_s8", "cuda_intrinsics::matrix::mma_sp_ordered_metadata_m16n8k64_s32_u8_s8_satfinite", "cuda_intrinsics::matrix::mma_sp_ordered_metadata_m16n8k64_s32_u8_satfinite", + "cuda_intrinsics::matrix::mma_sp_ordered_metadata_m16n8k8_f32_tf32", "cuda_intrinsics::matrix::movmatrix_trans_b16", "cuda_intrinsics::bf16x2::mul_bf16x2", "cuda_intrinsics::f16x2::mul_f16x2", @@ -2638,6 +2654,13 @@ pub(crate) fn is_generated_intrinsic_canonical_path(path: &str) -> bool { | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0206" | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0210" | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0209" + | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i1021" + | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i1020" + | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i1022" + | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i1019" + | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i1024" + | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i1023" + | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i1025" | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0171" | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0175" | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0172" @@ -2712,6 +2735,7 @@ pub(crate) fn is_generated_intrinsic_canonical_path(path: &str) -> bool { | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0182" | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0186" | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0185" + | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i1018" | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0305" | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0066" | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0076" @@ -3660,6 +3684,13 @@ pub(crate) fn is_generated_intrinsic_compatibility_path(path: &str) -> bool { | "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k128_s32_u4_s4" | "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k128_s32_u4_s4_satfinite" | "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k128_s32_u4_satfinite" + | "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k16_f16_f16" + | "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k16_f32_bf16" + | "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k16_f32_f16" + | "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k16_f32_tf32" + | "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k32_f16_f16" + | "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k32_f32_bf16" + | "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k32_f32_f16" | "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k32_s32_s8" | "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k32_s32_s8_satfinite" | "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k32_s32_s8_u8" @@ -3734,6 +3765,7 @@ pub(crate) fn is_generated_intrinsic_compatibility_path(path: &str) -> bool { | "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_s32_u8_s8" | "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_s32_u8_s8_satfinite" | "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_s32_u8_satfinite" + | "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k8_f32_tf32" | "cuda_device::wmma::movmatrix_trans_b16" | "cuda_device::bf16x2::mul_bf16x2" | "cuda_device::f16x2::mul_f16x2" diff --git a/cuda-oxide-book/compiler/mlir-dialects.md b/cuda-oxide-book/compiler/mlir-dialects.md index 87433bd8d1..56b4a7161e 100644 --- a/cuda-oxide-book/compiler/mlir-dialects.md +++ b/cuda-oxide-book/compiler/mlir-dialects.md @@ -296,11 +296,11 @@ they become `call` instructions to `@llvm.nvvm.*` intrinsics. ### Architecture Coverage -At catalog SHA-256 `02a6a6b3` (the stamp in every `ops/generated/` file +At catalog SHA-256 `20bc41c2` (the stamp in every `ops/generated/` file header), the dialect holds 576 operations across 42 modules, and they come from two different places. The split is the first thing to know about it, because it decides where -- and whether -- you would add one. If the header -stamp no longer starts with `02a6a6b3`, the counts on this page predate the +stamp no longer starts with `20bc41c2`, the counts on this page predate the catalog you are reading. **Hand-written**, directly under `crates/dialect-nvvm/src/ops/`. These are the @@ -320,7 +320,7 @@ describe. There are seven modules and 26 operations: **Generated**, under `ops/generated/`, from `intrinsics/catalog.json` by `cuda-intrinsics-gen`. Every file there opens with `// @generated ... DO NOT EDIT.`, and editing one by hand is undone by the next generator run. This is -the large majority -- 35 modules and 550 operations, resolved from 1017 catalog +the large majority -- 35 modules and 550 operations, resolved from 1025 catalog entries, since several intrinsics can share one structural op: | Area | Modules | Ops | diff --git a/intrinsics/abi-v1.toml b/intrinsics/abi-v1.toml index 3a9501ac4a..9e756aee3b 100644 --- a/intrinsics/abi-v1.toml +++ b/intrinsics/abi-v1.toml @@ -7089,3 +7089,59 @@ status = "active" catalog_id = "mbarrier_arrive_no_complete" operation_key = "barrier.mbarrier.arrive.no_complete.shared.cta" raw_rust_signature = { safe = false, arguments = ["*const u64", "u32"], result = "u64" } + +[[entry]] +abi_id = "i1018" +status = "active" +catalog_id = "mma_sp_ordered_metadata_m16n8k8_f32_tf32" +operation_key = "matrix.mma.sp.m16n8k8.row.col.f32.tf32.tf32.f32.not_applicable.ordered_metadata" +raw_rust_signature = { safe = false, arguments = ["[f32; 4]", "[u32; 2]", "[u32; 2]", "u32", "u32"], result = "[f32; 4]" } + +[[entry]] +abi_id = "i1019" +status = "active" +catalog_id = "mma_sp_ordered_metadata_m16n8k16_f32_tf32" +operation_key = "matrix.mma.sp.m16n8k16.row.col.f32.tf32.tf32.f32.not_applicable.ordered_metadata" +raw_rust_signature = { safe = false, arguments = ["[f32; 4]", "[u32; 4]", "[u32; 4]", "u32", "u32"], result = "[f32; 4]" } + +[[entry]] +abi_id = "i1020" +status = "active" +catalog_id = "mma_sp_ordered_metadata_m16n8k16_f32_bf16" +operation_key = "matrix.mma.sp.m16n8k16.row.col.f32.bf16.bf16.f32.not_applicable.ordered_metadata" +raw_rust_signature = { safe = false, arguments = ["[f32; 4]", "[u32; 2]", "[u32; 2]", "u32", "u32"], result = "[f32; 4]" } + +[[entry]] +abi_id = "i1021" +status = "active" +catalog_id = "mma_sp_ordered_metadata_m16n8k16_f16_f16" +operation_key = "matrix.mma.sp.m16n8k16.row.col.f16.f16.f16.f16.not_applicable.ordered_metadata" +raw_rust_signature = { safe = false, arguments = ["[u32; 2]", "[u32; 2]", "[u32; 2]", "u32", "u32"], result = "[u32; 2]" } + +[[entry]] +abi_id = "i1022" +status = "active" +catalog_id = "mma_sp_ordered_metadata_m16n8k16_f32_f16" +operation_key = "matrix.mma.sp.m16n8k16.row.col.f32.f16.f16.f32.not_applicable.ordered_metadata" +raw_rust_signature = { safe = false, arguments = ["[f32; 4]", "[u32; 2]", "[u32; 2]", "u32", "u32"], result = "[f32; 4]" } + +[[entry]] +abi_id = "i1023" +status = "active" +catalog_id = "mma_sp_ordered_metadata_m16n8k32_f32_bf16" +operation_key = "matrix.mma.sp.m16n8k32.row.col.f32.bf16.bf16.f32.not_applicable.ordered_metadata" +raw_rust_signature = { safe = false, arguments = ["[f32; 4]", "[u32; 4]", "[u32; 4]", "u32", "u32"], result = "[f32; 4]" } + +[[entry]] +abi_id = "i1024" +status = "active" +catalog_id = "mma_sp_ordered_metadata_m16n8k32_f16_f16" +operation_key = "matrix.mma.sp.m16n8k32.row.col.f16.f16.f16.f16.not_applicable.ordered_metadata" +raw_rust_signature = { safe = false, arguments = ["[u32; 2]", "[u32; 4]", "[u32; 4]", "u32", "u32"], result = "[u32; 2]" } + +[[entry]] +abi_id = "i1025" +status = "active" +catalog_id = "mma_sp_ordered_metadata_m16n8k32_f32_f16" +operation_key = "matrix.mma.sp.m16n8k32.row.col.f32.f16.f16.f32.not_applicable.ordered_metadata" +raw_rust_signature = { safe = false, arguments = ["[f32; 4]", "[u32; 4]", "[u32; 4]", "u32", "u32"], result = "[f32; 4]" } diff --git a/intrinsics/catalog.json b/intrinsics/catalog.json index 492421e7b6..03dfb5bae6 100644 --- a/intrinsics/catalog.json +++ b/intrinsics/catalog.json @@ -11,8 +11,8 @@ }, "inputs": { "imported_sha256": "3f54245b231a5b6e19f3225710c3865b7e1a106242cce873250ef5fdc32e532e", - "overlay_sha256": "93536ad1de7e6998757233dd621867bde7a01698617fe3902516685cdf35d7b7", - "abi_ledger_sha256": "56005538d9948936227e0ec1166a32d81137d0b608f5ccc43ec809d786f2e87f", + "overlay_sha256": "27bd921ce4ea1a6f8ad82f2b9a0435f43abacc327b734cd034729a24cb43c401", + "abi_ledger_sha256": "a34301233f6b8cfda7d876a07377d5478922e85f9ba58bdacd37b676f9f6fba8", "evidence_sha256": [ "cuda-12.0-libnvvm-12.0.140-ex2-f16.json:7102ea7d567ff2d2eb75a0384148d2e5eb6e605c26a5b98c71371fa3c46adef6", "cuda-12.9-libnvvm-12.9.86-f32x2.json:bc5bb505677989affa9ac1044da772b4eb349700dc65e16f09fffffa1f5c493e", @@ -46,6 +46,7 @@ "cuda-13.3-libnvvm-13.3.33-scalar-math.json:38afa3f8bf6588dfc1eafe90df3eee1c1bb953a5d4e58ca68a3b62df44289f0b", "cuda-13.3-libnvvm-13.3.33-sparse-mma-int8-m16n8k64.json:74b5dec9a9db352ea7eb1ee0b1470ba5a56f84f0ed55bf034a60fc29790b6d95", "cuda-13.3-libnvvm-13.3.33-sparse-mma-int8.json:ff0fd4a21e609d10993df1ce96a20e959dfbf2c9da0d397579957b18d2ad8a3f", + "cuda-13.3-libnvvm-13.3.33-sparse-mma-ordered-ampere-float.json:94d97593838d9c435ebdc0e0742c9267e72693c92fbcdae35504223cbb3c1515", "cuda-13.3-libnvvm-13.3.33-sparse-mma-ordered-f8f6f4-f16.json:a28dc4abd510e7c721fdcc1844f4d6f3c30b007ca0e6df77a51cbb2248d168c6", "cuda-13.3-libnvvm-13.3.33-sparse-mma-ordered-f8f6f4-f32.json:648cda8b8a673afaed08a7712f5e18272a5deb3c5a77214bc1f083cabc884b54", "cuda-13.3-libnvvm-13.3.33-sparse-mma-ordered-int4-m16n8k128.json:97d4924915387ce9852ad176d4e1264538f88fb6a20114cbf601297e0d089f32", @@ -106,6 +107,7 @@ "rust-llvm-23.1.0-16696adc-scalar-math.json:1a9e7994e07b5b53390df11a7e1805aa46176d21c8ed7e988433aee578c4dd47", "rust-llvm-23.1.0-16696adc-sparse-mma-int8-m16n8k64.json:2c0588c11569a4057647c099cfca9adfc449f3b3aea4e387f440a47e79d9b241", "rust-llvm-23.1.0-16696adc-sparse-mma-int8.json:9023c5c47bf1ad7266a13be8c4024d34e4e7d1efed6582affbbb9cdcdcfbea01", + "rust-llvm-23.1.0-16696adc-sparse-mma-ordered-ampere-float.json:c4356a2f779613e81041f257a2f976f3edf302be5b0445eab8888841cc89361f", "rust-llvm-23.1.0-16696adc-sparse-mma-ordered-f8f6f4-f16.json:8569d7303b1a5af418214f2548e4b10c825c06c524dbecbc35b8ab0d4e2cf7ba", "rust-llvm-23.1.0-16696adc-sparse-mma-ordered-f8f6f4-f32.json:d6b99f5f4fb88b145f24dba9da662e052137b05a6d2616731d08ab858a4e0541", "rust-llvm-23.1.0-16696adc-sparse-mma-ordered-int4-m16n8k128.json:3a65cb8976f0fb35ca50a7e58943ed092d4e33a8dba84b637402bd3224d7ef21", @@ -189718,17 +189720,17 @@ "summary": "Multiplies warp-distributed sparse unsigned A and unsigned B INT4 fragments with ordered sparsity metadata and adds a saturating s32 accumulator." }, { - "id": "mma_sp_ordered_metadata_m16n8k32_s32_s8", - "operation_key": "matrix.mma.sp.m16n8k32.row.col.s32.s8.s8.s32.wrapping.ordered_metadata", + "id": "mma_sp_ordered_metadata_m16n8k16_f16_f16", + "operation_key": "matrix.mma.sp.m16n8k16.row.col.f16.f16.f16.f16.not_applicable.ordered_metadata", "family": "sparse_mma", "source": { "kind": "llvm_imported", - "source_record": "int_nvvm_mma_sp_ordered_metadata_m16n8k32_row_col_s8" + "source_record": "int_nvvm_mma_sp_ordered_metadata_m16n8k16_row_col_f16_f16" }, "selections": [ { - "source_record": "anonymous_19644", - "asm": "mma.sp::ordered_metadata.sync.aligned.m16n8k32.row.col.s32.s8.s8.s32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1}},\n\t\t{{$rb0, $rb1}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}},\n\t\t$metadata,\n\t\t$selector;", + "source_record": "anonymous_19554", + "asm": "mma.sp::ordered_metadata.sync.aligned.m16n8k16.row.col.f16.f16.f16.f16\n\t\t{{$rd0, $rd1}},\n\t\t{{$ra0, $ra1}},\n\t\t{{$rb0, $rb1}},\n\t\t{{$rc0, $rc1}},\n\t\t$metadata,\n\t\t$selector;", "predicates": [ "Subtarget->getSmVersion() >= 80", "Subtarget->getPTXVersion() >= 85" @@ -189736,32 +189738,30 @@ } ], "rust": { - "abi_id": "i0171", + "abi_id": "i1021", "module": "matrix", - "name": "mma_sp_ordered_metadata_m16n8k32_s32_s8", + "name": "mma_sp_ordered_metadata_m16n8k16_f16_f16", "arguments": [ - "[i32; 4]", + "[u32; 2]", "[u32; 2]", "[u32; 2]", "u32", "u32" ], - "result": "[i32; 4]", + "result": "[u32; 2]", "safe": false, "must_use": true, "safe_allowlist_reason": null, - "canonical_path": "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0171", - "public_path": "cuda_intrinsics::matrix::mma_sp_ordered_metadata_m16n8k32_s32_s8", + "canonical_path": "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i1021", + "public_path": "cuda_intrinsics::matrix::mma_sp_ordered_metadata_m16n8k16_f16_f16", "compatibility_paths": [ - "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k32_s32_s8" + "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k16_f16_f16" ] }, "dialect": { "op_type": "SparseMmaOp", "op_name": "nvvm.sparse_mma", "operands": [ - "i32", - "i32", "i32", "i32", "u32", @@ -189772,37 +189772,31 @@ "u32" ], "results": [ - "i32", - "i32", "i32", "i32" ] }, "llvm": { - "symbol": "llvm.nvvm.mma.sp.ordered.metadata.m16n8k32.row.col.s8", + "symbol": "llvm.nvvm.mma.sp.ordered.metadata.m16n8k16.row.col.f16.f16", "arguments": [ - "i32", - "i32", - "i32", - "i32", - "i32", - "i32", - "i32", - "i32", + "v2f16", + "v2f16", + "v2f16", + "v2f16", + "v2f16", + "v2f16", "i32", "i32" ], "results": [ - "i32", - "i32", - "i32", - "i32" + "v2f16", + "v2f16" ], "properties": [ - "ImmArg", + "ImmArg", "IntrNoCallback", "IntrNoMem", - "Range" + "Range" ], "result_facts": { "no_undef": false, @@ -189826,7 +189820,7 @@ } ] }, - "ptx_result": "[i32; 4]", + "ptx_result": "[u32; 2]", "targets": "all", "ptx_isa_version": "9.3", "ptx_isa_section": "9.7.15.6.3 Multiply-and-Accumulate Instruction: mma.sp", @@ -189836,7 +189830,7 @@ "profile": "rust-llvm-23.1.0-16696adc", "version": "LLVM version 23.1.0-rust-1.100.0-nightly", "sha256": "2e5bc688625ca7d98bca9b5f0f0d14525d2eb59e8a9842964e480df3ffd1f921", - "status": "validated", + "status": "executed", "target_triple": "nvptx64-nvidia-cuda", "gpu_target": "sm_80", "ptx_feature": "+ptx85" @@ -189862,18 +189856,18 @@ "sha256": "2e5bc688625ca7d98bca9b5f0f0d14525d2eb59e8a9842964e480df3ffd1f921", "artifact_path": null, "build_id_prefix": null, - "status": "validated", + "status": "executed", "stages": [ { "targets": [ "sm_80", "ptx85" ], - "representation": "convergent ordered-metadata sparse m16n8k32 signed INT8 inline PTX with selector immediates 0 and 1", + "representation": "eight committed per-intrinsic convergent inline-PTX probe fixtures covering every selector immediate", "stage": "backend_codegen", "mechanism": "inline_ptx", "outcome": "succeeded", - "detail": "The selected LLVM 22 probe retained exactly two unguarded ordered-metadata instructions, one for each selector, at PTX 8.5 and sm_80.", + "detail": "Pinned LLVM 23.1.0-rust lowered the eight per-intrinsic probe fixtures at sm_80/+ptx85 into 59,900 bytes of PTX across eight files; their concatenation in lexicographic id order has SHA-256 2eaae1b352ef07684549050756eba1ae0eb57318cfa329a9f103f086296f81dc, and every fixture retains one unguarded exact ordered-metadata instruction per selector immediate (24 across the family). Typed declarations of all eight intrinsics fail selection at sm_75/+ptx85 and sm_80/+ptx80, and select at sm_80, sm_86, sm_89, and sm_90/+ptx85 plus sm_100/+ptx86.", "artifact_kind": null, "tool_path": null, "tool_version": null, @@ -189884,15 +189878,30 @@ "sm_80", "ptx85" ], - "representation": "exact-floor PTX for ordered-metadata sparse m16n8k32 INT8 MMA", + "representation": "exact-floor per-intrinsic probe PTX containing all eight ordered sparse floating MMA forms", "stage": "ptx_assembly", "mechanism": "inline_ptx", "outcome": "succeeded", - "detail": "CUDA 13.3 ptxas accepted both selector forms for all eight ordered-metadata INT8 variants at PTX 8.5 and sm_80.", - "artifact_kind": null, + "detail": "CUDA 13.3 ptxas accepted every selector form of all eight ordered-metadata sparse floating variants at PTX 8.5 and sm_80.", + "artifact_kind": "cubin", "tool_path": "/usr/local/cuda-13.3/bin/ptxas", "tool_version": "CUDA 13.3 V13.3.33 build cuda_13.3.r13.3/compiler.37862127_0", "tool_sha256": "7fdd01a4cf50e30746da98989c9272a907f491e6fd7fecfda14642e4375f88fb" + }, + { + "targets": [ + "sm_120", + "ptx85" + ], + "representation": "all eight generated ordered sparse floating MMA APIs checked across all 32 lanes and four logical accumulators per lane against an independent host GEMM oracle", + "stage": "runtime", + "mechanism": "inline_ptx", + "outcome": "succeeded", + "detail": "Re-measured with the asymmetric oracle on NVIDIA GeForce RTX 5090 (compute capability 12.0), NVIDIA driver 580.173.02, CUDA toolkit 13.3 V13.3.33. Command: cargo oxide run sparse_mma_ordered_float. Result: exit code 0; SUCCESS: all 8 variants; all 32 lanes and 4 logical accumulators/lane match host GEMM; positionally distinct A/B/C, all six ordered metadata codes (tf32: both), and a nonzero selector per selector domain executed; compute-sanitizer memcheck reports 0 errors.", + "artifact_kind": null, + "tool_path": null, + "tool_version": null, + "tool_sha256": null } ] }, @@ -189916,18 +189925,18 @@ "sha256": "b6a5db233133fb0ed693f8cb8aeb1d405254ce0ab10364478985292ec98cfcf0", "artifact_path": "/usr/local/cuda-13.3/nvvm/lib64/libnvvm.so.4.0.0", "build_id_prefix": "2330c0", - "status": "validated", + "status": "executed", "stages": [ { "targets": [ "compute_80", "ptx93" ], - "representation": "convergent ordered-metadata sparse m16n8k32 signed INT8 inline PTX in the combined coverage kernel", + "representation": "eight convergent side-effecting ordered-metadata sparse floating inline PTX calls in the sparse_mma_ordered_float coverage kernel", "stage": "backend_codegen", "mechanism": "inline_ptx", "outcome": "succeeded", - "detail": "The production generated_intrinsics route produced 214,910-byte compute_80 NVVM IR with SHA-256 1c3668d8f8d712f3ea880fded2e10a7e9e4f4265f24f738f104d5bde8e7aee6c and 61,044-byte LTOIR with SHA-256 901eed79871048a57271f434b99bab16cccd7169be6629d6cdb0498bb8f95ece. The ordered raw calls use one compile-time selector per variant and exercise both 0 and 1 across the family.", + "detail": "The production emit-ltoir route (cargo oxide emit-ltoir sparse_mma_ordered_float --arch sm_80) produced 159,170-byte compute_80 NVVM IR with SHA-256 b338c017795f39f98f756f1d87dc202d1db274479c6619fef9797cb5a95f7613, and CUDA 13.3 libNVVM -gen-lto compiled it to 37,468-byte LTOIR with SHA-256 ac6d8317ba99d9c4332a0ce8777024bc066a7304c6ed4b64c341f4248f6b6100; both artifacts are byte-identical across repeated runs, and the module carries all eight ordered raw calls with one compile-time selector per variant.", "artifact_kind": null, "tool_path": null, "tool_version": null, @@ -189938,34 +189947,64 @@ "sm_80", "ptx93" ], - "representation": "combined standard and ordered sparse m16n8k32 INT8 coverage kernel", + "representation": "nvJitLink PTX containing all eight ordered sparse floating MMA forms", + "stage": "ptx_assembly", + "mechanism": "inline_ptx", + "outcome": "succeeded", + "detail": "nvJitLink rendered the LTOIR as 83,805-byte PTX 9.3 for sm_80 (SHA-256 4a92814b0579bf19a0ab8aa4c8b2114ec2170c87711831b2a17a31d579bf6e87) retaining all eight ordered forms, and CUDA 13.3 ptxas assembled it into a 41,896-byte cubin with SHA-256 26aa4d2f38132bc6a219ec7b22655a77b412176f464fe93d6c8ae81ea1b9e88b.", + "artifact_kind": "cubin", + "tool_path": "/usr/local/cuda-13.3/bin/ptxas", + "tool_version": "CUDA 13.3 V13.3.33 build cuda_13.3.r13.3/compiler.37862127_0", + "tool_sha256": "7fdd01a4cf50e30746da98989c9272a907f491e6fd7fecfda14642e4375f88fb" + }, + { + "targets": [ + "sm_80", + "ptx93" + ], + "representation": "the 37,468-byte all-variant libNVVM LTOIR linked for sm_80", "stage": "device_link", "mechanism": "inline_ptx", "outcome": "succeeded", - "detail": "nvJitLink produced a 22,632-byte cubin with SHA-256 ae24b75fec8d2c8d668765c2513a34c6d707f3acef48d6e106cf256028d72c26; cuobjdump contained 20 IMMA.SP.16832 instructions across the standard and ordered coverage. The ordered half contains all eight raw variants plus two representative compatibility-path calls.", + "detail": "nvJitLink linked the real libNVVM LTOIR into a 41,896-byte sm_80 cubin with SHA-256 99aa489c3c80ed1414df0c6fe073cff99dcb66a55fd0057729322b54790ac1bf; its cuobjdump SASS contains exactly eight HMMA.SP instructions, one per variant: 1688.F32.TF32, 16816.F32.TF32, 16816.F32.BF16, 16816.F32, 16816.F16, 16832.F32.BF16, 16832.F32, and 16832.F16.", "artifact_kind": "cubin", "tool_path": "/usr/local/cuda-13.3/lib64/libnvJitLink.so.13.3.33", "tool_version": "V13.3.33", "tool_sha256": "3ba1e744347cd68617b862eccfd98b125482e882b7a6319f42abc9a768513db8" + }, + { + "targets": [ + "sm_120", + "ptx93" + ], + "representation": "all eight generated ordered sparse floating MMA APIs checked across all 32 lanes and four logical accumulators per lane against an independent host GEMM oracle", + "stage": "runtime", + "mechanism": "inline_ptx", + "outcome": "succeeded", + "detail": "Executed through the libNVVM route (NVVM IR materialized by libNVVM plus nvJitLink at load time) on NVIDIA GeForce RTX 5090 (compute capability 12.0), NVIDIA driver 580.173.02, CUDA toolkit 13.3 V13.3.33. Command: cargo oxide run sparse_mma_ordered_float --emit-nvvm-ir --arch sm_120. Result: exit code 0; SUCCESS: all 8 variants; all 32 lanes and 4 logical accumulators/lane match host GEMM; positionally distinct A/B/C, all six ordered metadata codes (tf32: both), and a nonzero selector per selector domain executed; compute-sanitizer memcheck reports 0 errors.", + "artifact_kind": null, + "tool_path": null, + "tool_version": null, + "tool_sha256": null } ] } ], "sparse_mma": { - "shape": "m16n8k32", - "accumulator": "s32", - "a_element": "s8", - "b_element": "s8", + "shape": "m16n8k16", + "accumulator": "f16", + "a_element": "f16", + "b_element": "f16", "a_layout": "row", "b_layout": "col", - "overflow": "wrapping", + "overflow": "not_applicable", "metadata": "ordered", - "selector": "immediate_zero_or_one", + "selector": "immediate_zero_through_three", "participation": "all_warp_lanes_same_instruction_and_qualifiers_no_exited_lanes", - "adapter": "c4_i32_a2_u32_b2_u32_metadata_u32_selector_u32_to_d4_i32", - "llvm_adapter": "a2_i32_b2_i32_c4_i32_metadata_i32_selector_i32_to_d4_i32", + "adapter": "c2_u32_a2_u32_b2_u32_metadata_u32_selector_u32_to_d2_u32", + "llvm_adapter": "a2_v2_f16_b2_v2_f16_c2_v2_f16_metadata_i32_selector_i32_to_d2_v2_f16", "compatibility_source": "generated_stub", - "runtime_validation": "unexecuted" + "runtime_validation": "executed" }, "lowering": "generated_sparse_mma", "expected_ptx": { @@ -189974,18 +190013,18 @@ "sp::ordered_metadata", "sync", "aligned", - "m16n8k32", + "m16n8k16", "row", "col", - "s32", - "s8", - "s8", - "s32" + "f16", + "f16", + "f16", + "f16" ], "operands": [ { "kind": "register_list", - "length": 4 + "length": 2 }, { "kind": "register_list", @@ -189997,7 +190036,7 @@ }, { "kind": "register_list", - "length": 4 + "length": 2 }, { "kind": "register" @@ -190007,20 +190046,20 @@ } ] }, - "summary": "Multiplies warp-distributed sparse signed A and signed B INT8 fragments with ordered sparsity metadata and adds a wrapping s32 accumulator." + "summary": "Multiplies warp-distributed ordered sparse f16 A and B fragments and adds a packed f16 accumulator." }, { - "id": "mma_sp_ordered_metadata_m16n8k32_s32_s8_satfinite", - "operation_key": "matrix.mma.sp.m16n8k32.row.col.s32.s8.s8.s32.satfinite.ordered_metadata", + "id": "mma_sp_ordered_metadata_m16n8k16_f32_bf16", + "operation_key": "matrix.mma.sp.m16n8k16.row.col.f32.bf16.bf16.f32.not_applicable.ordered_metadata", "family": "sparse_mma", "source": { "kind": "llvm_imported", - "source_record": "int_nvvm_mma_sp_ordered_metadata_m16n8k32_row_col_satfinite_s8" + "source_record": "int_nvvm_mma_sp_ordered_metadata_m16n8k16_row_col_bf16" }, "selections": [ { - "source_record": "anonymous_19705", - "asm": "mma.sp::ordered_metadata.sync.aligned.m16n8k32.row.col.satfinite.s32.s8.s8.s32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1}},\n\t\t{{$rb0, $rb1}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}},\n\t\t$metadata,\n\t\t$selector;", + "source_record": "anonymous_19524", + "asm": "mma.sp::ordered_metadata.sync.aligned.m16n8k16.row.col.f32.bf16.bf16.f32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1}},\n\t\t{{$rb0, $rb1}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}},\n\t\t$metadata,\n\t\t$selector;", "predicates": [ "Subtarget->getSmVersion() >= 80", "Subtarget->getPTXVersion() >= 85" @@ -190028,34 +190067,34 @@ } ], "rust": { - "abi_id": "i0175", + "abi_id": "i1020", "module": "matrix", - "name": "mma_sp_ordered_metadata_m16n8k32_s32_s8_satfinite", + "name": "mma_sp_ordered_metadata_m16n8k16_f32_bf16", "arguments": [ - "[i32; 4]", + "[f32; 4]", "[u32; 2]", "[u32; 2]", "u32", "u32" ], - "result": "[i32; 4]", + "result": "[f32; 4]", "safe": false, "must_use": true, "safe_allowlist_reason": null, - "canonical_path": "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0175", - "public_path": "cuda_intrinsics::matrix::mma_sp_ordered_metadata_m16n8k32_s32_s8_satfinite", + "canonical_path": "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i1020", + "public_path": "cuda_intrinsics::matrix::mma_sp_ordered_metadata_m16n8k16_f32_bf16", "compatibility_paths": [ - "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k32_s32_s8_satfinite" + "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k16_f32_bf16" ] }, "dialect": { "op_type": "SparseMmaOp", "op_name": "nvvm.sparse_mma", "operands": [ - "i32", - "i32", - "i32", - "i32", + "f32", + "f32", + "f32", + "f32", "u32", "u32", "u32", @@ -190064,37 +190103,37 @@ "u32" ], "results": [ - "i32", - "i32", - "i32", - "i32" + "f32", + "f32", + "f32", + "f32" ] }, "llvm": { - "symbol": "llvm.nvvm.mma.sp.ordered.metadata.m16n8k32.row.col.satfinite.s8", + "symbol": "llvm.nvvm.mma.sp.ordered.metadata.m16n8k16.row.col.bf16", "arguments": [ "i32", "i32", "i32", "i32", - "i32", - "i32", - "i32", - "i32", + "f32", + "f32", + "f32", + "f32", "i32", "i32" ], "results": [ - "i32", - "i32", - "i32", - "i32" + "f32", + "f32", + "f32", + "f32" ], "properties": [ "ImmArg", "IntrNoCallback", "IntrNoMem", - "Range" + "Range" ], "result_facts": { "no_undef": false, @@ -190118,7 +190157,7 @@ } ] }, - "ptx_result": "[i32; 4]", + "ptx_result": "[f32; 4]", "targets": "all", "ptx_isa_version": "9.3", "ptx_isa_section": "9.7.15.6.3 Multiply-and-Accumulate Instruction: mma.sp", @@ -190128,7 +190167,7 @@ "profile": "rust-llvm-23.1.0-16696adc", "version": "LLVM version 23.1.0-rust-1.100.0-nightly", "sha256": "2e5bc688625ca7d98bca9b5f0f0d14525d2eb59e8a9842964e480df3ffd1f921", - "status": "validated", + "status": "executed", "target_triple": "nvptx64-nvidia-cuda", "gpu_target": "sm_80", "ptx_feature": "+ptx85" @@ -190154,18 +190193,18 @@ "sha256": "2e5bc688625ca7d98bca9b5f0f0d14525d2eb59e8a9842964e480df3ffd1f921", "artifact_path": null, "build_id_prefix": null, - "status": "validated", + "status": "executed", "stages": [ { "targets": [ "sm_80", "ptx85" ], - "representation": "convergent ordered-metadata sparse m16n8k32 signed saturating INT8 inline PTX with selector immediates 0 and 1", + "representation": "eight committed per-intrinsic convergent inline-PTX probe fixtures covering every selector immediate", "stage": "backend_codegen", "mechanism": "inline_ptx", "outcome": "succeeded", - "detail": "The selected LLVM 22 probe retained exactly two unguarded ordered-metadata instructions, one for each selector, at PTX 8.5 and sm_80.", + "detail": "Pinned LLVM 23.1.0-rust lowered the eight per-intrinsic probe fixtures at sm_80/+ptx85 into 59,900 bytes of PTX across eight files; their concatenation in lexicographic id order has SHA-256 2eaae1b352ef07684549050756eba1ae0eb57318cfa329a9f103f086296f81dc, and every fixture retains one unguarded exact ordered-metadata instruction per selector immediate (24 across the family). Typed declarations of all eight intrinsics fail selection at sm_75/+ptx85 and sm_80/+ptx80, and select at sm_80, sm_86, sm_89, and sm_90/+ptx85 plus sm_100/+ptx86.", "artifact_kind": null, "tool_path": null, "tool_version": null, @@ -190176,15 +190215,30 @@ "sm_80", "ptx85" ], - "representation": "exact-floor PTX for ordered-metadata sparse m16n8k32 INT8 MMA", + "representation": "exact-floor per-intrinsic probe PTX containing all eight ordered sparse floating MMA forms", "stage": "ptx_assembly", "mechanism": "inline_ptx", "outcome": "succeeded", - "detail": "CUDA 13.3 ptxas accepted both selector forms for all eight ordered-metadata INT8 variants at PTX 8.5 and sm_80.", - "artifact_kind": null, + "detail": "CUDA 13.3 ptxas accepted every selector form of all eight ordered-metadata sparse floating variants at PTX 8.5 and sm_80.", + "artifact_kind": "cubin", "tool_path": "/usr/local/cuda-13.3/bin/ptxas", "tool_version": "CUDA 13.3 V13.3.33 build cuda_13.3.r13.3/compiler.37862127_0", "tool_sha256": "7fdd01a4cf50e30746da98989c9272a907f491e6fd7fecfda14642e4375f88fb" + }, + { + "targets": [ + "sm_120", + "ptx85" + ], + "representation": "all eight generated ordered sparse floating MMA APIs checked across all 32 lanes and four logical accumulators per lane against an independent host GEMM oracle", + "stage": "runtime", + "mechanism": "inline_ptx", + "outcome": "succeeded", + "detail": "Re-measured with the asymmetric oracle on NVIDIA GeForce RTX 5090 (compute capability 12.0), NVIDIA driver 580.173.02, CUDA toolkit 13.3 V13.3.33. Command: cargo oxide run sparse_mma_ordered_float. Result: exit code 0; SUCCESS: all 8 variants; all 32 lanes and 4 logical accumulators/lane match host GEMM; positionally distinct A/B/C, all six ordered metadata codes (tf32: both), and a nonzero selector per selector domain executed; compute-sanitizer memcheck reports 0 errors.", + "artifact_kind": null, + "tool_path": null, + "tool_version": null, + "tool_sha256": null } ] }, @@ -190208,18 +190262,18 @@ "sha256": "b6a5db233133fb0ed693f8cb8aeb1d405254ce0ab10364478985292ec98cfcf0", "artifact_path": "/usr/local/cuda-13.3/nvvm/lib64/libnvvm.so.4.0.0", "build_id_prefix": "2330c0", - "status": "validated", + "status": "executed", "stages": [ { "targets": [ "compute_80", "ptx93" ], - "representation": "convergent ordered-metadata sparse m16n8k32 signed saturating INT8 inline PTX in the combined coverage kernel", + "representation": "eight convergent side-effecting ordered-metadata sparse floating inline PTX calls in the sparse_mma_ordered_float coverage kernel", "stage": "backend_codegen", "mechanism": "inline_ptx", "outcome": "succeeded", - "detail": "The production generated_intrinsics route produced 214,910-byte compute_80 NVVM IR with SHA-256 1c3668d8f8d712f3ea880fded2e10a7e9e4f4265f24f738f104d5bde8e7aee6c and 61,044-byte LTOIR with SHA-256 901eed79871048a57271f434b99bab16cccd7169be6629d6cdb0498bb8f95ece. The ordered raw calls use one compile-time selector per variant and exercise both 0 and 1 across the family.", + "detail": "The production emit-ltoir route (cargo oxide emit-ltoir sparse_mma_ordered_float --arch sm_80) produced 159,170-byte compute_80 NVVM IR with SHA-256 b338c017795f39f98f756f1d87dc202d1db274479c6619fef9797cb5a95f7613, and CUDA 13.3 libNVVM -gen-lto compiled it to 37,468-byte LTOIR with SHA-256 ac6d8317ba99d9c4332a0ce8777024bc066a7304c6ed4b64c341f4248f6b6100; both artifacts are byte-identical across repeated runs, and the module carries all eight ordered raw calls with one compile-time selector per variant.", "artifact_kind": null, "tool_path": null, "tool_version": null, @@ -190230,34 +190284,64 @@ "sm_80", "ptx93" ], - "representation": "combined standard and ordered sparse m16n8k32 INT8 coverage kernel", + "representation": "nvJitLink PTX containing all eight ordered sparse floating MMA forms", + "stage": "ptx_assembly", + "mechanism": "inline_ptx", + "outcome": "succeeded", + "detail": "nvJitLink rendered the LTOIR as 83,805-byte PTX 9.3 for sm_80 (SHA-256 4a92814b0579bf19a0ab8aa4c8b2114ec2170c87711831b2a17a31d579bf6e87) retaining all eight ordered forms, and CUDA 13.3 ptxas assembled it into a 41,896-byte cubin with SHA-256 26aa4d2f38132bc6a219ec7b22655a77b412176f464fe93d6c8ae81ea1b9e88b.", + "artifact_kind": "cubin", + "tool_path": "/usr/local/cuda-13.3/bin/ptxas", + "tool_version": "CUDA 13.3 V13.3.33 build cuda_13.3.r13.3/compiler.37862127_0", + "tool_sha256": "7fdd01a4cf50e30746da98989c9272a907f491e6fd7fecfda14642e4375f88fb" + }, + { + "targets": [ + "sm_80", + "ptx93" + ], + "representation": "the 37,468-byte all-variant libNVVM LTOIR linked for sm_80", "stage": "device_link", "mechanism": "inline_ptx", "outcome": "succeeded", - "detail": "nvJitLink produced a 22,632-byte cubin with SHA-256 ae24b75fec8d2c8d668765c2513a34c6d707f3acef48d6e106cf256028d72c26; cuobjdump contained 20 IMMA.SP.16832 instructions across the standard and ordered coverage. The ordered half contains all eight raw variants plus two representative compatibility-path calls.", + "detail": "nvJitLink linked the real libNVVM LTOIR into a 41,896-byte sm_80 cubin with SHA-256 99aa489c3c80ed1414df0c6fe073cff99dcb66a55fd0057729322b54790ac1bf; its cuobjdump SASS contains exactly eight HMMA.SP instructions, one per variant: 1688.F32.TF32, 16816.F32.TF32, 16816.F32.BF16, 16816.F32, 16816.F16, 16832.F32.BF16, 16832.F32, and 16832.F16.", "artifact_kind": "cubin", "tool_path": "/usr/local/cuda-13.3/lib64/libnvJitLink.so.13.3.33", "tool_version": "V13.3.33", "tool_sha256": "3ba1e744347cd68617b862eccfd98b125482e882b7a6319f42abc9a768513db8" + }, + { + "targets": [ + "sm_120", + "ptx93" + ], + "representation": "all eight generated ordered sparse floating MMA APIs checked across all 32 lanes and four logical accumulators per lane against an independent host GEMM oracle", + "stage": "runtime", + "mechanism": "inline_ptx", + "outcome": "succeeded", + "detail": "Executed through the libNVVM route (NVVM IR materialized by libNVVM plus nvJitLink at load time) on NVIDIA GeForce RTX 5090 (compute capability 12.0), NVIDIA driver 580.173.02, CUDA toolkit 13.3 V13.3.33. Command: cargo oxide run sparse_mma_ordered_float --emit-nvvm-ir --arch sm_120. Result: exit code 0; SUCCESS: all 8 variants; all 32 lanes and 4 logical accumulators/lane match host GEMM; positionally distinct A/B/C, all six ordered metadata codes (tf32: both), and a nonzero selector per selector domain executed; compute-sanitizer memcheck reports 0 errors.", + "artifact_kind": null, + "tool_path": null, + "tool_version": null, + "tool_sha256": null } ] } ], "sparse_mma": { - "shape": "m16n8k32", - "accumulator": "s32", - "a_element": "s8", - "b_element": "s8", + "shape": "m16n8k16", + "accumulator": "f32", + "a_element": "bf16", + "b_element": "bf16", "a_layout": "row", "b_layout": "col", - "overflow": "satfinite", + "overflow": "not_applicable", "metadata": "ordered", - "selector": "immediate_zero_or_one", + "selector": "immediate_zero_through_three", "participation": "all_warp_lanes_same_instruction_and_qualifiers_no_exited_lanes", - "adapter": "c4_i32_a2_u32_b2_u32_metadata_u32_selector_u32_to_d4_i32", - "llvm_adapter": "a2_i32_b2_i32_c4_i32_metadata_i32_selector_i32_to_d4_i32", + "adapter": "c4_f32_a2_u32_b2_u32_metadata_u32_selector_u32_to_d4_f32", + "llvm_adapter": "a2_i32_b2_i32_c4_f32_metadata_i32_selector_i32_to_d4_f32", "compatibility_source": "generated_stub", - "runtime_validation": "unexecuted" + "runtime_validation": "executed" }, "lowering": "generated_sparse_mma", "expected_ptx": { @@ -190266,14 +190350,13 @@ "sp::ordered_metadata", "sync", "aligned", - "m16n8k32", + "m16n8k16", "row", "col", - "satfinite", - "s32", - "s8", - "s8", - "s32" + "f32", + "bf16", + "bf16", + "f32" ], "operands": [ { @@ -190300,20 +190383,20 @@ } ] }, - "summary": "Multiplies warp-distributed sparse signed A and signed B INT8 fragments with ordered sparsity metadata and adds a saturating s32 accumulator." + "summary": "Multiplies warp-distributed ordered sparse bf16 A and B fragments and adds a f32 accumulator." }, { - "id": "mma_sp_ordered_metadata_m16n8k32_s32_s8_u8", - "operation_key": "matrix.mma.sp.m16n8k32.row.col.s32.s8.u8.s32.wrapping.ordered_metadata", + "id": "mma_sp_ordered_metadata_m16n8k16_f32_f16", + "operation_key": "matrix.mma.sp.m16n8k16.row.col.f32.f16.f16.f32.not_applicable.ordered_metadata", "family": "sparse_mma", "source": { "kind": "llvm_imported", - "source_record": "int_nvvm_mma_sp_ordered_metadata_m16n8k32_row_col_s8_u8" + "source_record": "int_nvvm_mma_sp_ordered_metadata_m16n8k16_row_col_f32_f32" }, "selections": [ { - "source_record": "anonymous_19649", - "asm": "mma.sp::ordered_metadata.sync.aligned.m16n8k32.row.col.s32.s8.u8.s32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1}},\n\t\t{{$rb0, $rb1}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}},\n\t\t$metadata,\n\t\t$selector;", + "source_record": "anonymous_19558", + "asm": "mma.sp::ordered_metadata.sync.aligned.m16n8k16.row.col.f32.f16.f16.f32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1}},\n\t\t{{$rb0, $rb1}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}},\n\t\t$metadata,\n\t\t$selector;", "predicates": [ "Subtarget->getSmVersion() >= 80", "Subtarget->getPTXVersion() >= 85" @@ -190321,34 +190404,34 @@ } ], "rust": { - "abi_id": "i0172", + "abi_id": "i1022", "module": "matrix", - "name": "mma_sp_ordered_metadata_m16n8k32_s32_s8_u8", + "name": "mma_sp_ordered_metadata_m16n8k16_f32_f16", "arguments": [ - "[i32; 4]", + "[f32; 4]", "[u32; 2]", "[u32; 2]", "u32", "u32" ], - "result": "[i32; 4]", + "result": "[f32; 4]", "safe": false, "must_use": true, "safe_allowlist_reason": null, - "canonical_path": "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0172", - "public_path": "cuda_intrinsics::matrix::mma_sp_ordered_metadata_m16n8k32_s32_s8_u8", + "canonical_path": "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i1022", + "public_path": "cuda_intrinsics::matrix::mma_sp_ordered_metadata_m16n8k16_f32_f16", "compatibility_paths": [ - "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k32_s32_s8_u8" + "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k16_f32_f16" ] }, "dialect": { "op_type": "SparseMmaOp", "op_name": "nvvm.sparse_mma", "operands": [ - "i32", - "i32", - "i32", - "i32", + "f32", + "f32", + "f32", + "f32", "u32", "u32", "u32", @@ -190357,37 +190440,37 @@ "u32" ], "results": [ - "i32", - "i32", - "i32", - "i32" + "f32", + "f32", + "f32", + "f32" ] }, "llvm": { - "symbol": "llvm.nvvm.mma.sp.ordered.metadata.m16n8k32.row.col.s8.u8", + "symbol": "llvm.nvvm.mma.sp.ordered.metadata.m16n8k16.row.col.f32.f32", "arguments": [ - "i32", - "i32", - "i32", - "i32", - "i32", - "i32", - "i32", - "i32", + "v2f16", + "v2f16", + "v2f16", + "v2f16", + "f32", + "f32", + "f32", + "f32", "i32", "i32" ], "results": [ - "i32", - "i32", - "i32", - "i32" + "f32", + "f32", + "f32", + "f32" ], "properties": [ "ImmArg", "IntrNoCallback", "IntrNoMem", - "Range" + "Range" ], "result_facts": { "no_undef": false, @@ -190411,7 +190494,7 @@ } ] }, - "ptx_result": "[i32; 4]", + "ptx_result": "[f32; 4]", "targets": "all", "ptx_isa_version": "9.3", "ptx_isa_section": "9.7.15.6.3 Multiply-and-Accumulate Instruction: mma.sp", @@ -190421,7 +190504,7 @@ "profile": "rust-llvm-23.1.0-16696adc", "version": "LLVM version 23.1.0-rust-1.100.0-nightly", "sha256": "2e5bc688625ca7d98bca9b5f0f0d14525d2eb59e8a9842964e480df3ffd1f921", - "status": "validated", + "status": "executed", "target_triple": "nvptx64-nvidia-cuda", "gpu_target": "sm_80", "ptx_feature": "+ptx85" @@ -190447,18 +190530,18 @@ "sha256": "2e5bc688625ca7d98bca9b5f0f0d14525d2eb59e8a9842964e480df3ffd1f921", "artifact_path": null, "build_id_prefix": null, - "status": "validated", + "status": "executed", "stages": [ { "targets": [ "sm_80", "ptx85" ], - "representation": "convergent ordered-metadata sparse m16n8k32 mixed-sign INT8 inline PTX with selector immediates 0 and 1", + "representation": "eight committed per-intrinsic convergent inline-PTX probe fixtures covering every selector immediate", "stage": "backend_codegen", "mechanism": "inline_ptx", "outcome": "succeeded", - "detail": "The selected LLVM 22 probe retained exactly two unguarded ordered-metadata instructions, one for each selector, at PTX 8.5 and sm_80.", + "detail": "Pinned LLVM 23.1.0-rust lowered the eight per-intrinsic probe fixtures at sm_80/+ptx85 into 59,900 bytes of PTX across eight files; their concatenation in lexicographic id order has SHA-256 2eaae1b352ef07684549050756eba1ae0eb57318cfa329a9f103f086296f81dc, and every fixture retains one unguarded exact ordered-metadata instruction per selector immediate (24 across the family). Typed declarations of all eight intrinsics fail selection at sm_75/+ptx85 and sm_80/+ptx80, and select at sm_80, sm_86, sm_89, and sm_90/+ptx85 plus sm_100/+ptx86.", "artifact_kind": null, "tool_path": null, "tool_version": null, @@ -190469,15 +190552,30 @@ "sm_80", "ptx85" ], - "representation": "exact-floor PTX for ordered-metadata sparse m16n8k32 INT8 MMA", + "representation": "exact-floor per-intrinsic probe PTX containing all eight ordered sparse floating MMA forms", "stage": "ptx_assembly", "mechanism": "inline_ptx", "outcome": "succeeded", - "detail": "CUDA 13.3 ptxas accepted both selector forms for all eight ordered-metadata INT8 variants at PTX 8.5 and sm_80.", - "artifact_kind": null, + "detail": "CUDA 13.3 ptxas accepted every selector form of all eight ordered-metadata sparse floating variants at PTX 8.5 and sm_80.", + "artifact_kind": "cubin", "tool_path": "/usr/local/cuda-13.3/bin/ptxas", "tool_version": "CUDA 13.3 V13.3.33 build cuda_13.3.r13.3/compiler.37862127_0", "tool_sha256": "7fdd01a4cf50e30746da98989c9272a907f491e6fd7fecfda14642e4375f88fb" + }, + { + "targets": [ + "sm_120", + "ptx85" + ], + "representation": "all eight generated ordered sparse floating MMA APIs checked across all 32 lanes and four logical accumulators per lane against an independent host GEMM oracle", + "stage": "runtime", + "mechanism": "inline_ptx", + "outcome": "succeeded", + "detail": "Re-measured with the asymmetric oracle on NVIDIA GeForce RTX 5090 (compute capability 12.0), NVIDIA driver 580.173.02, CUDA toolkit 13.3 V13.3.33. Command: cargo oxide run sparse_mma_ordered_float. Result: exit code 0; SUCCESS: all 8 variants; all 32 lanes and 4 logical accumulators/lane match host GEMM; positionally distinct A/B/C, all six ordered metadata codes (tf32: both), and a nonzero selector per selector domain executed; compute-sanitizer memcheck reports 0 errors.", + "artifact_kind": null, + "tool_path": null, + "tool_version": null, + "tool_sha256": null } ] }, @@ -190501,18 +190599,18 @@ "sha256": "b6a5db233133fb0ed693f8cb8aeb1d405254ce0ab10364478985292ec98cfcf0", "artifact_path": "/usr/local/cuda-13.3/nvvm/lib64/libnvvm.so.4.0.0", "build_id_prefix": "2330c0", - "status": "validated", + "status": "executed", "stages": [ { "targets": [ "compute_80", "ptx93" ], - "representation": "convergent ordered-metadata sparse m16n8k32 mixed-sign INT8 inline PTX in the combined coverage kernel", + "representation": "eight convergent side-effecting ordered-metadata sparse floating inline PTX calls in the sparse_mma_ordered_float coverage kernel", "stage": "backend_codegen", "mechanism": "inline_ptx", "outcome": "succeeded", - "detail": "The production generated_intrinsics route produced 214,910-byte compute_80 NVVM IR with SHA-256 1c3668d8f8d712f3ea880fded2e10a7e9e4f4265f24f738f104d5bde8e7aee6c and 61,044-byte LTOIR with SHA-256 901eed79871048a57271f434b99bab16cccd7169be6629d6cdb0498bb8f95ece. The ordered raw calls use one compile-time selector per variant and exercise both 0 and 1 across the family.", + "detail": "The production emit-ltoir route (cargo oxide emit-ltoir sparse_mma_ordered_float --arch sm_80) produced 159,170-byte compute_80 NVVM IR with SHA-256 b338c017795f39f98f756f1d87dc202d1db274479c6619fef9797cb5a95f7613, and CUDA 13.3 libNVVM -gen-lto compiled it to 37,468-byte LTOIR with SHA-256 ac6d8317ba99d9c4332a0ce8777024bc066a7304c6ed4b64c341f4248f6b6100; both artifacts are byte-identical across repeated runs, and the module carries all eight ordered raw calls with one compile-time selector per variant.", "artifact_kind": null, "tool_path": null, "tool_version": null, @@ -190523,34 +190621,64 @@ "sm_80", "ptx93" ], - "representation": "combined standard and ordered sparse m16n8k32 INT8 coverage kernel", + "representation": "nvJitLink PTX containing all eight ordered sparse floating MMA forms", + "stage": "ptx_assembly", + "mechanism": "inline_ptx", + "outcome": "succeeded", + "detail": "nvJitLink rendered the LTOIR as 83,805-byte PTX 9.3 for sm_80 (SHA-256 4a92814b0579bf19a0ab8aa4c8b2114ec2170c87711831b2a17a31d579bf6e87) retaining all eight ordered forms, and CUDA 13.3 ptxas assembled it into a 41,896-byte cubin with SHA-256 26aa4d2f38132bc6a219ec7b22655a77b412176f464fe93d6c8ae81ea1b9e88b.", + "artifact_kind": "cubin", + "tool_path": "/usr/local/cuda-13.3/bin/ptxas", + "tool_version": "CUDA 13.3 V13.3.33 build cuda_13.3.r13.3/compiler.37862127_0", + "tool_sha256": "7fdd01a4cf50e30746da98989c9272a907f491e6fd7fecfda14642e4375f88fb" + }, + { + "targets": [ + "sm_80", + "ptx93" + ], + "representation": "the 37,468-byte all-variant libNVVM LTOIR linked for sm_80", "stage": "device_link", "mechanism": "inline_ptx", "outcome": "succeeded", - "detail": "nvJitLink produced a 22,632-byte cubin with SHA-256 ae24b75fec8d2c8d668765c2513a34c6d707f3acef48d6e106cf256028d72c26; cuobjdump contained 20 IMMA.SP.16832 instructions across the standard and ordered coverage. The ordered half contains all eight raw variants plus two representative compatibility-path calls.", + "detail": "nvJitLink linked the real libNVVM LTOIR into a 41,896-byte sm_80 cubin with SHA-256 99aa489c3c80ed1414df0c6fe073cff99dcb66a55fd0057729322b54790ac1bf; its cuobjdump SASS contains exactly eight HMMA.SP instructions, one per variant: 1688.F32.TF32, 16816.F32.TF32, 16816.F32.BF16, 16816.F32, 16816.F16, 16832.F32.BF16, 16832.F32, and 16832.F16.", "artifact_kind": "cubin", "tool_path": "/usr/local/cuda-13.3/lib64/libnvJitLink.so.13.3.33", "tool_version": "V13.3.33", "tool_sha256": "3ba1e744347cd68617b862eccfd98b125482e882b7a6319f42abc9a768513db8" + }, + { + "targets": [ + "sm_120", + "ptx93" + ], + "representation": "all eight generated ordered sparse floating MMA APIs checked across all 32 lanes and four logical accumulators per lane against an independent host GEMM oracle", + "stage": "runtime", + "mechanism": "inline_ptx", + "outcome": "succeeded", + "detail": "Executed through the libNVVM route (NVVM IR materialized by libNVVM plus nvJitLink at load time) on NVIDIA GeForce RTX 5090 (compute capability 12.0), NVIDIA driver 580.173.02, CUDA toolkit 13.3 V13.3.33. Command: cargo oxide run sparse_mma_ordered_float --emit-nvvm-ir --arch sm_120. Result: exit code 0; SUCCESS: all 8 variants; all 32 lanes and 4 logical accumulators/lane match host GEMM; positionally distinct A/B/C, all six ordered metadata codes (tf32: both), and a nonzero selector per selector domain executed; compute-sanitizer memcheck reports 0 errors.", + "artifact_kind": null, + "tool_path": null, + "tool_version": null, + "tool_sha256": null } ] } ], "sparse_mma": { - "shape": "m16n8k32", - "accumulator": "s32", - "a_element": "s8", - "b_element": "u8", + "shape": "m16n8k16", + "accumulator": "f32", + "a_element": "f16", + "b_element": "f16", "a_layout": "row", "b_layout": "col", - "overflow": "wrapping", + "overflow": "not_applicable", "metadata": "ordered", - "selector": "immediate_zero_or_one", + "selector": "immediate_zero_through_three", "participation": "all_warp_lanes_same_instruction_and_qualifiers_no_exited_lanes", - "adapter": "c4_i32_a2_u32_b2_u32_metadata_u32_selector_u32_to_d4_i32", - "llvm_adapter": "a2_i32_b2_i32_c4_i32_metadata_i32_selector_i32_to_d4_i32", + "adapter": "c4_f32_a2_u32_b2_u32_metadata_u32_selector_u32_to_d4_f32", + "llvm_adapter": "a2_v2_f16_b2_v2_f16_c4_f32_metadata_i32_selector_i32_to_d4_f32", "compatibility_source": "generated_stub", - "runtime_validation": "unexecuted" + "runtime_validation": "executed" }, "lowering": "generated_sparse_mma", "expected_ptx": { @@ -190559,13 +190687,13 @@ "sp::ordered_metadata", "sync", "aligned", - "m16n8k32", + "m16n8k16", "row", "col", - "s32", - "s8", - "u8", - "s32" + "f32", + "f16", + "f16", + "f32" ], "operands": [ { @@ -190592,20 +190720,20 @@ } ] }, - "summary": "Multiplies warp-distributed sparse signed A and unsigned B INT8 fragments with ordered sparsity metadata and adds a wrapping s32 accumulator." + "summary": "Multiplies warp-distributed ordered sparse f16 A and B fragments and adds a f32 accumulator." }, { - "id": "mma_sp_ordered_metadata_m16n8k32_s32_s8_u8_satfinite", - "operation_key": "matrix.mma.sp.m16n8k32.row.col.s32.s8.u8.s32.satfinite.ordered_metadata", + "id": "mma_sp_ordered_metadata_m16n8k16_f32_tf32", + "operation_key": "matrix.mma.sp.m16n8k16.row.col.f32.tf32.tf32.f32.not_applicable.ordered_metadata", "family": "sparse_mma", "source": { "kind": "llvm_imported", - "source_record": "int_nvvm_mma_sp_ordered_metadata_m16n8k32_row_col_satfinite_s8_u8" + "source_record": "int_nvvm_mma_sp_ordered_metadata_m16n8k16_row_col_tf32" }, "selections": [ { - "source_record": "anonymous_19708", - "asm": "mma.sp::ordered_metadata.sync.aligned.m16n8k32.row.col.satfinite.s32.s8.u8.s32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1}},\n\t\t{{$rb0, $rb1}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}},\n\t\t$metadata,\n\t\t$selector;", + "source_record": "anonymous_19546", + "asm": "mma.sp::ordered_metadata.sync.aligned.m16n8k16.row.col.f32.tf32.tf32.f32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1, $rb2, $rb3}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}},\n\t\t$metadata,\n\t\t$selector;", "predicates": [ "Subtarget->getSmVersion() >= 80", "Subtarget->getPTXVersion() >= 85" @@ -190613,34 +190741,38 @@ } ], "rust": { - "abi_id": "i0176", + "abi_id": "i1019", "module": "matrix", - "name": "mma_sp_ordered_metadata_m16n8k32_s32_s8_u8_satfinite", + "name": "mma_sp_ordered_metadata_m16n8k16_f32_tf32", "arguments": [ - "[i32; 4]", - "[u32; 2]", - "[u32; 2]", + "[f32; 4]", + "[u32; 4]", + "[u32; 4]", "u32", "u32" ], - "result": "[i32; 4]", + "result": "[f32; 4]", "safe": false, "must_use": true, "safe_allowlist_reason": null, - "canonical_path": "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0176", - "public_path": "cuda_intrinsics::matrix::mma_sp_ordered_metadata_m16n8k32_s32_s8_u8_satfinite", + "canonical_path": "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i1019", + "public_path": "cuda_intrinsics::matrix::mma_sp_ordered_metadata_m16n8k16_f32_tf32", "compatibility_paths": [ - "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k32_s32_s8_u8_satfinite" + "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k16_f32_tf32" ] }, "dialect": { "op_type": "SparseMmaOp", "op_name": "nvvm.sparse_mma", "operands": [ - "i32", - "i32", - "i32", - "i32", + "f32", + "f32", + "f32", + "f32", + "u32", + "u32", + "u32", + "u32", "u32", "u32", "u32", @@ -190649,14 +190781,14 @@ "u32" ], "results": [ - "i32", - "i32", - "i32", - "i32" + "f32", + "f32", + "f32", + "f32" ] }, "llvm": { - "symbol": "llvm.nvvm.mma.sp.ordered.metadata.m16n8k32.row.col.satfinite.s8.u8", + "symbol": "llvm.nvvm.mma.sp.ordered.metadata.m16n8k16.row.col.tf32", "arguments": [ "i32", "i32", @@ -190666,20 +190798,24 @@ "i32", "i32", "i32", + "f32", + "f32", + "f32", + "f32", "i32", "i32" ], "results": [ - "i32", - "i32", - "i32", - "i32" + "f32", + "f32", + "f32", + "f32" ], "properties": [ - "ImmArg", + "ImmArg", "IntrNoCallback", "IntrNoMem", - "Range" + "Range" ], "result_facts": { "no_undef": false, @@ -190703,7 +190839,7 @@ } ] }, - "ptx_result": "[i32; 4]", + "ptx_result": "[f32; 4]", "targets": "all", "ptx_isa_version": "9.3", "ptx_isa_section": "9.7.15.6.3 Multiply-and-Accumulate Instruction: mma.sp", @@ -190713,7 +190849,7 @@ "profile": "rust-llvm-23.1.0-16696adc", "version": "LLVM version 23.1.0-rust-1.100.0-nightly", "sha256": "2e5bc688625ca7d98bca9b5f0f0d14525d2eb59e8a9842964e480df3ffd1f921", - "status": "validated", + "status": "executed", "target_triple": "nvptx64-nvidia-cuda", "gpu_target": "sm_80", "ptx_feature": "+ptx85" @@ -190739,18 +190875,18 @@ "sha256": "2e5bc688625ca7d98bca9b5f0f0d14525d2eb59e8a9842964e480df3ffd1f921", "artifact_path": null, "build_id_prefix": null, - "status": "validated", + "status": "executed", "stages": [ { "targets": [ "sm_80", "ptx85" ], - "representation": "convergent ordered-metadata sparse m16n8k32 mixed-sign saturating INT8 inline PTX with selector immediates 0 and 1", + "representation": "eight committed per-intrinsic convergent inline-PTX probe fixtures covering every selector immediate", "stage": "backend_codegen", "mechanism": "inline_ptx", "outcome": "succeeded", - "detail": "The selected LLVM 22 probe retained exactly two unguarded ordered-metadata instructions, one for each selector, at PTX 8.5 and sm_80.", + "detail": "Pinned LLVM 23.1.0-rust lowered the eight per-intrinsic probe fixtures at sm_80/+ptx85 into 59,900 bytes of PTX across eight files; their concatenation in lexicographic id order has SHA-256 2eaae1b352ef07684549050756eba1ae0eb57318cfa329a9f103f086296f81dc, and every fixture retains one unguarded exact ordered-metadata instruction per selector immediate (24 across the family). Typed declarations of all eight intrinsics fail selection at sm_75/+ptx85 and sm_80/+ptx80, and select at sm_80, sm_86, sm_89, and sm_90/+ptx85 plus sm_100/+ptx86.", "artifact_kind": null, "tool_path": null, "tool_version": null, @@ -190761,15 +190897,30 @@ "sm_80", "ptx85" ], - "representation": "exact-floor PTX for ordered-metadata sparse m16n8k32 INT8 MMA", + "representation": "exact-floor per-intrinsic probe PTX containing all eight ordered sparse floating MMA forms", "stage": "ptx_assembly", "mechanism": "inline_ptx", "outcome": "succeeded", - "detail": "CUDA 13.3 ptxas accepted both selector forms for all eight ordered-metadata INT8 variants at PTX 8.5 and sm_80.", - "artifact_kind": null, + "detail": "CUDA 13.3 ptxas accepted every selector form of all eight ordered-metadata sparse floating variants at PTX 8.5 and sm_80.", + "artifact_kind": "cubin", "tool_path": "/usr/local/cuda-13.3/bin/ptxas", "tool_version": "CUDA 13.3 V13.3.33 build cuda_13.3.r13.3/compiler.37862127_0", "tool_sha256": "7fdd01a4cf50e30746da98989c9272a907f491e6fd7fecfda14642e4375f88fb" + }, + { + "targets": [ + "sm_120", + "ptx85" + ], + "representation": "all eight generated ordered sparse floating MMA APIs checked across all 32 lanes and four logical accumulators per lane against an independent host GEMM oracle", + "stage": "runtime", + "mechanism": "inline_ptx", + "outcome": "succeeded", + "detail": "Re-measured with the asymmetric oracle on NVIDIA GeForce RTX 5090 (compute capability 12.0), NVIDIA driver 580.173.02, CUDA toolkit 13.3 V13.3.33. Command: cargo oxide run sparse_mma_ordered_float. Result: exit code 0; SUCCESS: all 8 variants; all 32 lanes and 4 logical accumulators/lane match host GEMM; positionally distinct A/B/C, all six ordered metadata codes (tf32: both), and a nonzero selector per selector domain executed; compute-sanitizer memcheck reports 0 errors.", + "artifact_kind": null, + "tool_path": null, + "tool_version": null, + "tool_sha256": null } ] }, @@ -190793,18 +190944,18 @@ "sha256": "b6a5db233133fb0ed693f8cb8aeb1d405254ce0ab10364478985292ec98cfcf0", "artifact_path": "/usr/local/cuda-13.3/nvvm/lib64/libnvvm.so.4.0.0", "build_id_prefix": "2330c0", - "status": "validated", + "status": "executed", "stages": [ { "targets": [ "compute_80", "ptx93" ], - "representation": "convergent ordered-metadata sparse m16n8k32 mixed-sign saturating INT8 inline PTX in the combined coverage kernel", + "representation": "eight convergent side-effecting ordered-metadata sparse floating inline PTX calls in the sparse_mma_ordered_float coverage kernel", "stage": "backend_codegen", "mechanism": "inline_ptx", "outcome": "succeeded", - "detail": "The production generated_intrinsics route produced 214,910-byte compute_80 NVVM IR with SHA-256 1c3668d8f8d712f3ea880fded2e10a7e9e4f4265f24f738f104d5bde8e7aee6c and 61,044-byte LTOIR with SHA-256 901eed79871048a57271f434b99bab16cccd7169be6629d6cdb0498bb8f95ece. The ordered raw calls use one compile-time selector per variant and exercise both 0 and 1 across the family.", + "detail": "The production emit-ltoir route (cargo oxide emit-ltoir sparse_mma_ordered_float --arch sm_80) produced 159,170-byte compute_80 NVVM IR with SHA-256 b338c017795f39f98f756f1d87dc202d1db274479c6619fef9797cb5a95f7613, and CUDA 13.3 libNVVM -gen-lto compiled it to 37,468-byte LTOIR with SHA-256 ac6d8317ba99d9c4332a0ce8777024bc066a7304c6ed4b64c341f4248f6b6100; both artifacts are byte-identical across repeated runs, and the module carries all eight ordered raw calls with one compile-time selector per variant.", "artifact_kind": null, "tool_path": null, "tool_version": null, @@ -190815,34 +190966,64 @@ "sm_80", "ptx93" ], - "representation": "combined standard and ordered sparse m16n8k32 INT8 coverage kernel", + "representation": "nvJitLink PTX containing all eight ordered sparse floating MMA forms", + "stage": "ptx_assembly", + "mechanism": "inline_ptx", + "outcome": "succeeded", + "detail": "nvJitLink rendered the LTOIR as 83,805-byte PTX 9.3 for sm_80 (SHA-256 4a92814b0579bf19a0ab8aa4c8b2114ec2170c87711831b2a17a31d579bf6e87) retaining all eight ordered forms, and CUDA 13.3 ptxas assembled it into a 41,896-byte cubin with SHA-256 26aa4d2f38132bc6a219ec7b22655a77b412176f464fe93d6c8ae81ea1b9e88b.", + "artifact_kind": "cubin", + "tool_path": "/usr/local/cuda-13.3/bin/ptxas", + "tool_version": "CUDA 13.3 V13.3.33 build cuda_13.3.r13.3/compiler.37862127_0", + "tool_sha256": "7fdd01a4cf50e30746da98989c9272a907f491e6fd7fecfda14642e4375f88fb" + }, + { + "targets": [ + "sm_80", + "ptx93" + ], + "representation": "the 37,468-byte all-variant libNVVM LTOIR linked for sm_80", "stage": "device_link", "mechanism": "inline_ptx", "outcome": "succeeded", - "detail": "nvJitLink produced a 22,632-byte cubin with SHA-256 ae24b75fec8d2c8d668765c2513a34c6d707f3acef48d6e106cf256028d72c26; cuobjdump contained 20 IMMA.SP.16832 instructions across the standard and ordered coverage. The ordered half contains all eight raw variants plus two representative compatibility-path calls.", + "detail": "nvJitLink linked the real libNVVM LTOIR into a 41,896-byte sm_80 cubin with SHA-256 99aa489c3c80ed1414df0c6fe073cff99dcb66a55fd0057729322b54790ac1bf; its cuobjdump SASS contains exactly eight HMMA.SP instructions, one per variant: 1688.F32.TF32, 16816.F32.TF32, 16816.F32.BF16, 16816.F32, 16816.F16, 16832.F32.BF16, 16832.F32, and 16832.F16.", "artifact_kind": "cubin", "tool_path": "/usr/local/cuda-13.3/lib64/libnvJitLink.so.13.3.33", "tool_version": "V13.3.33", "tool_sha256": "3ba1e744347cd68617b862eccfd98b125482e882b7a6319f42abc9a768513db8" + }, + { + "targets": [ + "sm_120", + "ptx93" + ], + "representation": "all eight generated ordered sparse floating MMA APIs checked across all 32 lanes and four logical accumulators per lane against an independent host GEMM oracle", + "stage": "runtime", + "mechanism": "inline_ptx", + "outcome": "succeeded", + "detail": "Executed through the libNVVM route (NVVM IR materialized by libNVVM plus nvJitLink at load time) on NVIDIA GeForce RTX 5090 (compute capability 12.0), NVIDIA driver 580.173.02, CUDA toolkit 13.3 V13.3.33. Command: cargo oxide run sparse_mma_ordered_float --emit-nvvm-ir --arch sm_120. Result: exit code 0; SUCCESS: all 8 variants; all 32 lanes and 4 logical accumulators/lane match host GEMM; positionally distinct A/B/C, all six ordered metadata codes (tf32: both), and a nonzero selector per selector domain executed; compute-sanitizer memcheck reports 0 errors.", + "artifact_kind": null, + "tool_path": null, + "tool_version": null, + "tool_sha256": null } ] } ], "sparse_mma": { - "shape": "m16n8k32", - "accumulator": "s32", - "a_element": "s8", - "b_element": "u8", + "shape": "m16n8k16", + "accumulator": "f32", + "a_element": "tf32", + "b_element": "tf32", "a_layout": "row", "b_layout": "col", - "overflow": "satfinite", + "overflow": "not_applicable", "metadata": "ordered", "selector": "immediate_zero_or_one", "participation": "all_warp_lanes_same_instruction_and_qualifiers_no_exited_lanes", - "adapter": "c4_i32_a2_u32_b2_u32_metadata_u32_selector_u32_to_d4_i32", - "llvm_adapter": "a2_i32_b2_i32_c4_i32_metadata_i32_selector_i32_to_d4_i32", + "adapter": "c4_f32_a4_u32_b4_u32_metadata_u32_selector_u32_to_d4_f32", + "llvm_adapter": "a4_i32_b4_i32_c4_f32_metadata_i32_selector_i32_to_d4_f32", "compatibility_source": "generated_stub", - "runtime_validation": "unexecuted" + "runtime_validation": "executed" }, "lowering": "generated_sparse_mma", "expected_ptx": { @@ -190851,14 +191032,13 @@ "sp::ordered_metadata", "sync", "aligned", - "m16n8k32", + "m16n8k16", "row", "col", - "satfinite", - "s32", - "s8", - "u8", - "s32" + "f32", + "tf32", + "tf32", + "f32" ], "operands": [ { @@ -190867,11 +191047,11 @@ }, { "kind": "register_list", - "length": 2 + "length": 4 }, { "kind": "register_list", - "length": 2 + "length": 4 }, { "kind": "register_list", @@ -190885,20 +191065,20 @@ } ] }, - "summary": "Multiplies warp-distributed sparse signed A and unsigned B INT8 fragments with ordered sparsity metadata and adds a saturating s32 accumulator." + "summary": "Multiplies warp-distributed ordered sparse tf32 A and B fragments and adds a f32 accumulator." }, { - "id": "mma_sp_ordered_metadata_m16n8k32_s32_u8", - "operation_key": "matrix.mma.sp.m16n8k32.row.col.s32.u8.u8.s32.wrapping.ordered_metadata", + "id": "mma_sp_ordered_metadata_m16n8k32_f16_f16", + "operation_key": "matrix.mma.sp.m16n8k32.row.col.f16.f16.f16.f16.not_applicable.ordered_metadata", "family": "sparse_mma", "source": { "kind": "llvm_imported", - "source_record": "int_nvvm_mma_sp_ordered_metadata_m16n8k32_row_col_u8" + "source_record": "int_nvvm_mma_sp_ordered_metadata_m16n8k32_row_col_f16_f16" }, "selections": [ { - "source_record": "anonymous_19658", - "asm": "mma.sp::ordered_metadata.sync.aligned.m16n8k32.row.col.s32.u8.u8.s32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1}},\n\t\t{{$rb0, $rb1}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}},\n\t\t$metadata,\n\t\t$selector;", + "source_record": "anonymous_19566", + "asm": "mma.sp::ordered_metadata.sync.aligned.m16n8k32.row.col.f16.f16.f16.f16\n\t\t{{$rd0, $rd1}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1, $rb2, $rb3}},\n\t\t{{$rc0, $rc1}},\n\t\t$metadata,\n\t\t$selector;", "predicates": [ "Subtarget->getSmVersion() >= 80", "Subtarget->getPTXVersion() >= 85" @@ -190906,24 +191086,24 @@ } ], "rust": { - "abi_id": "i0173", + "abi_id": "i1024", "module": "matrix", - "name": "mma_sp_ordered_metadata_m16n8k32_s32_u8", + "name": "mma_sp_ordered_metadata_m16n8k32_f16_f16", "arguments": [ - "[i32; 4]", - "[u32; 2]", "[u32; 2]", + "[u32; 4]", + "[u32; 4]", "u32", "u32" ], - "result": "[i32; 4]", + "result": "[u32; 2]", "safe": false, "must_use": true, "safe_allowlist_reason": null, - "canonical_path": "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0173", - "public_path": "cuda_intrinsics::matrix::mma_sp_ordered_metadata_m16n8k32_s32_u8", + "canonical_path": "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i1024", + "public_path": "cuda_intrinsics::matrix::mma_sp_ordered_metadata_m16n8k32_f16_f16", "compatibility_paths": [ - "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k32_s32_u8" + "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k32_f16_f16" ] }, "dialect": { @@ -190932,8 +191112,10 @@ "operands": [ "i32", "i32", - "i32", - "i32", + "u32", + "u32", + "u32", + "u32", "u32", "u32", "u32", @@ -190942,37 +191124,35 @@ "u32" ], "results": [ - "i32", - "i32", "i32", "i32" ] }, "llvm": { - "symbol": "llvm.nvvm.mma.sp.ordered.metadata.m16n8k32.row.col.u8", + "symbol": "llvm.nvvm.mma.sp.ordered.metadata.m16n8k32.row.col.f16.f16", "arguments": [ - "i32", - "i32", - "i32", - "i32", - "i32", - "i32", - "i32", - "i32", + "v2f16", + "v2f16", + "v2f16", + "v2f16", + "v2f16", + "v2f16", + "v2f16", + "v2f16", + "v2f16", + "v2f16", "i32", "i32" ], "results": [ - "i32", - "i32", - "i32", - "i32" + "v2f16", + "v2f16" ], "properties": [ - "ImmArg", + "ImmArg", "IntrNoCallback", "IntrNoMem", - "Range" + "Range" ], "result_facts": { "no_undef": false, @@ -190996,7 +191176,7 @@ } ] }, - "ptx_result": "[i32; 4]", + "ptx_result": "[u32; 2]", "targets": "all", "ptx_isa_version": "9.3", "ptx_isa_section": "9.7.15.6.3 Multiply-and-Accumulate Instruction: mma.sp", @@ -191006,7 +191186,7 @@ "profile": "rust-llvm-23.1.0-16696adc", "version": "LLVM version 23.1.0-rust-1.100.0-nightly", "sha256": "2e5bc688625ca7d98bca9b5f0f0d14525d2eb59e8a9842964e480df3ffd1f921", - "status": "validated", + "status": "executed", "target_triple": "nvptx64-nvidia-cuda", "gpu_target": "sm_80", "ptx_feature": "+ptx85" @@ -191032,18 +191212,18 @@ "sha256": "2e5bc688625ca7d98bca9b5f0f0d14525d2eb59e8a9842964e480df3ffd1f921", "artifact_path": null, "build_id_prefix": null, - "status": "validated", + "status": "executed", "stages": [ { "targets": [ "sm_80", "ptx85" ], - "representation": "convergent ordered-metadata sparse m16n8k32 unsigned INT8 inline PTX with selector immediates 0 and 1", + "representation": "eight committed per-intrinsic convergent inline-PTX probe fixtures covering every selector immediate", "stage": "backend_codegen", "mechanism": "inline_ptx", "outcome": "succeeded", - "detail": "The selected LLVM 22 probe retained exactly two unguarded ordered-metadata instructions, one for each selector, at PTX 8.5 and sm_80.", + "detail": "Pinned LLVM 23.1.0-rust lowered the eight per-intrinsic probe fixtures at sm_80/+ptx85 into 59,900 bytes of PTX across eight files; their concatenation in lexicographic id order has SHA-256 2eaae1b352ef07684549050756eba1ae0eb57318cfa329a9f103f086296f81dc, and every fixture retains one unguarded exact ordered-metadata instruction per selector immediate (24 across the family). Typed declarations of all eight intrinsics fail selection at sm_75/+ptx85 and sm_80/+ptx80, and select at sm_80, sm_86, sm_89, and sm_90/+ptx85 plus sm_100/+ptx86.", "artifact_kind": null, "tool_path": null, "tool_version": null, @@ -191054,15 +191234,30 @@ "sm_80", "ptx85" ], - "representation": "exact-floor PTX for ordered-metadata sparse m16n8k32 INT8 MMA", + "representation": "exact-floor per-intrinsic probe PTX containing all eight ordered sparse floating MMA forms", "stage": "ptx_assembly", "mechanism": "inline_ptx", "outcome": "succeeded", - "detail": "CUDA 13.3 ptxas accepted both selector forms for all eight ordered-metadata INT8 variants at PTX 8.5 and sm_80.", - "artifact_kind": null, + "detail": "CUDA 13.3 ptxas accepted every selector form of all eight ordered-metadata sparse floating variants at PTX 8.5 and sm_80.", + "artifact_kind": "cubin", "tool_path": "/usr/local/cuda-13.3/bin/ptxas", "tool_version": "CUDA 13.3 V13.3.33 build cuda_13.3.r13.3/compiler.37862127_0", "tool_sha256": "7fdd01a4cf50e30746da98989c9272a907f491e6fd7fecfda14642e4375f88fb" + }, + { + "targets": [ + "sm_120", + "ptx85" + ], + "representation": "all eight generated ordered sparse floating MMA APIs checked across all 32 lanes and four logical accumulators per lane against an independent host GEMM oracle", + "stage": "runtime", + "mechanism": "inline_ptx", + "outcome": "succeeded", + "detail": "Re-measured with the asymmetric oracle on NVIDIA GeForce RTX 5090 (compute capability 12.0), NVIDIA driver 580.173.02, CUDA toolkit 13.3 V13.3.33. Command: cargo oxide run sparse_mma_ordered_float. Result: exit code 0; SUCCESS: all 8 variants; all 32 lanes and 4 logical accumulators/lane match host GEMM; positionally distinct A/B/C, all six ordered metadata codes (tf32: both), and a nonzero selector per selector domain executed; compute-sanitizer memcheck reports 0 errors.", + "artifact_kind": null, + "tool_path": null, + "tool_version": null, + "tool_sha256": null } ] }, @@ -191086,18 +191281,18 @@ "sha256": "b6a5db233133fb0ed693f8cb8aeb1d405254ce0ab10364478985292ec98cfcf0", "artifact_path": "/usr/local/cuda-13.3/nvvm/lib64/libnvvm.so.4.0.0", "build_id_prefix": "2330c0", - "status": "validated", + "status": "executed", "stages": [ { "targets": [ "compute_80", "ptx93" ], - "representation": "convergent ordered-metadata sparse m16n8k32 unsigned INT8 inline PTX in the combined coverage kernel", + "representation": "eight convergent side-effecting ordered-metadata sparse floating inline PTX calls in the sparse_mma_ordered_float coverage kernel", "stage": "backend_codegen", "mechanism": "inline_ptx", "outcome": "succeeded", - "detail": "The production generated_intrinsics route produced 214,910-byte compute_80 NVVM IR with SHA-256 1c3668d8f8d712f3ea880fded2e10a7e9e4f4265f24f738f104d5bde8e7aee6c and 61,044-byte LTOIR with SHA-256 901eed79871048a57271f434b99bab16cccd7169be6629d6cdb0498bb8f95ece. The ordered raw calls use one compile-time selector per variant and exercise both 0 and 1 across the family.", + "detail": "The production emit-ltoir route (cargo oxide emit-ltoir sparse_mma_ordered_float --arch sm_80) produced 159,170-byte compute_80 NVVM IR with SHA-256 b338c017795f39f98f756f1d87dc202d1db274479c6619fef9797cb5a95f7613, and CUDA 13.3 libNVVM -gen-lto compiled it to 37,468-byte LTOIR with SHA-256 ac6d8317ba99d9c4332a0ce8777024bc066a7304c6ed4b64c341f4248f6b6100; both artifacts are byte-identical across repeated runs, and the module carries all eight ordered raw calls with one compile-time selector per variant.", "artifact_kind": null, "tool_path": null, "tool_version": null, @@ -191108,34 +191303,64 @@ "sm_80", "ptx93" ], - "representation": "combined standard and ordered sparse m16n8k32 INT8 coverage kernel", + "representation": "nvJitLink PTX containing all eight ordered sparse floating MMA forms", + "stage": "ptx_assembly", + "mechanism": "inline_ptx", + "outcome": "succeeded", + "detail": "nvJitLink rendered the LTOIR as 83,805-byte PTX 9.3 for sm_80 (SHA-256 4a92814b0579bf19a0ab8aa4c8b2114ec2170c87711831b2a17a31d579bf6e87) retaining all eight ordered forms, and CUDA 13.3 ptxas assembled it into a 41,896-byte cubin with SHA-256 26aa4d2f38132bc6a219ec7b22655a77b412176f464fe93d6c8ae81ea1b9e88b.", + "artifact_kind": "cubin", + "tool_path": "/usr/local/cuda-13.3/bin/ptxas", + "tool_version": "CUDA 13.3 V13.3.33 build cuda_13.3.r13.3/compiler.37862127_0", + "tool_sha256": "7fdd01a4cf50e30746da98989c9272a907f491e6fd7fecfda14642e4375f88fb" + }, + { + "targets": [ + "sm_80", + "ptx93" + ], + "representation": "the 37,468-byte all-variant libNVVM LTOIR linked for sm_80", "stage": "device_link", "mechanism": "inline_ptx", "outcome": "succeeded", - "detail": "nvJitLink produced a 22,632-byte cubin with SHA-256 ae24b75fec8d2c8d668765c2513a34c6d707f3acef48d6e106cf256028d72c26; cuobjdump contained 20 IMMA.SP.16832 instructions across the standard and ordered coverage. The ordered half contains all eight raw variants plus two representative compatibility-path calls.", + "detail": "nvJitLink linked the real libNVVM LTOIR into a 41,896-byte sm_80 cubin with SHA-256 99aa489c3c80ed1414df0c6fe073cff99dcb66a55fd0057729322b54790ac1bf; its cuobjdump SASS contains exactly eight HMMA.SP instructions, one per variant: 1688.F32.TF32, 16816.F32.TF32, 16816.F32.BF16, 16816.F32, 16816.F16, 16832.F32.BF16, 16832.F32, and 16832.F16.", "artifact_kind": "cubin", "tool_path": "/usr/local/cuda-13.3/lib64/libnvJitLink.so.13.3.33", "tool_version": "V13.3.33", "tool_sha256": "3ba1e744347cd68617b862eccfd98b125482e882b7a6319f42abc9a768513db8" + }, + { + "targets": [ + "sm_120", + "ptx93" + ], + "representation": "all eight generated ordered sparse floating MMA APIs checked across all 32 lanes and four logical accumulators per lane against an independent host GEMM oracle", + "stage": "runtime", + "mechanism": "inline_ptx", + "outcome": "succeeded", + "detail": "Executed through the libNVVM route (NVVM IR materialized by libNVVM plus nvJitLink at load time) on NVIDIA GeForce RTX 5090 (compute capability 12.0), NVIDIA driver 580.173.02, CUDA toolkit 13.3 V13.3.33. Command: cargo oxide run sparse_mma_ordered_float --emit-nvvm-ir --arch sm_120. Result: exit code 0; SUCCESS: all 8 variants; all 32 lanes and 4 logical accumulators/lane match host GEMM; positionally distinct A/B/C, all six ordered metadata codes (tf32: both), and a nonzero selector per selector domain executed; compute-sanitizer memcheck reports 0 errors.", + "artifact_kind": null, + "tool_path": null, + "tool_version": null, + "tool_sha256": null } ] } ], "sparse_mma": { "shape": "m16n8k32", - "accumulator": "s32", - "a_element": "u8", - "b_element": "u8", + "accumulator": "f16", + "a_element": "f16", + "b_element": "f16", "a_layout": "row", "b_layout": "col", - "overflow": "wrapping", + "overflow": "not_applicable", "metadata": "ordered", "selector": "immediate_zero_or_one", "participation": "all_warp_lanes_same_instruction_and_qualifiers_no_exited_lanes", - "adapter": "c4_i32_a2_u32_b2_u32_metadata_u32_selector_u32_to_d4_i32", - "llvm_adapter": "a2_i32_b2_i32_c4_i32_metadata_i32_selector_i32_to_d4_i32", + "adapter": "c2_u32_a4_u32_b4_u32_metadata_u32_selector_u32_to_d2_u32", + "llvm_adapter": "a4_v2_f16_b4_v2_f16_c2_v2_f16_metadata_i32_selector_i32_to_d2_v2_f16", "compatibility_source": "generated_stub", - "runtime_validation": "unexecuted" + "runtime_validation": "executed" }, "lowering": "generated_sparse_mma", "expected_ptx": { @@ -191147,27 +191372,27 @@ "m16n8k32", "row", "col", - "s32", - "u8", - "u8", - "s32" + "f16", + "f16", + "f16", + "f16" ], "operands": [ { "kind": "register_list", - "length": 4 + "length": 2 }, { "kind": "register_list", - "length": 2 + "length": 4 }, { "kind": "register_list", - "length": 2 + "length": 4 }, { "kind": "register_list", - "length": 4 + "length": 2 }, { "kind": "register" @@ -191177,20 +191402,20 @@ } ] }, - "summary": "Multiplies warp-distributed sparse unsigned A and unsigned B INT8 fragments with ordered sparsity metadata and adds a wrapping s32 accumulator." + "summary": "Multiplies warp-distributed ordered sparse f16 A and B fragments and adds a packed f16 accumulator." }, { - "id": "mma_sp_ordered_metadata_m16n8k32_s32_u8_s8", - "operation_key": "matrix.mma.sp.m16n8k32.row.col.s32.u8.s8.s32.wrapping.ordered_metadata", + "id": "mma_sp_ordered_metadata_m16n8k32_f32_bf16", + "operation_key": "matrix.mma.sp.m16n8k32.row.col.f32.bf16.bf16.f32.not_applicable.ordered_metadata", "family": "sparse_mma", "source": { "kind": "llvm_imported", - "source_record": "int_nvvm_mma_sp_ordered_metadata_m16n8k32_row_col_u8_s8" + "source_record": "int_nvvm_mma_sp_ordered_metadata_m16n8k32_row_col_bf16" }, "selections": [ { - "source_record": "anonymous_19654", - "asm": "mma.sp::ordered_metadata.sync.aligned.m16n8k32.row.col.s32.u8.s8.s32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1}},\n\t\t{{$rb0, $rb1}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}},\n\t\t$metadata,\n\t\t$selector;", + "source_record": "anonymous_19532", + "asm": "mma.sp::ordered_metadata.sync.aligned.m16n8k32.row.col.f32.bf16.bf16.f32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1, $rb2, $rb3}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}},\n\t\t$metadata,\n\t\t$selector;", "predicates": [ "Subtarget->getSmVersion() >= 80", "Subtarget->getPTXVersion() >= 85" @@ -191198,34 +191423,38 @@ } ], "rust": { - "abi_id": "i0174", + "abi_id": "i1023", "module": "matrix", - "name": "mma_sp_ordered_metadata_m16n8k32_s32_u8_s8", + "name": "mma_sp_ordered_metadata_m16n8k32_f32_bf16", "arguments": [ - "[i32; 4]", - "[u32; 2]", - "[u32; 2]", + "[f32; 4]", + "[u32; 4]", + "[u32; 4]", "u32", "u32" ], - "result": "[i32; 4]", + "result": "[f32; 4]", "safe": false, "must_use": true, "safe_allowlist_reason": null, - "canonical_path": "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0174", - "public_path": "cuda_intrinsics::matrix::mma_sp_ordered_metadata_m16n8k32_s32_u8_s8", + "canonical_path": "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i1023", + "public_path": "cuda_intrinsics::matrix::mma_sp_ordered_metadata_m16n8k32_f32_bf16", "compatibility_paths": [ - "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k32_s32_u8_s8" + "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k32_f32_bf16" ] }, "dialect": { "op_type": "SparseMmaOp", "op_name": "nvvm.sparse_mma", "operands": [ - "i32", - "i32", - "i32", - "i32", + "f32", + "f32", + "f32", + "f32", + "u32", + "u32", + "u32", + "u32", "u32", "u32", "u32", @@ -191234,14 +191463,14 @@ "u32" ], "results": [ - "i32", - "i32", - "i32", - "i32" + "f32", + "f32", + "f32", + "f32" ] }, "llvm": { - "symbol": "llvm.nvvm.mma.sp.ordered.metadata.m16n8k32.row.col.u8.s8", + "symbol": "llvm.nvvm.mma.sp.ordered.metadata.m16n8k32.row.col.bf16", "arguments": [ "i32", "i32", @@ -191251,20 +191480,24 @@ "i32", "i32", "i32", + "f32", + "f32", + "f32", + "f32", "i32", "i32" ], "results": [ - "i32", - "i32", - "i32", - "i32" + "f32", + "f32", + "f32", + "f32" ], "properties": [ - "ImmArg", + "ImmArg", "IntrNoCallback", "IntrNoMem", - "Range" + "Range" ], "result_facts": { "no_undef": false, @@ -191288,7 +191521,7 @@ } ] }, - "ptx_result": "[i32; 4]", + "ptx_result": "[f32; 4]", "targets": "all", "ptx_isa_version": "9.3", "ptx_isa_section": "9.7.15.6.3 Multiply-and-Accumulate Instruction: mma.sp", @@ -191298,7 +191531,7 @@ "profile": "rust-llvm-23.1.0-16696adc", "version": "LLVM version 23.1.0-rust-1.100.0-nightly", "sha256": "2e5bc688625ca7d98bca9b5f0f0d14525d2eb59e8a9842964e480df3ffd1f921", - "status": "validated", + "status": "executed", "target_triple": "nvptx64-nvidia-cuda", "gpu_target": "sm_80", "ptx_feature": "+ptx85" @@ -191324,18 +191557,18 @@ "sha256": "2e5bc688625ca7d98bca9b5f0f0d14525d2eb59e8a9842964e480df3ffd1f921", "artifact_path": null, "build_id_prefix": null, - "status": "validated", + "status": "executed", "stages": [ { "targets": [ "sm_80", "ptx85" ], - "representation": "convergent ordered-metadata sparse m16n8k32 mixed-sign INT8 inline PTX with selector immediates 0 and 1", + "representation": "eight committed per-intrinsic convergent inline-PTX probe fixtures covering every selector immediate", "stage": "backend_codegen", "mechanism": "inline_ptx", "outcome": "succeeded", - "detail": "The selected LLVM 22 probe retained exactly two unguarded ordered-metadata instructions, one for each selector, at PTX 8.5 and sm_80.", + "detail": "Pinned LLVM 23.1.0-rust lowered the eight per-intrinsic probe fixtures at sm_80/+ptx85 into 59,900 bytes of PTX across eight files; their concatenation in lexicographic id order has SHA-256 2eaae1b352ef07684549050756eba1ae0eb57318cfa329a9f103f086296f81dc, and every fixture retains one unguarded exact ordered-metadata instruction per selector immediate (24 across the family). Typed declarations of all eight intrinsics fail selection at sm_75/+ptx85 and sm_80/+ptx80, and select at sm_80, sm_86, sm_89, and sm_90/+ptx85 plus sm_100/+ptx86.", "artifact_kind": null, "tool_path": null, "tool_version": null, @@ -191346,15 +191579,30 @@ "sm_80", "ptx85" ], - "representation": "exact-floor PTX for ordered-metadata sparse m16n8k32 INT8 MMA", + "representation": "exact-floor per-intrinsic probe PTX containing all eight ordered sparse floating MMA forms", "stage": "ptx_assembly", "mechanism": "inline_ptx", "outcome": "succeeded", - "detail": "CUDA 13.3 ptxas accepted both selector forms for all eight ordered-metadata INT8 variants at PTX 8.5 and sm_80.", - "artifact_kind": null, + "detail": "CUDA 13.3 ptxas accepted every selector form of all eight ordered-metadata sparse floating variants at PTX 8.5 and sm_80.", + "artifact_kind": "cubin", "tool_path": "/usr/local/cuda-13.3/bin/ptxas", "tool_version": "CUDA 13.3 V13.3.33 build cuda_13.3.r13.3/compiler.37862127_0", "tool_sha256": "7fdd01a4cf50e30746da98989c9272a907f491e6fd7fecfda14642e4375f88fb" + }, + { + "targets": [ + "sm_120", + "ptx85" + ], + "representation": "all eight generated ordered sparse floating MMA APIs checked across all 32 lanes and four logical accumulators per lane against an independent host GEMM oracle", + "stage": "runtime", + "mechanism": "inline_ptx", + "outcome": "succeeded", + "detail": "Re-measured with the asymmetric oracle on NVIDIA GeForce RTX 5090 (compute capability 12.0), NVIDIA driver 580.173.02, CUDA toolkit 13.3 V13.3.33. Command: cargo oxide run sparse_mma_ordered_float. Result: exit code 0; SUCCESS: all 8 variants; all 32 lanes and 4 logical accumulators/lane match host GEMM; positionally distinct A/B/C, all six ordered metadata codes (tf32: both), and a nonzero selector per selector domain executed; compute-sanitizer memcheck reports 0 errors.", + "artifact_kind": null, + "tool_path": null, + "tool_version": null, + "tool_sha256": null } ] }, @@ -191378,18 +191626,18 @@ "sha256": "b6a5db233133fb0ed693f8cb8aeb1d405254ce0ab10364478985292ec98cfcf0", "artifact_path": "/usr/local/cuda-13.3/nvvm/lib64/libnvvm.so.4.0.0", "build_id_prefix": "2330c0", - "status": "validated", + "status": "executed", "stages": [ { "targets": [ "compute_80", "ptx93" ], - "representation": "convergent ordered-metadata sparse m16n8k32 mixed-sign INT8 inline PTX in the combined coverage kernel", + "representation": "eight convergent side-effecting ordered-metadata sparse floating inline PTX calls in the sparse_mma_ordered_float coverage kernel", "stage": "backend_codegen", "mechanism": "inline_ptx", "outcome": "succeeded", - "detail": "The production generated_intrinsics route produced 214,910-byte compute_80 NVVM IR with SHA-256 1c3668d8f8d712f3ea880fded2e10a7e9e4f4265f24f738f104d5bde8e7aee6c and 61,044-byte LTOIR with SHA-256 901eed79871048a57271f434b99bab16cccd7169be6629d6cdb0498bb8f95ece. The ordered raw calls use one compile-time selector per variant and exercise both 0 and 1 across the family.", + "detail": "The production emit-ltoir route (cargo oxide emit-ltoir sparse_mma_ordered_float --arch sm_80) produced 159,170-byte compute_80 NVVM IR with SHA-256 b338c017795f39f98f756f1d87dc202d1db274479c6619fef9797cb5a95f7613, and CUDA 13.3 libNVVM -gen-lto compiled it to 37,468-byte LTOIR with SHA-256 ac6d8317ba99d9c4332a0ce8777024bc066a7304c6ed4b64c341f4248f6b6100; both artifacts are byte-identical across repeated runs, and the module carries all eight ordered raw calls with one compile-time selector per variant.", "artifact_kind": null, "tool_path": null, "tool_version": null, @@ -191400,34 +191648,64 @@ "sm_80", "ptx93" ], - "representation": "combined standard and ordered sparse m16n8k32 INT8 coverage kernel", + "representation": "nvJitLink PTX containing all eight ordered sparse floating MMA forms", + "stage": "ptx_assembly", + "mechanism": "inline_ptx", + "outcome": "succeeded", + "detail": "nvJitLink rendered the LTOIR as 83,805-byte PTX 9.3 for sm_80 (SHA-256 4a92814b0579bf19a0ab8aa4c8b2114ec2170c87711831b2a17a31d579bf6e87) retaining all eight ordered forms, and CUDA 13.3 ptxas assembled it into a 41,896-byte cubin with SHA-256 26aa4d2f38132bc6a219ec7b22655a77b412176f464fe93d6c8ae81ea1b9e88b.", + "artifact_kind": "cubin", + "tool_path": "/usr/local/cuda-13.3/bin/ptxas", + "tool_version": "CUDA 13.3 V13.3.33 build cuda_13.3.r13.3/compiler.37862127_0", + "tool_sha256": "7fdd01a4cf50e30746da98989c9272a907f491e6fd7fecfda14642e4375f88fb" + }, + { + "targets": [ + "sm_80", + "ptx93" + ], + "representation": "the 37,468-byte all-variant libNVVM LTOIR linked for sm_80", "stage": "device_link", "mechanism": "inline_ptx", "outcome": "succeeded", - "detail": "nvJitLink produced a 22,632-byte cubin with SHA-256 ae24b75fec8d2c8d668765c2513a34c6d707f3acef48d6e106cf256028d72c26; cuobjdump contained 20 IMMA.SP.16832 instructions across the standard and ordered coverage. The ordered half contains all eight raw variants plus two representative compatibility-path calls.", + "detail": "nvJitLink linked the real libNVVM LTOIR into a 41,896-byte sm_80 cubin with SHA-256 99aa489c3c80ed1414df0c6fe073cff99dcb66a55fd0057729322b54790ac1bf; its cuobjdump SASS contains exactly eight HMMA.SP instructions, one per variant: 1688.F32.TF32, 16816.F32.TF32, 16816.F32.BF16, 16816.F32, 16816.F16, 16832.F32.BF16, 16832.F32, and 16832.F16.", "artifact_kind": "cubin", "tool_path": "/usr/local/cuda-13.3/lib64/libnvJitLink.so.13.3.33", "tool_version": "V13.3.33", "tool_sha256": "3ba1e744347cd68617b862eccfd98b125482e882b7a6319f42abc9a768513db8" + }, + { + "targets": [ + "sm_120", + "ptx93" + ], + "representation": "all eight generated ordered sparse floating MMA APIs checked across all 32 lanes and four logical accumulators per lane against an independent host GEMM oracle", + "stage": "runtime", + "mechanism": "inline_ptx", + "outcome": "succeeded", + "detail": "Executed through the libNVVM route (NVVM IR materialized by libNVVM plus nvJitLink at load time) on NVIDIA GeForce RTX 5090 (compute capability 12.0), NVIDIA driver 580.173.02, CUDA toolkit 13.3 V13.3.33. Command: cargo oxide run sparse_mma_ordered_float --emit-nvvm-ir --arch sm_120. Result: exit code 0; SUCCESS: all 8 variants; all 32 lanes and 4 logical accumulators/lane match host GEMM; positionally distinct A/B/C, all six ordered metadata codes (tf32: both), and a nonzero selector per selector domain executed; compute-sanitizer memcheck reports 0 errors.", + "artifact_kind": null, + "tool_path": null, + "tool_version": null, + "tool_sha256": null } ] } ], "sparse_mma": { "shape": "m16n8k32", - "accumulator": "s32", - "a_element": "u8", - "b_element": "s8", + "accumulator": "f32", + "a_element": "bf16", + "b_element": "bf16", "a_layout": "row", "b_layout": "col", - "overflow": "wrapping", + "overflow": "not_applicable", "metadata": "ordered", "selector": "immediate_zero_or_one", "participation": "all_warp_lanes_same_instruction_and_qualifiers_no_exited_lanes", - "adapter": "c4_i32_a2_u32_b2_u32_metadata_u32_selector_u32_to_d4_i32", - "llvm_adapter": "a2_i32_b2_i32_c4_i32_metadata_i32_selector_i32_to_d4_i32", + "adapter": "c4_f32_a4_u32_b4_u32_metadata_u32_selector_u32_to_d4_f32", + "llvm_adapter": "a4_i32_b4_i32_c4_f32_metadata_i32_selector_i32_to_d4_f32", "compatibility_source": "generated_stub", - "runtime_validation": "unexecuted" + "runtime_validation": "executed" }, "lowering": "generated_sparse_mma", "expected_ptx": { @@ -191439,10 +191717,10 @@ "m16n8k32", "row", "col", - "s32", - "u8", - "s8", - "s32" + "f32", + "bf16", + "bf16", + "f32" ], "operands": [ { @@ -191451,11 +191729,11 @@ }, { "kind": "register_list", - "length": 2 + "length": 4 }, { "kind": "register_list", - "length": 2 + "length": 4 }, { "kind": "register_list", @@ -191469,20 +191747,20 @@ } ] }, - "summary": "Multiplies warp-distributed sparse unsigned A and signed B INT8 fragments with ordered sparsity metadata and adds a wrapping s32 accumulator." + "summary": "Multiplies warp-distributed ordered sparse bf16 A and B fragments and adds a f32 accumulator." }, { - "id": "mma_sp_ordered_metadata_m16n8k32_s32_u8_s8_satfinite", - "operation_key": "matrix.mma.sp.m16n8k32.row.col.s32.u8.s8.s32.satfinite.ordered_metadata", + "id": "mma_sp_ordered_metadata_m16n8k32_f32_f16", + "operation_key": "matrix.mma.sp.m16n8k32.row.col.f32.f16.f16.f32.not_applicable.ordered_metadata", "family": "sparse_mma", "source": { "kind": "llvm_imported", - "source_record": "int_nvvm_mma_sp_ordered_metadata_m16n8k32_row_col_satfinite_u8_s8" + "source_record": "int_nvvm_mma_sp_ordered_metadata_m16n8k32_row_col_f32_f32" }, "selections": [ { - "source_record": "anonymous_19711", - "asm": "mma.sp::ordered_metadata.sync.aligned.m16n8k32.row.col.satfinite.s32.u8.s8.s32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1}},\n\t\t{{$rb0, $rb1}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}},\n\t\t$metadata,\n\t\t$selector;", + "source_record": "anonymous_19570", + "asm": "mma.sp::ordered_metadata.sync.aligned.m16n8k32.row.col.f32.f16.f16.f32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1, $rb2, $rb3}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}},\n\t\t$metadata,\n\t\t$selector;", "predicates": [ "Subtarget->getSmVersion() >= 80", "Subtarget->getPTXVersion() >= 85" @@ -191490,34 +191768,38 @@ } ], "rust": { - "abi_id": "i0178", + "abi_id": "i1025", "module": "matrix", - "name": "mma_sp_ordered_metadata_m16n8k32_s32_u8_s8_satfinite", + "name": "mma_sp_ordered_metadata_m16n8k32_f32_f16", "arguments": [ - "[i32; 4]", - "[u32; 2]", - "[u32; 2]", + "[f32; 4]", + "[u32; 4]", + "[u32; 4]", "u32", "u32" ], - "result": "[i32; 4]", + "result": "[f32; 4]", "safe": false, "must_use": true, "safe_allowlist_reason": null, - "canonical_path": "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0178", - "public_path": "cuda_intrinsics::matrix::mma_sp_ordered_metadata_m16n8k32_s32_u8_s8_satfinite", + "canonical_path": "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i1025", + "public_path": "cuda_intrinsics::matrix::mma_sp_ordered_metadata_m16n8k32_f32_f16", "compatibility_paths": [ - "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k32_s32_u8_s8_satfinite" + "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k32_f32_f16" ] }, "dialect": { "op_type": "SparseMmaOp", "op_name": "nvvm.sparse_mma", "operands": [ - "i32", - "i32", - "i32", - "i32", + "f32", + "f32", + "f32", + "f32", + "u32", + "u32", + "u32", + "u32", "u32", "u32", "u32", @@ -191526,37 +191808,2132 @@ "u32" ], "results": [ - "i32", - "i32", - "i32", - "i32" + "f32", + "f32", + "f32", + "f32" ] }, "llvm": { - "symbol": "llvm.nvvm.mma.sp.ordered.metadata.m16n8k32.row.col.satfinite.u8.s8", + "symbol": "llvm.nvvm.mma.sp.ordered.metadata.m16n8k32.row.col.f32.f32", "arguments": [ - "i32", - "i32", - "i32", - "i32", - "i32", - "i32", - "i32", - "i32", + "v2f16", + "v2f16", + "v2f16", + "v2f16", + "v2f16", + "v2f16", + "v2f16", + "v2f16", + "f32", + "f32", + "f32", + "f32", "i32", "i32" ], "results": [ - "i32", - "i32", - "i32", - "i32" + "f32", + "f32", + "f32", + "f32" ], "properties": [ - "ImmArg", + "ImmArg", "IntrNoCallback", "IntrNoMem", - "Range" + "Range" + ], + "result_facts": { + "no_undef": false, + "range": null + } + }, + "semantics": { + "pure": false, + "memory": "none", + "convergent": true, + "execution_scope": "warp" + }, + "target": { + "minimum_ptx": "8.5", + "hardware": { + "kind": "any_of", + "alternatives": [ + { + "kind": "minimum_sm", + "sm": 80 + } + ] + }, + "ptx_result": "[f32; 4]", + "targets": "all", + "ptx_isa_version": "9.3", + "ptx_isa_section": "9.7.15.6.3 Multiply-and-Accumulate Instruction: mma.sp", + "ptx_isa_url": "https://docs.nvidia.com/cuda/parallel-thread-execution/#warp-level-matrix-instructions-mma-sp" + }, + "backend": { + "profile": "rust-llvm-23.1.0-16696adc", + "version": "LLVM version 23.1.0-rust-1.100.0-nightly", + "sha256": "2e5bc688625ca7d98bca9b5f0f0d14525d2eb59e8a9842964e480df3ffd1f921", + "status": "executed", + "target_triple": "nvptx64-nvidia-cuda", + "gpu_target": "sm_80", + "ptx_feature": "+ptx85" + }, + "backend_lowerings": [ + { + "backend": "llvm_nvptx", + "mechanism": "inline_ptx", + "evidence_profile": "rust-llvm-23.1.0-16696adc", + "target": { + "minimum_ptx": "8.5", + "hardware": { + "kind": "any_of", + "alternatives": [ + { + "kind": "minimum_sm", + "sm": 80 + } + ] + } + }, + "version": "LLVM version 23.1.0-rust-1.100.0-nightly", + "sha256": "2e5bc688625ca7d98bca9b5f0f0d14525d2eb59e8a9842964e480df3ffd1f921", + "artifact_path": null, + "build_id_prefix": null, + "status": "executed", + "stages": [ + { + "targets": [ + "sm_80", + "ptx85" + ], + "representation": "eight committed per-intrinsic convergent inline-PTX probe fixtures covering every selector immediate", + "stage": "backend_codegen", + "mechanism": "inline_ptx", + "outcome": "succeeded", + "detail": "Pinned LLVM 23.1.0-rust lowered the eight per-intrinsic probe fixtures at sm_80/+ptx85 into 59,900 bytes of PTX across eight files; their concatenation in lexicographic id order has SHA-256 2eaae1b352ef07684549050756eba1ae0eb57318cfa329a9f103f086296f81dc, and every fixture retains one unguarded exact ordered-metadata instruction per selector immediate (24 across the family). Typed declarations of all eight intrinsics fail selection at sm_75/+ptx85 and sm_80/+ptx80, and select at sm_80, sm_86, sm_89, and sm_90/+ptx85 plus sm_100/+ptx86.", + "artifact_kind": null, + "tool_path": null, + "tool_version": null, + "tool_sha256": null + }, + { + "targets": [ + "sm_80", + "ptx85" + ], + "representation": "exact-floor per-intrinsic probe PTX containing all eight ordered sparse floating MMA forms", + "stage": "ptx_assembly", + "mechanism": "inline_ptx", + "outcome": "succeeded", + "detail": "CUDA 13.3 ptxas accepted every selector form of all eight ordered-metadata sparse floating variants at PTX 8.5 and sm_80.", + "artifact_kind": "cubin", + "tool_path": "/usr/local/cuda-13.3/bin/ptxas", + "tool_version": "CUDA 13.3 V13.3.33 build cuda_13.3.r13.3/compiler.37862127_0", + "tool_sha256": "7fdd01a4cf50e30746da98989c9272a907f491e6fd7fecfda14642e4375f88fb" + }, + { + "targets": [ + "sm_120", + "ptx85" + ], + "representation": "all eight generated ordered sparse floating MMA APIs checked across all 32 lanes and four logical accumulators per lane against an independent host GEMM oracle", + "stage": "runtime", + "mechanism": "inline_ptx", + "outcome": "succeeded", + "detail": "Re-measured with the asymmetric oracle on NVIDIA GeForce RTX 5090 (compute capability 12.0), NVIDIA driver 580.173.02, CUDA toolkit 13.3 V13.3.33. Command: cargo oxide run sparse_mma_ordered_float. Result: exit code 0; SUCCESS: all 8 variants; all 32 lanes and 4 logical accumulators/lane match host GEMM; positionally distinct A/B/C, all six ordered metadata codes (tf32: both), and a nonzero selector per selector domain executed; compute-sanitizer memcheck reports 0 errors.", + "artifact_kind": null, + "tool_path": null, + "tool_version": null, + "tool_sha256": null + } + ] + }, + { + "backend": "lib_nvvm", + "mechanism": "inline_ptx", + "evidence_profile": "cuda-13.3-libnvvm-13.3.33", + "target": { + "minimum_ptx": "8.5", + "hardware": { + "kind": "any_of", + "alternatives": [ + { + "kind": "minimum_sm", + "sm": 80 + } + ] + } + }, + "version": "CUDA toolkit 13.3; nvcc/libNVVM release V13.3.33", + "sha256": "b6a5db233133fb0ed693f8cb8aeb1d405254ce0ab10364478985292ec98cfcf0", + "artifact_path": "/usr/local/cuda-13.3/nvvm/lib64/libnvvm.so.4.0.0", + "build_id_prefix": "2330c0", + "status": "executed", + "stages": [ + { + "targets": [ + "compute_80", + "ptx93" + ], + "representation": "eight convergent side-effecting ordered-metadata sparse floating inline PTX calls in the sparse_mma_ordered_float coverage kernel", + "stage": "backend_codegen", + "mechanism": "inline_ptx", + "outcome": "succeeded", + "detail": "The production emit-ltoir route (cargo oxide emit-ltoir sparse_mma_ordered_float --arch sm_80) produced 159,170-byte compute_80 NVVM IR with SHA-256 b338c017795f39f98f756f1d87dc202d1db274479c6619fef9797cb5a95f7613, and CUDA 13.3 libNVVM -gen-lto compiled it to 37,468-byte LTOIR with SHA-256 ac6d8317ba99d9c4332a0ce8777024bc066a7304c6ed4b64c341f4248f6b6100; both artifacts are byte-identical across repeated runs, and the module carries all eight ordered raw calls with one compile-time selector per variant.", + "artifact_kind": null, + "tool_path": null, + "tool_version": null, + "tool_sha256": null + }, + { + "targets": [ + "sm_80", + "ptx93" + ], + "representation": "nvJitLink PTX containing all eight ordered sparse floating MMA forms", + "stage": "ptx_assembly", + "mechanism": "inline_ptx", + "outcome": "succeeded", + "detail": "nvJitLink rendered the LTOIR as 83,805-byte PTX 9.3 for sm_80 (SHA-256 4a92814b0579bf19a0ab8aa4c8b2114ec2170c87711831b2a17a31d579bf6e87) retaining all eight ordered forms, and CUDA 13.3 ptxas assembled it into a 41,896-byte cubin with SHA-256 26aa4d2f38132bc6a219ec7b22655a77b412176f464fe93d6c8ae81ea1b9e88b.", + "artifact_kind": "cubin", + "tool_path": "/usr/local/cuda-13.3/bin/ptxas", + "tool_version": "CUDA 13.3 V13.3.33 build cuda_13.3.r13.3/compiler.37862127_0", + "tool_sha256": "7fdd01a4cf50e30746da98989c9272a907f491e6fd7fecfda14642e4375f88fb" + }, + { + "targets": [ + "sm_80", + "ptx93" + ], + "representation": "the 37,468-byte all-variant libNVVM LTOIR linked for sm_80", + "stage": "device_link", + "mechanism": "inline_ptx", + "outcome": "succeeded", + "detail": "nvJitLink linked the real libNVVM LTOIR into a 41,896-byte sm_80 cubin with SHA-256 99aa489c3c80ed1414df0c6fe073cff99dcb66a55fd0057729322b54790ac1bf; its cuobjdump SASS contains exactly eight HMMA.SP instructions, one per variant: 1688.F32.TF32, 16816.F32.TF32, 16816.F32.BF16, 16816.F32, 16816.F16, 16832.F32.BF16, 16832.F32, and 16832.F16.", + "artifact_kind": "cubin", + "tool_path": "/usr/local/cuda-13.3/lib64/libnvJitLink.so.13.3.33", + "tool_version": "V13.3.33", + "tool_sha256": "3ba1e744347cd68617b862eccfd98b125482e882b7a6319f42abc9a768513db8" + }, + { + "targets": [ + "sm_120", + "ptx93" + ], + "representation": "all eight generated ordered sparse floating MMA APIs checked across all 32 lanes and four logical accumulators per lane against an independent host GEMM oracle", + "stage": "runtime", + "mechanism": "inline_ptx", + "outcome": "succeeded", + "detail": "Executed through the libNVVM route (NVVM IR materialized by libNVVM plus nvJitLink at load time) on NVIDIA GeForce RTX 5090 (compute capability 12.0), NVIDIA driver 580.173.02, CUDA toolkit 13.3 V13.3.33. Command: cargo oxide run sparse_mma_ordered_float --emit-nvvm-ir --arch sm_120. Result: exit code 0; SUCCESS: all 8 variants; all 32 lanes and 4 logical accumulators/lane match host GEMM; positionally distinct A/B/C, all six ordered metadata codes (tf32: both), and a nonzero selector per selector domain executed; compute-sanitizer memcheck reports 0 errors.", + "artifact_kind": null, + "tool_path": null, + "tool_version": null, + "tool_sha256": null + } + ] + } + ], + "sparse_mma": { + "shape": "m16n8k32", + "accumulator": "f32", + "a_element": "f16", + "b_element": "f16", + "a_layout": "row", + "b_layout": "col", + "overflow": "not_applicable", + "metadata": "ordered", + "selector": "immediate_zero_or_one", + "participation": "all_warp_lanes_same_instruction_and_qualifiers_no_exited_lanes", + "adapter": "c4_f32_a4_u32_b4_u32_metadata_u32_selector_u32_to_d4_f32", + "llvm_adapter": "a4_v2_f16_b4_v2_f16_c4_f32_metadata_i32_selector_i32_to_d4_f32", + "compatibility_source": "generated_stub", + "runtime_validation": "executed" + }, + "lowering": "generated_sparse_mma", + "expected_ptx": { + "mnemonic": "mma", + "modifiers": [ + "sp::ordered_metadata", + "sync", + "aligned", + "m16n8k32", + "row", + "col", + "f32", + "f16", + "f16", + "f32" + ], + "operands": [ + { + "kind": "register_list", + "length": 4 + }, + { + "kind": "register_list", + "length": 4 + }, + { + "kind": "register_list", + "length": 4 + }, + { + "kind": "register_list", + "length": 4 + }, + { + "kind": "register" + }, + { + "kind": "immediate" + } + ] + }, + "summary": "Multiplies warp-distributed ordered sparse f16 A and B fragments and adds a f32 accumulator." + }, + { + "id": "mma_sp_ordered_metadata_m16n8k32_s32_s8", + "operation_key": "matrix.mma.sp.m16n8k32.row.col.s32.s8.s8.s32.wrapping.ordered_metadata", + "family": "sparse_mma", + "source": { + "kind": "llvm_imported", + "source_record": "int_nvvm_mma_sp_ordered_metadata_m16n8k32_row_col_s8" + }, + "selections": [ + { + "source_record": "anonymous_19644", + "asm": "mma.sp::ordered_metadata.sync.aligned.m16n8k32.row.col.s32.s8.s8.s32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1}},\n\t\t{{$rb0, $rb1}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}},\n\t\t$metadata,\n\t\t$selector;", + "predicates": [ + "Subtarget->getSmVersion() >= 80", + "Subtarget->getPTXVersion() >= 85" + ] + } + ], + "rust": { + "abi_id": "i0171", + "module": "matrix", + "name": "mma_sp_ordered_metadata_m16n8k32_s32_s8", + "arguments": [ + "[i32; 4]", + "[u32; 2]", + "[u32; 2]", + "u32", + "u32" + ], + "result": "[i32; 4]", + "safe": false, + "must_use": true, + "safe_allowlist_reason": null, + "canonical_path": "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0171", + "public_path": "cuda_intrinsics::matrix::mma_sp_ordered_metadata_m16n8k32_s32_s8", + "compatibility_paths": [ + "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k32_s32_s8" + ] + }, + "dialect": { + "op_type": "SparseMmaOp", + "op_name": "nvvm.sparse_mma", + "operands": [ + "i32", + "i32", + "i32", + "i32", + "u32", + "u32", + "u32", + "u32", + "u32", + "u32" + ], + "results": [ + "i32", + "i32", + "i32", + "i32" + ] + }, + "llvm": { + "symbol": "llvm.nvvm.mma.sp.ordered.metadata.m16n8k32.row.col.s8", + "arguments": [ + "i32", + "i32", + "i32", + "i32", + "i32", + "i32", + "i32", + "i32", + "i32", + "i32" + ], + "results": [ + "i32", + "i32", + "i32", + "i32" + ], + "properties": [ + "ImmArg", + "IntrNoCallback", + "IntrNoMem", + "Range" + ], + "result_facts": { + "no_undef": false, + "range": null + } + }, + "semantics": { + "pure": false, + "memory": "none", + "convergent": true, + "execution_scope": "warp" + }, + "target": { + "minimum_ptx": "8.5", + "hardware": { + "kind": "any_of", + "alternatives": [ + { + "kind": "minimum_sm", + "sm": 80 + } + ] + }, + "ptx_result": "[i32; 4]", + "targets": "all", + "ptx_isa_version": "9.3", + "ptx_isa_section": "9.7.15.6.3 Multiply-and-Accumulate Instruction: mma.sp", + "ptx_isa_url": "https://docs.nvidia.com/cuda/parallel-thread-execution/#warp-level-matrix-instructions-mma-sp" + }, + "backend": { + "profile": "rust-llvm-23.1.0-16696adc", + "version": "LLVM version 23.1.0-rust-1.100.0-nightly", + "sha256": "2e5bc688625ca7d98bca9b5f0f0d14525d2eb59e8a9842964e480df3ffd1f921", + "status": "validated", + "target_triple": "nvptx64-nvidia-cuda", + "gpu_target": "sm_80", + "ptx_feature": "+ptx85" + }, + "backend_lowerings": [ + { + "backend": "llvm_nvptx", + "mechanism": "inline_ptx", + "evidence_profile": "rust-llvm-23.1.0-16696adc", + "target": { + "minimum_ptx": "8.5", + "hardware": { + "kind": "any_of", + "alternatives": [ + { + "kind": "minimum_sm", + "sm": 80 + } + ] + } + }, + "version": "LLVM version 23.1.0-rust-1.100.0-nightly", + "sha256": "2e5bc688625ca7d98bca9b5f0f0d14525d2eb59e8a9842964e480df3ffd1f921", + "artifact_path": null, + "build_id_prefix": null, + "status": "validated", + "stages": [ + { + "targets": [ + "sm_80", + "ptx85" + ], + "representation": "convergent ordered-metadata sparse m16n8k32 signed INT8 inline PTX with selector immediates 0 and 1", + "stage": "backend_codegen", + "mechanism": "inline_ptx", + "outcome": "succeeded", + "detail": "The selected LLVM 22 probe retained exactly two unguarded ordered-metadata instructions, one for each selector, at PTX 8.5 and sm_80.", + "artifact_kind": null, + "tool_path": null, + "tool_version": null, + "tool_sha256": null + }, + { + "targets": [ + "sm_80", + "ptx85" + ], + "representation": "exact-floor PTX for ordered-metadata sparse m16n8k32 INT8 MMA", + "stage": "ptx_assembly", + "mechanism": "inline_ptx", + "outcome": "succeeded", + "detail": "CUDA 13.3 ptxas accepted both selector forms for all eight ordered-metadata INT8 variants at PTX 8.5 and sm_80.", + "artifact_kind": null, + "tool_path": "/usr/local/cuda-13.3/bin/ptxas", + "tool_version": "CUDA 13.3 V13.3.33 build cuda_13.3.r13.3/compiler.37862127_0", + "tool_sha256": "7fdd01a4cf50e30746da98989c9272a907f491e6fd7fecfda14642e4375f88fb" + } + ] + }, + { + "backend": "lib_nvvm", + "mechanism": "inline_ptx", + "evidence_profile": "cuda-13.3-libnvvm-13.3.33", + "target": { + "minimum_ptx": "8.5", + "hardware": { + "kind": "any_of", + "alternatives": [ + { + "kind": "minimum_sm", + "sm": 80 + } + ] + } + }, + "version": "CUDA toolkit 13.3; nvcc/libNVVM release V13.3.33", + "sha256": "b6a5db233133fb0ed693f8cb8aeb1d405254ce0ab10364478985292ec98cfcf0", + "artifact_path": "/usr/local/cuda-13.3/nvvm/lib64/libnvvm.so.4.0.0", + "build_id_prefix": "2330c0", + "status": "validated", + "stages": [ + { + "targets": [ + "compute_80", + "ptx93" + ], + "representation": "convergent ordered-metadata sparse m16n8k32 signed INT8 inline PTX in the combined coverage kernel", + "stage": "backend_codegen", + "mechanism": "inline_ptx", + "outcome": "succeeded", + "detail": "The production generated_intrinsics route produced 214,910-byte compute_80 NVVM IR with SHA-256 1c3668d8f8d712f3ea880fded2e10a7e9e4f4265f24f738f104d5bde8e7aee6c and 61,044-byte LTOIR with SHA-256 901eed79871048a57271f434b99bab16cccd7169be6629d6cdb0498bb8f95ece. The ordered raw calls use one compile-time selector per variant and exercise both 0 and 1 across the family.", + "artifact_kind": null, + "tool_path": null, + "tool_version": null, + "tool_sha256": null + }, + { + "targets": [ + "sm_80", + "ptx93" + ], + "representation": "combined standard and ordered sparse m16n8k32 INT8 coverage kernel", + "stage": "device_link", + "mechanism": "inline_ptx", + "outcome": "succeeded", + "detail": "nvJitLink produced a 22,632-byte cubin with SHA-256 ae24b75fec8d2c8d668765c2513a34c6d707f3acef48d6e106cf256028d72c26; cuobjdump contained 20 IMMA.SP.16832 instructions across the standard and ordered coverage. The ordered half contains all eight raw variants plus two representative compatibility-path calls.", + "artifact_kind": "cubin", + "tool_path": "/usr/local/cuda-13.3/lib64/libnvJitLink.so.13.3.33", + "tool_version": "V13.3.33", + "tool_sha256": "3ba1e744347cd68617b862eccfd98b125482e882b7a6319f42abc9a768513db8" + } + ] + } + ], + "sparse_mma": { + "shape": "m16n8k32", + "accumulator": "s32", + "a_element": "s8", + "b_element": "s8", + "a_layout": "row", + "b_layout": "col", + "overflow": "wrapping", + "metadata": "ordered", + "selector": "immediate_zero_or_one", + "participation": "all_warp_lanes_same_instruction_and_qualifiers_no_exited_lanes", + "adapter": "c4_i32_a2_u32_b2_u32_metadata_u32_selector_u32_to_d4_i32", + "llvm_adapter": "a2_i32_b2_i32_c4_i32_metadata_i32_selector_i32_to_d4_i32", + "compatibility_source": "generated_stub", + "runtime_validation": "unexecuted" + }, + "lowering": "generated_sparse_mma", + "expected_ptx": { + "mnemonic": "mma", + "modifiers": [ + "sp::ordered_metadata", + "sync", + "aligned", + "m16n8k32", + "row", + "col", + "s32", + "s8", + "s8", + "s32" + ], + "operands": [ + { + "kind": "register_list", + "length": 4 + }, + { + "kind": "register_list", + "length": 2 + }, + { + "kind": "register_list", + "length": 2 + }, + { + "kind": "register_list", + "length": 4 + }, + { + "kind": "register" + }, + { + "kind": "immediate" + } + ] + }, + "summary": "Multiplies warp-distributed sparse signed A and signed B INT8 fragments with ordered sparsity metadata and adds a wrapping s32 accumulator." + }, + { + "id": "mma_sp_ordered_metadata_m16n8k32_s32_s8_satfinite", + "operation_key": "matrix.mma.sp.m16n8k32.row.col.s32.s8.s8.s32.satfinite.ordered_metadata", + "family": "sparse_mma", + "source": { + "kind": "llvm_imported", + "source_record": "int_nvvm_mma_sp_ordered_metadata_m16n8k32_row_col_satfinite_s8" + }, + "selections": [ + { + "source_record": "anonymous_19705", + "asm": "mma.sp::ordered_metadata.sync.aligned.m16n8k32.row.col.satfinite.s32.s8.s8.s32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1}},\n\t\t{{$rb0, $rb1}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}},\n\t\t$metadata,\n\t\t$selector;", + "predicates": [ + "Subtarget->getSmVersion() >= 80", + "Subtarget->getPTXVersion() >= 85" + ] + } + ], + "rust": { + "abi_id": "i0175", + "module": "matrix", + "name": "mma_sp_ordered_metadata_m16n8k32_s32_s8_satfinite", + "arguments": [ + "[i32; 4]", + "[u32; 2]", + "[u32; 2]", + "u32", + "u32" + ], + "result": "[i32; 4]", + "safe": false, + "must_use": true, + "safe_allowlist_reason": null, + "canonical_path": "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0175", + "public_path": "cuda_intrinsics::matrix::mma_sp_ordered_metadata_m16n8k32_s32_s8_satfinite", + "compatibility_paths": [ + "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k32_s32_s8_satfinite" + ] + }, + "dialect": { + "op_type": "SparseMmaOp", + "op_name": "nvvm.sparse_mma", + "operands": [ + "i32", + "i32", + "i32", + "i32", + "u32", + "u32", + "u32", + "u32", + "u32", + "u32" + ], + "results": [ + "i32", + "i32", + "i32", + "i32" + ] + }, + "llvm": { + "symbol": "llvm.nvvm.mma.sp.ordered.metadata.m16n8k32.row.col.satfinite.s8", + "arguments": [ + "i32", + "i32", + "i32", + "i32", + "i32", + "i32", + "i32", + "i32", + "i32", + "i32" + ], + "results": [ + "i32", + "i32", + "i32", + "i32" + ], + "properties": [ + "ImmArg", + "IntrNoCallback", + "IntrNoMem", + "Range" + ], + "result_facts": { + "no_undef": false, + "range": null + } + }, + "semantics": { + "pure": false, + "memory": "none", + "convergent": true, + "execution_scope": "warp" + }, + "target": { + "minimum_ptx": "8.5", + "hardware": { + "kind": "any_of", + "alternatives": [ + { + "kind": "minimum_sm", + "sm": 80 + } + ] + }, + "ptx_result": "[i32; 4]", + "targets": "all", + "ptx_isa_version": "9.3", + "ptx_isa_section": "9.7.15.6.3 Multiply-and-Accumulate Instruction: mma.sp", + "ptx_isa_url": "https://docs.nvidia.com/cuda/parallel-thread-execution/#warp-level-matrix-instructions-mma-sp" + }, + "backend": { + "profile": "rust-llvm-23.1.0-16696adc", + "version": "LLVM version 23.1.0-rust-1.100.0-nightly", + "sha256": "2e5bc688625ca7d98bca9b5f0f0d14525d2eb59e8a9842964e480df3ffd1f921", + "status": "validated", + "target_triple": "nvptx64-nvidia-cuda", + "gpu_target": "sm_80", + "ptx_feature": "+ptx85" + }, + "backend_lowerings": [ + { + "backend": "llvm_nvptx", + "mechanism": "inline_ptx", + "evidence_profile": "rust-llvm-23.1.0-16696adc", + "target": { + "minimum_ptx": "8.5", + "hardware": { + "kind": "any_of", + "alternatives": [ + { + "kind": "minimum_sm", + "sm": 80 + } + ] + } + }, + "version": "LLVM version 23.1.0-rust-1.100.0-nightly", + "sha256": "2e5bc688625ca7d98bca9b5f0f0d14525d2eb59e8a9842964e480df3ffd1f921", + "artifact_path": null, + "build_id_prefix": null, + "status": "validated", + "stages": [ + { + "targets": [ + "sm_80", + "ptx85" + ], + "representation": "convergent ordered-metadata sparse m16n8k32 signed saturating INT8 inline PTX with selector immediates 0 and 1", + "stage": "backend_codegen", + "mechanism": "inline_ptx", + "outcome": "succeeded", + "detail": "The selected LLVM 22 probe retained exactly two unguarded ordered-metadata instructions, one for each selector, at PTX 8.5 and sm_80.", + "artifact_kind": null, + "tool_path": null, + "tool_version": null, + "tool_sha256": null + }, + { + "targets": [ + "sm_80", + "ptx85" + ], + "representation": "exact-floor PTX for ordered-metadata sparse m16n8k32 INT8 MMA", + "stage": "ptx_assembly", + "mechanism": "inline_ptx", + "outcome": "succeeded", + "detail": "CUDA 13.3 ptxas accepted both selector forms for all eight ordered-metadata INT8 variants at PTX 8.5 and sm_80.", + "artifact_kind": null, + "tool_path": "/usr/local/cuda-13.3/bin/ptxas", + "tool_version": "CUDA 13.3 V13.3.33 build cuda_13.3.r13.3/compiler.37862127_0", + "tool_sha256": "7fdd01a4cf50e30746da98989c9272a907f491e6fd7fecfda14642e4375f88fb" + } + ] + }, + { + "backend": "lib_nvvm", + "mechanism": "inline_ptx", + "evidence_profile": "cuda-13.3-libnvvm-13.3.33", + "target": { + "minimum_ptx": "8.5", + "hardware": { + "kind": "any_of", + "alternatives": [ + { + "kind": "minimum_sm", + "sm": 80 + } + ] + } + }, + "version": "CUDA toolkit 13.3; nvcc/libNVVM release V13.3.33", + "sha256": "b6a5db233133fb0ed693f8cb8aeb1d405254ce0ab10364478985292ec98cfcf0", + "artifact_path": "/usr/local/cuda-13.3/nvvm/lib64/libnvvm.so.4.0.0", + "build_id_prefix": "2330c0", + "status": "validated", + "stages": [ + { + "targets": [ + "compute_80", + "ptx93" + ], + "representation": "convergent ordered-metadata sparse m16n8k32 signed saturating INT8 inline PTX in the combined coverage kernel", + "stage": "backend_codegen", + "mechanism": "inline_ptx", + "outcome": "succeeded", + "detail": "The production generated_intrinsics route produced 214,910-byte compute_80 NVVM IR with SHA-256 1c3668d8f8d712f3ea880fded2e10a7e9e4f4265f24f738f104d5bde8e7aee6c and 61,044-byte LTOIR with SHA-256 901eed79871048a57271f434b99bab16cccd7169be6629d6cdb0498bb8f95ece. The ordered raw calls use one compile-time selector per variant and exercise both 0 and 1 across the family.", + "artifact_kind": null, + "tool_path": null, + "tool_version": null, + "tool_sha256": null + }, + { + "targets": [ + "sm_80", + "ptx93" + ], + "representation": "combined standard and ordered sparse m16n8k32 INT8 coverage kernel", + "stage": "device_link", + "mechanism": "inline_ptx", + "outcome": "succeeded", + "detail": "nvJitLink produced a 22,632-byte cubin with SHA-256 ae24b75fec8d2c8d668765c2513a34c6d707f3acef48d6e106cf256028d72c26; cuobjdump contained 20 IMMA.SP.16832 instructions across the standard and ordered coverage. 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4]", + "targets": "all", + "ptx_isa_version": "9.3", + "ptx_isa_section": "9.7.15.6.3 Multiply-and-Accumulate Instruction: mma.sp", + "ptx_isa_url": "https://docs.nvidia.com/cuda/parallel-thread-execution/#warp-level-matrix-instructions-mma-sp" + }, + "backend": { + "profile": "rust-llvm-23.1.0-16696adc", + "version": "LLVM version 23.1.0-rust-1.100.0-nightly", + "sha256": "2e5bc688625ca7d98bca9b5f0f0d14525d2eb59e8a9842964e480df3ffd1f921", + "status": "validated", + "target_triple": "nvptx64-nvidia-cuda", + "gpu_target": "sm_80", + "ptx_feature": "+ptx85" + }, + "backend_lowerings": [ + { + "backend": "llvm_nvptx", + "mechanism": "inline_ptx", + "evidence_profile": "rust-llvm-23.1.0-16696adc", + "target": { + "minimum_ptx": "8.5", + "hardware": { + "kind": "any_of", + "alternatives": [ + { + "kind": "minimum_sm", + "sm": 80 + } + ] + } + }, + "version": "LLVM version 23.1.0-rust-1.100.0-nightly", + "sha256": "2e5bc688625ca7d98bca9b5f0f0d14525d2eb59e8a9842964e480df3ffd1f921", + "artifact_path": null, + "build_id_prefix": null, + "status": "validated", + "stages": [ + { + "targets": [ + "sm_80", + "ptx85" + ], + "representation": "convergent ordered-metadata sparse m16n8k32 mixed-sign INT8 inline PTX with selector immediates 0 and 1", + "stage": "backend_codegen", + "mechanism": "inline_ptx", + "outcome": "succeeded", + "detail": "The selected LLVM 22 probe retained exactly two unguarded ordered-metadata instructions, one for each selector, at PTX 8.5 and sm_80.", + "artifact_kind": null, + "tool_path": null, + "tool_version": null, + "tool_sha256": null + }, + { + "targets": [ + "sm_80", + "ptx85" + ], + "representation": "exact-floor PTX for ordered-metadata sparse m16n8k32 INT8 MMA", + "stage": "ptx_assembly", + "mechanism": "inline_ptx", + "outcome": "succeeded", + "detail": "CUDA 13.3 ptxas accepted both selector forms for all eight ordered-metadata INT8 variants at PTX 8.5 and sm_80.", + "artifact_kind": null, + "tool_path": "/usr/local/cuda-13.3/bin/ptxas", + "tool_version": "CUDA 13.3 V13.3.33 build cuda_13.3.r13.3/compiler.37862127_0", + "tool_sha256": "7fdd01a4cf50e30746da98989c9272a907f491e6fd7fecfda14642e4375f88fb" + } + ] + }, + { + "backend": "lib_nvvm", + "mechanism": "inline_ptx", + "evidence_profile": "cuda-13.3-libnvvm-13.3.33", + "target": { + "minimum_ptx": "8.5", + "hardware": { + "kind": "any_of", + "alternatives": [ + { + "kind": "minimum_sm", + "sm": 80 + } + ] + } + }, + "version": "CUDA toolkit 13.3; nvcc/libNVVM release V13.3.33", + "sha256": "b6a5db233133fb0ed693f8cb8aeb1d405254ce0ab10364478985292ec98cfcf0", + "artifact_path": "/usr/local/cuda-13.3/nvvm/lib64/libnvvm.so.4.0.0", + "build_id_prefix": "2330c0", + "status": "validated", + "stages": [ + { + "targets": [ + "compute_80", + "ptx93" + ], + "representation": "convergent ordered-metadata sparse m16n8k32 mixed-sign INT8 inline PTX in the combined coverage kernel", + "stage": "backend_codegen", + "mechanism": "inline_ptx", + "outcome": "succeeded", + "detail": "The production generated_intrinsics route produced 214,910-byte compute_80 NVVM IR with SHA-256 1c3668d8f8d712f3ea880fded2e10a7e9e4f4265f24f738f104d5bde8e7aee6c and 61,044-byte LTOIR with SHA-256 901eed79871048a57271f434b99bab16cccd7169be6629d6cdb0498bb8f95ece. The ordered raw calls use one compile-time selector per variant and exercise both 0 and 1 across the family.", + "artifact_kind": null, + "tool_path": null, + "tool_version": null, + "tool_sha256": null + }, + { + "targets": [ + "sm_80", + "ptx93" + ], + "representation": "combined standard and ordered sparse m16n8k32 INT8 coverage kernel", + "stage": "device_link", + "mechanism": "inline_ptx", + "outcome": "succeeded", + "detail": "nvJitLink produced a 22,632-byte cubin with SHA-256 ae24b75fec8d2c8d668765c2513a34c6d707f3acef48d6e106cf256028d72c26; cuobjdump contained 20 IMMA.SP.16832 instructions across the standard and ordered coverage. The ordered half contains all eight raw variants plus two representative compatibility-path calls.", + "artifact_kind": "cubin", + "tool_path": "/usr/local/cuda-13.3/lib64/libnvJitLink.so.13.3.33", + "tool_version": "V13.3.33", + "tool_sha256": "3ba1e744347cd68617b862eccfd98b125482e882b7a6319f42abc9a768513db8" + } + ] + } + ], + "sparse_mma": { + "shape": "m16n8k32", + "accumulator": "s32", + "a_element": "s8", + "b_element": "u8", + "a_layout": "row", + "b_layout": "col", + "overflow": "wrapping", + "metadata": "ordered", + "selector": "immediate_zero_or_one", + "participation": "all_warp_lanes_same_instruction_and_qualifiers_no_exited_lanes", + "adapter": "c4_i32_a2_u32_b2_u32_metadata_u32_selector_u32_to_d4_i32", + "llvm_adapter": "a2_i32_b2_i32_c4_i32_metadata_i32_selector_i32_to_d4_i32", + "compatibility_source": "generated_stub", + "runtime_validation": "unexecuted" + }, + "lowering": "generated_sparse_mma", + "expected_ptx": { + "mnemonic": "mma", + "modifiers": [ + "sp::ordered_metadata", + "sync", + "aligned", + "m16n8k32", + "row", + "col", + "s32", + "s8", + "u8", + "s32" + ], + "operands": [ + { + "kind": "register_list", + "length": 4 + }, + { + "kind": "register_list", + "length": 2 + }, + { + "kind": "register_list", + "length": 2 + }, + { + "kind": "register_list", + "length": 4 + }, + { + "kind": "register" + }, + { + "kind": "immediate" + } + ] + }, + "summary": "Multiplies warp-distributed sparse signed A and unsigned B INT8 fragments with ordered sparsity metadata and adds a wrapping s32 accumulator." + }, + { + "id": "mma_sp_ordered_metadata_m16n8k32_s32_s8_u8_satfinite", + "operation_key": "matrix.mma.sp.m16n8k32.row.col.s32.s8.u8.s32.satfinite.ordered_metadata", + "family": "sparse_mma", + "source": { + "kind": "llvm_imported", + "source_record": "int_nvvm_mma_sp_ordered_metadata_m16n8k32_row_col_satfinite_s8_u8" + }, + "selections": [ + { + "source_record": "anonymous_19708", + "asm": "mma.sp::ordered_metadata.sync.aligned.m16n8k32.row.col.satfinite.s32.s8.u8.s32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1}},\n\t\t{{$rb0, $rb1}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}},\n\t\t$metadata,\n\t\t$selector;", + "predicates": [ + "Subtarget->getSmVersion() >= 80", + "Subtarget->getPTXVersion() >= 85" + ] + } + ], + "rust": { + "abi_id": "i0176", + "module": "matrix", + "name": "mma_sp_ordered_metadata_m16n8k32_s32_s8_u8_satfinite", + "arguments": [ + "[i32; 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4]", + "targets": "all", + "ptx_isa_version": "9.3", + "ptx_isa_section": "9.7.15.6.3 Multiply-and-Accumulate Instruction: mma.sp", + "ptx_isa_url": "https://docs.nvidia.com/cuda/parallel-thread-execution/#warp-level-matrix-instructions-mma-sp" + }, + "backend": { + "profile": "rust-llvm-23.1.0-16696adc", + "version": "LLVM version 23.1.0-rust-1.100.0-nightly", + "sha256": "2e5bc688625ca7d98bca9b5f0f0d14525d2eb59e8a9842964e480df3ffd1f921", + "status": "validated", + "target_triple": "nvptx64-nvidia-cuda", + "gpu_target": "sm_80", + "ptx_feature": "+ptx85" + }, + "backend_lowerings": [ + { + "backend": "llvm_nvptx", + "mechanism": "inline_ptx", + "evidence_profile": "rust-llvm-23.1.0-16696adc", + "target": { + "minimum_ptx": "8.5", + "hardware": { + "kind": "any_of", + "alternatives": [ + { + "kind": "minimum_sm", + "sm": 80 + } + ] + } + }, + "version": "LLVM version 23.1.0-rust-1.100.0-nightly", + "sha256": "2e5bc688625ca7d98bca9b5f0f0d14525d2eb59e8a9842964e480df3ffd1f921", + "artifact_path": null, + "build_id_prefix": null, + "status": "validated", + "stages": [ + { + "targets": [ + "sm_80", + "ptx85" + ], + "representation": "convergent ordered-metadata sparse m16n8k32 mixed-sign saturating INT8 inline PTX with selector immediates 0 and 1", + "stage": "backend_codegen", + "mechanism": "inline_ptx", + "outcome": "succeeded", + "detail": "The selected LLVM 22 probe retained exactly two unguarded ordered-metadata instructions, one for each selector, at PTX 8.5 and sm_80.", + "artifact_kind": null, + "tool_path": null, + "tool_version": null, + "tool_sha256": null + }, + { + "targets": [ + "sm_80", + "ptx85" + ], + "representation": "exact-floor PTX for ordered-metadata sparse m16n8k32 INT8 MMA", + "stage": "ptx_assembly", + "mechanism": "inline_ptx", + "outcome": "succeeded", + "detail": "CUDA 13.3 ptxas accepted both selector forms for all eight ordered-metadata INT8 variants at PTX 8.5 and sm_80.", + "artifact_kind": null, + "tool_path": "/usr/local/cuda-13.3/bin/ptxas", + "tool_version": "CUDA 13.3 V13.3.33 build cuda_13.3.r13.3/compiler.37862127_0", + "tool_sha256": "7fdd01a4cf50e30746da98989c9272a907f491e6fd7fecfda14642e4375f88fb" + } + ] + }, + { + "backend": "lib_nvvm", + "mechanism": "inline_ptx", + "evidence_profile": "cuda-13.3-libnvvm-13.3.33", + "target": { + "minimum_ptx": "8.5", + "hardware": { + "kind": "any_of", + "alternatives": [ + { + "kind": "minimum_sm", + "sm": 80 + } + ] + } + }, + "version": "CUDA toolkit 13.3; nvcc/libNVVM release V13.3.33", + "sha256": "b6a5db233133fb0ed693f8cb8aeb1d405254ce0ab10364478985292ec98cfcf0", + "artifact_path": "/usr/local/cuda-13.3/nvvm/lib64/libnvvm.so.4.0.0", + "build_id_prefix": "2330c0", + "status": "validated", + "stages": [ + { + "targets": [ + "compute_80", + "ptx93" + ], + "representation": "convergent ordered-metadata sparse m16n8k32 mixed-sign saturating INT8 inline PTX in the combined coverage kernel", + "stage": "backend_codegen", + "mechanism": "inline_ptx", + "outcome": "succeeded", + "detail": "The production generated_intrinsics route produced 214,910-byte compute_80 NVVM IR with SHA-256 1c3668d8f8d712f3ea880fded2e10a7e9e4f4265f24f738f104d5bde8e7aee6c and 61,044-byte LTOIR with SHA-256 901eed79871048a57271f434b99bab16cccd7169be6629d6cdb0498bb8f95ece. The ordered raw calls use one compile-time selector per variant and exercise both 0 and 1 across the family.", + "artifact_kind": null, + "tool_path": null, + "tool_version": null, + "tool_sha256": null + }, + { + "targets": [ + "sm_80", + "ptx93" + ], + "representation": "combined standard and ordered sparse m16n8k32 INT8 coverage kernel", + "stage": "device_link", + "mechanism": "inline_ptx", + "outcome": "succeeded", + "detail": "nvJitLink produced a 22,632-byte cubin with SHA-256 ae24b75fec8d2c8d668765c2513a34c6d707f3acef48d6e106cf256028d72c26; cuobjdump contained 20 IMMA.SP.16832 instructions across the standard and ordered coverage. The ordered half contains all eight raw variants plus two representative compatibility-path calls.", + "artifact_kind": "cubin", + "tool_path": "/usr/local/cuda-13.3/lib64/libnvJitLink.so.13.3.33", + "tool_version": "V13.3.33", + "tool_sha256": "3ba1e744347cd68617b862eccfd98b125482e882b7a6319f42abc9a768513db8" + } + ] + } + ], + "sparse_mma": { + "shape": "m16n8k32", + "accumulator": "s32", + "a_element": "s8", + "b_element": "u8", + "a_layout": "row", + "b_layout": "col", + "overflow": "satfinite", + "metadata": "ordered", + "selector": "immediate_zero_or_one", + "participation": "all_warp_lanes_same_instruction_and_qualifiers_no_exited_lanes", + "adapter": "c4_i32_a2_u32_b2_u32_metadata_u32_selector_u32_to_d4_i32", + "llvm_adapter": "a2_i32_b2_i32_c4_i32_metadata_i32_selector_i32_to_d4_i32", + "compatibility_source": "generated_stub", + "runtime_validation": "unexecuted" + }, + "lowering": "generated_sparse_mma", + "expected_ptx": { + "mnemonic": "mma", + "modifiers": [ + "sp::ordered_metadata", + "sync", + "aligned", + "m16n8k32", + "row", + "col", + "satfinite", + "s32", + "s8", + "u8", + "s32" + ], + "operands": [ + { + "kind": "register_list", + "length": 4 + }, + { + "kind": "register_list", + "length": 2 + }, + { + "kind": "register_list", + "length": 2 + }, + { + "kind": "register_list", + "length": 4 + }, + { + "kind": "register" + }, + { + "kind": "immediate" + } + ] + }, + "summary": "Multiplies warp-distributed sparse signed A and unsigned B INT8 fragments with ordered sparsity metadata and adds a saturating s32 accumulator." + }, + { + "id": "mma_sp_ordered_metadata_m16n8k32_s32_u8", + "operation_key": "matrix.mma.sp.m16n8k32.row.col.s32.u8.u8.s32.wrapping.ordered_metadata", + "family": "sparse_mma", + "source": { + "kind": "llvm_imported", + "source_record": "int_nvvm_mma_sp_ordered_metadata_m16n8k32_row_col_u8" + }, + "selections": [ + { + "source_record": "anonymous_19658", + "asm": "mma.sp::ordered_metadata.sync.aligned.m16n8k32.row.col.s32.u8.u8.s32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1}},\n\t\t{{$rb0, $rb1}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}},\n\t\t$metadata,\n\t\t$selector;", + "predicates": [ + "Subtarget->getSmVersion() >= 80", + "Subtarget->getPTXVersion() >= 85" + ] + } + ], + "rust": { + "abi_id": "i0173", + "module": "matrix", + "name": "mma_sp_ordered_metadata_m16n8k32_s32_u8", + "arguments": [ + "[i32; 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4]", + "targets": "all", + "ptx_isa_version": "9.3", + "ptx_isa_section": "9.7.15.6.3 Multiply-and-Accumulate Instruction: mma.sp", + "ptx_isa_url": "https://docs.nvidia.com/cuda/parallel-thread-execution/#warp-level-matrix-instructions-mma-sp" + }, + "backend": { + "profile": "rust-llvm-23.1.0-16696adc", + "version": "LLVM version 23.1.0-rust-1.100.0-nightly", + "sha256": "2e5bc688625ca7d98bca9b5f0f0d14525d2eb59e8a9842964e480df3ffd1f921", + "status": "validated", + "target_triple": "nvptx64-nvidia-cuda", + "gpu_target": "sm_80", + "ptx_feature": "+ptx85" + }, + "backend_lowerings": [ + { + "backend": "llvm_nvptx", + "mechanism": "inline_ptx", + "evidence_profile": "rust-llvm-23.1.0-16696adc", + "target": { + "minimum_ptx": "8.5", + "hardware": { + "kind": "any_of", + "alternatives": [ + { + "kind": "minimum_sm", + "sm": 80 + } + ] + } + }, + "version": "LLVM version 23.1.0-rust-1.100.0-nightly", + "sha256": "2e5bc688625ca7d98bca9b5f0f0d14525d2eb59e8a9842964e480df3ffd1f921", + "artifact_path": null, + "build_id_prefix": null, + "status": "validated", + "stages": [ + { + "targets": [ + "sm_80", + "ptx85" + ], + "representation": "convergent ordered-metadata sparse m16n8k32 unsigned INT8 inline PTX with selector immediates 0 and 1", + "stage": "backend_codegen", + "mechanism": "inline_ptx", + "outcome": "succeeded", + "detail": "The selected LLVM 22 probe retained exactly two unguarded ordered-metadata instructions, one for each selector, at PTX 8.5 and sm_80.", + "artifact_kind": null, + "tool_path": null, + "tool_version": null, + "tool_sha256": null + }, + { + "targets": [ + "sm_80", + "ptx85" + ], + "representation": "exact-floor PTX for ordered-metadata sparse m16n8k32 INT8 MMA", + "stage": "ptx_assembly", + "mechanism": "inline_ptx", + "outcome": "succeeded", + "detail": "CUDA 13.3 ptxas accepted both selector forms for all eight ordered-metadata INT8 variants at PTX 8.5 and sm_80.", + "artifact_kind": null, + "tool_path": "/usr/local/cuda-13.3/bin/ptxas", + "tool_version": "CUDA 13.3 V13.3.33 build cuda_13.3.r13.3/compiler.37862127_0", + "tool_sha256": "7fdd01a4cf50e30746da98989c9272a907f491e6fd7fecfda14642e4375f88fb" + } + ] + }, + { + "backend": "lib_nvvm", + "mechanism": "inline_ptx", + "evidence_profile": "cuda-13.3-libnvvm-13.3.33", + "target": { + "minimum_ptx": "8.5", + "hardware": { + "kind": "any_of", + "alternatives": [ + { + "kind": "minimum_sm", + "sm": 80 + } + ] + } + }, + "version": "CUDA toolkit 13.3; nvcc/libNVVM release V13.3.33", + "sha256": "b6a5db233133fb0ed693f8cb8aeb1d405254ce0ab10364478985292ec98cfcf0", + "artifact_path": "/usr/local/cuda-13.3/nvvm/lib64/libnvvm.so.4.0.0", + "build_id_prefix": "2330c0", + "status": "validated", + "stages": [ + { + "targets": [ + "compute_80", + "ptx93" + ], + "representation": "convergent ordered-metadata sparse m16n8k32 unsigned INT8 inline PTX in the combined coverage kernel", + "stage": "backend_codegen", + "mechanism": "inline_ptx", + "outcome": "succeeded", + "detail": "The production generated_intrinsics route produced 214,910-byte compute_80 NVVM IR with SHA-256 1c3668d8f8d712f3ea880fded2e10a7e9e4f4265f24f738f104d5bde8e7aee6c and 61,044-byte LTOIR with SHA-256 901eed79871048a57271f434b99bab16cccd7169be6629d6cdb0498bb8f95ece. The ordered raw calls use one compile-time selector per variant and exercise both 0 and 1 across the family.", + "artifact_kind": null, + "tool_path": null, + "tool_version": null, + "tool_sha256": null + }, + { + "targets": [ + "sm_80", + "ptx93" + ], + "representation": "combined standard and ordered sparse m16n8k32 INT8 coverage kernel", + "stage": "device_link", + "mechanism": "inline_ptx", + "outcome": "succeeded", + "detail": "nvJitLink produced a 22,632-byte cubin with SHA-256 ae24b75fec8d2c8d668765c2513a34c6d707f3acef48d6e106cf256028d72c26; cuobjdump contained 20 IMMA.SP.16832 instructions across the standard and ordered coverage. The ordered half contains all eight raw variants plus two representative compatibility-path calls.", + "artifact_kind": "cubin", + "tool_path": "/usr/local/cuda-13.3/lib64/libnvJitLink.so.13.3.33", + "tool_version": "V13.3.33", + "tool_sha256": "3ba1e744347cd68617b862eccfd98b125482e882b7a6319f42abc9a768513db8" + } + ] + } + ], + "sparse_mma": { + "shape": "m16n8k32", + "accumulator": "s32", + "a_element": "u8", + "b_element": "u8", + "a_layout": "row", + "b_layout": "col", + "overflow": "wrapping", + "metadata": "ordered", + "selector": "immediate_zero_or_one", + "participation": "all_warp_lanes_same_instruction_and_qualifiers_no_exited_lanes", + "adapter": "c4_i32_a2_u32_b2_u32_metadata_u32_selector_u32_to_d4_i32", + "llvm_adapter": "a2_i32_b2_i32_c4_i32_metadata_i32_selector_i32_to_d4_i32", + "compatibility_source": "generated_stub", + "runtime_validation": "unexecuted" + }, + "lowering": "generated_sparse_mma", + "expected_ptx": { + "mnemonic": "mma", + "modifiers": [ + "sp::ordered_metadata", + "sync", + "aligned", + "m16n8k32", + "row", + "col", + "s32", + "u8", + "u8", + "s32" + ], + "operands": [ + { + "kind": "register_list", + "length": 4 + }, + { + "kind": "register_list", + "length": 2 + }, + { + "kind": "register_list", + "length": 2 + }, + { + "kind": "register_list", + "length": 4 + }, + { + "kind": "register" + }, + { + "kind": "immediate" + } + ] + }, + "summary": "Multiplies warp-distributed sparse unsigned A and unsigned B INT8 fragments with ordered sparsity metadata and adds a wrapping s32 accumulator." + }, + { + "id": "mma_sp_ordered_metadata_m16n8k32_s32_u8_s8", + "operation_key": "matrix.mma.sp.m16n8k32.row.col.s32.u8.s8.s32.wrapping.ordered_metadata", + "family": "sparse_mma", + "source": { + "kind": "llvm_imported", + "source_record": "int_nvvm_mma_sp_ordered_metadata_m16n8k32_row_col_u8_s8" + }, + "selections": [ + { + "source_record": "anonymous_19654", + "asm": "mma.sp::ordered_metadata.sync.aligned.m16n8k32.row.col.s32.u8.s8.s32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1}},\n\t\t{{$rb0, $rb1}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}},\n\t\t$metadata,\n\t\t$selector;", + "predicates": [ + "Subtarget->getSmVersion() >= 80", + "Subtarget->getPTXVersion() >= 85" + ] + } + ], + "rust": { + "abi_id": "i0174", + "module": "matrix", + "name": "mma_sp_ordered_metadata_m16n8k32_s32_u8_s8", + "arguments": [ + "[i32; 4]", + "[u32; 2]", + "[u32; 2]", + "u32", + "u32" + ], + "result": "[i32; 4]", + "safe": false, + "must_use": true, + "safe_allowlist_reason": null, + "canonical_path": "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0174", + "public_path": "cuda_intrinsics::matrix::mma_sp_ordered_metadata_m16n8k32_s32_u8_s8", + "compatibility_paths": [ + "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k32_s32_u8_s8" + ] + }, + "dialect": { + "op_type": "SparseMmaOp", + "op_name": "nvvm.sparse_mma", + "operands": [ + "i32", + "i32", + "i32", + "i32", + "u32", + "u32", + "u32", + "u32", + "u32", + "u32" + ], + "results": [ + "i32", + "i32", + "i32", + "i32" + ] + }, + "llvm": { + "symbol": "llvm.nvvm.mma.sp.ordered.metadata.m16n8k32.row.col.u8.s8", + "arguments": [ + "i32", + "i32", + "i32", + "i32", + "i32", + "i32", + "i32", + "i32", + "i32", + "i32" + ], + "results": [ + "i32", + "i32", + "i32", + "i32" + ], + "properties": [ + "ImmArg", + "IntrNoCallback", + "IntrNoMem", + "Range" + ], + "result_facts": { + "no_undef": false, + "range": null + } + }, + "semantics": { + "pure": false, + "memory": "none", + "convergent": true, + "execution_scope": "warp" + }, + "target": { + "minimum_ptx": "8.5", + "hardware": { + "kind": "any_of", + "alternatives": [ + { + "kind": "minimum_sm", + "sm": 80 + } + ] + }, + "ptx_result": "[i32; 4]", + "targets": "all", + "ptx_isa_version": "9.3", + "ptx_isa_section": "9.7.15.6.3 Multiply-and-Accumulate Instruction: mma.sp", + "ptx_isa_url": "https://docs.nvidia.com/cuda/parallel-thread-execution/#warp-level-matrix-instructions-mma-sp" + }, + "backend": { + "profile": "rust-llvm-23.1.0-16696adc", + "version": "LLVM version 23.1.0-rust-1.100.0-nightly", + "sha256": "2e5bc688625ca7d98bca9b5f0f0d14525d2eb59e8a9842964e480df3ffd1f921", + "status": "validated", + "target_triple": "nvptx64-nvidia-cuda", + "gpu_target": "sm_80", + "ptx_feature": "+ptx85" + }, + "backend_lowerings": [ + { + "backend": "llvm_nvptx", + "mechanism": "inline_ptx", + "evidence_profile": "rust-llvm-23.1.0-16696adc", + "target": { + "minimum_ptx": "8.5", + "hardware": { + "kind": "any_of", + "alternatives": [ + { + "kind": "minimum_sm", + "sm": 80 + } + ] + } + }, + "version": "LLVM version 23.1.0-rust-1.100.0-nightly", + "sha256": "2e5bc688625ca7d98bca9b5f0f0d14525d2eb59e8a9842964e480df3ffd1f921", + "artifact_path": null, + "build_id_prefix": null, + "status": "validated", + "stages": [ + { + "targets": [ + "sm_80", + "ptx85" + ], + "representation": "convergent ordered-metadata sparse m16n8k32 mixed-sign INT8 inline PTX with selector immediates 0 and 1", + "stage": "backend_codegen", + "mechanism": "inline_ptx", + "outcome": "succeeded", + "detail": "The selected LLVM 22 probe retained exactly two unguarded ordered-metadata instructions, one for each selector, at PTX 8.5 and sm_80.", + "artifact_kind": null, + "tool_path": null, + "tool_version": null, + "tool_sha256": null + }, + { + "targets": [ + "sm_80", + "ptx85" + ], + "representation": "exact-floor PTX for ordered-metadata sparse m16n8k32 INT8 MMA", + "stage": "ptx_assembly", + "mechanism": "inline_ptx", + "outcome": "succeeded", + "detail": "CUDA 13.3 ptxas accepted both selector forms for all eight ordered-metadata INT8 variants at PTX 8.5 and sm_80.", + "artifact_kind": null, + "tool_path": "/usr/local/cuda-13.3/bin/ptxas", + "tool_version": "CUDA 13.3 V13.3.33 build cuda_13.3.r13.3/compiler.37862127_0", + "tool_sha256": "7fdd01a4cf50e30746da98989c9272a907f491e6fd7fecfda14642e4375f88fb" + } + ] + }, + { + "backend": "lib_nvvm", + "mechanism": "inline_ptx", + "evidence_profile": "cuda-13.3-libnvvm-13.3.33", + "target": { + "minimum_ptx": "8.5", + "hardware": { + "kind": "any_of", + "alternatives": [ + { + "kind": "minimum_sm", + "sm": 80 + } + ] + } + }, + "version": "CUDA toolkit 13.3; nvcc/libNVVM release V13.3.33", + "sha256": "b6a5db233133fb0ed693f8cb8aeb1d405254ce0ab10364478985292ec98cfcf0", + "artifact_path": "/usr/local/cuda-13.3/nvvm/lib64/libnvvm.so.4.0.0", + "build_id_prefix": "2330c0", + "status": "validated", + "stages": [ + { + "targets": [ + "compute_80", + "ptx93" + ], + "representation": "convergent ordered-metadata sparse m16n8k32 mixed-sign INT8 inline PTX in the combined coverage kernel", + "stage": "backend_codegen", + "mechanism": "inline_ptx", + "outcome": "succeeded", + "detail": "The production generated_intrinsics route produced 214,910-byte compute_80 NVVM IR with SHA-256 1c3668d8f8d712f3ea880fded2e10a7e9e4f4265f24f738f104d5bde8e7aee6c and 61,044-byte LTOIR with SHA-256 901eed79871048a57271f434b99bab16cccd7169be6629d6cdb0498bb8f95ece. The ordered raw calls use one compile-time selector per variant and exercise both 0 and 1 across the family.", + "artifact_kind": null, + "tool_path": null, + "tool_version": null, + "tool_sha256": null + }, + { + "targets": [ + "sm_80", + "ptx93" + ], + "representation": "combined standard and ordered sparse m16n8k32 INT8 coverage kernel", + "stage": "device_link", + "mechanism": "inline_ptx", + "outcome": "succeeded", + "detail": "nvJitLink produced a 22,632-byte cubin with SHA-256 ae24b75fec8d2c8d668765c2513a34c6d707f3acef48d6e106cf256028d72c26; cuobjdump contained 20 IMMA.SP.16832 instructions across the standard and ordered coverage. The ordered half contains all eight raw variants plus two representative compatibility-path calls.", + "artifact_kind": "cubin", + "tool_path": "/usr/local/cuda-13.3/lib64/libnvJitLink.so.13.3.33", + "tool_version": "V13.3.33", + "tool_sha256": "3ba1e744347cd68617b862eccfd98b125482e882b7a6319f42abc9a768513db8" + } + ] + } + ], + "sparse_mma": { + "shape": "m16n8k32", + "accumulator": "s32", + "a_element": "u8", + "b_element": "s8", + "a_layout": "row", + "b_layout": "col", + "overflow": "wrapping", + "metadata": "ordered", + "selector": "immediate_zero_or_one", + "participation": "all_warp_lanes_same_instruction_and_qualifiers_no_exited_lanes", + "adapter": "c4_i32_a2_u32_b2_u32_metadata_u32_selector_u32_to_d4_i32", + "llvm_adapter": "a2_i32_b2_i32_c4_i32_metadata_i32_selector_i32_to_d4_i32", + "compatibility_source": "generated_stub", + "runtime_validation": "unexecuted" + }, + "lowering": "generated_sparse_mma", + "expected_ptx": { + "mnemonic": "mma", + "modifiers": [ + "sp::ordered_metadata", + "sync", + "aligned", + "m16n8k32", + "row", + "col", + "s32", + "u8", + "s8", + "s32" + ], + "operands": [ + { + "kind": "register_list", + "length": 4 + }, + { + "kind": "register_list", + "length": 2 + }, + { + "kind": "register_list", + "length": 2 + }, + { + "kind": "register_list", + "length": 4 + }, + { + "kind": "register" + }, + { + "kind": "immediate" + } + ] + }, + "summary": "Multiplies warp-distributed sparse unsigned A and signed B INT8 fragments with ordered sparsity metadata and adds a wrapping s32 accumulator." + }, + { + "id": "mma_sp_ordered_metadata_m16n8k32_s32_u8_s8_satfinite", + "operation_key": "matrix.mma.sp.m16n8k32.row.col.s32.u8.s8.s32.satfinite.ordered_metadata", + "family": "sparse_mma", + "source": { + "kind": "llvm_imported", + "source_record": "int_nvvm_mma_sp_ordered_metadata_m16n8k32_row_col_satfinite_u8_s8" + }, + "selections": [ + { + "source_record": "anonymous_19711", + "asm": "mma.sp::ordered_metadata.sync.aligned.m16n8k32.row.col.satfinite.s32.u8.s8.s32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1}},\n\t\t{{$rb0, $rb1}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}},\n\t\t$metadata,\n\t\t$selector;", + "predicates": [ + "Subtarget->getSmVersion() >= 80", + "Subtarget->getPTXVersion() >= 85" + ] + } + ], + "rust": { + "abi_id": "i0178", + "module": "matrix", + "name": "mma_sp_ordered_metadata_m16n8k32_s32_u8_s8_satfinite", + "arguments": [ + "[i32; 4]", + "[u32; 2]", + "[u32; 2]", + "u32", + "u32" + ], + "result": "[i32; 4]", + "safe": false, + "must_use": true, + "safe_allowlist_reason": null, + "canonical_path": "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0178", + "public_path": "cuda_intrinsics::matrix::mma_sp_ordered_metadata_m16n8k32_s32_u8_s8_satfinite", + "compatibility_paths": [ + "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k32_s32_u8_s8_satfinite" + ] + }, + "dialect": { + "op_type": "SparseMmaOp", + "op_name": "nvvm.sparse_mma", + "operands": [ + "i32", + "i32", + "i32", + "i32", + "u32", + "u32", + "u32", + "u32", + "u32", + "u32" + ], + "results": [ + "i32", + "i32", + "i32", + "i32" + ] + }, + "llvm": { + "symbol": "llvm.nvvm.mma.sp.ordered.metadata.m16n8k32.row.col.satfinite.u8.s8", + "arguments": [ + "i32", + "i32", + "i32", + "i32", + "i32", + "i32", + "i32", + "i32", + "i32", + "i32" + ], + "results": [ + "i32", + "i32", + "i32", + "i32" + ], + "properties": [ + "ImmArg", + "IntrNoCallback", + "IntrNoMem", + "Range" ], "result_facts": { "no_undef": false, @@ -191762,45 +194139,337 @@ } ] }, - "summary": "Multiplies warp-distributed sparse unsigned A and signed B INT8 fragments with ordered sparsity metadata and adds a saturating s32 accumulator." + "summary": "Multiplies warp-distributed sparse unsigned A and signed B INT8 fragments with ordered sparsity metadata and adds a saturating s32 accumulator." + }, + { + "id": "mma_sp_ordered_metadata_m16n8k32_s32_u8_satfinite", + "operation_key": "matrix.mma.sp.m16n8k32.row.col.s32.u8.u8.s32.satfinite.ordered_metadata", + "family": "sparse_mma", + "source": { + "kind": "llvm_imported", + "source_record": "int_nvvm_mma_sp_ordered_metadata_m16n8k32_row_col_satfinite_u8" + }, + "selections": [ + { + "source_record": "anonymous_19714", + "asm": "mma.sp::ordered_metadata.sync.aligned.m16n8k32.row.col.satfinite.s32.u8.u8.s32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1}},\n\t\t{{$rb0, $rb1}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}},\n\t\t$metadata,\n\t\t$selector;", + "predicates": [ + "Subtarget->getSmVersion() >= 80", + "Subtarget->getPTXVersion() >= 85" + ] + } + ], + "rust": { + "abi_id": "i0177", + "module": "matrix", + "name": "mma_sp_ordered_metadata_m16n8k32_s32_u8_satfinite", + "arguments": [ + "[i32; 4]", + "[u32; 2]", + "[u32; 2]", + "u32", + "u32" + ], + "result": "[i32; 4]", + "safe": false, + "must_use": true, + "safe_allowlist_reason": null, + "canonical_path": "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0177", + "public_path": "cuda_intrinsics::matrix::mma_sp_ordered_metadata_m16n8k32_s32_u8_satfinite", + "compatibility_paths": [ + "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k32_s32_u8_satfinite" + ] + }, + "dialect": { + "op_type": "SparseMmaOp", + "op_name": "nvvm.sparse_mma", + "operands": [ + "i32", + "i32", + "i32", + "i32", + "u32", + "u32", + "u32", + "u32", + "u32", + "u32" + ], + "results": [ + "i32", + "i32", + "i32", + "i32" + ] + }, + "llvm": { + "symbol": "llvm.nvvm.mma.sp.ordered.metadata.m16n8k32.row.col.satfinite.u8", + "arguments": [ + "i32", + "i32", + "i32", + "i32", + "i32", + "i32", + "i32", + "i32", + "i32", + "i32" + ], + "results": [ + "i32", + "i32", + "i32", + "i32" + ], + "properties": [ + "ImmArg", + "IntrNoCallback", + "IntrNoMem", + "Range" + ], + "result_facts": { + "no_undef": false, + "range": null + } + }, + "semantics": { + "pure": false, + "memory": "none", + "convergent": true, + "execution_scope": "warp" + }, + "target": { + "minimum_ptx": "8.5", + "hardware": { + "kind": "any_of", + "alternatives": [ + { + "kind": "minimum_sm", + "sm": 80 + } + ] + }, + "ptx_result": "[i32; 4]", + "targets": "all", + "ptx_isa_version": "9.3", + "ptx_isa_section": "9.7.15.6.3 Multiply-and-Accumulate Instruction: mma.sp", + "ptx_isa_url": "https://docs.nvidia.com/cuda/parallel-thread-execution/#warp-level-matrix-instructions-mma-sp" + }, + "backend": { + "profile": "rust-llvm-23.1.0-16696adc", + "version": "LLVM version 23.1.0-rust-1.100.0-nightly", + "sha256": "2e5bc688625ca7d98bca9b5f0f0d14525d2eb59e8a9842964e480df3ffd1f921", + "status": "validated", + "target_triple": "nvptx64-nvidia-cuda", + "gpu_target": "sm_80", + "ptx_feature": "+ptx85" + }, + "backend_lowerings": [ + { + "backend": "llvm_nvptx", + "mechanism": "inline_ptx", + "evidence_profile": "rust-llvm-23.1.0-16696adc", + "target": { + "minimum_ptx": "8.5", + "hardware": { + "kind": "any_of", + "alternatives": [ + { + "kind": "minimum_sm", + "sm": 80 + } + ] + } + }, + "version": "LLVM version 23.1.0-rust-1.100.0-nightly", + "sha256": "2e5bc688625ca7d98bca9b5f0f0d14525d2eb59e8a9842964e480df3ffd1f921", + "artifact_path": null, + "build_id_prefix": null, + "status": "validated", + "stages": [ + { + "targets": [ + "sm_80", + "ptx85" + ], + "representation": "convergent ordered-metadata sparse m16n8k32 unsigned saturating INT8 inline PTX with selector immediates 0 and 1", + "stage": "backend_codegen", + "mechanism": "inline_ptx", + "outcome": "succeeded", + "detail": "The selected LLVM 22 probe retained exactly two unguarded ordered-metadata instructions, one for each selector, at PTX 8.5 and sm_80.", + "artifact_kind": null, + "tool_path": null, + "tool_version": null, + "tool_sha256": null + }, + { + "targets": [ + "sm_80", + "ptx85" + ], + "representation": "exact-floor PTX for ordered-metadata sparse m16n8k32 INT8 MMA", + "stage": "ptx_assembly", + "mechanism": "inline_ptx", + "outcome": "succeeded", + "detail": "CUDA 13.3 ptxas accepted both selector forms for all eight ordered-metadata INT8 variants at PTX 8.5 and sm_80.", + "artifact_kind": null, + "tool_path": "/usr/local/cuda-13.3/bin/ptxas", + "tool_version": "CUDA 13.3 V13.3.33 build cuda_13.3.r13.3/compiler.37862127_0", + "tool_sha256": "7fdd01a4cf50e30746da98989c9272a907f491e6fd7fecfda14642e4375f88fb" + } + ] + }, + { + "backend": "lib_nvvm", + "mechanism": "inline_ptx", + "evidence_profile": "cuda-13.3-libnvvm-13.3.33", + "target": { + "minimum_ptx": "8.5", + "hardware": { + "kind": "any_of", + "alternatives": [ + { + "kind": "minimum_sm", + "sm": 80 + } + ] + } + }, + "version": "CUDA toolkit 13.3; nvcc/libNVVM release V13.3.33", + "sha256": "b6a5db233133fb0ed693f8cb8aeb1d405254ce0ab10364478985292ec98cfcf0", + "artifact_path": "/usr/local/cuda-13.3/nvvm/lib64/libnvvm.so.4.0.0", + "build_id_prefix": "2330c0", + "status": "validated", + "stages": [ + { + "targets": [ + "compute_80", + "ptx93" + ], + "representation": "convergent ordered-metadata sparse m16n8k32 unsigned saturating INT8 inline PTX in the combined coverage kernel", + "stage": "backend_codegen", + "mechanism": "inline_ptx", + "outcome": "succeeded", + "detail": "The production generated_intrinsics route produced 214,910-byte compute_80 NVVM IR with SHA-256 1c3668d8f8d712f3ea880fded2e10a7e9e4f4265f24f738f104d5bde8e7aee6c and 61,044-byte LTOIR with SHA-256 901eed79871048a57271f434b99bab16cccd7169be6629d6cdb0498bb8f95ece. The ordered raw calls use one compile-time selector per variant and exercise both 0 and 1 across the family.", + "artifact_kind": null, + "tool_path": null, + "tool_version": null, + "tool_sha256": null + }, + { + "targets": [ + "sm_80", + "ptx93" + ], + "representation": "combined standard and ordered sparse m16n8k32 INT8 coverage kernel", + "stage": "device_link", + "mechanism": "inline_ptx", + "outcome": "succeeded", + "detail": "nvJitLink produced a 22,632-byte cubin with SHA-256 ae24b75fec8d2c8d668765c2513a34c6d707f3acef48d6e106cf256028d72c26; cuobjdump contained 20 IMMA.SP.16832 instructions across the standard and ordered coverage. The ordered half contains all eight raw variants plus two representative compatibility-path calls.", + "artifact_kind": "cubin", + "tool_path": "/usr/local/cuda-13.3/lib64/libnvJitLink.so.13.3.33", + "tool_version": "V13.3.33", + "tool_sha256": "3ba1e744347cd68617b862eccfd98b125482e882b7a6319f42abc9a768513db8" + } + ] + } + ], + "sparse_mma": { + "shape": "m16n8k32", + "accumulator": "s32", + "a_element": "u8", + "b_element": "u8", + "a_layout": "row", + "b_layout": "col", + "overflow": "satfinite", + "metadata": "ordered", + "selector": "immediate_zero_or_one", + "participation": "all_warp_lanes_same_instruction_and_qualifiers_no_exited_lanes", + "adapter": "c4_i32_a2_u32_b2_u32_metadata_u32_selector_u32_to_d4_i32", + "llvm_adapter": "a2_i32_b2_i32_c4_i32_metadata_i32_selector_i32_to_d4_i32", + "compatibility_source": "generated_stub", + "runtime_validation": "unexecuted" + }, + "lowering": "generated_sparse_mma", + "expected_ptx": { + "mnemonic": "mma", + "modifiers": [ + "sp::ordered_metadata", + "sync", + "aligned", + "m16n8k32", + "row", + "col", + "satfinite", + "s32", + "u8", + "u8", + "s32" + ], + "operands": [ + { + "kind": "register_list", + "length": 4 + }, + { + "kind": "register_list", + "length": 2 + }, + { + "kind": "register_list", + "length": 2 + }, + { + "kind": "register_list", + "length": 4 + }, + { + "kind": "register" + }, + { + "kind": "immediate" + } + ] + }, + "summary": "Multiplies warp-distributed sparse unsigned A and unsigned B INT8 fragments with ordered sparsity metadata and adds a saturating s32 accumulator." }, { - "id": "mma_sp_ordered_metadata_m16n8k32_s32_u8_satfinite", - "operation_key": "matrix.mma.sp.m16n8k32.row.col.s32.u8.u8.s32.satfinite.ordered_metadata", + "id": "mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e2m1_e2m1_f16", + "operation_key": "matrix.mma.sp.m16n8k64.row.col.kind_f8f6f4.f16.e2m1.e2m1.f16.not_applicable.ordered_metadata", "family": "sparse_mma", "source": { "kind": "llvm_imported", - "source_record": "int_nvvm_mma_sp_ordered_metadata_m16n8k32_row_col_satfinite_u8" + "source_record": "int_nvvm_mma_sp_ordered_metadata_m16n8k64_row_col_kind_f8f6f4_f16_e2m1_e2m1_f16" }, "selections": [ { - "source_record": "anonymous_19714", - "asm": "mma.sp::ordered_metadata.sync.aligned.m16n8k32.row.col.satfinite.s32.u8.u8.s32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1}},\n\t\t{{$rb0, $rb1}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}},\n\t\t$metadata,\n\t\t$selector;", + "source_record": "anonymous_19936", + "asm": "mma.sp::ordered_metadata.sync.aligned.m16n8k64.row.col.kind::f8f6f4.f16.e2m1.e2m1.f16\n\t\t{{$rd0, $rd1}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1, $rb2, $rb3}},\n\t\t{{$rc0, $rc1}},\n\t\t$metadata,\n\t\t$selector;", "predicates": [ - "Subtarget->getSmVersion() >= 80", - "Subtarget->getPTXVersion() >= 85" + "Subtarget->hasMMABlockScale()" ] } ], "rust": { - "abi_id": "i0177", + "abi_id": "i0525", "module": "matrix", - "name": "mma_sp_ordered_metadata_m16n8k32_s32_u8_satfinite", + "name": "mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e2m1_e2m1_f16", "arguments": [ - "[i32; 4]", - "[u32; 2]", "[u32; 2]", + "[u32; 4]", + "[u32; 4]", "u32", "u32" ], - "result": "[i32; 4]", + "result": "[u32; 2]", "safe": false, "must_use": true, "safe_allowlist_reason": null, - "canonical_path": "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0177", - "public_path": "cuda_intrinsics::matrix::mma_sp_ordered_metadata_m16n8k32_s32_u8_satfinite", + "canonical_path": "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0525", + "public_path": "cuda_intrinsics::matrix::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e2m1_e2m1_f16", "compatibility_paths": [ - "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k32_s32_u8_satfinite" + "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e2m1_e2m1_f16" ] }, "dialect": { @@ -191809,8 +194478,10 @@ "operands": [ "i32", "i32", - "i32", - "i32", + "u32", + "u32", + "u32", + "u32", "u32", "u32", "u32", @@ -191819,14 +194490,12 @@ "u32" ], "results": [ - "i32", - "i32", "i32", "i32" ] }, "llvm": { - "symbol": "llvm.nvvm.mma.sp.ordered.metadata.m16n8k32.row.col.satfinite.u8", + "symbol": "llvm.nvvm.mma.sp.ordered.metadata.m16n8k64.row.col.kind.f8f6f4.f16.e2m1.e2m1.f16", "arguments": [ "i32", "i32", @@ -191836,20 +194505,20 @@ "i32", "i32", "i32", + "v2f16", + "v2f16", "i32", "i32" ], "results": [ - "i32", - "i32", - "i32", - "i32" + "v2f16", + "v2f16" ], "properties": [ - "ImmArg", + "ImmArg", "IntrNoCallback", "IntrNoMem", - "Range" + "Range" ], "result_facts": { "no_undef": false, @@ -191863,18 +194532,30 @@ "execution_scope": "warp" }, "target": { - "minimum_ptx": "8.5", + "minimum_ptx": "8.7", "hardware": { "kind": "any_of", "alternatives": [ { - "kind": "minimum_sm", - "sm": 80 + "kind": "exact_architecture", + "sm": 120 + }, + { + "kind": "family_target", + "sm": 120 + }, + { + "kind": "exact_architecture", + "sm": 121 + }, + { + "kind": "family_target", + "sm": 121 } ] }, - "ptx_result": "[i32; 4]", - "targets": "all", + "ptx_result": "[u32; 2]", + "targets": "sm_120a|sm_120f|sm_121a|sm_121f", "ptx_isa_version": "9.3", "ptx_isa_section": "9.7.15.6.3 Multiply-and-Accumulate Instruction: mma.sp", "ptx_isa_url": "https://docs.nvidia.com/cuda/parallel-thread-execution/#warp-level-matrix-instructions-mma-sp" @@ -191885,8 +194566,8 @@ "sha256": "2e5bc688625ca7d98bca9b5f0f0d14525d2eb59e8a9842964e480df3ffd1f921", "status": "validated", "target_triple": "nvptx64-nvidia-cuda", - "gpu_target": "sm_80", - "ptx_feature": "+ptx85" + "gpu_target": "sm_120a", + "ptx_feature": "+ptx87" }, "backend_lowerings": [ { @@ -191894,13 +194575,25 @@ "mechanism": "inline_ptx", "evidence_profile": "rust-llvm-23.1.0-16696adc", "target": { - "minimum_ptx": "8.5", + "minimum_ptx": "8.7", "hardware": { "kind": "any_of", "alternatives": [ { - "kind": "minimum_sm", - "sm": 80 + "kind": "exact_architecture", + "sm": 120 + }, + { + "kind": "family_target", + "sm": 120 + }, + { + "kind": "exact_architecture", + "sm": 121 + }, + { + "kind": "family_target", + "sm": 121 } ] } @@ -191913,14 +194606,29 @@ "stages": [ { "targets": [ - "sm_80", - "ptx85" + "sm_120a", + "ptx87" ], - "representation": "convergent ordered-metadata sparse m16n8k32 unsigned saturating INT8 inline PTX with selector immediates 0 and 1", + "representation": "typed declaration and convergence comparison", + "stage": "declaration_canonicalization", + "mechanism": "typed_nvvm", + "outcome": "succeeded", + "detail": "The 23,732-byte typed source (SHA-256 ce6f6e73ffd41f5f6c6cf658ff41ce903b7c90afaca38a6279281d2ee8ff60e0) confirmed the imported A4, B4, C2-v2f16, metadata, selector signature. All 25 declarations canonicalized to nocallback nounwind memory(none), with selector immarg range [0,1), and without convergent. Optimization retained only 25 of 50 duplicate typed calls, so this is comparison evidence and not the selected production carrier.", + "artifact_kind": null, + "tool_path": null, + "tool_version": null, + "tool_sha256": null + }, + { + "targets": [ + "sm_120a", + "ptx87" + ], + "representation": "convergent ordered kind::f8f6f4 packed-F16 inline PTX in public C, A, B, metadata, selector order", "stage": "backend_codegen", "mechanism": "inline_ptx", "outcome": "succeeded", - "detail": "The selected LLVM 22 probe retained exactly two unguarded ordered-metadata instructions, one for each selector, at PTX 8.5 and sm_80.", + "detail": "Pinned LLVM lowered the 18,084-byte all-forms source (SHA-256 cf0e3082d15b64340dab3480ede99adff7d8bada7b8cdfec2fa91e990562ca5e) to 8,991-byte PTX (SHA-256 fc0b67574e5ed2b3cab9a6cdd97d86cd0574c4704f35b0fb73ebaea5acbcb725) containing the exact 25-form matrix. The convergent inline duplicate fixture retained all 50 calls.", "artifact_kind": null, "tool_path": null, "tool_version": null, @@ -191928,15 +194636,105 @@ }, { "targets": [ - "sm_80", - "ptx85" + "sm_120a", + "ptx87" ], - "representation": "exact-floor PTX for ordered-metadata sparse m16n8k32 INT8 MMA", + "representation": "exact-floor ordered kind::f8f6f4 packed-F16 PTX", "stage": "ptx_assembly", "mechanism": "inline_ptx", "outcome": "succeeded", - "detail": "CUDA 13.3 ptxas accepted both selector forms for all eight ordered-metadata INT8 variants at PTX 8.5 and sm_80.", + "detail": "CUDA 13.3 ptxas produced a 9,728-byte cubin (SHA-256 560446ab6b41e45ca208fddc2c1439d9e851b1b67a9de920e6e81026863352b2); its 27,724-byte SASS dump (SHA-256 3c27689195cd558cd3df06db75ba6e46b1905d39e636536c0a52e01ba3323270) retains 25 unique QMMA forms. PTX 8.6, sm_120, sm_100a, selector 1, and dynamic selectors were rejected.", + "artifact_kind": "cubin", + "tool_path": "/usr/local/cuda-13.3/bin/ptxas", + "tool_version": "CUDA 13.3 V13.3.33 build cuda_13.3.r13.3/compiler.37862127_0", + "tool_sha256": "7fdd01a4cf50e30746da98989c9272a907f491e6fd7fecfda14642e4375f88fb" + }, + { + "targets": [ + "sm_120f", + "ptx88" + ], + "representation": "convergent ordered kind::f8f6f4 packed-F16 inline PTX", + "stage": "backend_codegen", + "mechanism": "inline_ptx", + "outcome": "succeeded", + "detail": "Pinned LLVM emitted 8,991-byte PTX (SHA-256 08692523a26e16fd8a05a2646f71a3ade9e95aa2c3f41028f870d7c9bcab999b) containing the exact 25-form matrix with no unresolved calls.", + "artifact_kind": null, + "tool_path": null, + "tool_version": null, + "tool_sha256": null + }, + { + "targets": [ + "sm_120f", + "ptx88" + ], + "representation": "exact-floor ordered kind::f8f6f4 packed-F16 PTX", + "stage": "ptx_assembly", + "mechanism": "inline_ptx", + "outcome": "succeeded", + "detail": "CUDA 13.3 ptxas produced a 9,728-byte cubin (SHA-256 90a0b9bf02df8ca3cb34f867b29b56a65d79a5c9033ea9dc5084ee210b5f6f1d); its 27,701-byte SASS dump (SHA-256 80831cd9a7cde8fd67343302591ea08a30327606719fb232d8e28e812d9c5e46) retains 25 unique QMMA forms.", + "artifact_kind": "cubin", + "tool_path": "/usr/local/cuda-13.3/bin/ptxas", + "tool_version": "CUDA 13.3 V13.3.33 build cuda_13.3.r13.3/compiler.37862127_0", + "tool_sha256": "7fdd01a4cf50e30746da98989c9272a907f491e6fd7fecfda14642e4375f88fb" + }, + { + "targets": [ + "sm_121a", + "ptx88" + ], + "representation": "convergent ordered kind::f8f6f4 packed-F16 inline PTX", + "stage": "backend_codegen", + "mechanism": "inline_ptx", + "outcome": "succeeded", + "detail": "Pinned LLVM emitted 8,991-byte PTX (SHA-256 afec2d0be50c3984867f5402585ba0dbd4f3fe3ac74e6527ab47628ebefd2be4) containing the exact 25-form matrix with no unresolved calls.", + "artifact_kind": null, + "tool_path": null, + "tool_version": null, + "tool_sha256": null + }, + { + "targets": [ + "sm_121a", + "ptx88" + ], + "representation": "exact-floor ordered kind::f8f6f4 packed-F16 PTX", + "stage": "ptx_assembly", + "mechanism": "inline_ptx", + "outcome": "succeeded", + "detail": "CUDA 13.3 ptxas produced a 9,728-byte cubin (SHA-256 acd74cced6969aaf6f09afb935d33978ed2753a7f1558240dc4607027b15d502); its 27,724-byte SASS dump (SHA-256 16087533ef8f20e8804dda13de37ea8fce10b505d82ca7c93c5d9d484b0b26e9) retains 25 unique QMMA forms.", + "artifact_kind": "cubin", + "tool_path": "/usr/local/cuda-13.3/bin/ptxas", + "tool_version": "CUDA 13.3 V13.3.33 build cuda_13.3.r13.3/compiler.37862127_0", + "tool_sha256": "7fdd01a4cf50e30746da98989c9272a907f491e6fd7fecfda14642e4375f88fb" + }, + { + "targets": [ + "sm_121f", + "ptx88" + ], + "representation": "convergent ordered kind::f8f6f4 packed-F16 inline PTX", + "stage": "backend_codegen", + "mechanism": "inline_ptx", + "outcome": "succeeded", + "detail": "Pinned LLVM emitted 8,991-byte PTX (SHA-256 fae27977151c805ee3bc805a88241f4d4318f0575c558106ed9ba6a0a94f0699) containing the exact 25-form matrix with no unresolved calls.", "artifact_kind": null, + "tool_path": null, + "tool_version": null, + "tool_sha256": null + }, + { + "targets": [ + "sm_121f", + "ptx88" + ], + "representation": "exact-floor ordered kind::f8f6f4 packed-F16 PTX", + "stage": "ptx_assembly", + "mechanism": "inline_ptx", + "outcome": "succeeded", + "detail": "CUDA 13.3 ptxas produced a 9,728-byte cubin (SHA-256 501b5715323e83c1543a76999f6fb747c6ce1ab0be09aeb637fb95ce69cb28da); its 27,701-byte SASS dump (SHA-256 677ac56dab06986c7ec8938dcc82e23d3637bca8f58282140d0fbce8f483d353) retains 25 unique QMMA forms.", + "artifact_kind": "cubin", "tool_path": "/usr/local/cuda-13.3/bin/ptxas", "tool_version": "CUDA 13.3 V13.3.33 build cuda_13.3.r13.3/compiler.37862127_0", "tool_sha256": "7fdd01a4cf50e30746da98989c9272a907f491e6fd7fecfda14642e4375f88fb" @@ -191948,13 +194746,25 @@ "mechanism": "inline_ptx", "evidence_profile": "cuda-13.3-libnvvm-13.3.33", "target": { - "minimum_ptx": "8.5", + "minimum_ptx": "8.7", "hardware": { "kind": "any_of", "alternatives": [ { - "kind": "minimum_sm", - "sm": 80 + "kind": "exact_architecture", + "sm": 120 + }, + { + "kind": "family_target", + "sm": 120 + }, + { + "kind": "exact_architecture", + "sm": 121 + }, + { + "kind": "family_target", + "sm": 121 } ] } @@ -191967,14 +194777,14 @@ "stages": [ { "targets": [ - "compute_80", + "compute_120a", "ptx93" ], - "representation": "convergent ordered-metadata sparse m16n8k32 unsigned saturating INT8 inline PTX in the combined coverage kernel", + "representation": "convergent ordered kind::f8f6f4 packed-F16 inline PTX in public C, A, B, metadata, selector order", "stage": "backend_codegen", "mechanism": "inline_ptx", "outcome": "succeeded", - "detail": "The production generated_intrinsics route produced 214,910-byte compute_80 NVVM IR with SHA-256 1c3668d8f8d712f3ea880fded2e10a7e9e4f4265f24f738f104d5bde8e7aee6c and 61,044-byte LTOIR with SHA-256 901eed79871048a57271f434b99bab16cccd7169be6629d6cdb0498bb8f95ece. The ordered raw calls use one compile-time selector per variant and exercise both 0 and 1 across the family.", + "detail": "CUDA 13.3 libNVVM retained the exact 25-form matrix in 8,886-byte PTX (SHA-256 fe613b565fd6028eaaff9b7df078c93af5b47163f19a9685a43bd6dee28fea6d), produced 11,504-byte LTOIR (SHA-256 aac8c70c26474ccd692e45a453d9f7236c8e040d66dd47047b582524d9deff4c), and emitted no unresolved llvm.nvvm calls or extern declarations.", "artifact_kind": null, "tool_path": null, "tool_version": null, @@ -191982,16 +194792,166 @@ }, { "targets": [ - "sm_80", + "sm_120a", "ptx93" ], - "representation": "combined standard and ordered sparse m16n8k32 INT8 coverage kernel", + "representation": "libNVVM-emitted ordered kind::f8f6f4 packed-F16 PTX", + "stage": "ptx_assembly", + "mechanism": "inline_ptx", + "outcome": "succeeded", + "detail": "CUDA 13.3 ptxas produced a 9,728-byte cubin (SHA-256 560446ab6b41e45ca208fddc2c1439d9e851b1b67a9de920e6e81026863352b2) retaining all 25 unique QMMA forms; the 27,724-byte SASS dump has SHA-256 3c27689195cd558cd3df06db75ba6e46b1905d39e636536c0a52e01ba3323270.", + "artifact_kind": "cubin", + "tool_path": "/usr/local/cuda-13.3/bin/ptxas", + "tool_version": "CUDA 13.3 V13.3.33 build cuda_13.3.r13.3/compiler.37862127_0", + "tool_sha256": "7fdd01a4cf50e30746da98989c9272a907f491e6fd7fecfda14642e4375f88fb" + }, + { + "targets": [ + "sm_120a", + "ptx93" + ], + "representation": "libNVVM LTOIR retaining the ordered kind::f8f6f4 packed-F16 matrix", "stage": "device_link", "mechanism": "inline_ptx", "outcome": "succeeded", - "detail": "nvJitLink produced a 22,632-byte cubin with SHA-256 ae24b75fec8d2c8d668765c2513a34c6d707f3acef48d6e106cf256028d72c26; cuobjdump contained 20 IMMA.SP.16832 instructions across the standard and ordered coverage. The ordered half contains all eight raw variants plus two representative compatibility-path calls.", + "detail": "CUDA 13.3 nvJitLink produced a 9,856-byte cubin (SHA-256 a7acfd0a342d4b87745305a9c0eb0b7fc1a4e6a8afffdd63bfcbc6a9188a35fb); its 27,724-byte SASS dump (SHA-256 3c27689195cd558cd3df06db75ba6e46b1905d39e636536c0a52e01ba3323270) retains 25 unique QMMA forms.", "artifact_kind": "cubin", - "tool_path": "/usr/local/cuda-13.3/lib64/libnvJitLink.so.13.3.33", + "tool_path": "/usr/local/cuda-13.3/targets/x86_64-linux/lib/libnvJitLink.so.13.3.33", + "tool_version": "V13.3.33", + "tool_sha256": "3ba1e744347cd68617b862eccfd98b125482e882b7a6319f42abc9a768513db8" + }, + { + "targets": [ + "compute_120f", + "ptx93" + ], + "representation": "convergent ordered kind::f8f6f4 packed-F16 inline PTX", + "stage": "backend_codegen", + "mechanism": "inline_ptx", + "outcome": "succeeded", + "detail": "CUDA 13.3 libNVVM retained the exact 25-form matrix in 8,886-byte PTX (SHA-256 51f4c9986dc2523a8745ee1a131c400b87b714f44c881d6d102b363529e1b429), produced 11,500-byte LTOIR (SHA-256 678e88e228100ca0802c84918f31d08c024a76e9078074fc6e8671b342d27a6e), and emitted no unresolved calls.", + "artifact_kind": null, + "tool_path": null, + "tool_version": null, + "tool_sha256": null + }, + { + "targets": [ + "sm_120f", + "ptx93" + ], + "representation": "libNVVM-emitted ordered kind::f8f6f4 packed-F16 PTX", + "stage": "ptx_assembly", + "mechanism": "inline_ptx", + "outcome": "succeeded", + "detail": "CUDA 13.3 ptxas produced a 9,728-byte cubin (SHA-256 90a0b9bf02df8ca3cb34f867b29b56a65d79a5c9033ea9dc5084ee210b5f6f1d); its 27,701-byte SASS dump (SHA-256 80831cd9a7cde8fd67343302591ea08a30327606719fb232d8e28e812d9c5e46) retains 25 unique QMMA forms.", + "artifact_kind": "cubin", + "tool_path": "/usr/local/cuda-13.3/bin/ptxas", + "tool_version": "CUDA 13.3 V13.3.33 build cuda_13.3.r13.3/compiler.37862127_0", + "tool_sha256": "7fdd01a4cf50e30746da98989c9272a907f491e6fd7fecfda14642e4375f88fb" + }, + { + "targets": [ + "sm_120f", + "ptx93" + ], + "representation": "libNVVM LTOIR retaining the ordered kind::f8f6f4 packed-F16 matrix", + "stage": "device_link", + "mechanism": "inline_ptx", + "outcome": "succeeded", + "detail": "CUDA 13.3 nvJitLink produced a 9,856-byte cubin (SHA-256 e3da7f6df18cbc6f195ebf2127f542d93d22301d33406ad9fc86209583209b1b); its terminal SASS matches the 27,701-byte ptxas result and retains 25 unique QMMA forms.", + "artifact_kind": "cubin", + "tool_path": "/usr/local/cuda-13.3/targets/x86_64-linux/lib/libnvJitLink.so.13.3.33", + "tool_version": "V13.3.33", + "tool_sha256": "3ba1e744347cd68617b862eccfd98b125482e882b7a6319f42abc9a768513db8" + }, + { + "targets": [ + "compute_121a", + "ptx93" + ], + "representation": "convergent ordered kind::f8f6f4 packed-F16 inline PTX", + "stage": "backend_codegen", + "mechanism": "inline_ptx", + "outcome": "succeeded", + "detail": "CUDA 13.3 libNVVM retained the exact 25-form matrix in 8,886-byte PTX (SHA-256 d667d6730fb487ff7b7812afbb66ca3ddc3ece9ee59230883d91a7286fb8cf35), produced 11,504-byte LTOIR (SHA-256 2c1de19d40ea54c10e3f7f9c5fdad148f8fed26db5a775c63301e695d4a486b8), and emitted no unresolved calls.", + "artifact_kind": null, + "tool_path": null, + "tool_version": null, + "tool_sha256": null + }, + { + "targets": [ + "sm_121a", + "ptx93" + ], + "representation": "libNVVM-emitted ordered kind::f8f6f4 packed-F16 PTX", + "stage": "ptx_assembly", + "mechanism": "inline_ptx", + "outcome": "succeeded", + "detail": "CUDA 13.3 ptxas produced a 9,728-byte cubin (SHA-256 acd74cced6969aaf6f09afb935d33978ed2753a7f1558240dc4607027b15d502); its 27,724-byte SASS dump (SHA-256 16087533ef8f20e8804dda13de37ea8fce10b505d82ca7c93c5d9d484b0b26e9) retains 25 unique QMMA forms.", + "artifact_kind": "cubin", + "tool_path": "/usr/local/cuda-13.3/bin/ptxas", + "tool_version": "CUDA 13.3 V13.3.33 build cuda_13.3.r13.3/compiler.37862127_0", + "tool_sha256": "7fdd01a4cf50e30746da98989c9272a907f491e6fd7fecfda14642e4375f88fb" + }, + { + "targets": [ + "sm_121a", + "ptx93" + ], + "representation": "libNVVM LTOIR retaining the ordered kind::f8f6f4 packed-F16 matrix", + "stage": "device_link", + "mechanism": "inline_ptx", + "outcome": "succeeded", + "detail": "CUDA 13.3 nvJitLink produced a 9,856-byte cubin (SHA-256 5686bd4d7d44b05d50052c4e12c6385af60430e6717e53c535acc7e5b17daac6); its terminal SASS matches the 27,724-byte ptxas result and retains 25 unique QMMA forms.", + "artifact_kind": "cubin", + "tool_path": "/usr/local/cuda-13.3/targets/x86_64-linux/lib/libnvJitLink.so.13.3.33", + "tool_version": "V13.3.33", + "tool_sha256": "3ba1e744347cd68617b862eccfd98b125482e882b7a6319f42abc9a768513db8" + }, + { + "targets": [ + "compute_121f", + "ptx93" + ], + "representation": "convergent ordered kind::f8f6f4 packed-F16 inline PTX", + "stage": "backend_codegen", + "mechanism": "inline_ptx", + "outcome": "succeeded", + "detail": "CUDA 13.3 libNVVM retained the exact 25-form matrix in 8,886-byte PTX (SHA-256 8a939f3816e414a14d24fe9e2bcb28b97f30db931b2c71c6c0e1c2c793329855), produced 11,500-byte LTOIR (SHA-256 778bc963dbd6301055eaf20892234aea60113ca053682d6c6010b1f1b915bcbe), and emitted no unresolved calls.", + "artifact_kind": null, + "tool_path": null, + "tool_version": null, + "tool_sha256": null + }, + { + "targets": [ + "sm_121f", + "ptx93" + ], + "representation": "libNVVM-emitted ordered kind::f8f6f4 packed-F16 PTX", + "stage": "ptx_assembly", + "mechanism": "inline_ptx", + "outcome": "succeeded", + "detail": "CUDA 13.3 ptxas produced a 9,728-byte cubin (SHA-256 501b5715323e83c1543a76999f6fb747c6ce1ab0be09aeb637fb95ce69cb28da); its 27,701-byte SASS dump (SHA-256 677ac56dab06986c7ec8938dcc82e23d3637bca8f58282140d0fbce8f483d353) retains 25 unique QMMA forms.", + "artifact_kind": "cubin", + "tool_path": "/usr/local/cuda-13.3/bin/ptxas", + "tool_version": "CUDA 13.3 V13.3.33 build cuda_13.3.r13.3/compiler.37862127_0", + "tool_sha256": "7fdd01a4cf50e30746da98989c9272a907f491e6fd7fecfda14642e4375f88fb" + }, + { + "targets": [ + "sm_121f", + "ptx93" + ], + "representation": "libNVVM LTOIR retaining the ordered kind::f8f6f4 packed-F16 matrix", + "stage": "device_link", + "mechanism": "inline_ptx", + "outcome": "succeeded", + "detail": "CUDA 13.3 nvJitLink produced a 9,856-byte cubin (SHA-256 7dbcfbe36d9fca5c8916689289754c0041ace50971ff0f9a337c649bc326e2f5); its terminal SASS matches the 27,701-byte ptxas result and retains 25 unique QMMA forms.", + "artifact_kind": "cubin", + "tool_path": "/usr/local/cuda-13.3/targets/x86_64-linux/lib/libnvJitLink.so.13.3.33", "tool_version": "V13.3.33", "tool_sha256": "3ba1e744347cd68617b862eccfd98b125482e882b7a6319f42abc9a768513db8" } @@ -191999,18 +194959,18 @@ } ], "sparse_mma": { - "shape": "m16n8k32", - "accumulator": "s32", - "a_element": "u8", - "b_element": "u8", + "shape": "m16n8k64", + "accumulator": "f16", + "a_element": "e2m1", + "b_element": "e2m1", "a_layout": "row", "b_layout": "col", - "overflow": "satfinite", + "overflow": "not_applicable", "metadata": "ordered", - "selector": "immediate_zero_or_one", + "selector": "immediate_zero", "participation": "all_warp_lanes_same_instruction_and_qualifiers_no_exited_lanes", - "adapter": "c4_i32_a2_u32_b2_u32_metadata_u32_selector_u32_to_d4_i32", - "llvm_adapter": "a2_i32_b2_i32_c4_i32_metadata_i32_selector_i32_to_d4_i32", + "adapter": "c2_u32_a4_u32_b4_u32_metadata_u32_selector_u32_to_d2_u32", + "llvm_adapter": "a4_i32_b4_i32_c2_v2_f16_metadata_i32_selector_i32_to_d2_v2_f16", "compatibility_source": "generated_stub", "runtime_validation": "unexecuted" }, @@ -192021,31 +194981,31 @@ "sp::ordered_metadata", "sync", "aligned", - "m16n8k32", + "m16n8k64", "row", "col", - "satfinite", - "s32", - "u8", - "u8", - "s32" + "kind::f8f6f4", + "f16", + "e2m1", + "e2m1", + "f16" ], "operands": [ { "kind": "register_list", - "length": 4 + "length": 2 }, { "kind": "register_list", - "length": 2 + "length": 4 }, { "kind": "register_list", - "length": 2 + "length": 4 }, { "kind": "register_list", - "length": 4 + "length": 2 }, { "kind": "register" @@ -192055,29 +195015,29 @@ } ] }, - "summary": "Multiplies warp-distributed sparse unsigned A and unsigned B INT8 fragments with ordered sparsity metadata and adds a saturating s32 accumulator." + "summary": "Multiplies warp-distributed sparse e2m1 A and e2m1 B fragments and adds a packed F16 accumulator." }, { - "id": "mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e2m1_e2m1_f16", - "operation_key": "matrix.mma.sp.m16n8k64.row.col.kind_f8f6f4.f16.e2m1.e2m1.f16.not_applicable.ordered_metadata", + "id": "mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e2m1_e2m3_f16", + "operation_key": "matrix.mma.sp.m16n8k64.row.col.kind_f8f6f4.f16.e2m1.e2m3.f16.not_applicable.ordered_metadata", "family": "sparse_mma", "source": { "kind": "llvm_imported", - "source_record": "int_nvvm_mma_sp_ordered_metadata_m16n8k64_row_col_kind_f8f6f4_f16_e2m1_e2m1_f16" + "source_record": "int_nvvm_mma_sp_ordered_metadata_m16n8k64_row_col_kind_f8f6f4_f16_e2m1_e2m3_f16" }, "selections": [ { - "source_record": "anonymous_19936", - "asm": "mma.sp::ordered_metadata.sync.aligned.m16n8k64.row.col.kind::f8f6f4.f16.e2m1.e2m1.f16\n\t\t{{$rd0, $rd1}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1, $rb2, $rb3}},\n\t\t{{$rc0, $rc1}},\n\t\t$metadata,\n\t\t$selector;", + "source_record": "anonymous_19928", + "asm": "mma.sp::ordered_metadata.sync.aligned.m16n8k64.row.col.kind::f8f6f4.f16.e2m1.e2m3.f16\n\t\t{{$rd0, $rd1}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1, $rb2, $rb3}},\n\t\t{{$rc0, $rc1}},\n\t\t$metadata,\n\t\t$selector;", "predicates": [ "Subtarget->hasMMABlockScale()" ] } ], "rust": { - "abi_id": "i0525", + "abi_id": "i0526", "module": "matrix", - "name": "mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e2m1_e2m1_f16", + "name": "mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e2m1_e2m3_f16", "arguments": [ "[u32; 2]", "[u32; 4]", @@ -192089,10 +195049,10 @@ "safe": false, "must_use": true, "safe_allowlist_reason": null, - "canonical_path": "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0525", - "public_path": "cuda_intrinsics::matrix::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e2m1_e2m1_f16", + "canonical_path": "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0526", + "public_path": "cuda_intrinsics::matrix::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e2m1_e2m3_f16", "compatibility_paths": [ - "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e2m1_e2m1_f16" + "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e2m1_e2m3_f16" ] }, "dialect": { @@ -192118,7 +195078,7 @@ ] }, "llvm": { - "symbol": "llvm.nvvm.mma.sp.ordered.metadata.m16n8k64.row.col.kind.f8f6f4.f16.e2m1.e2m1.f16", + "symbol": "llvm.nvvm.mma.sp.ordered.metadata.m16n8k64.row.col.kind.f8f6f4.f16.e2m1.e2m3.f16", "arguments": [ "i32", "i32", @@ -192585,7 +195545,7 @@ "shape": "m16n8k64", "accumulator": "f16", "a_element": "e2m1", - "b_element": "e2m1", + "b_element": "e2m3", "a_layout": "row", "b_layout": "col", "overflow": "not_applicable", @@ -192610,7 +195570,7 @@ "kind::f8f6f4", "f16", "e2m1", - "e2m1", + "e2m3", "f16" ], "operands": [ @@ -192638,29 +195598,29 @@ } ] }, - "summary": "Multiplies warp-distributed sparse e2m1 A and e2m1 B fragments and adds a packed F16 accumulator." + "summary": "Multiplies warp-distributed sparse e2m1 A and e2m3 B fragments and adds a packed F16 accumulator." }, { - "id": "mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e2m1_e2m3_f16", - "operation_key": "matrix.mma.sp.m16n8k64.row.col.kind_f8f6f4.f16.e2m1.e2m3.f16.not_applicable.ordered_metadata", + "id": "mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e2m1_e3m2_f16", + "operation_key": "matrix.mma.sp.m16n8k64.row.col.kind_f8f6f4.f16.e2m1.e3m2.f16.not_applicable.ordered_metadata", "family": "sparse_mma", "source": { "kind": "llvm_imported", - "source_record": "int_nvvm_mma_sp_ordered_metadata_m16n8k64_row_col_kind_f8f6f4_f16_e2m1_e2m3_f16" + "source_record": "int_nvvm_mma_sp_ordered_metadata_m16n8k64_row_col_kind_f8f6f4_f16_e2m1_e3m2_f16" }, "selections": [ { - "source_record": "anonymous_19928", - "asm": "mma.sp::ordered_metadata.sync.aligned.m16n8k64.row.col.kind::f8f6f4.f16.e2m1.e2m3.f16\n\t\t{{$rd0, $rd1}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1, $rb2, $rb3}},\n\t\t{{$rc0, $rc1}},\n\t\t$metadata,\n\t\t$selector;", + "source_record": "anonymous_19920", + "asm": "mma.sp::ordered_metadata.sync.aligned.m16n8k64.row.col.kind::f8f6f4.f16.e2m1.e3m2.f16\n\t\t{{$rd0, $rd1}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1, $rb2, $rb3}},\n\t\t{{$rc0, $rc1}},\n\t\t$metadata,\n\t\t$selector;", "predicates": [ "Subtarget->hasMMABlockScale()" ] } ], "rust": { - "abi_id": "i0526", + "abi_id": "i0527", "module": "matrix", - "name": "mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e2m1_e2m3_f16", + "name": "mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e2m1_e3m2_f16", "arguments": [ "[u32; 2]", "[u32; 4]", @@ -192672,10 +195632,10 @@ "safe": false, "must_use": true, "safe_allowlist_reason": null, - "canonical_path": "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0526", - "public_path": "cuda_intrinsics::matrix::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e2m1_e2m3_f16", + "canonical_path": "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0527", + "public_path": "cuda_intrinsics::matrix::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e2m1_e3m2_f16", "compatibility_paths": [ - "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e2m1_e2m3_f16" + "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e2m1_e3m2_f16" ] }, "dialect": { @@ -192701,7 +195661,7 @@ ] }, "llvm": { - "symbol": "llvm.nvvm.mma.sp.ordered.metadata.m16n8k64.row.col.kind.f8f6f4.f16.e2m1.e2m3.f16", + "symbol": "llvm.nvvm.mma.sp.ordered.metadata.m16n8k64.row.col.kind.f8f6f4.f16.e2m1.e3m2.f16", "arguments": [ "i32", "i32", @@ -193168,7 +196128,7 @@ "shape": "m16n8k64", "accumulator": "f16", "a_element": "e2m1", - "b_element": "e2m3", + "b_element": "e3m2", "a_layout": "row", "b_layout": "col", "overflow": "not_applicable", @@ -193193,7 +196153,7 @@ "kind::f8f6f4", "f16", "e2m1", - "e2m3", + "e3m2", "f16" ], "operands": [ @@ -193221,29 +196181,29 @@ } ] }, - "summary": "Multiplies warp-distributed sparse e2m1 A and e2m3 B fragments and adds a packed F16 accumulator." + "summary": "Multiplies warp-distributed sparse e2m1 A and e3m2 B fragments and adds a packed F16 accumulator." }, { - "id": "mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e2m1_e3m2_f16", - "operation_key": "matrix.mma.sp.m16n8k64.row.col.kind_f8f6f4.f16.e2m1.e3m2.f16.not_applicable.ordered_metadata", + "id": "mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e2m1_e4m3_f16", + "operation_key": "matrix.mma.sp.m16n8k64.row.col.kind_f8f6f4.f16.e2m1.e4m3.f16.not_applicable.ordered_metadata", "family": "sparse_mma", "source": { "kind": "llvm_imported", - "source_record": "int_nvvm_mma_sp_ordered_metadata_m16n8k64_row_col_kind_f8f6f4_f16_e2m1_e3m2_f16" + "source_record": "int_nvvm_mma_sp_ordered_metadata_m16n8k64_row_col_kind_f8f6f4_f16_e2m1_e4m3_f16" }, "selections": [ { - "source_record": "anonymous_19920", - "asm": "mma.sp::ordered_metadata.sync.aligned.m16n8k64.row.col.kind::f8f6f4.f16.e2m1.e3m2.f16\n\t\t{{$rd0, $rd1}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1, $rb2, $rb3}},\n\t\t{{$rc0, $rc1}},\n\t\t$metadata,\n\t\t$selector;", + "source_record": "anonymous_19904", + "asm": "mma.sp::ordered_metadata.sync.aligned.m16n8k64.row.col.kind::f8f6f4.f16.e2m1.e4m3.f16\n\t\t{{$rd0, $rd1}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1, $rb2, $rb3}},\n\t\t{{$rc0, $rc1}},\n\t\t$metadata,\n\t\t$selector;", "predicates": [ "Subtarget->hasMMABlockScale()" ] } ], "rust": { - "abi_id": "i0527", + "abi_id": "i0528", "module": "matrix", - "name": "mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e2m1_e3m2_f16", + "name": "mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e2m1_e4m3_f16", "arguments": [ "[u32; 2]", "[u32; 4]", @@ -193255,10 +196215,10 @@ "safe": false, "must_use": true, "safe_allowlist_reason": null, - "canonical_path": "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0527", - "public_path": "cuda_intrinsics::matrix::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e2m1_e3m2_f16", + "canonical_path": "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0528", + "public_path": "cuda_intrinsics::matrix::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e2m1_e4m3_f16", "compatibility_paths": [ - "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e2m1_e3m2_f16" + "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e2m1_e4m3_f16" ] }, "dialect": { @@ -193284,7 +196244,7 @@ ] }, "llvm": { - "symbol": "llvm.nvvm.mma.sp.ordered.metadata.m16n8k64.row.col.kind.f8f6f4.f16.e2m1.e3m2.f16", + "symbol": "llvm.nvvm.mma.sp.ordered.metadata.m16n8k64.row.col.kind.f8f6f4.f16.e2m1.e4m3.f16", "arguments": [ "i32", "i32", @@ -193751,7 +196711,7 @@ "shape": "m16n8k64", "accumulator": "f16", "a_element": "e2m1", - "b_element": "e3m2", + "b_element": "e4m3", "a_layout": "row", "b_layout": "col", "overflow": "not_applicable", @@ -193776,7 +196736,7 @@ "kind::f8f6f4", "f16", "e2m1", - "e3m2", + "e4m3", "f16" ], "operands": [ @@ -193804,29 +196764,29 @@ } ] }, - "summary": "Multiplies warp-distributed sparse e2m1 A and e3m2 B fragments and adds a packed F16 accumulator." + "summary": "Multiplies warp-distributed sparse e2m1 A and e4m3 B fragments and adds a packed F16 accumulator." }, { - "id": "mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e2m1_e4m3_f16", - "operation_key": "matrix.mma.sp.m16n8k64.row.col.kind_f8f6f4.f16.e2m1.e4m3.f16.not_applicable.ordered_metadata", + "id": "mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e2m1_e5m2_f16", + "operation_key": "matrix.mma.sp.m16n8k64.row.col.kind_f8f6f4.f16.e2m1.e5m2.f16.not_applicable.ordered_metadata", "family": "sparse_mma", "source": { "kind": "llvm_imported", - "source_record": "int_nvvm_mma_sp_ordered_metadata_m16n8k64_row_col_kind_f8f6f4_f16_e2m1_e4m3_f16" + "source_record": "int_nvvm_mma_sp_ordered_metadata_m16n8k64_row_col_kind_f8f6f4_f16_e2m1_e5m2_f16" }, "selections": [ { - "source_record": "anonymous_19904", - "asm": "mma.sp::ordered_metadata.sync.aligned.m16n8k64.row.col.kind::f8f6f4.f16.e2m1.e4m3.f16\n\t\t{{$rd0, $rd1}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1, $rb2, $rb3}},\n\t\t{{$rc0, $rc1}},\n\t\t$metadata,\n\t\t$selector;", + "source_record": "anonymous_19912", + "asm": "mma.sp::ordered_metadata.sync.aligned.m16n8k64.row.col.kind::f8f6f4.f16.e2m1.e5m2.f16\n\t\t{{$rd0, $rd1}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1, $rb2, $rb3}},\n\t\t{{$rc0, $rc1}},\n\t\t$metadata,\n\t\t$selector;", "predicates": [ "Subtarget->hasMMABlockScale()" ] } ], "rust": { - "abi_id": "i0528", + "abi_id": "i0529", "module": "matrix", - "name": "mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e2m1_e4m3_f16", + "name": "mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e2m1_e5m2_f16", "arguments": [ "[u32; 2]", "[u32; 4]", @@ -193838,10 +196798,10 @@ "safe": false, "must_use": true, "safe_allowlist_reason": null, - "canonical_path": "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0528", - "public_path": "cuda_intrinsics::matrix::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e2m1_e4m3_f16", + "canonical_path": "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0529", + "public_path": "cuda_intrinsics::matrix::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e2m1_e5m2_f16", "compatibility_paths": [ - "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e2m1_e4m3_f16" + "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e2m1_e5m2_f16" ] }, "dialect": { @@ -193867,7 +196827,7 @@ ] }, "llvm": { - "symbol": "llvm.nvvm.mma.sp.ordered.metadata.m16n8k64.row.col.kind.f8f6f4.f16.e2m1.e4m3.f16", + "symbol": "llvm.nvvm.mma.sp.ordered.metadata.m16n8k64.row.col.kind.f8f6f4.f16.e2m1.e5m2.f16", "arguments": [ "i32", "i32", @@ -194334,7 +197294,7 @@ "shape": "m16n8k64", "accumulator": "f16", "a_element": "e2m1", - "b_element": "e4m3", + "b_element": "e5m2", "a_layout": "row", "b_layout": "col", "overflow": "not_applicable", @@ -194359,7 +197319,7 @@ "kind::f8f6f4", "f16", "e2m1", - "e4m3", + "e5m2", "f16" ], "operands": [ @@ -194387,29 +197347,29 @@ } ] }, - "summary": "Multiplies warp-distributed sparse e2m1 A and e4m3 B fragments and adds a packed F16 accumulator." + "summary": "Multiplies warp-distributed sparse e2m1 A and e5m2 B fragments and adds a packed F16 accumulator." }, { - "id": "mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e2m1_e5m2_f16", - "operation_key": "matrix.mma.sp.m16n8k64.row.col.kind_f8f6f4.f16.e2m1.e5m2.f16.not_applicable.ordered_metadata", + "id": "mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e2m3_e2m1_f16", + "operation_key": "matrix.mma.sp.m16n8k64.row.col.kind_f8f6f4.f16.e2m3.e2m1.f16.not_applicable.ordered_metadata", "family": "sparse_mma", "source": { "kind": "llvm_imported", - "source_record": "int_nvvm_mma_sp_ordered_metadata_m16n8k64_row_col_kind_f8f6f4_f16_e2m1_e5m2_f16" + "source_record": "int_nvvm_mma_sp_ordered_metadata_m16n8k64_row_col_kind_f8f6f4_f16_e2m3_e2m1_f16" }, "selections": [ { - "source_record": "anonymous_19912", - "asm": "mma.sp::ordered_metadata.sync.aligned.m16n8k64.row.col.kind::f8f6f4.f16.e2m1.e5m2.f16\n\t\t{{$rd0, $rd1}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1, $rb2, $rb3}},\n\t\t{{$rc0, $rc1}},\n\t\t$metadata,\n\t\t$selector;", + "source_record": "anonymous_19895", + "asm": "mma.sp::ordered_metadata.sync.aligned.m16n8k64.row.col.kind::f8f6f4.f16.e2m3.e2m1.f16\n\t\t{{$rd0, $rd1}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1, $rb2, $rb3}},\n\t\t{{$rc0, $rc1}},\n\t\t$metadata,\n\t\t$selector;", "predicates": [ "Subtarget->hasMMABlockScale()" ] } ], "rust": { - "abi_id": "i0529", + "abi_id": "i0530", "module": "matrix", - "name": "mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e2m1_e5m2_f16", + "name": "mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e2m3_e2m1_f16", "arguments": [ "[u32; 2]", "[u32; 4]", @@ -194421,10 +197381,10 @@ "safe": false, "must_use": true, "safe_allowlist_reason": null, - "canonical_path": "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0529", - "public_path": "cuda_intrinsics::matrix::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e2m1_e5m2_f16", + "canonical_path": "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0530", + "public_path": "cuda_intrinsics::matrix::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e2m3_e2m1_f16", "compatibility_paths": [ - "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e2m1_e5m2_f16" + "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e2m3_e2m1_f16" ] }, "dialect": { @@ -194450,7 +197410,7 @@ ] }, "llvm": { - "symbol": "llvm.nvvm.mma.sp.ordered.metadata.m16n8k64.row.col.kind.f8f6f4.f16.e2m1.e5m2.f16", + "symbol": "llvm.nvvm.mma.sp.ordered.metadata.m16n8k64.row.col.kind.f8f6f4.f16.e2m3.e2m1.f16", "arguments": [ "i32", "i32", @@ -194916,8 +197876,8 @@ "sparse_mma": { "shape": "m16n8k64", "accumulator": "f16", - "a_element": "e2m1", - "b_element": "e5m2", + "a_element": "e2m3", + "b_element": "e2m1", "a_layout": "row", "b_layout": "col", "overflow": "not_applicable", @@ -194941,8 +197901,8 @@ "col", "kind::f8f6f4", "f16", + "e2m3", "e2m1", - "e5m2", "f16" ], "operands": [ @@ -194970,29 +197930,29 @@ } ] }, - "summary": "Multiplies warp-distributed sparse e2m1 A and e5m2 B fragments and adds a packed F16 accumulator." + "summary": "Multiplies warp-distributed sparse e2m3 A and e2m1 B fragments and adds a packed F16 accumulator." }, { - "id": "mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e2m3_e2m1_f16", - "operation_key": "matrix.mma.sp.m16n8k64.row.col.kind_f8f6f4.f16.e2m3.e2m1.f16.not_applicable.ordered_metadata", + "id": "mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e2m3_e2m3_f16", + "operation_key": "matrix.mma.sp.m16n8k64.row.col.kind_f8f6f4.f16.e2m3.e2m3.f16.not_applicable.ordered_metadata", "family": "sparse_mma", "source": { "kind": "llvm_imported", - "source_record": "int_nvvm_mma_sp_ordered_metadata_m16n8k64_row_col_kind_f8f6f4_f16_e2m3_e2m1_f16" + "source_record": "int_nvvm_mma_sp_ordered_metadata_m16n8k64_row_col_kind_f8f6f4_f16_e2m3_e2m3_f16" }, "selections": [ { - "source_record": "anonymous_19895", - "asm": "mma.sp::ordered_metadata.sync.aligned.m16n8k64.row.col.kind::f8f6f4.f16.e2m3.e2m1.f16\n\t\t{{$rd0, $rd1}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1, $rb2, $rb3}},\n\t\t{{$rc0, $rc1}},\n\t\t$metadata,\n\t\t$selector;", + "source_record": "anonymous_19887", + "asm": "mma.sp::ordered_metadata.sync.aligned.m16n8k64.row.col.kind::f8f6f4.f16.e2m3.e2m3.f16\n\t\t{{$rd0, $rd1}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1, $rb2, $rb3}},\n\t\t{{$rc0, $rc1}},\n\t\t$metadata,\n\t\t$selector;", "predicates": [ "Subtarget->hasMMABlockScale()" ] } ], "rust": { - "abi_id": "i0530", + "abi_id": "i0531", "module": "matrix", - "name": "mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e2m3_e2m1_f16", + "name": "mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e2m3_e2m3_f16", "arguments": [ "[u32; 2]", "[u32; 4]", @@ -195004,10 +197964,10 @@ "safe": false, "must_use": true, "safe_allowlist_reason": null, - "canonical_path": "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0530", - "public_path": "cuda_intrinsics::matrix::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e2m3_e2m1_f16", + "canonical_path": "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0531", + "public_path": "cuda_intrinsics::matrix::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e2m3_e2m3_f16", "compatibility_paths": [ - "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e2m3_e2m1_f16" + "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e2m3_e2m3_f16" ] }, "dialect": { @@ -195033,7 +197993,7 @@ ] }, "llvm": { - "symbol": "llvm.nvvm.mma.sp.ordered.metadata.m16n8k64.row.col.kind.f8f6f4.f16.e2m3.e2m1.f16", + "symbol": "llvm.nvvm.mma.sp.ordered.metadata.m16n8k64.row.col.kind.f8f6f4.f16.e2m3.e2m3.f16", "arguments": [ "i32", "i32", @@ -195500,7 +198460,7 @@ "shape": "m16n8k64", "accumulator": "f16", "a_element": "e2m3", - "b_element": "e2m1", + "b_element": "e2m3", "a_layout": "row", "b_layout": "col", "overflow": "not_applicable", @@ -195525,7 +198485,7 @@ "kind::f8f6f4", "f16", "e2m3", - "e2m1", + "e2m3", "f16" ], "operands": [ @@ -195553,29 +198513,29 @@ } ] }, - "summary": "Multiplies warp-distributed sparse e2m3 A and e2m1 B fragments and adds a packed F16 accumulator." + "summary": "Multiplies warp-distributed sparse e2m3 A and e2m3 B fragments and adds a packed F16 accumulator." }, { - "id": "mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e2m3_e2m3_f16", - "operation_key": "matrix.mma.sp.m16n8k64.row.col.kind_f8f6f4.f16.e2m3.e2m3.f16.not_applicable.ordered_metadata", + "id": "mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e2m3_e3m2_f16", + "operation_key": "matrix.mma.sp.m16n8k64.row.col.kind_f8f6f4.f16.e2m3.e3m2.f16.not_applicable.ordered_metadata", "family": "sparse_mma", "source": { "kind": "llvm_imported", - "source_record": "int_nvvm_mma_sp_ordered_metadata_m16n8k64_row_col_kind_f8f6f4_f16_e2m3_e2m3_f16" + "source_record": "int_nvvm_mma_sp_ordered_metadata_m16n8k64_row_col_kind_f8f6f4_f16_e2m3_e3m2_f16" }, "selections": [ { - "source_record": "anonymous_19887", - "asm": "mma.sp::ordered_metadata.sync.aligned.m16n8k64.row.col.kind::f8f6f4.f16.e2m3.e2m3.f16\n\t\t{{$rd0, $rd1}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1, $rb2, $rb3}},\n\t\t{{$rc0, $rc1}},\n\t\t$metadata,\n\t\t$selector;", + "source_record": "anonymous_19879", + "asm": "mma.sp::ordered_metadata.sync.aligned.m16n8k64.row.col.kind::f8f6f4.f16.e2m3.e3m2.f16\n\t\t{{$rd0, $rd1}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1, $rb2, $rb3}},\n\t\t{{$rc0, $rc1}},\n\t\t$metadata,\n\t\t$selector;", "predicates": [ "Subtarget->hasMMABlockScale()" ] } ], "rust": { - "abi_id": "i0531", + "abi_id": "i0532", "module": "matrix", - "name": "mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e2m3_e2m3_f16", + "name": "mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e2m3_e3m2_f16", "arguments": [ "[u32; 2]", "[u32; 4]", @@ -195587,10 +198547,10 @@ "safe": false, "must_use": true, "safe_allowlist_reason": null, - "canonical_path": "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0531", - "public_path": "cuda_intrinsics::matrix::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e2m3_e2m3_f16", + "canonical_path": "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0532", + "public_path": "cuda_intrinsics::matrix::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e2m3_e3m2_f16", "compatibility_paths": [ - "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e2m3_e2m3_f16" + "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e2m3_e3m2_f16" ] }, "dialect": { @@ -195616,7 +198576,7 @@ ] }, "llvm": { - "symbol": "llvm.nvvm.mma.sp.ordered.metadata.m16n8k64.row.col.kind.f8f6f4.f16.e2m3.e2m3.f16", + "symbol": "llvm.nvvm.mma.sp.ordered.metadata.m16n8k64.row.col.kind.f8f6f4.f16.e2m3.e3m2.f16", "arguments": [ "i32", "i32", @@ -196083,7 +199043,7 @@ "shape": "m16n8k64", "accumulator": "f16", "a_element": "e2m3", - "b_element": "e2m3", + "b_element": "e3m2", "a_layout": "row", "b_layout": "col", "overflow": "not_applicable", @@ -196108,7 +199068,7 @@ "kind::f8f6f4", "f16", "e2m3", - "e2m3", + "e3m2", "f16" ], "operands": [ @@ -196136,29 +199096,29 @@ } ] }, - "summary": "Multiplies warp-distributed sparse e2m3 A and e2m3 B fragments and adds a packed F16 accumulator." + "summary": "Multiplies warp-distributed sparse e2m3 A and e3m2 B fragments and adds a packed F16 accumulator." }, { - "id": "mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e2m3_e3m2_f16", - "operation_key": "matrix.mma.sp.m16n8k64.row.col.kind_f8f6f4.f16.e2m3.e3m2.f16.not_applicable.ordered_metadata", + "id": "mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e2m3_e4m3_f16", + "operation_key": "matrix.mma.sp.m16n8k64.row.col.kind_f8f6f4.f16.e2m3.e4m3.f16.not_applicable.ordered_metadata", "family": "sparse_mma", "source": { "kind": "llvm_imported", - "source_record": "int_nvvm_mma_sp_ordered_metadata_m16n8k64_row_col_kind_f8f6f4_f16_e2m3_e3m2_f16" + "source_record": "int_nvvm_mma_sp_ordered_metadata_m16n8k64_row_col_kind_f8f6f4_f16_e2m3_e4m3_f16" }, "selections": [ { - "source_record": "anonymous_19879", - "asm": "mma.sp::ordered_metadata.sync.aligned.m16n8k64.row.col.kind::f8f6f4.f16.e2m3.e3m2.f16\n\t\t{{$rd0, $rd1}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1, $rb2, $rb3}},\n\t\t{{$rc0, $rc1}},\n\t\t$metadata,\n\t\t$selector;", + "source_record": "anonymous_19863", + "asm": "mma.sp::ordered_metadata.sync.aligned.m16n8k64.row.col.kind::f8f6f4.f16.e2m3.e4m3.f16\n\t\t{{$rd0, $rd1}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1, $rb2, $rb3}},\n\t\t{{$rc0, $rc1}},\n\t\t$metadata,\n\t\t$selector;", "predicates": [ "Subtarget->hasMMABlockScale()" ] } ], "rust": { - "abi_id": "i0532", + "abi_id": "i0533", "module": "matrix", - "name": "mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e2m3_e3m2_f16", + "name": "mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e2m3_e4m3_f16", "arguments": [ "[u32; 2]", "[u32; 4]", @@ -196170,10 +199130,10 @@ "safe": false, "must_use": true, "safe_allowlist_reason": null, - "canonical_path": "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0532", - "public_path": "cuda_intrinsics::matrix::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e2m3_e3m2_f16", + "canonical_path": "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0533", + "public_path": "cuda_intrinsics::matrix::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e2m3_e4m3_f16", "compatibility_paths": [ - "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e2m3_e3m2_f16" + "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e2m3_e4m3_f16" ] }, "dialect": { @@ -196199,7 +199159,7 @@ ] }, "llvm": { - "symbol": "llvm.nvvm.mma.sp.ordered.metadata.m16n8k64.row.col.kind.f8f6f4.f16.e2m3.e3m2.f16", + "symbol": "llvm.nvvm.mma.sp.ordered.metadata.m16n8k64.row.col.kind.f8f6f4.f16.e2m3.e4m3.f16", "arguments": [ "i32", "i32", @@ -196666,7 +199626,7 @@ "shape": "m16n8k64", "accumulator": "f16", "a_element": "e2m3", - "b_element": "e3m2", + "b_element": "e4m3", "a_layout": "row", "b_layout": "col", "overflow": "not_applicable", @@ -196691,7 +199651,7 @@ "kind::f8f6f4", "f16", "e2m3", - "e3m2", + "e4m3", "f16" ], "operands": [ @@ -196719,29 +199679,29 @@ } ] }, - "summary": "Multiplies warp-distributed sparse e2m3 A and e3m2 B fragments and adds a packed F16 accumulator." + "summary": "Multiplies warp-distributed sparse e2m3 A and e4m3 B fragments and adds a packed F16 accumulator." }, { - "id": "mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e2m3_e4m3_f16", - "operation_key": "matrix.mma.sp.m16n8k64.row.col.kind_f8f6f4.f16.e2m3.e4m3.f16.not_applicable.ordered_metadata", + "id": "mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e2m3_e5m2_f16", + "operation_key": "matrix.mma.sp.m16n8k64.row.col.kind_f8f6f4.f16.e2m3.e5m2.f16.not_applicable.ordered_metadata", "family": "sparse_mma", "source": { "kind": "llvm_imported", - "source_record": "int_nvvm_mma_sp_ordered_metadata_m16n8k64_row_col_kind_f8f6f4_f16_e2m3_e4m3_f16" + "source_record": "int_nvvm_mma_sp_ordered_metadata_m16n8k64_row_col_kind_f8f6f4_f16_e2m3_e5m2_f16" }, "selections": [ { - "source_record": "anonymous_19863", - "asm": "mma.sp::ordered_metadata.sync.aligned.m16n8k64.row.col.kind::f8f6f4.f16.e2m3.e4m3.f16\n\t\t{{$rd0, $rd1}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1, $rb2, $rb3}},\n\t\t{{$rc0, $rc1}},\n\t\t$metadata,\n\t\t$selector;", + "source_record": "anonymous_19871", + "asm": "mma.sp::ordered_metadata.sync.aligned.m16n8k64.row.col.kind::f8f6f4.f16.e2m3.e5m2.f16\n\t\t{{$rd0, $rd1}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1, $rb2, $rb3}},\n\t\t{{$rc0, $rc1}},\n\t\t$metadata,\n\t\t$selector;", "predicates": [ "Subtarget->hasMMABlockScale()" ] } ], "rust": { - "abi_id": "i0533", + "abi_id": "i0534", "module": "matrix", - "name": "mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e2m3_e4m3_f16", + "name": "mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e2m3_e5m2_f16", "arguments": [ "[u32; 2]", "[u32; 4]", @@ -196753,10 +199713,10 @@ "safe": false, "must_use": true, "safe_allowlist_reason": null, - "canonical_path": "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0533", - "public_path": "cuda_intrinsics::matrix::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e2m3_e4m3_f16", + "canonical_path": "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0534", + "public_path": "cuda_intrinsics::matrix::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e2m3_e5m2_f16", "compatibility_paths": [ - "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e2m3_e4m3_f16" + "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e2m3_e5m2_f16" ] }, "dialect": { @@ -196782,7 +199742,7 @@ ] }, "llvm": { - "symbol": "llvm.nvvm.mma.sp.ordered.metadata.m16n8k64.row.col.kind.f8f6f4.f16.e2m3.e4m3.f16", + "symbol": "llvm.nvvm.mma.sp.ordered.metadata.m16n8k64.row.col.kind.f8f6f4.f16.e2m3.e5m2.f16", "arguments": [ "i32", "i32", @@ -197249,7 +200209,7 @@ "shape": "m16n8k64", "accumulator": "f16", "a_element": "e2m3", - "b_element": "e4m3", + "b_element": "e5m2", "a_layout": "row", "b_layout": "col", "overflow": "not_applicable", @@ -197274,7 +200234,7 @@ "kind::f8f6f4", "f16", "e2m3", - "e4m3", + "e5m2", "f16" ], "operands": [ @@ -197302,29 +200262,29 @@ } ] }, - "summary": "Multiplies warp-distributed sparse e2m3 A and e4m3 B fragments and adds a packed F16 accumulator." + "summary": "Multiplies warp-distributed sparse e2m3 A and e5m2 B fragments and adds a packed F16 accumulator." }, { - "id": "mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e2m3_e5m2_f16", - "operation_key": "matrix.mma.sp.m16n8k64.row.col.kind_f8f6f4.f16.e2m3.e5m2.f16.not_applicable.ordered_metadata", + "id": "mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e3m2_e2m1_f16", + "operation_key": "matrix.mma.sp.m16n8k64.row.col.kind_f8f6f4.f16.e3m2.e2m1.f16.not_applicable.ordered_metadata", "family": "sparse_mma", "source": { "kind": "llvm_imported", - "source_record": "int_nvvm_mma_sp_ordered_metadata_m16n8k64_row_col_kind_f8f6f4_f16_e2m3_e5m2_f16" + "source_record": "int_nvvm_mma_sp_ordered_metadata_m16n8k64_row_col_kind_f8f6f4_f16_e3m2_e2m1_f16" }, "selections": [ { - "source_record": "anonymous_19871", - "asm": "mma.sp::ordered_metadata.sync.aligned.m16n8k64.row.col.kind::f8f6f4.f16.e2m3.e5m2.f16\n\t\t{{$rd0, $rd1}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1, $rb2, $rb3}},\n\t\t{{$rc0, $rc1}},\n\t\t$metadata,\n\t\t$selector;", + "source_record": "anonymous_19854", + "asm": "mma.sp::ordered_metadata.sync.aligned.m16n8k64.row.col.kind::f8f6f4.f16.e3m2.e2m1.f16\n\t\t{{$rd0, $rd1}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1, $rb2, $rb3}},\n\t\t{{$rc0, $rc1}},\n\t\t$metadata,\n\t\t$selector;", "predicates": [ "Subtarget->hasMMABlockScale()" ] } ], "rust": { - "abi_id": "i0534", + "abi_id": "i0535", "module": "matrix", - "name": "mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e2m3_e5m2_f16", + "name": "mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e3m2_e2m1_f16", "arguments": [ "[u32; 2]", "[u32; 4]", @@ -197336,10 +200296,10 @@ "safe": false, "must_use": true, "safe_allowlist_reason": null, - "canonical_path": "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0534", - "public_path": "cuda_intrinsics::matrix::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e2m3_e5m2_f16", + "canonical_path": "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0535", + "public_path": "cuda_intrinsics::matrix::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e3m2_e2m1_f16", "compatibility_paths": [ - "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e2m3_e5m2_f16" + "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e3m2_e2m1_f16" ] }, "dialect": { @@ -197365,7 +200325,7 @@ ] }, "llvm": { - "symbol": "llvm.nvvm.mma.sp.ordered.metadata.m16n8k64.row.col.kind.f8f6f4.f16.e2m3.e5m2.f16", + "symbol": "llvm.nvvm.mma.sp.ordered.metadata.m16n8k64.row.col.kind.f8f6f4.f16.e3m2.e2m1.f16", "arguments": [ "i32", "i32", @@ -197831,8 +200791,8 @@ "sparse_mma": { "shape": "m16n8k64", "accumulator": "f16", - "a_element": "e2m3", - "b_element": "e5m2", + "a_element": "e3m2", + "b_element": "e2m1", "a_layout": "row", "b_layout": "col", "overflow": "not_applicable", @@ -197856,8 +200816,8 @@ "col", "kind::f8f6f4", "f16", - "e2m3", - "e5m2", + "e3m2", + "e2m1", "f16" ], "operands": [ @@ -197885,29 +200845,29 @@ } ] }, - "summary": "Multiplies warp-distributed sparse e2m3 A and e5m2 B fragments and adds a packed F16 accumulator." + "summary": "Multiplies warp-distributed sparse e3m2 A and e2m1 B fragments and adds a packed F16 accumulator." }, { - "id": "mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e3m2_e2m1_f16", - "operation_key": "matrix.mma.sp.m16n8k64.row.col.kind_f8f6f4.f16.e3m2.e2m1.f16.not_applicable.ordered_metadata", + "id": "mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e3m2_e2m3_f16", + "operation_key": "matrix.mma.sp.m16n8k64.row.col.kind_f8f6f4.f16.e3m2.e2m3.f16.not_applicable.ordered_metadata", "family": "sparse_mma", "source": { "kind": "llvm_imported", - "source_record": "int_nvvm_mma_sp_ordered_metadata_m16n8k64_row_col_kind_f8f6f4_f16_e3m2_e2m1_f16" + "source_record": "int_nvvm_mma_sp_ordered_metadata_m16n8k64_row_col_kind_f8f6f4_f16_e3m2_e2m3_f16" }, "selections": [ { - "source_record": "anonymous_19854", - "asm": "mma.sp::ordered_metadata.sync.aligned.m16n8k64.row.col.kind::f8f6f4.f16.e3m2.e2m1.f16\n\t\t{{$rd0, $rd1}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1, $rb2, $rb3}},\n\t\t{{$rc0, $rc1}},\n\t\t$metadata,\n\t\t$selector;", + "source_record": "anonymous_19846", + "asm": "mma.sp::ordered_metadata.sync.aligned.m16n8k64.row.col.kind::f8f6f4.f16.e3m2.e2m3.f16\n\t\t{{$rd0, $rd1}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1, $rb2, $rb3}},\n\t\t{{$rc0, $rc1}},\n\t\t$metadata,\n\t\t$selector;", "predicates": [ "Subtarget->hasMMABlockScale()" ] } ], "rust": { - "abi_id": "i0535", + "abi_id": "i0536", "module": "matrix", - "name": "mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e3m2_e2m1_f16", + "name": "mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e3m2_e2m3_f16", "arguments": [ "[u32; 2]", "[u32; 4]", @@ -197919,10 +200879,10 @@ "safe": false, "must_use": true, "safe_allowlist_reason": null, - "canonical_path": "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0535", - "public_path": "cuda_intrinsics::matrix::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e3m2_e2m1_f16", + "canonical_path": "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0536", + "public_path": "cuda_intrinsics::matrix::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e3m2_e2m3_f16", "compatibility_paths": [ - "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e3m2_e2m1_f16" + "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e3m2_e2m3_f16" ] }, "dialect": { @@ -197948,7 +200908,7 @@ ] }, "llvm": { - "symbol": "llvm.nvvm.mma.sp.ordered.metadata.m16n8k64.row.col.kind.f8f6f4.f16.e3m2.e2m1.f16", + "symbol": "llvm.nvvm.mma.sp.ordered.metadata.m16n8k64.row.col.kind.f8f6f4.f16.e3m2.e2m3.f16", "arguments": [ "i32", "i32", @@ -198415,7 +201375,7 @@ "shape": "m16n8k64", "accumulator": "f16", "a_element": "e3m2", - "b_element": "e2m1", + "b_element": "e2m3", "a_layout": "row", "b_layout": "col", "overflow": "not_applicable", @@ -198440,7 +201400,7 @@ "kind::f8f6f4", "f16", "e3m2", - "e2m1", + "e2m3", "f16" ], "operands": [ @@ -198468,29 +201428,29 @@ } ] }, - "summary": "Multiplies warp-distributed sparse e3m2 A and e2m1 B fragments and adds a packed F16 accumulator." + "summary": "Multiplies warp-distributed sparse e3m2 A and e2m3 B fragments and adds a packed F16 accumulator." }, { - "id": "mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e3m2_e2m3_f16", - "operation_key": "matrix.mma.sp.m16n8k64.row.col.kind_f8f6f4.f16.e3m2.e2m3.f16.not_applicable.ordered_metadata", + "id": "mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e3m2_e3m2_f16", + "operation_key": "matrix.mma.sp.m16n8k64.row.col.kind_f8f6f4.f16.e3m2.e3m2.f16.not_applicable.ordered_metadata", "family": "sparse_mma", "source": { "kind": "llvm_imported", - "source_record": "int_nvvm_mma_sp_ordered_metadata_m16n8k64_row_col_kind_f8f6f4_f16_e3m2_e2m3_f16" + "source_record": "int_nvvm_mma_sp_ordered_metadata_m16n8k64_row_col_kind_f8f6f4_f16_e3m2_e3m2_f16" }, "selections": [ { - "source_record": "anonymous_19846", - "asm": "mma.sp::ordered_metadata.sync.aligned.m16n8k64.row.col.kind::f8f6f4.f16.e3m2.e2m3.f16\n\t\t{{$rd0, $rd1}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1, $rb2, $rb3}},\n\t\t{{$rc0, $rc1}},\n\t\t$metadata,\n\t\t$selector;", + "source_record": "anonymous_19838", + "asm": "mma.sp::ordered_metadata.sync.aligned.m16n8k64.row.col.kind::f8f6f4.f16.e3m2.e3m2.f16\n\t\t{{$rd0, $rd1}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1, $rb2, $rb3}},\n\t\t{{$rc0, $rc1}},\n\t\t$metadata,\n\t\t$selector;", "predicates": [ "Subtarget->hasMMABlockScale()" ] } ], "rust": { - "abi_id": "i0536", + "abi_id": "i0537", "module": "matrix", - "name": "mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e3m2_e2m3_f16", + "name": "mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e3m2_e3m2_f16", "arguments": [ "[u32; 2]", "[u32; 4]", @@ -198502,10 +201462,10 @@ "safe": false, "must_use": true, "safe_allowlist_reason": null, - "canonical_path": "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0536", - "public_path": "cuda_intrinsics::matrix::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e3m2_e2m3_f16", + "canonical_path": "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0537", + "public_path": "cuda_intrinsics::matrix::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e3m2_e3m2_f16", "compatibility_paths": [ - "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e3m2_e2m3_f16" + "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e3m2_e3m2_f16" ] }, "dialect": { @@ -198531,7 +201491,7 @@ ] }, "llvm": { - "symbol": "llvm.nvvm.mma.sp.ordered.metadata.m16n8k64.row.col.kind.f8f6f4.f16.e3m2.e2m3.f16", + "symbol": "llvm.nvvm.mma.sp.ordered.metadata.m16n8k64.row.col.kind.f8f6f4.f16.e3m2.e3m2.f16", "arguments": [ "i32", "i32", @@ -198998,7 +201958,7 @@ "shape": "m16n8k64", "accumulator": "f16", "a_element": "e3m2", - "b_element": "e2m3", + "b_element": "e3m2", "a_layout": "row", "b_layout": "col", "overflow": "not_applicable", @@ -199023,7 +201983,7 @@ "kind::f8f6f4", "f16", "e3m2", - "e2m3", + "e3m2", "f16" ], "operands": [ @@ -199051,29 +202011,29 @@ } ] }, - "summary": "Multiplies warp-distributed sparse e3m2 A and e2m3 B fragments and adds a packed F16 accumulator." + "summary": "Multiplies warp-distributed sparse e3m2 A and e3m2 B fragments and adds a packed F16 accumulator." }, { - "id": "mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e3m2_e3m2_f16", - "operation_key": "matrix.mma.sp.m16n8k64.row.col.kind_f8f6f4.f16.e3m2.e3m2.f16.not_applicable.ordered_metadata", + "id": "mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e3m2_e4m3_f16", + "operation_key": "matrix.mma.sp.m16n8k64.row.col.kind_f8f6f4.f16.e3m2.e4m3.f16.not_applicable.ordered_metadata", "family": "sparse_mma", "source": { "kind": "llvm_imported", - "source_record": "int_nvvm_mma_sp_ordered_metadata_m16n8k64_row_col_kind_f8f6f4_f16_e3m2_e3m2_f16" + "source_record": "int_nvvm_mma_sp_ordered_metadata_m16n8k64_row_col_kind_f8f6f4_f16_e3m2_e4m3_f16" }, "selections": [ { - "source_record": "anonymous_19838", - "asm": "mma.sp::ordered_metadata.sync.aligned.m16n8k64.row.col.kind::f8f6f4.f16.e3m2.e3m2.f16\n\t\t{{$rd0, $rd1}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1, $rb2, $rb3}},\n\t\t{{$rc0, $rc1}},\n\t\t$metadata,\n\t\t$selector;", + "source_record": "anonymous_19822", + "asm": "mma.sp::ordered_metadata.sync.aligned.m16n8k64.row.col.kind::f8f6f4.f16.e3m2.e4m3.f16\n\t\t{{$rd0, $rd1}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1, $rb2, $rb3}},\n\t\t{{$rc0, $rc1}},\n\t\t$metadata,\n\t\t$selector;", "predicates": [ "Subtarget->hasMMABlockScale()" ] } ], "rust": { - "abi_id": "i0537", + "abi_id": "i0538", "module": "matrix", - "name": "mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e3m2_e3m2_f16", + "name": "mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e3m2_e4m3_f16", "arguments": [ "[u32; 2]", "[u32; 4]", @@ -199085,10 +202045,10 @@ "safe": false, "must_use": true, "safe_allowlist_reason": null, - "canonical_path": "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0537", - "public_path": "cuda_intrinsics::matrix::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e3m2_e3m2_f16", + "canonical_path": "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0538", + "public_path": "cuda_intrinsics::matrix::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e3m2_e4m3_f16", "compatibility_paths": [ - "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e3m2_e3m2_f16" + "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e3m2_e4m3_f16" ] }, "dialect": { @@ -199114,7 +202074,7 @@ ] }, "llvm": { - "symbol": "llvm.nvvm.mma.sp.ordered.metadata.m16n8k64.row.col.kind.f8f6f4.f16.e3m2.e3m2.f16", + "symbol": "llvm.nvvm.mma.sp.ordered.metadata.m16n8k64.row.col.kind.f8f6f4.f16.e3m2.e4m3.f16", "arguments": [ "i32", "i32", @@ -199581,7 +202541,7 @@ "shape": "m16n8k64", "accumulator": "f16", "a_element": "e3m2", - "b_element": "e3m2", + "b_element": "e4m3", "a_layout": "row", "b_layout": "col", "overflow": "not_applicable", @@ -199606,7 +202566,7 @@ "kind::f8f6f4", "f16", "e3m2", - "e3m2", + "e4m3", "f16" ], "operands": [ @@ -199634,29 +202594,29 @@ } ] }, - "summary": "Multiplies warp-distributed sparse e3m2 A and e3m2 B fragments and adds a packed F16 accumulator." + "summary": "Multiplies warp-distributed sparse e3m2 A and e4m3 B fragments and adds a packed F16 accumulator." }, { - "id": "mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e3m2_e4m3_f16", - "operation_key": "matrix.mma.sp.m16n8k64.row.col.kind_f8f6f4.f16.e3m2.e4m3.f16.not_applicable.ordered_metadata", + "id": "mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e3m2_e5m2_f16", + "operation_key": "matrix.mma.sp.m16n8k64.row.col.kind_f8f6f4.f16.e3m2.e5m2.f16.not_applicable.ordered_metadata", "family": "sparse_mma", "source": { "kind": "llvm_imported", - "source_record": "int_nvvm_mma_sp_ordered_metadata_m16n8k64_row_col_kind_f8f6f4_f16_e3m2_e4m3_f16" + "source_record": "int_nvvm_mma_sp_ordered_metadata_m16n8k64_row_col_kind_f8f6f4_f16_e3m2_e5m2_f16" }, "selections": [ { - "source_record": "anonymous_19822", - "asm": "mma.sp::ordered_metadata.sync.aligned.m16n8k64.row.col.kind::f8f6f4.f16.e3m2.e4m3.f16\n\t\t{{$rd0, $rd1}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1, $rb2, $rb3}},\n\t\t{{$rc0, $rc1}},\n\t\t$metadata,\n\t\t$selector;", + "source_record": "anonymous_19830", + "asm": "mma.sp::ordered_metadata.sync.aligned.m16n8k64.row.col.kind::f8f6f4.f16.e3m2.e5m2.f16\n\t\t{{$rd0, $rd1}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1, $rb2, $rb3}},\n\t\t{{$rc0, $rc1}},\n\t\t$metadata,\n\t\t$selector;", "predicates": [ "Subtarget->hasMMABlockScale()" ] } ], "rust": { - "abi_id": "i0538", + "abi_id": "i0539", "module": "matrix", - "name": "mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e3m2_e4m3_f16", + "name": "mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e3m2_e5m2_f16", "arguments": [ "[u32; 2]", "[u32; 4]", @@ -199668,10 +202628,10 @@ "safe": false, "must_use": true, "safe_allowlist_reason": null, - "canonical_path": "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0538", - "public_path": "cuda_intrinsics::matrix::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e3m2_e4m3_f16", + "canonical_path": "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0539", + "public_path": "cuda_intrinsics::matrix::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e3m2_e5m2_f16", "compatibility_paths": [ - "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e3m2_e4m3_f16" + "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e3m2_e5m2_f16" ] }, "dialect": { @@ -199697,7 +202657,7 @@ ] }, "llvm": { - "symbol": "llvm.nvvm.mma.sp.ordered.metadata.m16n8k64.row.col.kind.f8f6f4.f16.e3m2.e4m3.f16", + "symbol": "llvm.nvvm.mma.sp.ordered.metadata.m16n8k64.row.col.kind.f8f6f4.f16.e3m2.e5m2.f16", "arguments": [ "i32", "i32", @@ -200164,7 +203124,7 @@ "shape": "m16n8k64", "accumulator": "f16", "a_element": "e3m2", - "b_element": "e4m3", + "b_element": "e5m2", "a_layout": "row", "b_layout": "col", "overflow": "not_applicable", @@ -200189,7 +203149,7 @@ "kind::f8f6f4", "f16", "e3m2", - "e4m3", + "e5m2", "f16" ], "operands": [ @@ -200217,29 +203177,29 @@ } ] }, - "summary": "Multiplies warp-distributed sparse e3m2 A and e4m3 B fragments and adds a packed F16 accumulator." + "summary": "Multiplies warp-distributed sparse e3m2 A and e5m2 B fragments and adds a packed F16 accumulator." }, { - "id": "mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e3m2_e5m2_f16", - "operation_key": "matrix.mma.sp.m16n8k64.row.col.kind_f8f6f4.f16.e3m2.e5m2.f16.not_applicable.ordered_metadata", + "id": "mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e4m3_e2m1_f16", + "operation_key": "matrix.mma.sp.m16n8k64.row.col.kind_f8f6f4.f16.e4m3.e2m1.f16.not_applicable.ordered_metadata", "family": "sparse_mma", "source": { "kind": "llvm_imported", - "source_record": "int_nvvm_mma_sp_ordered_metadata_m16n8k64_row_col_kind_f8f6f4_f16_e3m2_e5m2_f16" + "source_record": "int_nvvm_mma_sp_ordered_metadata_m16n8k64_row_col_kind_f8f6f4_f16_e4m3_e2m1_f16" }, "selections": [ { - "source_record": "anonymous_19830", - "asm": "mma.sp::ordered_metadata.sync.aligned.m16n8k64.row.col.kind::f8f6f4.f16.e3m2.e5m2.f16\n\t\t{{$rd0, $rd1}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1, $rb2, $rb3}},\n\t\t{{$rc0, $rc1}},\n\t\t$metadata,\n\t\t$selector;", + "source_record": "anonymous_19772", + "asm": "mma.sp::ordered_metadata.sync.aligned.m16n8k64.row.col.kind::f8f6f4.f16.e4m3.e2m1.f16\n\t\t{{$rd0, $rd1}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1, $rb2, $rb3}},\n\t\t{{$rc0, $rc1}},\n\t\t$metadata,\n\t\t$selector;", "predicates": [ "Subtarget->hasMMABlockScale()" ] } ], "rust": { - "abi_id": "i0539", + "abi_id": "i0540", "module": "matrix", - "name": "mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e3m2_e5m2_f16", + "name": "mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e4m3_e2m1_f16", "arguments": [ "[u32; 2]", "[u32; 4]", @@ -200251,10 +203211,10 @@ "safe": false, "must_use": true, "safe_allowlist_reason": null, - "canonical_path": "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0539", - "public_path": "cuda_intrinsics::matrix::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e3m2_e5m2_f16", + "canonical_path": "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0540", + "public_path": "cuda_intrinsics::matrix::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e4m3_e2m1_f16", "compatibility_paths": [ - "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e3m2_e5m2_f16" + "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e4m3_e2m1_f16" ] }, "dialect": { @@ -200280,7 +203240,7 @@ ] }, "llvm": { - "symbol": "llvm.nvvm.mma.sp.ordered.metadata.m16n8k64.row.col.kind.f8f6f4.f16.e3m2.e5m2.f16", + "symbol": "llvm.nvvm.mma.sp.ordered.metadata.m16n8k64.row.col.kind.f8f6f4.f16.e4m3.e2m1.f16", "arguments": [ "i32", "i32", @@ -200746,8 +203706,8 @@ "sparse_mma": { "shape": "m16n8k64", "accumulator": "f16", - "a_element": "e3m2", - "b_element": "e5m2", + "a_element": "e4m3", + "b_element": "e2m1", "a_layout": "row", "b_layout": "col", "overflow": "not_applicable", @@ -200771,8 +203731,8 @@ "col", "kind::f8f6f4", "f16", - "e3m2", - "e5m2", + "e4m3", + "e2m1", "f16" ], "operands": [ @@ -200800,29 +203760,29 @@ } ] }, - "summary": "Multiplies warp-distributed sparse e3m2 A and e5m2 B fragments and adds a packed F16 accumulator." + "summary": "Multiplies warp-distributed sparse e4m3 A and e2m1 B fragments and adds a packed F16 accumulator." }, { - "id": "mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e4m3_e2m1_f16", - "operation_key": "matrix.mma.sp.m16n8k64.row.col.kind_f8f6f4.f16.e4m3.e2m1.f16.not_applicable.ordered_metadata", + "id": "mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e4m3_e2m3_f16", + "operation_key": "matrix.mma.sp.m16n8k64.row.col.kind_f8f6f4.f16.e4m3.e2m3.f16.not_applicable.ordered_metadata", "family": "sparse_mma", "source": { "kind": "llvm_imported", - "source_record": "int_nvvm_mma_sp_ordered_metadata_m16n8k64_row_col_kind_f8f6f4_f16_e4m3_e2m1_f16" + "source_record": "int_nvvm_mma_sp_ordered_metadata_m16n8k64_row_col_kind_f8f6f4_f16_e4m3_e2m3_f16" }, "selections": [ { - "source_record": "anonymous_19772", - "asm": "mma.sp::ordered_metadata.sync.aligned.m16n8k64.row.col.kind::f8f6f4.f16.e4m3.e2m1.f16\n\t\t{{$rd0, $rd1}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1, $rb2, $rb3}},\n\t\t{{$rc0, $rc1}},\n\t\t$metadata,\n\t\t$selector;", + "source_record": "anonymous_19763", + "asm": "mma.sp::ordered_metadata.sync.aligned.m16n8k64.row.col.kind::f8f6f4.f16.e4m3.e2m3.f16\n\t\t{{$rd0, $rd1}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1, $rb2, $rb3}},\n\t\t{{$rc0, $rc1}},\n\t\t$metadata,\n\t\t$selector;", "predicates": [ "Subtarget->hasMMABlockScale()" ] } ], "rust": { - "abi_id": "i0540", + "abi_id": "i0541", "module": "matrix", - "name": "mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e4m3_e2m1_f16", + "name": "mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e4m3_e2m3_f16", "arguments": [ "[u32; 2]", "[u32; 4]", @@ -200834,10 +203794,10 @@ "safe": false, "must_use": true, "safe_allowlist_reason": null, - "canonical_path": "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0540", - "public_path": "cuda_intrinsics::matrix::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e4m3_e2m1_f16", + "canonical_path": "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0541", + "public_path": "cuda_intrinsics::matrix::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e4m3_e2m3_f16", "compatibility_paths": [ - "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e4m3_e2m1_f16" + "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e4m3_e2m3_f16" ] }, "dialect": { @@ -200863,7 +203823,7 @@ ] }, "llvm": { - "symbol": "llvm.nvvm.mma.sp.ordered.metadata.m16n8k64.row.col.kind.f8f6f4.f16.e4m3.e2m1.f16", + "symbol": "llvm.nvvm.mma.sp.ordered.metadata.m16n8k64.row.col.kind.f8f6f4.f16.e4m3.e2m3.f16", "arguments": [ "i32", "i32", @@ -201330,7 +204290,7 @@ "shape": "m16n8k64", "accumulator": "f16", "a_element": "e4m3", - "b_element": "e2m1", + "b_element": "e2m3", "a_layout": "row", "b_layout": "col", "overflow": "not_applicable", @@ -201355,7 +204315,7 @@ "kind::f8f6f4", "f16", "e4m3", - "e2m1", + "e2m3", "f16" ], "operands": [ @@ -201383,29 +204343,29 @@ } ] }, - "summary": "Multiplies warp-distributed sparse e4m3 A and e2m1 B fragments and adds a packed F16 accumulator." + "summary": "Multiplies warp-distributed sparse e4m3 A and e2m3 B fragments and adds a packed F16 accumulator." }, { - "id": "mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e4m3_e2m3_f16", - "operation_key": "matrix.mma.sp.m16n8k64.row.col.kind_f8f6f4.f16.e4m3.e2m3.f16.not_applicable.ordered_metadata", + "id": "mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e4m3_e3m2_f16", + "operation_key": "matrix.mma.sp.m16n8k64.row.col.kind_f8f6f4.f16.e4m3.e3m2.f16.not_applicable.ordered_metadata", "family": "sparse_mma", "source": { "kind": "llvm_imported", - "source_record": "int_nvvm_mma_sp_ordered_metadata_m16n8k64_row_col_kind_f8f6f4_f16_e4m3_e2m3_f16" + "source_record": "int_nvvm_mma_sp_ordered_metadata_m16n8k64_row_col_kind_f8f6f4_f16_e4m3_e3m2_f16" }, "selections": [ { - "source_record": "anonymous_19763", - "asm": "mma.sp::ordered_metadata.sync.aligned.m16n8k64.row.col.kind::f8f6f4.f16.e4m3.e2m3.f16\n\t\t{{$rd0, $rd1}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1, $rb2, $rb3}},\n\t\t{{$rc0, $rc1}},\n\t\t$metadata,\n\t\t$selector;", + "source_record": "anonymous_19754", + "asm": "mma.sp::ordered_metadata.sync.aligned.m16n8k64.row.col.kind::f8f6f4.f16.e4m3.e3m2.f16\n\t\t{{$rd0, $rd1}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1, $rb2, $rb3}},\n\t\t{{$rc0, $rc1}},\n\t\t$metadata,\n\t\t$selector;", "predicates": [ "Subtarget->hasMMABlockScale()" ] } ], "rust": { - "abi_id": "i0541", + "abi_id": "i0542", "module": "matrix", - "name": "mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e4m3_e2m3_f16", + "name": "mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e4m3_e3m2_f16", "arguments": [ "[u32; 2]", "[u32; 4]", @@ -201417,10 +204377,10 @@ "safe": false, "must_use": true, "safe_allowlist_reason": null, - "canonical_path": "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0541", - "public_path": "cuda_intrinsics::matrix::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e4m3_e2m3_f16", + "canonical_path": "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0542", + "public_path": "cuda_intrinsics::matrix::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e4m3_e3m2_f16", "compatibility_paths": [ - "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e4m3_e2m3_f16" + "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e4m3_e3m2_f16" ] }, "dialect": { @@ -201446,7 +204406,7 @@ ] }, "llvm": { - "symbol": "llvm.nvvm.mma.sp.ordered.metadata.m16n8k64.row.col.kind.f8f6f4.f16.e4m3.e2m3.f16", + "symbol": "llvm.nvvm.mma.sp.ordered.metadata.m16n8k64.row.col.kind.f8f6f4.f16.e4m3.e3m2.f16", "arguments": [ "i32", "i32", @@ -201913,7 +204873,7 @@ "shape": "m16n8k64", "accumulator": "f16", "a_element": "e4m3", - "b_element": "e2m3", + "b_element": "e3m2", "a_layout": "row", "b_layout": "col", "overflow": "not_applicable", @@ -201938,7 +204898,7 @@ "kind::f8f6f4", "f16", "e4m3", - "e2m3", + "e3m2", "f16" ], "operands": [ @@ -201966,29 +204926,29 @@ } ] }, - "summary": "Multiplies warp-distributed sparse e4m3 A and e2m3 B fragments and adds a packed F16 accumulator." + "summary": "Multiplies warp-distributed sparse e4m3 A and e3m2 B fragments and adds a packed F16 accumulator." }, { - "id": "mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e4m3_e3m2_f16", - "operation_key": "matrix.mma.sp.m16n8k64.row.col.kind_f8f6f4.f16.e4m3.e3m2.f16.not_applicable.ordered_metadata", + "id": "mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e4m3_e4m3_f16", + "operation_key": "matrix.mma.sp.m16n8k64.row.col.kind_f8f6f4.f16.e4m3.e4m3.f16.not_applicable.ordered_metadata", "family": "sparse_mma", "source": { "kind": "llvm_imported", - "source_record": "int_nvvm_mma_sp_ordered_metadata_m16n8k64_row_col_kind_f8f6f4_f16_e4m3_e3m2_f16" + "source_record": "int_nvvm_mma_sp_ordered_metadata_m16n8k64_row_col_kind_f8f6f4_f16_e4m3_e4m3_f16" }, "selections": [ { - "source_record": "anonymous_19754", - "asm": "mma.sp::ordered_metadata.sync.aligned.m16n8k64.row.col.kind::f8f6f4.f16.e4m3.e3m2.f16\n\t\t{{$rd0, $rd1}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1, $rb2, $rb3}},\n\t\t{{$rc0, $rc1}},\n\t\t$metadata,\n\t\t$selector;", + "source_record": "anonymous_19734", + "asm": "mma.sp::ordered_metadata.sync.aligned.m16n8k64.row.col.kind::f8f6f4.f16.e4m3.e4m3.f16\n\t\t{{$rd0, $rd1}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1, $rb2, $rb3}},\n\t\t{{$rc0, $rc1}},\n\t\t$metadata,\n\t\t$selector;", "predicates": [ "Subtarget->hasMMABlockScale()" ] } ], "rust": { - "abi_id": "i0542", + "abi_id": "i0543", "module": "matrix", - "name": "mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e4m3_e3m2_f16", + "name": "mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e4m3_e4m3_f16", "arguments": [ "[u32; 2]", "[u32; 4]", @@ -202000,10 +204960,10 @@ "safe": false, "must_use": true, "safe_allowlist_reason": null, - "canonical_path": "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0542", - "public_path": "cuda_intrinsics::matrix::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e4m3_e3m2_f16", + "canonical_path": "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0543", + "public_path": "cuda_intrinsics::matrix::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e4m3_e4m3_f16", "compatibility_paths": [ - "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e4m3_e3m2_f16" + "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e4m3_e4m3_f16" ] }, "dialect": { @@ -202029,7 +204989,7 @@ ] }, "llvm": { - "symbol": "llvm.nvvm.mma.sp.ordered.metadata.m16n8k64.row.col.kind.f8f6f4.f16.e4m3.e3m2.f16", + "symbol": "llvm.nvvm.mma.sp.ordered.metadata.m16n8k64.row.col.kind.f8f6f4.f16.e4m3.e4m3.f16", "arguments": [ "i32", "i32", @@ -202496,7 +205456,7 @@ "shape": "m16n8k64", "accumulator": "f16", "a_element": "e4m3", - "b_element": "e3m2", + "b_element": "e4m3", "a_layout": "row", "b_layout": "col", "overflow": "not_applicable", @@ -202521,7 +205481,7 @@ "kind::f8f6f4", "f16", "e4m3", - "e3m2", + "e4m3", "f16" ], "operands": [ @@ -202549,29 +205509,29 @@ } ] }, - "summary": "Multiplies warp-distributed sparse e4m3 A and e3m2 B fragments and adds a packed F16 accumulator." + "summary": "Multiplies warp-distributed sparse e4m3 A and e4m3 B fragments and adds a packed F16 accumulator." }, { - "id": "mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e4m3_e4m3_f16", - "operation_key": "matrix.mma.sp.m16n8k64.row.col.kind_f8f6f4.f16.e4m3.e4m3.f16.not_applicable.ordered_metadata", + "id": "mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e4m3_e5m2_f16", + "operation_key": "matrix.mma.sp.m16n8k64.row.col.kind_f8f6f4.f16.e4m3.e5m2.f16.not_applicable.ordered_metadata", "family": "sparse_mma", "source": { "kind": "llvm_imported", - "source_record": "int_nvvm_mma_sp_ordered_metadata_m16n8k64_row_col_kind_f8f6f4_f16_e4m3_e4m3_f16" + "source_record": "int_nvvm_mma_sp_ordered_metadata_m16n8k64_row_col_kind_f8f6f4_f16_e4m3_e5m2_f16" }, "selections": [ { - "source_record": "anonymous_19734", - "asm": "mma.sp::ordered_metadata.sync.aligned.m16n8k64.row.col.kind::f8f6f4.f16.e4m3.e4m3.f16\n\t\t{{$rd0, $rd1}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1, $rb2, $rb3}},\n\t\t{{$rc0, $rc1}},\n\t\t$metadata,\n\t\t$selector;", + "source_record": "anonymous_19745", + "asm": "mma.sp::ordered_metadata.sync.aligned.m16n8k64.row.col.kind::f8f6f4.f16.e4m3.e5m2.f16\n\t\t{{$rd0, $rd1}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1, $rb2, $rb3}},\n\t\t{{$rc0, $rc1}},\n\t\t$metadata,\n\t\t$selector;", "predicates": [ "Subtarget->hasMMABlockScale()" ] } ], "rust": { - "abi_id": "i0543", + "abi_id": "i0544", "module": "matrix", - "name": "mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e4m3_e4m3_f16", + "name": "mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e4m3_e5m2_f16", "arguments": [ "[u32; 2]", "[u32; 4]", @@ -202583,10 +205543,10 @@ "safe": false, "must_use": true, "safe_allowlist_reason": null, - "canonical_path": "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0543", - "public_path": "cuda_intrinsics::matrix::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e4m3_e4m3_f16", + "canonical_path": "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0544", + "public_path": "cuda_intrinsics::matrix::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e4m3_e5m2_f16", "compatibility_paths": [ - "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e4m3_e4m3_f16" + "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e4m3_e5m2_f16" ] }, "dialect": { @@ -202612,7 +205572,7 @@ ] }, "llvm": { - "symbol": "llvm.nvvm.mma.sp.ordered.metadata.m16n8k64.row.col.kind.f8f6f4.f16.e4m3.e4m3.f16", + "symbol": "llvm.nvvm.mma.sp.ordered.metadata.m16n8k64.row.col.kind.f8f6f4.f16.e4m3.e5m2.f16", "arguments": [ "i32", "i32", @@ -203079,7 +206039,7 @@ "shape": "m16n8k64", "accumulator": "f16", "a_element": "e4m3", - "b_element": "e4m3", + "b_element": "e5m2", "a_layout": "row", "b_layout": "col", "overflow": "not_applicable", @@ -203104,7 +206064,7 @@ "kind::f8f6f4", "f16", "e4m3", - "e4m3", + "e5m2", "f16" ], "operands": [ @@ -203132,29 +206092,29 @@ } ] }, - "summary": "Multiplies warp-distributed sparse e4m3 A and e4m3 B fragments and adds a packed F16 accumulator." + "summary": "Multiplies warp-distributed sparse e4m3 A and e5m2 B fragments and adds a packed F16 accumulator." }, { - "id": "mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e4m3_e5m2_f16", - "operation_key": "matrix.mma.sp.m16n8k64.row.col.kind_f8f6f4.f16.e4m3.e5m2.f16.not_applicable.ordered_metadata", + "id": "mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e5m2_e2m1_f16", + "operation_key": "matrix.mma.sp.m16n8k64.row.col.kind_f8f6f4.f16.e5m2.e2m1.f16.not_applicable.ordered_metadata", "family": "sparse_mma", "source": { "kind": "llvm_imported", - "source_record": "int_nvvm_mma_sp_ordered_metadata_m16n8k64_row_col_kind_f8f6f4_f16_e4m3_e5m2_f16" + "source_record": "int_nvvm_mma_sp_ordered_metadata_m16n8k64_row_col_kind_f8f6f4_f16_e5m2_e2m1_f16" }, "selections": [ { - "source_record": "anonymous_19745", - "asm": "mma.sp::ordered_metadata.sync.aligned.m16n8k64.row.col.kind::f8f6f4.f16.e4m3.e5m2.f16\n\t\t{{$rd0, $rd1}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1, $rb2, $rb3}},\n\t\t{{$rc0, $rc1}},\n\t\t$metadata,\n\t\t$selector;", + "source_record": "anonymous_19813", + "asm": "mma.sp::ordered_metadata.sync.aligned.m16n8k64.row.col.kind::f8f6f4.f16.e5m2.e2m1.f16\n\t\t{{$rd0, $rd1}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1, $rb2, $rb3}},\n\t\t{{$rc0, $rc1}},\n\t\t$metadata,\n\t\t$selector;", "predicates": [ "Subtarget->hasMMABlockScale()" ] } ], "rust": { - "abi_id": "i0544", + "abi_id": "i0545", "module": "matrix", - "name": "mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e4m3_e5m2_f16", + "name": "mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e5m2_e2m1_f16", "arguments": [ "[u32; 2]", "[u32; 4]", @@ -203166,10 +206126,10 @@ "safe": false, "must_use": true, "safe_allowlist_reason": null, - "canonical_path": "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0544", - "public_path": "cuda_intrinsics::matrix::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e4m3_e5m2_f16", + "canonical_path": "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0545", + "public_path": "cuda_intrinsics::matrix::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e5m2_e2m1_f16", "compatibility_paths": [ - "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e4m3_e5m2_f16" + "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e5m2_e2m1_f16" ] }, "dialect": { @@ -203195,7 +206155,7 @@ ] }, "llvm": { - "symbol": "llvm.nvvm.mma.sp.ordered.metadata.m16n8k64.row.col.kind.f8f6f4.f16.e4m3.e5m2.f16", + "symbol": "llvm.nvvm.mma.sp.ordered.metadata.m16n8k64.row.col.kind.f8f6f4.f16.e5m2.e2m1.f16", "arguments": [ "i32", "i32", @@ -203661,8 +206621,8 @@ "sparse_mma": { "shape": "m16n8k64", "accumulator": "f16", - "a_element": "e4m3", - "b_element": "e5m2", + "a_element": "e5m2", + "b_element": "e2m1", "a_layout": "row", "b_layout": "col", "overflow": "not_applicable", @@ -203686,8 +206646,8 @@ "col", "kind::f8f6f4", "f16", - "e4m3", "e5m2", + "e2m1", "f16" ], "operands": [ @@ -203715,29 +206675,29 @@ } ] }, - "summary": "Multiplies warp-distributed sparse e4m3 A and e5m2 B fragments and adds a packed F16 accumulator." + "summary": "Multiplies warp-distributed sparse e5m2 A and e2m1 B fragments and adds a packed F16 accumulator." }, { - "id": "mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e5m2_e2m1_f16", - "operation_key": "matrix.mma.sp.m16n8k64.row.col.kind_f8f6f4.f16.e5m2.e2m1.f16.not_applicable.ordered_metadata", + "id": "mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e5m2_e2m3_f16", + "operation_key": "matrix.mma.sp.m16n8k64.row.col.kind_f8f6f4.f16.e5m2.e2m3.f16.not_applicable.ordered_metadata", "family": "sparse_mma", "source": { "kind": "llvm_imported", - "source_record": "int_nvvm_mma_sp_ordered_metadata_m16n8k64_row_col_kind_f8f6f4_f16_e5m2_e2m1_f16" + "source_record": "int_nvvm_mma_sp_ordered_metadata_m16n8k64_row_col_kind_f8f6f4_f16_e5m2_e2m3_f16" }, "selections": [ { - "source_record": "anonymous_19813", - "asm": "mma.sp::ordered_metadata.sync.aligned.m16n8k64.row.col.kind::f8f6f4.f16.e5m2.e2m1.f16\n\t\t{{$rd0, $rd1}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1, $rb2, $rb3}},\n\t\t{{$rc0, $rc1}},\n\t\t$metadata,\n\t\t$selector;", + "source_record": "anonymous_19805", + "asm": "mma.sp::ordered_metadata.sync.aligned.m16n8k64.row.col.kind::f8f6f4.f16.e5m2.e2m3.f16\n\t\t{{$rd0, $rd1}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1, $rb2, $rb3}},\n\t\t{{$rc0, $rc1}},\n\t\t$metadata,\n\t\t$selector;", "predicates": [ "Subtarget->hasMMABlockScale()" ] } ], "rust": { - "abi_id": "i0545", + "abi_id": "i0546", "module": "matrix", - "name": "mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e5m2_e2m1_f16", + "name": "mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e5m2_e2m3_f16", "arguments": [ "[u32; 2]", "[u32; 4]", @@ -203749,10 +206709,10 @@ "safe": false, "must_use": true, "safe_allowlist_reason": null, - "canonical_path": "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0545", - "public_path": "cuda_intrinsics::matrix::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e5m2_e2m1_f16", + "canonical_path": "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0546", + "public_path": "cuda_intrinsics::matrix::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e5m2_e2m3_f16", "compatibility_paths": [ - "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e5m2_e2m1_f16" + "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e5m2_e2m3_f16" ] }, "dialect": { @@ -203778,7 +206738,7 @@ ] }, "llvm": { - "symbol": "llvm.nvvm.mma.sp.ordered.metadata.m16n8k64.row.col.kind.f8f6f4.f16.e5m2.e2m1.f16", + "symbol": "llvm.nvvm.mma.sp.ordered.metadata.m16n8k64.row.col.kind.f8f6f4.f16.e5m2.e2m3.f16", "arguments": [ "i32", "i32", @@ -204245,7 +207205,7 @@ "shape": "m16n8k64", "accumulator": "f16", "a_element": "e5m2", - "b_element": "e2m1", + "b_element": "e2m3", "a_layout": "row", "b_layout": "col", "overflow": "not_applicable", @@ -204270,7 +207230,7 @@ "kind::f8f6f4", "f16", "e5m2", - "e2m1", + "e2m3", "f16" ], "operands": [ @@ -204298,29 +207258,29 @@ } ] }, - "summary": "Multiplies warp-distributed sparse e5m2 A and e2m1 B fragments and adds a packed F16 accumulator." + "summary": "Multiplies warp-distributed sparse e5m2 A and e2m3 B fragments and adds a packed F16 accumulator." }, { - "id": "mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e5m2_e2m3_f16", - "operation_key": "matrix.mma.sp.m16n8k64.row.col.kind_f8f6f4.f16.e5m2.e2m3.f16.not_applicable.ordered_metadata", + "id": "mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e5m2_e3m2_f16", + "operation_key": "matrix.mma.sp.m16n8k64.row.col.kind_f8f6f4.f16.e5m2.e3m2.f16.not_applicable.ordered_metadata", "family": "sparse_mma", "source": { "kind": "llvm_imported", - "source_record": "int_nvvm_mma_sp_ordered_metadata_m16n8k64_row_col_kind_f8f6f4_f16_e5m2_e2m3_f16" + "source_record": "int_nvvm_mma_sp_ordered_metadata_m16n8k64_row_col_kind_f8f6f4_f16_e5m2_e3m2_f16" }, "selections": [ { - "source_record": "anonymous_19805", - "asm": "mma.sp::ordered_metadata.sync.aligned.m16n8k64.row.col.kind::f8f6f4.f16.e5m2.e2m3.f16\n\t\t{{$rd0, $rd1}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1, $rb2, $rb3}},\n\t\t{{$rc0, $rc1}},\n\t\t$metadata,\n\t\t$selector;", + "source_record": "anonymous_19797", + "asm": "mma.sp::ordered_metadata.sync.aligned.m16n8k64.row.col.kind::f8f6f4.f16.e5m2.e3m2.f16\n\t\t{{$rd0, $rd1}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1, $rb2, $rb3}},\n\t\t{{$rc0, $rc1}},\n\t\t$metadata,\n\t\t$selector;", "predicates": [ "Subtarget->hasMMABlockScale()" ] } ], "rust": { - "abi_id": "i0546", + "abi_id": "i0547", "module": "matrix", - "name": "mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e5m2_e2m3_f16", + "name": "mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e5m2_e3m2_f16", "arguments": [ "[u32; 2]", "[u32; 4]", @@ -204332,10 +207292,10 @@ "safe": false, "must_use": true, "safe_allowlist_reason": null, - "canonical_path": "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0546", - "public_path": "cuda_intrinsics::matrix::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e5m2_e2m3_f16", + "canonical_path": "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0547", + "public_path": "cuda_intrinsics::matrix::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e5m2_e3m2_f16", "compatibility_paths": [ - "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e5m2_e2m3_f16" + "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e5m2_e3m2_f16" ] }, "dialect": { @@ -204361,7 +207321,7 @@ ] }, "llvm": { - "symbol": "llvm.nvvm.mma.sp.ordered.metadata.m16n8k64.row.col.kind.f8f6f4.f16.e5m2.e2m3.f16", + "symbol": "llvm.nvvm.mma.sp.ordered.metadata.m16n8k64.row.col.kind.f8f6f4.f16.e5m2.e3m2.f16", "arguments": [ "i32", "i32", @@ -204828,7 +207788,7 @@ "shape": "m16n8k64", "accumulator": "f16", "a_element": "e5m2", - "b_element": "e2m3", + "b_element": "e3m2", "a_layout": "row", "b_layout": "col", "overflow": "not_applicable", @@ -204853,7 +207813,7 @@ "kind::f8f6f4", "f16", "e5m2", - "e2m3", + "e3m2", "f16" ], "operands": [ @@ -204881,29 +207841,29 @@ } ] }, - "summary": "Multiplies warp-distributed sparse e5m2 A and e2m3 B fragments and adds a packed F16 accumulator." + "summary": "Multiplies warp-distributed sparse e5m2 A and e3m2 B fragments and adds a packed F16 accumulator." }, { - "id": "mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e5m2_e3m2_f16", - "operation_key": "matrix.mma.sp.m16n8k64.row.col.kind_f8f6f4.f16.e5m2.e3m2.f16.not_applicable.ordered_metadata", + "id": "mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e5m2_e4m3_f16", + "operation_key": "matrix.mma.sp.m16n8k64.row.col.kind_f8f6f4.f16.e5m2.e4m3.f16.not_applicable.ordered_metadata", "family": "sparse_mma", "source": { "kind": "llvm_imported", - "source_record": "int_nvvm_mma_sp_ordered_metadata_m16n8k64_row_col_kind_f8f6f4_f16_e5m2_e3m2_f16" + "source_record": "int_nvvm_mma_sp_ordered_metadata_m16n8k64_row_col_kind_f8f6f4_f16_e5m2_e4m3_f16" }, "selections": [ { - "source_record": "anonymous_19797", - "asm": "mma.sp::ordered_metadata.sync.aligned.m16n8k64.row.col.kind::f8f6f4.f16.e5m2.e3m2.f16\n\t\t{{$rd0, $rd1}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1, $rb2, $rb3}},\n\t\t{{$rc0, $rc1}},\n\t\t$metadata,\n\t\t$selector;", + "source_record": "anonymous_19781", + "asm": "mma.sp::ordered_metadata.sync.aligned.m16n8k64.row.col.kind::f8f6f4.f16.e5m2.e4m3.f16\n\t\t{{$rd0, $rd1}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1, $rb2, $rb3}},\n\t\t{{$rc0, $rc1}},\n\t\t$metadata,\n\t\t$selector;", "predicates": [ "Subtarget->hasMMABlockScale()" ] } ], "rust": { - "abi_id": "i0547", + "abi_id": "i0548", "module": "matrix", - "name": "mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e5m2_e3m2_f16", + "name": "mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e5m2_e4m3_f16", "arguments": [ "[u32; 2]", "[u32; 4]", @@ -204915,10 +207875,10 @@ "safe": false, "must_use": true, "safe_allowlist_reason": null, - "canonical_path": "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0547", - "public_path": "cuda_intrinsics::matrix::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e5m2_e3m2_f16", + "canonical_path": "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0548", + "public_path": "cuda_intrinsics::matrix::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e5m2_e4m3_f16", "compatibility_paths": [ - "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e5m2_e3m2_f16" + "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e5m2_e4m3_f16" ] }, "dialect": { @@ -204944,7 +207904,7 @@ ] }, "llvm": { - "symbol": "llvm.nvvm.mma.sp.ordered.metadata.m16n8k64.row.col.kind.f8f6f4.f16.e5m2.e3m2.f16", + "symbol": "llvm.nvvm.mma.sp.ordered.metadata.m16n8k64.row.col.kind.f8f6f4.f16.e5m2.e4m3.f16", "arguments": [ "i32", "i32", @@ -205411,7 +208371,7 @@ "shape": "m16n8k64", "accumulator": "f16", "a_element": "e5m2", - "b_element": "e3m2", + "b_element": "e4m3", "a_layout": "row", "b_layout": "col", "overflow": "not_applicable", @@ -205436,7 +208396,7 @@ "kind::f8f6f4", "f16", "e5m2", - "e3m2", + "e4m3", "f16" ], "operands": [ @@ -205464,29 +208424,29 @@ } ] }, - "summary": "Multiplies warp-distributed sparse e5m2 A and e3m2 B fragments and adds a packed F16 accumulator." + "summary": "Multiplies warp-distributed sparse e5m2 A and e4m3 B fragments and adds a packed F16 accumulator." }, { - "id": "mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e5m2_e4m3_f16", - "operation_key": "matrix.mma.sp.m16n8k64.row.col.kind_f8f6f4.f16.e5m2.e4m3.f16.not_applicable.ordered_metadata", + "id": "mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e5m2_e5m2_f16", + "operation_key": "matrix.mma.sp.m16n8k64.row.col.kind_f8f6f4.f16.e5m2.e5m2.f16.not_applicable.ordered_metadata", "family": "sparse_mma", "source": { "kind": "llvm_imported", - "source_record": "int_nvvm_mma_sp_ordered_metadata_m16n8k64_row_col_kind_f8f6f4_f16_e5m2_e4m3_f16" + "source_record": "int_nvvm_mma_sp_ordered_metadata_m16n8k64_row_col_kind_f8f6f4_f16_e5m2_e5m2_f16" }, "selections": [ { - "source_record": "anonymous_19781", - "asm": "mma.sp::ordered_metadata.sync.aligned.m16n8k64.row.col.kind::f8f6f4.f16.e5m2.e4m3.f16\n\t\t{{$rd0, $rd1}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1, $rb2, $rb3}},\n\t\t{{$rc0, $rc1}},\n\t\t$metadata,\n\t\t$selector;", + "source_record": "anonymous_19789", + "asm": "mma.sp::ordered_metadata.sync.aligned.m16n8k64.row.col.kind::f8f6f4.f16.e5m2.e5m2.f16\n\t\t{{$rd0, $rd1}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1, $rb2, $rb3}},\n\t\t{{$rc0, $rc1}},\n\t\t$metadata,\n\t\t$selector;", "predicates": [ "Subtarget->hasMMABlockScale()" ] } ], "rust": { - "abi_id": "i0548", + "abi_id": "i0549", "module": "matrix", - "name": "mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e5m2_e4m3_f16", + "name": "mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e5m2_e5m2_f16", "arguments": [ "[u32; 2]", "[u32; 4]", @@ -205498,10 +208458,10 @@ "safe": false, "must_use": true, "safe_allowlist_reason": null, - "canonical_path": "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0548", - "public_path": "cuda_intrinsics::matrix::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e5m2_e4m3_f16", + "canonical_path": "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0549", + "public_path": "cuda_intrinsics::matrix::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e5m2_e5m2_f16", "compatibility_paths": [ - "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e5m2_e4m3_f16" + "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e5m2_e5m2_f16" ] }, "dialect": { @@ -205527,7 +208487,7 @@ ] }, "llvm": { - "symbol": "llvm.nvvm.mma.sp.ordered.metadata.m16n8k64.row.col.kind.f8f6f4.f16.e5m2.e4m3.f16", + "symbol": "llvm.nvvm.mma.sp.ordered.metadata.m16n8k64.row.col.kind.f8f6f4.f16.e5m2.e5m2.f16", "arguments": [ "i32", "i32", @@ -205994,7 +208954,7 @@ "shape": "m16n8k64", "accumulator": "f16", "a_element": "e5m2", - "b_element": "e4m3", + "b_element": "e5m2", "a_layout": "row", "b_layout": "col", "overflow": "not_applicable", @@ -206019,7 +208979,7 @@ "kind::f8f6f4", "f16", "e5m2", - "e4m3", + "e5m2", "f16" ], "operands": [ @@ -206047,52 +209007,54 @@ } ] }, - "summary": "Multiplies warp-distributed sparse e5m2 A and e4m3 B fragments and adds a packed F16 accumulator." + "summary": "Multiplies warp-distributed sparse e5m2 A and e5m2 B fragments and adds a packed F16 accumulator." }, { - "id": "mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e5m2_e5m2_f16", - "operation_key": "matrix.mma.sp.m16n8k64.row.col.kind_f8f6f4.f16.e5m2.e5m2.f16.not_applicable.ordered_metadata", + "id": "mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e2m1_e2m1_f32", + "operation_key": "matrix.mma.sp.m16n8k64.row.col.kind_f8f6f4.f32.e2m1.e2m1.f32.not_applicable.ordered_metadata", "family": "sparse_mma", "source": { "kind": "llvm_imported", - "source_record": "int_nvvm_mma_sp_ordered_metadata_m16n8k64_row_col_kind_f8f6f4_f16_e5m2_e5m2_f16" + "source_record": "int_nvvm_mma_sp_ordered_metadata_m16n8k64_row_col_kind_f8f6f4_f32_e2m1_e2m1_f32" }, "selections": [ { - "source_record": "anonymous_19789", - "asm": "mma.sp::ordered_metadata.sync.aligned.m16n8k64.row.col.kind::f8f6f4.f16.e5m2.e5m2.f16\n\t\t{{$rd0, $rd1}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1, $rb2, $rb3}},\n\t\t{{$rc0, $rc1}},\n\t\t$metadata,\n\t\t$selector;", + "source_record": "anonymous_19940", + "asm": "mma.sp::ordered_metadata.sync.aligned.m16n8k64.row.col.kind::f8f6f4.f32.e2m1.e2m1.f32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1, $rb2, $rb3}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}},\n\t\t$metadata,\n\t\t$selector;", "predicates": [ "Subtarget->hasMMABlockScale()" ] } ], "rust": { - "abi_id": "i0549", + "abi_id": "i0227", "module": "matrix", - "name": "mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e5m2_e5m2_f16", + "name": "mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e2m1_e2m1_f32", "arguments": [ - "[u32; 2]", + "[f32; 4]", "[u32; 4]", "[u32; 4]", "u32", "u32" ], - "result": "[u32; 2]", + "result": "[f32; 4]", "safe": false, "must_use": true, "safe_allowlist_reason": null, - "canonical_path": "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0549", - "public_path": "cuda_intrinsics::matrix::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e5m2_e5m2_f16", + "canonical_path": "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0227", + "public_path": "cuda_intrinsics::matrix::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e2m1_e2m1_f32", "compatibility_paths": [ - "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e5m2_e5m2_f16" + "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e2m1_e2m1_f32" ] }, "dialect": { "op_type": "SparseMmaOp", "op_name": "nvvm.sparse_mma", "operands": [ - "i32", - "i32", + "f32", + "f32", + "f32", + "f32", "u32", "u32", "u32", @@ -206105,12 +209067,14 @@ "u32" ], "results": [ - "i32", - "i32" + "f32", + "f32", + "f32", + "f32" ] }, "llvm": { - "symbol": "llvm.nvvm.mma.sp.ordered.metadata.m16n8k64.row.col.kind.f8f6f4.f16.e5m2.e5m2.f16", + "symbol": "llvm.nvvm.mma.sp.ordered.metadata.m16n8k64.row.col.kind.f8f6f4.f32.e2m1.e2m1.f32", "arguments": [ "i32", "i32", @@ -206120,20 +209084,24 @@ "i32", "i32", "i32", - "v2f16", - "v2f16", + "f32", + "f32", + "f32", + "f32", "i32", "i32" ], "results": [ - "v2f16", - "v2f16" + "f32", + "f32", + "f32", + "f32" ], "properties": [ - "ImmArg", + "ImmArg", "IntrNoCallback", "IntrNoMem", - "Range" + "Range" ], "result_facts": { "no_undef": false, @@ -206169,7 +209137,7 @@ } ] }, - "ptx_result": "[u32; 2]", + "ptx_result": "[f32; 4]", "targets": "sm_120a|sm_120f|sm_121a|sm_121f", "ptx_isa_version": "9.3", "ptx_isa_section": "9.7.15.6.3 Multiply-and-Accumulate Instruction: mma.sp", @@ -206224,26 +209192,11 @@ "sm_120a", "ptx87" ], - "representation": "typed declaration and convergence comparison", - "stage": "declaration_canonicalization", - "mechanism": "typed_nvvm", - "outcome": "succeeded", - "detail": "The 23,732-byte typed source (SHA-256 ce6f6e73ffd41f5f6c6cf658ff41ce903b7c90afaca38a6279281d2ee8ff60e0) confirmed the imported A4, B4, C2-v2f16, metadata, selector signature. All 25 declarations canonicalized to nocallback nounwind memory(none), with selector immarg range [0,1), and without convergent. Optimization retained only 25 of 50 duplicate typed calls, so this is comparison evidence and not the selected production carrier.", - "artifact_kind": null, - "tool_path": null, - "tool_version": null, - "tool_sha256": null - }, - { - "targets": [ - "sm_120a", - "ptx87" - ], - "representation": "convergent ordered kind::f8f6f4 packed-F16 inline PTX in public C, A, B, metadata, selector order", + "representation": "convergent ordered kind::f8f6f4 F32 inline PTX in public C, A, B, metadata, selector order", "stage": "backend_codegen", "mechanism": "inline_ptx", "outcome": "succeeded", - "detail": "Pinned LLVM lowered the 18,084-byte all-forms source (SHA-256 cf0e3082d15b64340dab3480ede99adff7d8bada7b8cdfec2fa91e990562ca5e) to 8,991-byte PTX (SHA-256 fc0b67574e5ed2b3cab9a6cdd97d86cd0574c4704f35b0fb73ebaea5acbcb725) containing the exact 25-form matrix. The convergent inline duplicate fixture retained all 50 calls.", + "detail": "Pinned LLVM lowered the 28,839-byte all-forms source (SHA-256 5518d5dfb092f5ae3ccefe1e7e66eb4df9db7da480722e390587490c6ce8832a) to 12,015-byte PTX (SHA-256 0d93ea01d39bc512b96becf2ad799522d9d5187c17d521294eecd4e69c055e66) containing the exact 25-form matrix at sm_120a and PTX 8.7.", "artifact_kind": null, "tool_path": null, "tool_version": null, @@ -206254,26 +209207,62 @@ "sm_120a", "ptx87" ], - "representation": "exact-floor ordered kind::f8f6f4 packed-F16 PTX", + "representation": "exact-floor ordered kind::f8f6f4 F32 PTX", "stage": "ptx_assembly", "mechanism": "inline_ptx", "outcome": "succeeded", - "detail": "CUDA 13.3 ptxas produced a 9,728-byte cubin (SHA-256 560446ab6b41e45ca208fddc2c1439d9e851b1b67a9de920e6e81026863352b2); its 27,724-byte SASS dump (SHA-256 3c27689195cd558cd3df06db75ba6e46b1905d39e636536c0a52e01ba3323270) retains 25 unique QMMA forms. PTX 8.6, sm_120, sm_100a, selector 1, and dynamic selectors were rejected.", + "detail": "CUDA 13.3 ptxas produced a 12,144-byte cubin (SHA-256 7769d4fe1de8cdf6644b911bc3654ab220f4dd28cc44a83e28793a5d3f381cf3); its 38,172-byte SASS dump (SHA-256 34df448cb5d7367b36657270961981955bb76cc1dd5dd221f673f174c6e10b0a) retains 25 unique QMMA forms. PTX 8.6, sm_120, selector 1, and dynamic selectors were rejected.", "artifact_kind": "cubin", "tool_path": "/usr/local/cuda-13.3/bin/ptxas", "tool_version": "CUDA 13.3 V13.3.33 build cuda_13.3.r13.3/compiler.37862127_0", "tool_sha256": "7fdd01a4cf50e30746da98989c9272a907f491e6fd7fecfda14642e4375f88fb" - }, + } + ] + }, + { + "backend": "lib_nvvm", + "mechanism": "inline_ptx", + "evidence_profile": "cuda-13.3-libnvvm-13.3.33", + "target": { + "minimum_ptx": "8.7", + "hardware": { + "kind": "any_of", + "alternatives": [ + { + "kind": "exact_architecture", + "sm": 120 + }, + { + "kind": "family_target", + "sm": 120 + }, + { + "kind": "exact_architecture", + "sm": 121 + }, + { + "kind": "family_target", + "sm": 121 + } + ] + } + }, + "version": "CUDA toolkit 13.3; nvcc/libNVVM release V13.3.33", + "sha256": "b6a5db233133fb0ed693f8cb8aeb1d405254ce0ab10364478985292ec98cfcf0", + "artifact_path": "/usr/local/cuda-13.3/nvvm/lib64/libnvvm.so.4.0.0", + "build_id_prefix": "2330c0", + "status": "validated", + "stages": [ { "targets": [ - "sm_120f", - "ptx88" + "compute_120a", + "ptx93" ], - "representation": "convergent ordered kind::f8f6f4 packed-F16 inline PTX", + "representation": "convergent ordered kind::f8f6f4 F32 inline PTX in public C, A, B, metadata, selector order", "stage": "backend_codegen", "mechanism": "inline_ptx", "outcome": "succeeded", - "detail": "Pinned LLVM emitted 8,991-byte PTX (SHA-256 08692523a26e16fd8a05a2646f71a3ade9e95aa2c3f41028f870d7c9bcab999b) containing the exact 25-form matrix with no unresolved calls.", + "detail": "CUDA 13.3 libNVVM retained the exact 25-form matrix in 11,910-byte PTX (SHA-256 a096494f6b066927107cf222f784d1a586ed1cf3ab766669b741e429f03f4427) and produced 14,052-byte LTOIR (SHA-256 99941daa24a78884788ed0908a3764f596c527e6ab621d6085c549aea9575377).", "artifact_kind": null, "tool_path": null, "tool_version": null, @@ -206281,14 +209270,14 @@ }, { "targets": [ - "sm_120f", - "ptx88" + "sm_120a", + "ptx93" ], - "representation": "exact-floor ordered kind::f8f6f4 packed-F16 PTX", + "representation": "libNVVM-emitted ordered kind::f8f6f4 F32 PTX", "stage": "ptx_assembly", "mechanism": "inline_ptx", "outcome": "succeeded", - "detail": "CUDA 13.3 ptxas produced a 9,728-byte cubin (SHA-256 90a0b9bf02df8ca3cb34f867b29b56a65d79a5c9033ea9dc5084ee210b5f6f1d); its 27,701-byte SASS dump (SHA-256 80831cd9a7cde8fd67343302591ea08a30327606719fb232d8e28e812d9c5e46) retains 25 unique QMMA forms.", + "detail": "CUDA 13.3 ptxas produced a 12,144-byte cubin (SHA-256 7769d4fe1de8cdf6644b911bc3654ab220f4dd28cc44a83e28793a5d3f381cf3) retaining all 25 unique QMMA forms.", "artifact_kind": "cubin", "tool_path": "/usr/local/cuda-13.3/bin/ptxas", "tool_version": "CUDA 13.3 V13.3.33 build cuda_13.3.r13.3/compiler.37862127_0", @@ -206296,44 +209285,269 @@ }, { "targets": [ - "sm_121a", - "ptx88" + "sm_120a", + "ptx93" ], - "representation": "convergent ordered kind::f8f6f4 packed-F16 inline PTX", - "stage": "backend_codegen", + "representation": "libNVVM LTOIR retaining the ordered kind::f8f6f4 F32 matrix", + "stage": "device_link", "mechanism": "inline_ptx", "outcome": "succeeded", - "detail": "Pinned LLVM emitted 8,991-byte PTX (SHA-256 afec2d0be50c3984867f5402585ba0dbd4f3fe3ac74e6527ab47628ebefd2be4) containing the exact 25-form matrix with no unresolved calls.", - "artifact_kind": null, - "tool_path": null, - "tool_version": null, - "tool_sha256": null + "detail": "CUDA 13.3 nvJitLink produced a 12,144-byte cubin (SHA-256 62457debbb99023b09b3701e14974a97cfc5761f931ebf9f0d9e2bada3e3a642); its 38,172-byte SASS dump (SHA-256 34df448cb5d7367b36657270961981955bb76cc1dd5dd221f673f174c6e10b0a) retains 25 unique QMMA forms.", + "artifact_kind": "cubin", + "tool_path": "/usr/local/cuda-13.3/lib64/libnvJitLink.so.13.3.33", + "tool_version": "V13.3.33", + "tool_sha256": "3ba1e744347cd68617b862eccfd98b125482e882b7a6319f42abc9a768513db8" + } + ] + } + ], + "sparse_mma": { + "shape": "m16n8k64", + "accumulator": "f32", + "a_element": "e2m1", + "b_element": "e2m1", + "a_layout": "row", + "b_layout": "col", + "overflow": "not_applicable", + "metadata": "ordered", + "selector": "immediate_zero", + "participation": "all_warp_lanes_same_instruction_and_qualifiers_no_exited_lanes", + "adapter": "c4_f32_a4_u32_b4_u32_metadata_u32_selector_u32_to_d4_f32", + "llvm_adapter": "a4_i32_b4_i32_c4_f32_metadata_i32_selector_i32_to_d4_f32", + "compatibility_source": "generated_stub", + "runtime_validation": "unexecuted" + }, + "lowering": "generated_sparse_mma", + "expected_ptx": { + "mnemonic": "mma", + "modifiers": [ + "sp::ordered_metadata", + "sync", + "aligned", + "m16n8k64", + "row", + "col", + "kind::f8f6f4", + "f32", + "e2m1", + "e2m1", + "f32" + ], + "operands": [ + { + "kind": "register_list", + "length": 4 + }, + { + "kind": "register_list", + "length": 4 + }, + { + "kind": "register_list", + "length": 4 + }, + { + "kind": "register_list", + "length": 4 + }, + { + "kind": "register" + }, + { + "kind": "immediate" + } + ] + }, + "summary": "Multiplies warp-distributed sparse e2m1 A and e2m1 B fragments and adds an f32 accumulator." + }, + { + "id": "mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e2m1_e2m3_f32", + "operation_key": "matrix.mma.sp.m16n8k64.row.col.kind_f8f6f4.f32.e2m1.e2m3.f32.not_applicable.ordered_metadata", + "family": "sparse_mma", + "source": { + "kind": "llvm_imported", + "source_record": "int_nvvm_mma_sp_ordered_metadata_m16n8k64_row_col_kind_f8f6f4_f32_e2m1_e2m3_f32" + }, + "selections": [ + { + "source_record": "anonymous_19932", + "asm": "mma.sp::ordered_metadata.sync.aligned.m16n8k64.row.col.kind::f8f6f4.f32.e2m1.e2m3.f32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1, $rb2, $rb3}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}},\n\t\t$metadata,\n\t\t$selector;", + "predicates": [ + "Subtarget->hasMMABlockScale()" + ] + } + ], + "rust": { + "abi_id": "i0228", + "module": "matrix", + "name": "mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e2m1_e2m3_f32", + "arguments": [ + "[f32; 4]", + "[u32; 4]", + "[u32; 4]", + "u32", + "u32" + ], + "result": "[f32; 4]", + "safe": false, + "must_use": true, + "safe_allowlist_reason": null, + "canonical_path": "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0228", + "public_path": "cuda_intrinsics::matrix::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e2m1_e2m3_f32", + "compatibility_paths": [ + "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e2m1_e2m3_f32" + ] + }, + "dialect": { + "op_type": "SparseMmaOp", + "op_name": "nvvm.sparse_mma", + "operands": [ + "f32", + "f32", + "f32", + "f32", + "u32", + "u32", + "u32", + "u32", + "u32", + "u32", + "u32", + "u32", + "u32", + "u32" + ], + "results": [ + "f32", + "f32", + "f32", + "f32" + ] + }, + "llvm": { + "symbol": "llvm.nvvm.mma.sp.ordered.metadata.m16n8k64.row.col.kind.f8f6f4.f32.e2m1.e2m3.f32", + "arguments": [ + "i32", + "i32", + "i32", + "i32", + "i32", + "i32", + "i32", + "i32", + "f32", + "f32", + "f32", + "f32", + "i32", + "i32" + ], + "results": [ + "f32", + "f32", + "f32", + "f32" + ], + "properties": [ + "ImmArg", + "IntrNoCallback", + "IntrNoMem", + "Range" + ], + "result_facts": { + "no_undef": false, + "range": null + } + }, + "semantics": { + "pure": false, + "memory": "none", + "convergent": true, + "execution_scope": "warp" + }, + "target": { + "minimum_ptx": "8.7", + "hardware": { + "kind": "any_of", + "alternatives": [ + { + "kind": "exact_architecture", + "sm": 120 }, { - "targets": [ - "sm_121a", - "ptx88" - ], - "representation": "exact-floor ordered kind::f8f6f4 packed-F16 PTX", - "stage": "ptx_assembly", - "mechanism": "inline_ptx", - "outcome": "succeeded", - "detail": "CUDA 13.3 ptxas produced a 9,728-byte cubin (SHA-256 acd74cced6969aaf6f09afb935d33978ed2753a7f1558240dc4607027b15d502); its 27,724-byte SASS dump (SHA-256 16087533ef8f20e8804dda13de37ea8fce10b505d82ca7c93c5d9d484b0b26e9) retains 25 unique QMMA forms.", - "artifact_kind": "cubin", - "tool_path": "/usr/local/cuda-13.3/bin/ptxas", - "tool_version": "CUDA 13.3 V13.3.33 build cuda_13.3.r13.3/compiler.37862127_0", - "tool_sha256": "7fdd01a4cf50e30746da98989c9272a907f491e6fd7fecfda14642e4375f88fb" + "kind": "family_target", + "sm": 120 }, + { + "kind": "exact_architecture", + "sm": 121 + }, + { + "kind": "family_target", + "sm": 121 + } + ] + }, + "ptx_result": "[f32; 4]", + "targets": "sm_120a|sm_120f|sm_121a|sm_121f", + "ptx_isa_version": "9.3", + "ptx_isa_section": "9.7.15.6.3 Multiply-and-Accumulate Instruction: mma.sp", + "ptx_isa_url": "https://docs.nvidia.com/cuda/parallel-thread-execution/#warp-level-matrix-instructions-mma-sp" + }, + "backend": { + "profile": "rust-llvm-23.1.0-16696adc", + "version": "LLVM version 23.1.0-rust-1.100.0-nightly", + "sha256": "2e5bc688625ca7d98bca9b5f0f0d14525d2eb59e8a9842964e480df3ffd1f921", + "status": "validated", + "target_triple": "nvptx64-nvidia-cuda", + "gpu_target": "sm_120a", + "ptx_feature": "+ptx87" + }, + "backend_lowerings": [ + { + "backend": "llvm_nvptx", + "mechanism": "inline_ptx", + "evidence_profile": "rust-llvm-23.1.0-16696adc", + "target": { + "minimum_ptx": "8.7", + "hardware": { + "kind": "any_of", + "alternatives": [ + { + "kind": "exact_architecture", + "sm": 120 + }, + { + "kind": "family_target", + "sm": 120 + }, + { + "kind": "exact_architecture", + "sm": 121 + }, + { + "kind": "family_target", + "sm": 121 + } + ] + } + }, + "version": "LLVM version 23.1.0-rust-1.100.0-nightly", + "sha256": "2e5bc688625ca7d98bca9b5f0f0d14525d2eb59e8a9842964e480df3ffd1f921", + "artifact_path": null, + "build_id_prefix": null, + "status": "validated", + "stages": [ { "targets": [ - "sm_121f", - "ptx88" + "sm_120a", + "ptx87" ], - "representation": "convergent ordered kind::f8f6f4 packed-F16 inline PTX", + "representation": "convergent ordered kind::f8f6f4 F32 inline PTX in public C, A, B, metadata, selector order", "stage": "backend_codegen", "mechanism": "inline_ptx", "outcome": "succeeded", - "detail": "Pinned LLVM emitted 8,991-byte PTX (SHA-256 fae27977151c805ee3bc805a88241f4d4318f0575c558106ed9ba6a0a94f0699) containing the exact 25-form matrix with no unresolved calls.", + "detail": "Pinned LLVM lowered the 28,839-byte all-forms source (SHA-256 5518d5dfb092f5ae3ccefe1e7e66eb4df9db7da480722e390587490c6ce8832a) to 12,015-byte PTX (SHA-256 0d93ea01d39bc512b96becf2ad799522d9d5187c17d521294eecd4e69c055e66) containing the exact 25-form matrix at sm_120a and PTX 8.7.", "artifact_kind": null, "tool_path": null, "tool_version": null, @@ -206341,14 +209555,14 @@ }, { "targets": [ - "sm_121f", - "ptx88" + "sm_120a", + "ptx87" ], - "representation": "exact-floor ordered kind::f8f6f4 packed-F16 PTX", + "representation": "exact-floor ordered kind::f8f6f4 F32 PTX", "stage": "ptx_assembly", "mechanism": "inline_ptx", "outcome": "succeeded", - "detail": "CUDA 13.3 ptxas produced a 9,728-byte cubin (SHA-256 501b5715323e83c1543a76999f6fb747c6ce1ab0be09aeb637fb95ce69cb28da); its 27,701-byte SASS dump (SHA-256 677ac56dab06986c7ec8938dcc82e23d3637bca8f58282140d0fbce8f483d353) retains 25 unique QMMA forms.", + "detail": "CUDA 13.3 ptxas produced a 12,144-byte cubin (SHA-256 7769d4fe1de8cdf6644b911bc3654ab220f4dd28cc44a83e28793a5d3f381cf3); its 38,172-byte SASS dump (SHA-256 34df448cb5d7367b36657270961981955bb76cc1dd5dd221f673f174c6e10b0a) retains 25 unique QMMA forms. PTX 8.6, sm_120, selector 1, and dynamic selectors were rejected.", "artifact_kind": "cubin", "tool_path": "/usr/local/cuda-13.3/bin/ptxas", "tool_version": "CUDA 13.3 V13.3.33 build cuda_13.3.r13.3/compiler.37862127_0", @@ -206395,11 +209609,11 @@ "compute_120a", "ptx93" ], - "representation": "convergent ordered kind::f8f6f4 packed-F16 inline PTX in public C, A, B, metadata, selector order", + "representation": "convergent ordered kind::f8f6f4 F32 inline PTX in public C, A, B, metadata, selector order", "stage": "backend_codegen", "mechanism": "inline_ptx", "outcome": "succeeded", - "detail": "CUDA 13.3 libNVVM retained the exact 25-form matrix in 8,886-byte PTX (SHA-256 fe613b565fd6028eaaff9b7df078c93af5b47163f19a9685a43bd6dee28fea6d), produced 11,504-byte LTOIR (SHA-256 aac8c70c26474ccd692e45a453d9f7236c8e040d66dd47047b582524d9deff4c), and emitted no unresolved llvm.nvvm calls or extern declarations.", + "detail": "CUDA 13.3 libNVVM retained the exact 25-form matrix in 11,910-byte PTX (SHA-256 a096494f6b066927107cf222f784d1a586ed1cf3ab766669b741e429f03f4427) and produced 14,052-byte LTOIR (SHA-256 99941daa24a78884788ed0908a3764f596c527e6ab621d6085c549aea9575377).", "artifact_kind": null, "tool_path": null, "tool_version": null, @@ -206410,11 +209624,11 @@ "sm_120a", "ptx93" ], - "representation": "libNVVM-emitted ordered kind::f8f6f4 packed-F16 PTX", + "representation": "libNVVM-emitted ordered kind::f8f6f4 F32 PTX", "stage": "ptx_assembly", "mechanism": "inline_ptx", "outcome": "succeeded", - "detail": "CUDA 13.3 ptxas produced a 9,728-byte cubin (SHA-256 560446ab6b41e45ca208fddc2c1439d9e851b1b67a9de920e6e81026863352b2) retaining all 25 unique QMMA forms; the 27,724-byte SASS dump has SHA-256 3c27689195cd558cd3df06db75ba6e46b1905d39e636536c0a52e01ba3323270.", + "detail": "CUDA 13.3 ptxas produced a 12,144-byte cubin (SHA-256 7769d4fe1de8cdf6644b911bc3654ab220f4dd28cc44a83e28793a5d3f381cf3) retaining all 25 unique QMMA forms.", "artifact_kind": "cubin", "tool_path": "/usr/local/cuda-13.3/bin/ptxas", "tool_version": "CUDA 13.3 V13.3.33 build cuda_13.3.r13.3/compiler.37862127_0", @@ -206425,148 +209639,13 @@ "sm_120a", "ptx93" ], - "representation": "libNVVM LTOIR retaining the ordered kind::f8f6f4 packed-F16 matrix", - "stage": "device_link", - "mechanism": "inline_ptx", - "outcome": "succeeded", - "detail": "CUDA 13.3 nvJitLink produced a 9,856-byte cubin (SHA-256 a7acfd0a342d4b87745305a9c0eb0b7fc1a4e6a8afffdd63bfcbc6a9188a35fb); its 27,724-byte SASS dump (SHA-256 3c27689195cd558cd3df06db75ba6e46b1905d39e636536c0a52e01ba3323270) retains 25 unique QMMA forms.", - "artifact_kind": "cubin", - "tool_path": "/usr/local/cuda-13.3/targets/x86_64-linux/lib/libnvJitLink.so.13.3.33", - "tool_version": "V13.3.33", - "tool_sha256": "3ba1e744347cd68617b862eccfd98b125482e882b7a6319f42abc9a768513db8" - }, - { - "targets": [ - "compute_120f", - "ptx93" - ], - "representation": "convergent ordered kind::f8f6f4 packed-F16 inline PTX", - "stage": "backend_codegen", - "mechanism": "inline_ptx", - "outcome": "succeeded", - "detail": "CUDA 13.3 libNVVM retained the exact 25-form matrix in 8,886-byte PTX (SHA-256 51f4c9986dc2523a8745ee1a131c400b87b714f44c881d6d102b363529e1b429), produced 11,500-byte LTOIR (SHA-256 678e88e228100ca0802c84918f31d08c024a76e9078074fc6e8671b342d27a6e), and emitted no unresolved calls.", - "artifact_kind": null, - "tool_path": null, - "tool_version": null, - "tool_sha256": null - }, - { - "targets": [ - "sm_120f", - "ptx93" - ], - "representation": "libNVVM-emitted ordered kind::f8f6f4 packed-F16 PTX", - "stage": "ptx_assembly", - "mechanism": "inline_ptx", - "outcome": "succeeded", - "detail": "CUDA 13.3 ptxas produced a 9,728-byte cubin (SHA-256 90a0b9bf02df8ca3cb34f867b29b56a65d79a5c9033ea9dc5084ee210b5f6f1d); its 27,701-byte SASS dump (SHA-256 80831cd9a7cde8fd67343302591ea08a30327606719fb232d8e28e812d9c5e46) retains 25 unique QMMA forms.", - "artifact_kind": "cubin", - "tool_path": "/usr/local/cuda-13.3/bin/ptxas", - "tool_version": "CUDA 13.3 V13.3.33 build cuda_13.3.r13.3/compiler.37862127_0", - "tool_sha256": "7fdd01a4cf50e30746da98989c9272a907f491e6fd7fecfda14642e4375f88fb" - }, - { - "targets": [ - "sm_120f", - "ptx93" - ], - "representation": "libNVVM LTOIR retaining the ordered kind::f8f6f4 packed-F16 matrix", - "stage": "device_link", - "mechanism": "inline_ptx", - "outcome": "succeeded", - "detail": "CUDA 13.3 nvJitLink produced a 9,856-byte cubin (SHA-256 e3da7f6df18cbc6f195ebf2127f542d93d22301d33406ad9fc86209583209b1b); its terminal SASS matches the 27,701-byte ptxas result and retains 25 unique QMMA forms.", - "artifact_kind": "cubin", - "tool_path": "/usr/local/cuda-13.3/targets/x86_64-linux/lib/libnvJitLink.so.13.3.33", - "tool_version": "V13.3.33", - "tool_sha256": "3ba1e744347cd68617b862eccfd98b125482e882b7a6319f42abc9a768513db8" - }, - { - "targets": [ - "compute_121a", - "ptx93" - ], - "representation": "convergent ordered kind::f8f6f4 packed-F16 inline PTX", - "stage": "backend_codegen", - "mechanism": "inline_ptx", - "outcome": "succeeded", - "detail": "CUDA 13.3 libNVVM retained the exact 25-form matrix in 8,886-byte PTX (SHA-256 d667d6730fb487ff7b7812afbb66ca3ddc3ece9ee59230883d91a7286fb8cf35), produced 11,504-byte LTOIR (SHA-256 2c1de19d40ea54c10e3f7f9c5fdad148f8fed26db5a775c63301e695d4a486b8), and emitted no unresolved calls.", - "artifact_kind": null, - "tool_path": null, - "tool_version": null, - "tool_sha256": null - }, - { - "targets": [ - "sm_121a", - "ptx93" - ], - "representation": "libNVVM-emitted ordered kind::f8f6f4 packed-F16 PTX", - "stage": "ptx_assembly", - "mechanism": "inline_ptx", - "outcome": "succeeded", - "detail": "CUDA 13.3 ptxas produced a 9,728-byte cubin (SHA-256 acd74cced6969aaf6f09afb935d33978ed2753a7f1558240dc4607027b15d502); its 27,724-byte SASS dump (SHA-256 16087533ef8f20e8804dda13de37ea8fce10b505d82ca7c93c5d9d484b0b26e9) retains 25 unique QMMA forms.", - "artifact_kind": "cubin", - "tool_path": "/usr/local/cuda-13.3/bin/ptxas", - "tool_version": "CUDA 13.3 V13.3.33 build cuda_13.3.r13.3/compiler.37862127_0", - "tool_sha256": "7fdd01a4cf50e30746da98989c9272a907f491e6fd7fecfda14642e4375f88fb" - }, - { - "targets": [ - "sm_121a", - "ptx93" - ], - "representation": "libNVVM LTOIR retaining the ordered kind::f8f6f4 packed-F16 matrix", - "stage": "device_link", - "mechanism": "inline_ptx", - "outcome": "succeeded", - "detail": "CUDA 13.3 nvJitLink produced a 9,856-byte cubin (SHA-256 5686bd4d7d44b05d50052c4e12c6385af60430e6717e53c535acc7e5b17daac6); its terminal SASS matches the 27,724-byte ptxas result and retains 25 unique QMMA forms.", - "artifact_kind": "cubin", - "tool_path": "/usr/local/cuda-13.3/targets/x86_64-linux/lib/libnvJitLink.so.13.3.33", - "tool_version": "V13.3.33", - "tool_sha256": "3ba1e744347cd68617b862eccfd98b125482e882b7a6319f42abc9a768513db8" - }, - { - "targets": [ - "compute_121f", - "ptx93" - ], - "representation": "convergent ordered kind::f8f6f4 packed-F16 inline PTX", - "stage": "backend_codegen", - "mechanism": "inline_ptx", - "outcome": "succeeded", - "detail": "CUDA 13.3 libNVVM retained the exact 25-form matrix in 8,886-byte PTX (SHA-256 8a939f3816e414a14d24fe9e2bcb28b97f30db931b2c71c6c0e1c2c793329855), produced 11,500-byte LTOIR (SHA-256 778bc963dbd6301055eaf20892234aea60113ca053682d6c6010b1f1b915bcbe), and emitted no unresolved calls.", - "artifact_kind": null, - "tool_path": null, - "tool_version": null, - "tool_sha256": null - }, - { - "targets": [ - "sm_121f", - "ptx93" - ], - "representation": "libNVVM-emitted ordered kind::f8f6f4 packed-F16 PTX", - "stage": "ptx_assembly", - "mechanism": "inline_ptx", - "outcome": "succeeded", - "detail": "CUDA 13.3 ptxas produced a 9,728-byte cubin (SHA-256 501b5715323e83c1543a76999f6fb747c6ce1ab0be09aeb637fb95ce69cb28da); its 27,701-byte SASS dump (SHA-256 677ac56dab06986c7ec8938dcc82e23d3637bca8f58282140d0fbce8f483d353) retains 25 unique QMMA forms.", - "artifact_kind": "cubin", - "tool_path": "/usr/local/cuda-13.3/bin/ptxas", - "tool_version": "CUDA 13.3 V13.3.33 build cuda_13.3.r13.3/compiler.37862127_0", - "tool_sha256": "7fdd01a4cf50e30746da98989c9272a907f491e6fd7fecfda14642e4375f88fb" - }, - { - "targets": [ - "sm_121f", - "ptx93" - ], - "representation": "libNVVM LTOIR retaining the ordered kind::f8f6f4 packed-F16 matrix", + "representation": "libNVVM LTOIR retaining the ordered kind::f8f6f4 F32 matrix", "stage": "device_link", "mechanism": "inline_ptx", "outcome": "succeeded", - "detail": "CUDA 13.3 nvJitLink produced a 9,856-byte cubin (SHA-256 7dbcfbe36d9fca5c8916689289754c0041ace50971ff0f9a337c649bc326e2f5); its terminal SASS matches the 27,701-byte ptxas result and retains 25 unique QMMA forms.", + "detail": "CUDA 13.3 nvJitLink produced a 12,144-byte cubin (SHA-256 62457debbb99023b09b3701e14974a97cfc5761f931ebf9f0d9e2bada3e3a642); its 38,172-byte SASS dump (SHA-256 34df448cb5d7367b36657270961981955bb76cc1dd5dd221f673f174c6e10b0a) retains 25 unique QMMA forms.", "artifact_kind": "cubin", - "tool_path": "/usr/local/cuda-13.3/targets/x86_64-linux/lib/libnvJitLink.so.13.3.33", + "tool_path": "/usr/local/cuda-13.3/lib64/libnvJitLink.so.13.3.33", "tool_version": "V13.3.33", "tool_sha256": "3ba1e744347cd68617b862eccfd98b125482e882b7a6319f42abc9a768513db8" } @@ -206575,17 +209654,17 @@ ], "sparse_mma": { "shape": "m16n8k64", - "accumulator": "f16", - "a_element": "e5m2", - "b_element": "e5m2", + "accumulator": "f32", + "a_element": "e2m1", + "b_element": "e2m3", "a_layout": "row", "b_layout": "col", "overflow": "not_applicable", "metadata": "ordered", "selector": "immediate_zero", "participation": "all_warp_lanes_same_instruction_and_qualifiers_no_exited_lanes", - "adapter": "c2_u32_a4_u32_b4_u32_metadata_u32_selector_u32_to_d2_u32", - "llvm_adapter": "a4_i32_b4_i32_c2_v2_f16_metadata_i32_selector_i32_to_d2_v2_f16", + "adapter": "c4_f32_a4_u32_b4_u32_metadata_u32_selector_u32_to_d4_f32", + "llvm_adapter": "a4_i32_b4_i32_c4_f32_metadata_i32_selector_i32_to_d4_f32", "compatibility_source": "generated_stub", "runtime_validation": "unexecuted" }, @@ -206600,15 +209679,15 @@ "row", "col", "kind::f8f6f4", - "f16", - "e5m2", - "e5m2", - "f16" + "f32", + "e2m1", + "e2m3", + "f32" ], "operands": [ { "kind": "register_list", - "length": 2 + "length": 4 }, { "kind": "register_list", @@ -206620,7 +209699,7 @@ }, { "kind": "register_list", - "length": 2 + "length": 4 }, { "kind": "register" @@ -206630,29 +209709,29 @@ } ] }, - "summary": "Multiplies warp-distributed sparse e5m2 A and e5m2 B fragments and adds a packed F16 accumulator." + "summary": "Multiplies warp-distributed sparse e2m1 A and e2m3 B fragments and adds an f32 accumulator." }, { - "id": "mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e2m1_e2m1_f32", - "operation_key": "matrix.mma.sp.m16n8k64.row.col.kind_f8f6f4.f32.e2m1.e2m1.f32.not_applicable.ordered_metadata", + "id": "mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e2m1_e3m2_f32", + "operation_key": "matrix.mma.sp.m16n8k64.row.col.kind_f8f6f4.f32.e2m1.e3m2.f32.not_applicable.ordered_metadata", "family": "sparse_mma", "source": { "kind": "llvm_imported", - "source_record": "int_nvvm_mma_sp_ordered_metadata_m16n8k64_row_col_kind_f8f6f4_f32_e2m1_e2m1_f32" + "source_record": "int_nvvm_mma_sp_ordered_metadata_m16n8k64_row_col_kind_f8f6f4_f32_e2m1_e3m2_f32" }, "selections": [ { - "source_record": "anonymous_19940", - "asm": "mma.sp::ordered_metadata.sync.aligned.m16n8k64.row.col.kind::f8f6f4.f32.e2m1.e2m1.f32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1, $rb2, $rb3}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}},\n\t\t$metadata,\n\t\t$selector;", + "source_record": "anonymous_19924", + "asm": "mma.sp::ordered_metadata.sync.aligned.m16n8k64.row.col.kind::f8f6f4.f32.e2m1.e3m2.f32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1, $rb2, $rb3}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}},\n\t\t$metadata,\n\t\t$selector;", "predicates": [ "Subtarget->hasMMABlockScale()" ] } ], "rust": { - "abi_id": "i0227", + "abi_id": "i0229", "module": "matrix", - "name": "mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e2m1_e2m1_f32", + "name": "mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e2m1_e3m2_f32", "arguments": [ "[f32; 4]", "[u32; 4]", @@ -206664,10 +209743,10 @@ "safe": false, "must_use": true, "safe_allowlist_reason": null, - "canonical_path": "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0227", - "public_path": "cuda_intrinsics::matrix::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e2m1_e2m1_f32", + "canonical_path": "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0229", + "public_path": "cuda_intrinsics::matrix::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e2m1_e3m2_f32", "compatibility_paths": [ - "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e2m1_e2m1_f32" + "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e2m1_e3m2_f32" ] }, "dialect": { @@ -206697,7 +209776,7 @@ ] }, "llvm": { - "symbol": "llvm.nvvm.mma.sp.ordered.metadata.m16n8k64.row.col.kind.f8f6f4.f32.e2m1.e2m1.f32", + "symbol": "llvm.nvvm.mma.sp.ordered.metadata.m16n8k64.row.col.kind.f8f6f4.f32.e2m1.e3m2.f32", "arguments": [ "i32", "i32", @@ -206928,7 +210007,7 @@ "shape": "m16n8k64", "accumulator": "f32", "a_element": "e2m1", - "b_element": "e2m1", + "b_element": "e3m2", "a_layout": "row", "b_layout": "col", "overflow": "not_applicable", @@ -206953,7 +210032,7 @@ "kind::f8f6f4", "f32", "e2m1", - "e2m1", + "e3m2", "f32" ], "operands": [ @@ -206981,29 +210060,29 @@ } ] }, - "summary": "Multiplies warp-distributed sparse e2m1 A and e2m1 B fragments and adds an f32 accumulator." + "summary": "Multiplies warp-distributed sparse e2m1 A and e3m2 B fragments and adds an f32 accumulator." }, { - "id": "mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e2m1_e2m3_f32", - "operation_key": "matrix.mma.sp.m16n8k64.row.col.kind_f8f6f4.f32.e2m1.e2m3.f32.not_applicable.ordered_metadata", + "id": "mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e2m1_e4m3_f32", + "operation_key": "matrix.mma.sp.m16n8k64.row.col.kind_f8f6f4.f32.e2m1.e4m3.f32.not_applicable.ordered_metadata", "family": "sparse_mma", "source": { "kind": "llvm_imported", - "source_record": "int_nvvm_mma_sp_ordered_metadata_m16n8k64_row_col_kind_f8f6f4_f32_e2m1_e2m3_f32" + "source_record": "int_nvvm_mma_sp_ordered_metadata_m16n8k64_row_col_kind_f8f6f4_f32_e2m1_e4m3_f32" }, "selections": [ { - "source_record": "anonymous_19932", - "asm": "mma.sp::ordered_metadata.sync.aligned.m16n8k64.row.col.kind::f8f6f4.f32.e2m1.e2m3.f32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1, $rb2, $rb3}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}},\n\t\t$metadata,\n\t\t$selector;", + "source_record": "anonymous_19908", + "asm": "mma.sp::ordered_metadata.sync.aligned.m16n8k64.row.col.kind::f8f6f4.f32.e2m1.e4m3.f32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1, $rb2, $rb3}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}},\n\t\t$metadata,\n\t\t$selector;", "predicates": [ "Subtarget->hasMMABlockScale()" ] } ], "rust": { - "abi_id": "i0228", + "abi_id": "i0230", "module": "matrix", - "name": "mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e2m1_e2m3_f32", + "name": "mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e2m1_e4m3_f32", "arguments": [ "[f32; 4]", "[u32; 4]", @@ -207015,10 +210094,10 @@ "safe": false, "must_use": true, "safe_allowlist_reason": null, - "canonical_path": "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0228", - "public_path": "cuda_intrinsics::matrix::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e2m1_e2m3_f32", + "canonical_path": "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0230", + "public_path": "cuda_intrinsics::matrix::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e2m1_e4m3_f32", "compatibility_paths": [ - "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e2m1_e2m3_f32" + "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e2m1_e4m3_f32" ] }, "dialect": { @@ -207048,7 +210127,7 @@ ] }, "llvm": { - "symbol": "llvm.nvvm.mma.sp.ordered.metadata.m16n8k64.row.col.kind.f8f6f4.f32.e2m1.e2m3.f32", + "symbol": "llvm.nvvm.mma.sp.ordered.metadata.m16n8k64.row.col.kind.f8f6f4.f32.e2m1.e4m3.f32", "arguments": [ "i32", "i32", @@ -207279,7 +210358,7 @@ "shape": "m16n8k64", "accumulator": "f32", "a_element": "e2m1", - "b_element": "e2m3", + "b_element": "e4m3", "a_layout": "row", "b_layout": "col", "overflow": "not_applicable", @@ -207304,7 +210383,7 @@ "kind::f8f6f4", "f32", "e2m1", - "e2m3", + "e4m3", "f32" ], "operands": [ @@ -207332,29 +210411,29 @@ } ] }, - "summary": "Multiplies warp-distributed sparse e2m1 A and e2m3 B fragments and adds an f32 accumulator." + "summary": "Multiplies warp-distributed sparse e2m1 A and e4m3 B fragments and adds an f32 accumulator." }, { - "id": "mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e2m1_e3m2_f32", - "operation_key": "matrix.mma.sp.m16n8k64.row.col.kind_f8f6f4.f32.e2m1.e3m2.f32.not_applicable.ordered_metadata", + "id": "mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e2m1_e5m2_f32", + "operation_key": "matrix.mma.sp.m16n8k64.row.col.kind_f8f6f4.f32.e2m1.e5m2.f32.not_applicable.ordered_metadata", "family": "sparse_mma", "source": { "kind": "llvm_imported", - "source_record": "int_nvvm_mma_sp_ordered_metadata_m16n8k64_row_col_kind_f8f6f4_f32_e2m1_e3m2_f32" + "source_record": "int_nvvm_mma_sp_ordered_metadata_m16n8k64_row_col_kind_f8f6f4_f32_e2m1_e5m2_f32" }, "selections": [ { - "source_record": "anonymous_19924", - "asm": "mma.sp::ordered_metadata.sync.aligned.m16n8k64.row.col.kind::f8f6f4.f32.e2m1.e3m2.f32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1, $rb2, $rb3}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}},\n\t\t$metadata,\n\t\t$selector;", + "source_record": "anonymous_19916", + "asm": "mma.sp::ordered_metadata.sync.aligned.m16n8k64.row.col.kind::f8f6f4.f32.e2m1.e5m2.f32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1, $rb2, $rb3}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}},\n\t\t$metadata,\n\t\t$selector;", "predicates": [ "Subtarget->hasMMABlockScale()" ] } ], "rust": { - "abi_id": "i0229", + "abi_id": "i0231", "module": "matrix", - "name": "mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e2m1_e3m2_f32", + "name": "mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e2m1_e5m2_f32", "arguments": [ "[f32; 4]", "[u32; 4]", @@ -207366,10 +210445,10 @@ "safe": false, "must_use": true, "safe_allowlist_reason": null, - "canonical_path": "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0229", - "public_path": "cuda_intrinsics::matrix::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e2m1_e3m2_f32", + "canonical_path": "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0231", + "public_path": "cuda_intrinsics::matrix::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e2m1_e5m2_f32", "compatibility_paths": [ - "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e2m1_e3m2_f32" + "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e2m1_e5m2_f32" ] }, "dialect": { @@ -207399,7 +210478,7 @@ ] }, "llvm": { - "symbol": "llvm.nvvm.mma.sp.ordered.metadata.m16n8k64.row.col.kind.f8f6f4.f32.e2m1.e3m2.f32", + "symbol": "llvm.nvvm.mma.sp.ordered.metadata.m16n8k64.row.col.kind.f8f6f4.f32.e2m1.e5m2.f32", "arguments": [ "i32", "i32", @@ -207630,7 +210709,7 @@ "shape": "m16n8k64", "accumulator": "f32", "a_element": "e2m1", - "b_element": "e3m2", + "b_element": "e5m2", "a_layout": "row", "b_layout": "col", "overflow": "not_applicable", @@ -207655,7 +210734,7 @@ "kind::f8f6f4", "f32", "e2m1", - "e3m2", + "e5m2", "f32" ], "operands": [ @@ -207683,29 +210762,29 @@ } ] }, - "summary": "Multiplies warp-distributed sparse e2m1 A and e3m2 B fragments and adds an f32 accumulator." + "summary": "Multiplies warp-distributed sparse e2m1 A and e5m2 B fragments and adds an f32 accumulator." }, { - "id": "mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e2m1_e4m3_f32", - "operation_key": "matrix.mma.sp.m16n8k64.row.col.kind_f8f6f4.f32.e2m1.e4m3.f32.not_applicable.ordered_metadata", + "id": "mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e2m3_e2m1_f32", + "operation_key": "matrix.mma.sp.m16n8k64.row.col.kind_f8f6f4.f32.e2m3.e2m1.f32.not_applicable.ordered_metadata", "family": "sparse_mma", "source": { "kind": "llvm_imported", - "source_record": "int_nvvm_mma_sp_ordered_metadata_m16n8k64_row_col_kind_f8f6f4_f32_e2m1_e4m3_f32" + "source_record": "int_nvvm_mma_sp_ordered_metadata_m16n8k64_row_col_kind_f8f6f4_f32_e2m3_e2m1_f32" }, "selections": [ { - "source_record": "anonymous_19908", - "asm": "mma.sp::ordered_metadata.sync.aligned.m16n8k64.row.col.kind::f8f6f4.f32.e2m1.e4m3.f32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1, $rb2, $rb3}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}},\n\t\t$metadata,\n\t\t$selector;", + "source_record": "anonymous_19899", + "asm": "mma.sp::ordered_metadata.sync.aligned.m16n8k64.row.col.kind::f8f6f4.f32.e2m3.e2m1.f32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1, $rb2, $rb3}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}},\n\t\t$metadata,\n\t\t$selector;", "predicates": [ "Subtarget->hasMMABlockScale()" ] } ], "rust": { - "abi_id": "i0230", + "abi_id": "i0232", "module": "matrix", - "name": "mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e2m1_e4m3_f32", + "name": "mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e2m3_e2m1_f32", "arguments": [ "[f32; 4]", "[u32; 4]", @@ -207717,10 +210796,10 @@ "safe": false, "must_use": true, "safe_allowlist_reason": null, - "canonical_path": "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0230", - "public_path": "cuda_intrinsics::matrix::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e2m1_e4m3_f32", + "canonical_path": "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0232", + "public_path": "cuda_intrinsics::matrix::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e2m3_e2m1_f32", "compatibility_paths": [ - "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e2m1_e4m3_f32" + "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e2m3_e2m1_f32" ] }, "dialect": { @@ -207750,7 +210829,7 @@ ] }, "llvm": { - "symbol": "llvm.nvvm.mma.sp.ordered.metadata.m16n8k64.row.col.kind.f8f6f4.f32.e2m1.e4m3.f32", + "symbol": "llvm.nvvm.mma.sp.ordered.metadata.m16n8k64.row.col.kind.f8f6f4.f32.e2m3.e2m1.f32", "arguments": [ "i32", "i32", @@ -207980,8 +211059,8 @@ "sparse_mma": { "shape": "m16n8k64", "accumulator": "f32", - "a_element": "e2m1", - "b_element": "e4m3", + "a_element": "e2m3", + "b_element": "e2m1", "a_layout": "row", "b_layout": "col", "overflow": "not_applicable", @@ -208005,8 +211084,8 @@ "col", "kind::f8f6f4", "f32", + "e2m3", "e2m1", - "e4m3", "f32" ], "operands": [ @@ -208034,29 +211113,29 @@ } ] }, - "summary": "Multiplies warp-distributed sparse e2m1 A and e4m3 B fragments and adds an f32 accumulator." + "summary": "Multiplies warp-distributed sparse e2m3 A and e2m1 B fragments and adds an f32 accumulator." }, { - "id": "mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e2m1_e5m2_f32", - "operation_key": "matrix.mma.sp.m16n8k64.row.col.kind_f8f6f4.f32.e2m1.e5m2.f32.not_applicable.ordered_metadata", + "id": "mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e2m3_e2m3_f32", + "operation_key": "matrix.mma.sp.m16n8k64.row.col.kind_f8f6f4.f32.e2m3.e2m3.f32.not_applicable.ordered_metadata", "family": "sparse_mma", "source": { "kind": "llvm_imported", - "source_record": "int_nvvm_mma_sp_ordered_metadata_m16n8k64_row_col_kind_f8f6f4_f32_e2m1_e5m2_f32" + "source_record": "int_nvvm_mma_sp_ordered_metadata_m16n8k64_row_col_kind_f8f6f4_f32_e2m3_e2m3_f32" }, "selections": [ { - "source_record": "anonymous_19916", - "asm": "mma.sp::ordered_metadata.sync.aligned.m16n8k64.row.col.kind::f8f6f4.f32.e2m1.e5m2.f32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1, $rb2, $rb3}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}},\n\t\t$metadata,\n\t\t$selector;", + "source_record": "anonymous_19891", + "asm": "mma.sp::ordered_metadata.sync.aligned.m16n8k64.row.col.kind::f8f6f4.f32.e2m3.e2m3.f32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1, $rb2, $rb3}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}},\n\t\t$metadata,\n\t\t$selector;", "predicates": [ "Subtarget->hasMMABlockScale()" ] } ], "rust": { - "abi_id": "i0231", + "abi_id": "i0233", "module": "matrix", - "name": "mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e2m1_e5m2_f32", + "name": "mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e2m3_e2m3_f32", "arguments": [ "[f32; 4]", "[u32; 4]", @@ -208068,10 +211147,10 @@ "safe": false, "must_use": true, "safe_allowlist_reason": null, - "canonical_path": "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0231", - "public_path": "cuda_intrinsics::matrix::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e2m1_e5m2_f32", + "canonical_path": "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0233", + "public_path": "cuda_intrinsics::matrix::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e2m3_e2m3_f32", "compatibility_paths": [ - "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e2m1_e5m2_f32" + "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e2m3_e2m3_f32" ] }, "dialect": { @@ -208101,7 +211180,7 @@ ] }, "llvm": { - "symbol": "llvm.nvvm.mma.sp.ordered.metadata.m16n8k64.row.col.kind.f8f6f4.f32.e2m1.e5m2.f32", + "symbol": "llvm.nvvm.mma.sp.ordered.metadata.m16n8k64.row.col.kind.f8f6f4.f32.e2m3.e2m3.f32", "arguments": [ "i32", "i32", @@ -208331,8 +211410,8 @@ "sparse_mma": { "shape": "m16n8k64", "accumulator": "f32", - "a_element": "e2m1", - "b_element": "e5m2", + "a_element": "e2m3", + "b_element": "e2m3", "a_layout": "row", "b_layout": "col", "overflow": "not_applicable", @@ -208356,8 +211435,8 @@ "col", "kind::f8f6f4", "f32", - "e2m1", - "e5m2", + "e2m3", + "e2m3", "f32" ], "operands": [ @@ -208385,29 +211464,29 @@ } ] }, - "summary": "Multiplies warp-distributed sparse e2m1 A and e5m2 B fragments and adds an f32 accumulator." + "summary": "Multiplies warp-distributed sparse e2m3 A and e2m3 B fragments and adds an f32 accumulator." }, { - "id": "mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e2m3_e2m1_f32", - "operation_key": "matrix.mma.sp.m16n8k64.row.col.kind_f8f6f4.f32.e2m3.e2m1.f32.not_applicable.ordered_metadata", + "id": "mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e2m3_e3m2_f32", + "operation_key": "matrix.mma.sp.m16n8k64.row.col.kind_f8f6f4.f32.e2m3.e3m2.f32.not_applicable.ordered_metadata", "family": "sparse_mma", "source": { "kind": "llvm_imported", - "source_record": "int_nvvm_mma_sp_ordered_metadata_m16n8k64_row_col_kind_f8f6f4_f32_e2m3_e2m1_f32" + "source_record": "int_nvvm_mma_sp_ordered_metadata_m16n8k64_row_col_kind_f8f6f4_f32_e2m3_e3m2_f32" }, "selections": [ { - "source_record": "anonymous_19899", - "asm": "mma.sp::ordered_metadata.sync.aligned.m16n8k64.row.col.kind::f8f6f4.f32.e2m3.e2m1.f32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1, $rb2, $rb3}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}},\n\t\t$metadata,\n\t\t$selector;", + "source_record": "anonymous_19883", + "asm": "mma.sp::ordered_metadata.sync.aligned.m16n8k64.row.col.kind::f8f6f4.f32.e2m3.e3m2.f32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1, $rb2, $rb3}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}},\n\t\t$metadata,\n\t\t$selector;", "predicates": [ "Subtarget->hasMMABlockScale()" ] } ], "rust": { - "abi_id": "i0232", + "abi_id": "i0234", "module": "matrix", - "name": "mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e2m3_e2m1_f32", + "name": "mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e2m3_e3m2_f32", "arguments": [ "[f32; 4]", "[u32; 4]", @@ -208419,10 +211498,10 @@ "safe": false, "must_use": true, "safe_allowlist_reason": null, - "canonical_path": "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0232", - "public_path": "cuda_intrinsics::matrix::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e2m3_e2m1_f32", + "canonical_path": "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0234", + "public_path": "cuda_intrinsics::matrix::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e2m3_e3m2_f32", "compatibility_paths": [ - "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e2m3_e2m1_f32" + "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e2m3_e3m2_f32" ] }, "dialect": { @@ -208452,7 +211531,7 @@ ] }, "llvm": { - "symbol": "llvm.nvvm.mma.sp.ordered.metadata.m16n8k64.row.col.kind.f8f6f4.f32.e2m3.e2m1.f32", + "symbol": "llvm.nvvm.mma.sp.ordered.metadata.m16n8k64.row.col.kind.f8f6f4.f32.e2m3.e3m2.f32", "arguments": [ "i32", "i32", @@ -208683,7 +211762,7 @@ "shape": "m16n8k64", "accumulator": "f32", "a_element": "e2m3", - "b_element": "e2m1", + "b_element": "e3m2", "a_layout": "row", "b_layout": "col", "overflow": "not_applicable", @@ -208708,7 +211787,7 @@ "kind::f8f6f4", "f32", "e2m3", - "e2m1", + "e3m2", "f32" ], "operands": [ @@ -208736,29 +211815,29 @@ } ] }, - "summary": "Multiplies warp-distributed sparse e2m3 A and e2m1 B fragments and adds an f32 accumulator." + "summary": "Multiplies warp-distributed sparse e2m3 A and e3m2 B fragments and adds an f32 accumulator." }, { - "id": "mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e2m3_e2m3_f32", - "operation_key": "matrix.mma.sp.m16n8k64.row.col.kind_f8f6f4.f32.e2m3.e2m3.f32.not_applicable.ordered_metadata", + "id": "mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e2m3_e4m3_f32", + "operation_key": "matrix.mma.sp.m16n8k64.row.col.kind_f8f6f4.f32.e2m3.e4m3.f32.not_applicable.ordered_metadata", "family": "sparse_mma", "source": { "kind": "llvm_imported", - "source_record": "int_nvvm_mma_sp_ordered_metadata_m16n8k64_row_col_kind_f8f6f4_f32_e2m3_e2m3_f32" + "source_record": "int_nvvm_mma_sp_ordered_metadata_m16n8k64_row_col_kind_f8f6f4_f32_e2m3_e4m3_f32" }, "selections": [ { - "source_record": "anonymous_19891", - "asm": "mma.sp::ordered_metadata.sync.aligned.m16n8k64.row.col.kind::f8f6f4.f32.e2m3.e2m3.f32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1, $rb2, $rb3}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}},\n\t\t$metadata,\n\t\t$selector;", + "source_record": "anonymous_19867", + "asm": "mma.sp::ordered_metadata.sync.aligned.m16n8k64.row.col.kind::f8f6f4.f32.e2m3.e4m3.f32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1, $rb2, $rb3}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}},\n\t\t$metadata,\n\t\t$selector;", "predicates": [ "Subtarget->hasMMABlockScale()" ] } ], "rust": { - "abi_id": "i0233", + "abi_id": "i0235", "module": "matrix", - "name": "mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e2m3_e2m3_f32", + "name": "mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e2m3_e4m3_f32", "arguments": [ "[f32; 4]", "[u32; 4]", @@ -208770,10 +211849,10 @@ "safe": false, "must_use": true, "safe_allowlist_reason": null, - "canonical_path": "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0233", - "public_path": "cuda_intrinsics::matrix::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e2m3_e2m3_f32", + "canonical_path": "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0235", + "public_path": "cuda_intrinsics::matrix::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e2m3_e4m3_f32", "compatibility_paths": [ - "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e2m3_e2m3_f32" + "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e2m3_e4m3_f32" ] }, "dialect": { @@ -208803,7 +211882,7 @@ ] }, "llvm": { - "symbol": "llvm.nvvm.mma.sp.ordered.metadata.m16n8k64.row.col.kind.f8f6f4.f32.e2m3.e2m3.f32", + "symbol": "llvm.nvvm.mma.sp.ordered.metadata.m16n8k64.row.col.kind.f8f6f4.f32.e2m3.e4m3.f32", "arguments": [ "i32", "i32", @@ -209034,7 +212113,7 @@ "shape": "m16n8k64", "accumulator": "f32", "a_element": "e2m3", - "b_element": "e2m3", + "b_element": "e4m3", "a_layout": "row", "b_layout": "col", "overflow": "not_applicable", @@ -209059,7 +212138,7 @@ "kind::f8f6f4", "f32", "e2m3", - "e2m3", + "e4m3", "f32" ], "operands": [ @@ -209087,29 +212166,29 @@ } ] }, - "summary": "Multiplies warp-distributed sparse e2m3 A and e2m3 B fragments and adds an f32 accumulator." + "summary": "Multiplies warp-distributed sparse e2m3 A and e4m3 B fragments and adds an f32 accumulator." }, { - "id": "mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e2m3_e3m2_f32", - "operation_key": "matrix.mma.sp.m16n8k64.row.col.kind_f8f6f4.f32.e2m3.e3m2.f32.not_applicable.ordered_metadata", + "id": "mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e2m3_e5m2_f32", + "operation_key": "matrix.mma.sp.m16n8k64.row.col.kind_f8f6f4.f32.e2m3.e5m2.f32.not_applicable.ordered_metadata", "family": "sparse_mma", "source": { "kind": "llvm_imported", - "source_record": "int_nvvm_mma_sp_ordered_metadata_m16n8k64_row_col_kind_f8f6f4_f32_e2m3_e3m2_f32" + "source_record": "int_nvvm_mma_sp_ordered_metadata_m16n8k64_row_col_kind_f8f6f4_f32_e2m3_e5m2_f32" }, "selections": [ { - "source_record": "anonymous_19883", - "asm": "mma.sp::ordered_metadata.sync.aligned.m16n8k64.row.col.kind::f8f6f4.f32.e2m3.e3m2.f32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1, $rb2, $rb3}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}},\n\t\t$metadata,\n\t\t$selector;", + "source_record": "anonymous_19875", + "asm": "mma.sp::ordered_metadata.sync.aligned.m16n8k64.row.col.kind::f8f6f4.f32.e2m3.e5m2.f32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1, $rb2, $rb3}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}},\n\t\t$metadata,\n\t\t$selector;", "predicates": [ "Subtarget->hasMMABlockScale()" ] } ], "rust": { - "abi_id": "i0234", + "abi_id": "i0236", "module": "matrix", - "name": "mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e2m3_e3m2_f32", + "name": "mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e2m3_e5m2_f32", "arguments": [ "[f32; 4]", "[u32; 4]", @@ -209121,10 +212200,10 @@ "safe": false, "must_use": true, "safe_allowlist_reason": null, - "canonical_path": "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0234", - "public_path": "cuda_intrinsics::matrix::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e2m3_e3m2_f32", + "canonical_path": "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0236", + "public_path": "cuda_intrinsics::matrix::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e2m3_e5m2_f32", "compatibility_paths": [ - "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e2m3_e3m2_f32" + "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e2m3_e5m2_f32" ] }, "dialect": { @@ -209154,7 +212233,7 @@ ] }, "llvm": { - "symbol": "llvm.nvvm.mma.sp.ordered.metadata.m16n8k64.row.col.kind.f8f6f4.f32.e2m3.e3m2.f32", + "symbol": "llvm.nvvm.mma.sp.ordered.metadata.m16n8k64.row.col.kind.f8f6f4.f32.e2m3.e5m2.f32", "arguments": [ "i32", "i32", @@ -209385,7 +212464,7 @@ "shape": "m16n8k64", "accumulator": "f32", "a_element": "e2m3", - "b_element": "e3m2", + "b_element": "e5m2", "a_layout": "row", "b_layout": "col", "overflow": "not_applicable", @@ -209410,7 +212489,7 @@ "kind::f8f6f4", "f32", "e2m3", - "e3m2", + "e5m2", "f32" ], "operands": [ @@ -209438,29 +212517,29 @@ } ] }, - "summary": "Multiplies warp-distributed sparse e2m3 A and e3m2 B fragments and adds an f32 accumulator." + "summary": "Multiplies warp-distributed sparse e2m3 A and e5m2 B fragments and adds an f32 accumulator." }, { - "id": "mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e2m3_e4m3_f32", - "operation_key": "matrix.mma.sp.m16n8k64.row.col.kind_f8f6f4.f32.e2m3.e4m3.f32.not_applicable.ordered_metadata", + "id": "mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e3m2_e2m1_f32", + "operation_key": "matrix.mma.sp.m16n8k64.row.col.kind_f8f6f4.f32.e3m2.e2m1.f32.not_applicable.ordered_metadata", "family": "sparse_mma", "source": { "kind": "llvm_imported", - "source_record": "int_nvvm_mma_sp_ordered_metadata_m16n8k64_row_col_kind_f8f6f4_f32_e2m3_e4m3_f32" + "source_record": "int_nvvm_mma_sp_ordered_metadata_m16n8k64_row_col_kind_f8f6f4_f32_e3m2_e2m1_f32" }, "selections": [ { - "source_record": "anonymous_19867", - "asm": "mma.sp::ordered_metadata.sync.aligned.m16n8k64.row.col.kind::f8f6f4.f32.e2m3.e4m3.f32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1, $rb2, $rb3}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}},\n\t\t$metadata,\n\t\t$selector;", + "source_record": "anonymous_19858", + "asm": "mma.sp::ordered_metadata.sync.aligned.m16n8k64.row.col.kind::f8f6f4.f32.e3m2.e2m1.f32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1, $rb2, $rb3}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}},\n\t\t$metadata,\n\t\t$selector;", "predicates": [ "Subtarget->hasMMABlockScale()" ] } ], "rust": { - "abi_id": "i0235", + "abi_id": "i0237", "module": "matrix", - "name": "mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e2m3_e4m3_f32", + "name": "mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e3m2_e2m1_f32", "arguments": [ "[f32; 4]", "[u32; 4]", @@ -209472,10 +212551,10 @@ "safe": false, "must_use": true, "safe_allowlist_reason": null, - "canonical_path": "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0235", - "public_path": "cuda_intrinsics::matrix::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e2m3_e4m3_f32", + "canonical_path": "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0237", + "public_path": "cuda_intrinsics::matrix::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e3m2_e2m1_f32", "compatibility_paths": [ - "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e2m3_e4m3_f32" + "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e3m2_e2m1_f32" ] }, "dialect": { @@ -209505,7 +212584,7 @@ ] }, "llvm": { - "symbol": "llvm.nvvm.mma.sp.ordered.metadata.m16n8k64.row.col.kind.f8f6f4.f32.e2m3.e4m3.f32", + "symbol": "llvm.nvvm.mma.sp.ordered.metadata.m16n8k64.row.col.kind.f8f6f4.f32.e3m2.e2m1.f32", "arguments": [ "i32", "i32", @@ -209735,8 +212814,8 @@ "sparse_mma": { "shape": "m16n8k64", "accumulator": "f32", - "a_element": "e2m3", - "b_element": "e4m3", + "a_element": "e3m2", + "b_element": "e2m1", "a_layout": "row", "b_layout": "col", "overflow": "not_applicable", @@ -209760,8 +212839,8 @@ "col", "kind::f8f6f4", "f32", - "e2m3", - "e4m3", + "e3m2", + "e2m1", "f32" ], "operands": [ @@ -209789,29 +212868,29 @@ } ] }, - "summary": "Multiplies warp-distributed sparse e2m3 A and e4m3 B fragments and adds an f32 accumulator." + "summary": "Multiplies warp-distributed sparse e3m2 A and e2m1 B fragments and adds an f32 accumulator." }, { - "id": "mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e2m3_e5m2_f32", - "operation_key": "matrix.mma.sp.m16n8k64.row.col.kind_f8f6f4.f32.e2m3.e5m2.f32.not_applicable.ordered_metadata", + "id": "mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e3m2_e2m3_f32", + "operation_key": "matrix.mma.sp.m16n8k64.row.col.kind_f8f6f4.f32.e3m2.e2m3.f32.not_applicable.ordered_metadata", "family": "sparse_mma", "source": { "kind": "llvm_imported", - "source_record": "int_nvvm_mma_sp_ordered_metadata_m16n8k64_row_col_kind_f8f6f4_f32_e2m3_e5m2_f32" + "source_record": "int_nvvm_mma_sp_ordered_metadata_m16n8k64_row_col_kind_f8f6f4_f32_e3m2_e2m3_f32" }, "selections": [ { - "source_record": "anonymous_19875", - "asm": "mma.sp::ordered_metadata.sync.aligned.m16n8k64.row.col.kind::f8f6f4.f32.e2m3.e5m2.f32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1, $rb2, $rb3}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}},\n\t\t$metadata,\n\t\t$selector;", + "source_record": "anonymous_19850", + "asm": "mma.sp::ordered_metadata.sync.aligned.m16n8k64.row.col.kind::f8f6f4.f32.e3m2.e2m3.f32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1, $rb2, $rb3}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}},\n\t\t$metadata,\n\t\t$selector;", "predicates": [ "Subtarget->hasMMABlockScale()" ] } ], "rust": { - "abi_id": "i0236", + "abi_id": "i0238", "module": "matrix", - "name": "mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e2m3_e5m2_f32", + "name": "mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e3m2_e2m3_f32", "arguments": [ "[f32; 4]", "[u32; 4]", @@ -209823,10 +212902,10 @@ "safe": false, "must_use": true, "safe_allowlist_reason": null, - "canonical_path": "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0236", - "public_path": "cuda_intrinsics::matrix::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e2m3_e5m2_f32", + "canonical_path": "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0238", + "public_path": "cuda_intrinsics::matrix::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e3m2_e2m3_f32", "compatibility_paths": [ - "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e2m3_e5m2_f32" + "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e3m2_e2m3_f32" ] }, "dialect": { @@ -209856,7 +212935,7 @@ ] }, "llvm": { - "symbol": "llvm.nvvm.mma.sp.ordered.metadata.m16n8k64.row.col.kind.f8f6f4.f32.e2m3.e5m2.f32", + "symbol": "llvm.nvvm.mma.sp.ordered.metadata.m16n8k64.row.col.kind.f8f6f4.f32.e3m2.e2m3.f32", "arguments": [ "i32", "i32", @@ -210086,8 +213165,8 @@ "sparse_mma": { "shape": "m16n8k64", "accumulator": "f32", - "a_element": "e2m3", - "b_element": "e5m2", + "a_element": "e3m2", + "b_element": "e2m3", "a_layout": "row", "b_layout": "col", "overflow": "not_applicable", @@ -210111,8 +213190,8 @@ "col", "kind::f8f6f4", "f32", + "e3m2", "e2m3", - "e5m2", "f32" ], "operands": [ @@ -210140,29 +213219,29 @@ } ] }, - "summary": "Multiplies warp-distributed sparse e2m3 A and e5m2 B fragments and adds an f32 accumulator." + "summary": "Multiplies warp-distributed sparse e3m2 A and e2m3 B fragments and adds an f32 accumulator." }, { - "id": "mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e3m2_e2m1_f32", - "operation_key": "matrix.mma.sp.m16n8k64.row.col.kind_f8f6f4.f32.e3m2.e2m1.f32.not_applicable.ordered_metadata", + "id": "mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e3m2_e3m2_f32", + "operation_key": "matrix.mma.sp.m16n8k64.row.col.kind_f8f6f4.f32.e3m2.e3m2.f32.not_applicable.ordered_metadata", "family": "sparse_mma", "source": { "kind": "llvm_imported", - "source_record": "int_nvvm_mma_sp_ordered_metadata_m16n8k64_row_col_kind_f8f6f4_f32_e3m2_e2m1_f32" + "source_record": "int_nvvm_mma_sp_ordered_metadata_m16n8k64_row_col_kind_f8f6f4_f32_e3m2_e3m2_f32" }, "selections": [ { - "source_record": "anonymous_19858", - "asm": "mma.sp::ordered_metadata.sync.aligned.m16n8k64.row.col.kind::f8f6f4.f32.e3m2.e2m1.f32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1, $rb2, $rb3}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}},\n\t\t$metadata,\n\t\t$selector;", + "source_record": "anonymous_19842", + "asm": "mma.sp::ordered_metadata.sync.aligned.m16n8k64.row.col.kind::f8f6f4.f32.e3m2.e3m2.f32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1, $rb2, $rb3}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}},\n\t\t$metadata,\n\t\t$selector;", "predicates": [ "Subtarget->hasMMABlockScale()" ] } ], "rust": { - "abi_id": "i0237", + "abi_id": "i0239", "module": "matrix", - "name": "mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e3m2_e2m1_f32", + "name": "mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e3m2_e3m2_f32", "arguments": [ "[f32; 4]", "[u32; 4]", @@ -210174,10 +213253,10 @@ "safe": false, "must_use": true, "safe_allowlist_reason": null, - "canonical_path": "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0237", - "public_path": "cuda_intrinsics::matrix::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e3m2_e2m1_f32", + "canonical_path": "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0239", + "public_path": "cuda_intrinsics::matrix::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e3m2_e3m2_f32", "compatibility_paths": [ - "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e3m2_e2m1_f32" + "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e3m2_e3m2_f32" ] }, "dialect": { @@ -210207,7 +213286,7 @@ ] }, "llvm": { - "symbol": "llvm.nvvm.mma.sp.ordered.metadata.m16n8k64.row.col.kind.f8f6f4.f32.e3m2.e2m1.f32", + "symbol": "llvm.nvvm.mma.sp.ordered.metadata.m16n8k64.row.col.kind.f8f6f4.f32.e3m2.e3m2.f32", "arguments": [ "i32", "i32", @@ -210438,7 +213517,7 @@ "shape": "m16n8k64", "accumulator": "f32", "a_element": "e3m2", - "b_element": "e2m1", + "b_element": "e3m2", "a_layout": "row", "b_layout": "col", "overflow": "not_applicable", @@ -210463,7 +213542,7 @@ "kind::f8f6f4", "f32", "e3m2", - "e2m1", + "e3m2", "f32" ], "operands": [ @@ -210491,29 +213570,29 @@ } ] }, - "summary": "Multiplies warp-distributed sparse e3m2 A and e2m1 B fragments and adds an f32 accumulator." + "summary": "Multiplies warp-distributed sparse e3m2 A and e3m2 B fragments and adds an f32 accumulator." }, { - "id": "mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e3m2_e2m3_f32", - "operation_key": "matrix.mma.sp.m16n8k64.row.col.kind_f8f6f4.f32.e3m2.e2m3.f32.not_applicable.ordered_metadata", + "id": "mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e3m2_e4m3_f32", + "operation_key": "matrix.mma.sp.m16n8k64.row.col.kind_f8f6f4.f32.e3m2.e4m3.f32.not_applicable.ordered_metadata", "family": "sparse_mma", "source": { "kind": "llvm_imported", - "source_record": "int_nvvm_mma_sp_ordered_metadata_m16n8k64_row_col_kind_f8f6f4_f32_e3m2_e2m3_f32" + "source_record": "int_nvvm_mma_sp_ordered_metadata_m16n8k64_row_col_kind_f8f6f4_f32_e3m2_e4m3_f32" }, "selections": [ { - "source_record": "anonymous_19850", - "asm": "mma.sp::ordered_metadata.sync.aligned.m16n8k64.row.col.kind::f8f6f4.f32.e3m2.e2m3.f32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1, $rb2, $rb3}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}},\n\t\t$metadata,\n\t\t$selector;", + "source_record": "anonymous_19826", + "asm": "mma.sp::ordered_metadata.sync.aligned.m16n8k64.row.col.kind::f8f6f4.f32.e3m2.e4m3.f32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1, $rb2, $rb3}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}},\n\t\t$metadata,\n\t\t$selector;", "predicates": [ "Subtarget->hasMMABlockScale()" ] } ], "rust": { - "abi_id": "i0238", + "abi_id": "i0240", "module": "matrix", - "name": "mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e3m2_e2m3_f32", + "name": "mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e3m2_e4m3_f32", "arguments": [ "[f32; 4]", "[u32; 4]", @@ -210525,10 +213604,10 @@ "safe": false, "must_use": true, "safe_allowlist_reason": null, - "canonical_path": "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0238", - "public_path": "cuda_intrinsics::matrix::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e3m2_e2m3_f32", + "canonical_path": "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0240", + "public_path": "cuda_intrinsics::matrix::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e3m2_e4m3_f32", "compatibility_paths": [ - "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e3m2_e2m3_f32" + "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e3m2_e4m3_f32" ] }, "dialect": { @@ -210558,7 +213637,7 @@ ] }, "llvm": { - "symbol": "llvm.nvvm.mma.sp.ordered.metadata.m16n8k64.row.col.kind.f8f6f4.f32.e3m2.e2m3.f32", + "symbol": "llvm.nvvm.mma.sp.ordered.metadata.m16n8k64.row.col.kind.f8f6f4.f32.e3m2.e4m3.f32", "arguments": [ "i32", "i32", @@ -210789,7 +213868,7 @@ "shape": "m16n8k64", "accumulator": "f32", "a_element": "e3m2", - "b_element": "e2m3", + "b_element": "e4m3", "a_layout": "row", "b_layout": "col", "overflow": "not_applicable", @@ -210814,7 +213893,7 @@ "kind::f8f6f4", "f32", "e3m2", - "e2m3", + "e4m3", "f32" ], "operands": [ @@ -210842,29 +213921,29 @@ } ] }, - "summary": "Multiplies warp-distributed sparse e3m2 A and e2m3 B fragments and adds an f32 accumulator." + "summary": "Multiplies warp-distributed sparse e3m2 A and e4m3 B fragments and adds an f32 accumulator." }, { - "id": "mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e3m2_e3m2_f32", - "operation_key": "matrix.mma.sp.m16n8k64.row.col.kind_f8f6f4.f32.e3m2.e3m2.f32.not_applicable.ordered_metadata", + "id": "mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e3m2_e5m2_f32", + "operation_key": "matrix.mma.sp.m16n8k64.row.col.kind_f8f6f4.f32.e3m2.e5m2.f32.not_applicable.ordered_metadata", "family": "sparse_mma", "source": { "kind": "llvm_imported", - "source_record": "int_nvvm_mma_sp_ordered_metadata_m16n8k64_row_col_kind_f8f6f4_f32_e3m2_e3m2_f32" + "source_record": "int_nvvm_mma_sp_ordered_metadata_m16n8k64_row_col_kind_f8f6f4_f32_e3m2_e5m2_f32" }, "selections": [ { - "source_record": "anonymous_19842", - "asm": "mma.sp::ordered_metadata.sync.aligned.m16n8k64.row.col.kind::f8f6f4.f32.e3m2.e3m2.f32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1, $rb2, $rb3}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}},\n\t\t$metadata,\n\t\t$selector;", + "source_record": "anonymous_19834", + "asm": "mma.sp::ordered_metadata.sync.aligned.m16n8k64.row.col.kind::f8f6f4.f32.e3m2.e5m2.f32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1, $rb2, $rb3}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}},\n\t\t$metadata,\n\t\t$selector;", "predicates": [ "Subtarget->hasMMABlockScale()" ] } ], "rust": { - "abi_id": "i0239", + "abi_id": "i0241", "module": "matrix", - "name": "mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e3m2_e3m2_f32", + "name": "mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e3m2_e5m2_f32", "arguments": [ "[f32; 4]", "[u32; 4]", @@ -210876,10 +213955,10 @@ "safe": false, "must_use": true, "safe_allowlist_reason": null, - "canonical_path": "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0239", - "public_path": "cuda_intrinsics::matrix::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e3m2_e3m2_f32", + "canonical_path": "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0241", + "public_path": "cuda_intrinsics::matrix::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e3m2_e5m2_f32", "compatibility_paths": [ - "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e3m2_e3m2_f32" + "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e3m2_e5m2_f32" ] }, "dialect": { @@ -210909,7 +213988,7 @@ ] }, "llvm": { - "symbol": "llvm.nvvm.mma.sp.ordered.metadata.m16n8k64.row.col.kind.f8f6f4.f32.e3m2.e3m2.f32", + "symbol": "llvm.nvvm.mma.sp.ordered.metadata.m16n8k64.row.col.kind.f8f6f4.f32.e3m2.e5m2.f32", "arguments": [ "i32", "i32", @@ -211140,7 +214219,7 @@ "shape": "m16n8k64", "accumulator": "f32", "a_element": "e3m2", - "b_element": "e3m2", + "b_element": "e5m2", "a_layout": "row", "b_layout": "col", "overflow": "not_applicable", @@ -211165,7 +214244,7 @@ "kind::f8f6f4", "f32", "e3m2", - "e3m2", + "e5m2", "f32" ], "operands": [ @@ -211193,29 +214272,29 @@ } ] }, - "summary": "Multiplies warp-distributed sparse e3m2 A and e3m2 B fragments and adds an f32 accumulator." + "summary": "Multiplies warp-distributed sparse e3m2 A and e5m2 B fragments and adds an f32 accumulator." }, { - "id": "mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e3m2_e4m3_f32", - "operation_key": "matrix.mma.sp.m16n8k64.row.col.kind_f8f6f4.f32.e3m2.e4m3.f32.not_applicable.ordered_metadata", + "id": "mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e4m3_e2m1_f32", + "operation_key": "matrix.mma.sp.m16n8k64.row.col.kind_f8f6f4.f32.e4m3.e2m1.f32.not_applicable.ordered_metadata", "family": "sparse_mma", "source": { "kind": "llvm_imported", - "source_record": "int_nvvm_mma_sp_ordered_metadata_m16n8k64_row_col_kind_f8f6f4_f32_e3m2_e4m3_f32" + "source_record": "int_nvvm_mma_sp_ordered_metadata_m16n8k64_row_col_kind_f8f6f4_f32_e4m3_e2m1_f32" }, "selections": [ { - "source_record": "anonymous_19826", - "asm": "mma.sp::ordered_metadata.sync.aligned.m16n8k64.row.col.kind::f8f6f4.f32.e3m2.e4m3.f32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1, $rb2, $rb3}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}},\n\t\t$metadata,\n\t\t$selector;", + "source_record": "anonymous_19776", + "asm": "mma.sp::ordered_metadata.sync.aligned.m16n8k64.row.col.kind::f8f6f4.f32.e4m3.e2m1.f32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1, $rb2, $rb3}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}},\n\t\t$metadata,\n\t\t$selector;", "predicates": [ "Subtarget->hasMMABlockScale()" ] } ], "rust": { - "abi_id": "i0240", + "abi_id": "i0242", "module": "matrix", - "name": "mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e3m2_e4m3_f32", + "name": "mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e4m3_e2m1_f32", "arguments": [ "[f32; 4]", "[u32; 4]", @@ -211227,10 +214306,10 @@ "safe": false, "must_use": true, "safe_allowlist_reason": null, - "canonical_path": "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0240", - "public_path": "cuda_intrinsics::matrix::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e3m2_e4m3_f32", + "canonical_path": "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0242", + "public_path": "cuda_intrinsics::matrix::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e4m3_e2m1_f32", "compatibility_paths": [ - "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e3m2_e4m3_f32" + "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e4m3_e2m1_f32" ] }, "dialect": { @@ -211260,7 +214339,7 @@ ] }, "llvm": { - "symbol": "llvm.nvvm.mma.sp.ordered.metadata.m16n8k64.row.col.kind.f8f6f4.f32.e3m2.e4m3.f32", + "symbol": "llvm.nvvm.mma.sp.ordered.metadata.m16n8k64.row.col.kind.f8f6f4.f32.e4m3.e2m1.f32", "arguments": [ "i32", "i32", @@ -211490,8 +214569,8 @@ "sparse_mma": { "shape": "m16n8k64", "accumulator": "f32", - "a_element": "e3m2", - "b_element": "e4m3", + "a_element": "e4m3", + "b_element": "e2m1", "a_layout": "row", "b_layout": "col", "overflow": "not_applicable", @@ -211515,8 +214594,8 @@ "col", "kind::f8f6f4", "f32", - "e3m2", "e4m3", + "e2m1", "f32" ], "operands": [ @@ -211544,29 +214623,29 @@ } ] }, - "summary": "Multiplies warp-distributed sparse e3m2 A and e4m3 B fragments and adds an f32 accumulator." + "summary": "Multiplies warp-distributed sparse e4m3 A and e2m1 B fragments and adds an f32 accumulator." }, { - "id": "mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e3m2_e5m2_f32", - "operation_key": "matrix.mma.sp.m16n8k64.row.col.kind_f8f6f4.f32.e3m2.e5m2.f32.not_applicable.ordered_metadata", + "id": "mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e4m3_e2m3_f32", + "operation_key": "matrix.mma.sp.m16n8k64.row.col.kind_f8f6f4.f32.e4m3.e2m3.f32.not_applicable.ordered_metadata", "family": "sparse_mma", "source": { "kind": "llvm_imported", - "source_record": "int_nvvm_mma_sp_ordered_metadata_m16n8k64_row_col_kind_f8f6f4_f32_e3m2_e5m2_f32" + "source_record": "int_nvvm_mma_sp_ordered_metadata_m16n8k64_row_col_kind_f8f6f4_f32_e4m3_e2m3_f32" }, "selections": [ { - "source_record": "anonymous_19834", - "asm": "mma.sp::ordered_metadata.sync.aligned.m16n8k64.row.col.kind::f8f6f4.f32.e3m2.e5m2.f32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1, $rb2, $rb3}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}},\n\t\t$metadata,\n\t\t$selector;", + "source_record": "anonymous_19767", + "asm": "mma.sp::ordered_metadata.sync.aligned.m16n8k64.row.col.kind::f8f6f4.f32.e4m3.e2m3.f32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1, $rb2, $rb3}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}},\n\t\t$metadata,\n\t\t$selector;", "predicates": [ "Subtarget->hasMMABlockScale()" ] } ], "rust": { - "abi_id": "i0241", + "abi_id": "i0243", "module": "matrix", - "name": "mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e3m2_e5m2_f32", + "name": "mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e4m3_e2m3_f32", "arguments": [ "[f32; 4]", "[u32; 4]", @@ -211578,10 +214657,10 @@ "safe": false, "must_use": true, "safe_allowlist_reason": null, - "canonical_path": "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0241", - "public_path": "cuda_intrinsics::matrix::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e3m2_e5m2_f32", + "canonical_path": "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0243", + "public_path": "cuda_intrinsics::matrix::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e4m3_e2m3_f32", "compatibility_paths": [ - "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e3m2_e5m2_f32" + "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e4m3_e2m3_f32" ] }, "dialect": { @@ -211611,7 +214690,7 @@ ] }, "llvm": { - "symbol": "llvm.nvvm.mma.sp.ordered.metadata.m16n8k64.row.col.kind.f8f6f4.f32.e3m2.e5m2.f32", + "symbol": "llvm.nvvm.mma.sp.ordered.metadata.m16n8k64.row.col.kind.f8f6f4.f32.e4m3.e2m3.f32", "arguments": [ "i32", "i32", @@ -211841,8 +214920,8 @@ "sparse_mma": { "shape": "m16n8k64", "accumulator": "f32", - "a_element": "e3m2", - "b_element": "e5m2", + "a_element": "e4m3", + "b_element": "e2m3", "a_layout": "row", "b_layout": "col", "overflow": "not_applicable", @@ -211866,8 +214945,8 @@ "col", "kind::f8f6f4", "f32", - "e3m2", - "e5m2", + "e4m3", + "e2m3", "f32" ], "operands": [ @@ -211895,29 +214974,29 @@ } ] }, - "summary": "Multiplies warp-distributed sparse e3m2 A and e5m2 B fragments and adds an f32 accumulator." + "summary": "Multiplies warp-distributed sparse e4m3 A and e2m3 B fragments and adds an f32 accumulator." }, { - "id": "mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e4m3_e2m1_f32", - "operation_key": "matrix.mma.sp.m16n8k64.row.col.kind_f8f6f4.f32.e4m3.e2m1.f32.not_applicable.ordered_metadata", + "id": "mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e4m3_e3m2_f32", + "operation_key": "matrix.mma.sp.m16n8k64.row.col.kind_f8f6f4.f32.e4m3.e3m2.f32.not_applicable.ordered_metadata", "family": "sparse_mma", "source": { "kind": "llvm_imported", - "source_record": "int_nvvm_mma_sp_ordered_metadata_m16n8k64_row_col_kind_f8f6f4_f32_e4m3_e2m1_f32" + "source_record": "int_nvvm_mma_sp_ordered_metadata_m16n8k64_row_col_kind_f8f6f4_f32_e4m3_e3m2_f32" }, "selections": [ { - "source_record": "anonymous_19776", - "asm": "mma.sp::ordered_metadata.sync.aligned.m16n8k64.row.col.kind::f8f6f4.f32.e4m3.e2m1.f32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1, $rb2, $rb3}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}},\n\t\t$metadata,\n\t\t$selector;", + "source_record": "anonymous_19758", + "asm": "mma.sp::ordered_metadata.sync.aligned.m16n8k64.row.col.kind::f8f6f4.f32.e4m3.e3m2.f32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1, $rb2, $rb3}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}},\n\t\t$metadata,\n\t\t$selector;", "predicates": [ "Subtarget->hasMMABlockScale()" ] } ], "rust": { - "abi_id": "i0242", + "abi_id": "i0244", "module": "matrix", - "name": "mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e4m3_e2m1_f32", + "name": "mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e4m3_e3m2_f32", "arguments": [ "[f32; 4]", "[u32; 4]", @@ -211929,10 +215008,10 @@ "safe": false, "must_use": true, "safe_allowlist_reason": null, - "canonical_path": "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0242", - "public_path": "cuda_intrinsics::matrix::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e4m3_e2m1_f32", + "canonical_path": "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0244", + "public_path": "cuda_intrinsics::matrix::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e4m3_e3m2_f32", "compatibility_paths": [ - "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e4m3_e2m1_f32" + "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e4m3_e3m2_f32" ] }, "dialect": { @@ -211962,7 +215041,7 @@ ] }, "llvm": { - "symbol": "llvm.nvvm.mma.sp.ordered.metadata.m16n8k64.row.col.kind.f8f6f4.f32.e4m3.e2m1.f32", + "symbol": "llvm.nvvm.mma.sp.ordered.metadata.m16n8k64.row.col.kind.f8f6f4.f32.e4m3.e3m2.f32", "arguments": [ "i32", "i32", @@ -212193,7 +215272,7 @@ "shape": "m16n8k64", "accumulator": "f32", "a_element": "e4m3", - "b_element": "e2m1", + "b_element": "e3m2", "a_layout": "row", "b_layout": "col", "overflow": "not_applicable", @@ -212218,7 +215297,7 @@ "kind::f8f6f4", "f32", "e4m3", - "e2m1", + "e3m2", "f32" ], "operands": [ @@ -212246,29 +215325,29 @@ } ] }, - "summary": "Multiplies warp-distributed sparse e4m3 A and e2m1 B fragments and adds an f32 accumulator." + "summary": "Multiplies warp-distributed sparse e4m3 A and e3m2 B fragments and adds an f32 accumulator." }, { - "id": "mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e4m3_e2m3_f32", - "operation_key": "matrix.mma.sp.m16n8k64.row.col.kind_f8f6f4.f32.e4m3.e2m3.f32.not_applicable.ordered_metadata", + "id": "mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e4m3_e4m3_f32", + "operation_key": "matrix.mma.sp.m16n8k64.row.col.kind_f8f6f4.f32.e4m3.e4m3.f32.not_applicable.ordered_metadata", "family": "sparse_mma", "source": { "kind": "llvm_imported", - "source_record": "int_nvvm_mma_sp_ordered_metadata_m16n8k64_row_col_kind_f8f6f4_f32_e4m3_e2m3_f32" + "source_record": "int_nvvm_mma_sp_ordered_metadata_m16n8k64_row_col_kind_f8f6f4_f32_e4m3_e4m3_f32" }, "selections": [ { - "source_record": "anonymous_19767", - "asm": "mma.sp::ordered_metadata.sync.aligned.m16n8k64.row.col.kind::f8f6f4.f32.e4m3.e2m3.f32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1, $rb2, $rb3}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}},\n\t\t$metadata,\n\t\t$selector;", + "source_record": "anonymous_19740", + "asm": "mma.sp::ordered_metadata.sync.aligned.m16n8k64.row.col.kind::f8f6f4.f32.e4m3.e4m3.f32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1, $rb2, $rb3}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}},\n\t\t$metadata,\n\t\t$selector;", "predicates": [ "Subtarget->hasMMABlockScale()" ] } ], "rust": { - "abi_id": "i0243", + "abi_id": "i0245", "module": "matrix", - "name": "mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e4m3_e2m3_f32", + "name": "mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e4m3_e4m3_f32", "arguments": [ "[f32; 4]", "[u32; 4]", @@ -212280,10 +215359,10 @@ "safe": false, "must_use": true, "safe_allowlist_reason": null, - "canonical_path": "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0243", - "public_path": "cuda_intrinsics::matrix::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e4m3_e2m3_f32", + "canonical_path": "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0245", + "public_path": "cuda_intrinsics::matrix::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e4m3_e4m3_f32", "compatibility_paths": [ - "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e4m3_e2m3_f32" + "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e4m3_e4m3_f32" ] }, "dialect": { @@ -212313,7 +215392,7 @@ ] }, "llvm": { - "symbol": "llvm.nvvm.mma.sp.ordered.metadata.m16n8k64.row.col.kind.f8f6f4.f32.e4m3.e2m3.f32", + "symbol": "llvm.nvvm.mma.sp.ordered.metadata.m16n8k64.row.col.kind.f8f6f4.f32.e4m3.e4m3.f32", "arguments": [ "i32", "i32", @@ -212544,7 +215623,7 @@ "shape": "m16n8k64", "accumulator": "f32", "a_element": "e4m3", - "b_element": "e2m3", + "b_element": "e4m3", "a_layout": "row", "b_layout": "col", "overflow": "not_applicable", @@ -212569,7 +215648,7 @@ "kind::f8f6f4", "f32", "e4m3", - "e2m3", + "e4m3", "f32" ], "operands": [ @@ -212597,29 +215676,29 @@ } ] }, - "summary": "Multiplies warp-distributed sparse e4m3 A and e2m3 B fragments and adds an f32 accumulator." + "summary": "Multiplies warp-distributed sparse e4m3 A and e4m3 B fragments and adds an f32 accumulator." }, { - "id": "mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e4m3_e3m2_f32", - "operation_key": "matrix.mma.sp.m16n8k64.row.col.kind_f8f6f4.f32.e4m3.e3m2.f32.not_applicable.ordered_metadata", + "id": "mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e4m3_e5m2_f32", + "operation_key": "matrix.mma.sp.m16n8k64.row.col.kind_f8f6f4.f32.e4m3.e5m2.f32.not_applicable.ordered_metadata", "family": "sparse_mma", "source": { "kind": "llvm_imported", - "source_record": "int_nvvm_mma_sp_ordered_metadata_m16n8k64_row_col_kind_f8f6f4_f32_e4m3_e3m2_f32" + "source_record": "int_nvvm_mma_sp_ordered_metadata_m16n8k64_row_col_kind_f8f6f4_f32_e4m3_e5m2_f32" }, "selections": [ { - "source_record": "anonymous_19758", - "asm": "mma.sp::ordered_metadata.sync.aligned.m16n8k64.row.col.kind::f8f6f4.f32.e4m3.e3m2.f32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1, $rb2, $rb3}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}},\n\t\t$metadata,\n\t\t$selector;", + "source_record": "anonymous_19749", + "asm": "mma.sp::ordered_metadata.sync.aligned.m16n8k64.row.col.kind::f8f6f4.f32.e4m3.e5m2.f32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1, $rb2, $rb3}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}},\n\t\t$metadata,\n\t\t$selector;", "predicates": [ "Subtarget->hasMMABlockScale()" ] } ], "rust": { - "abi_id": "i0244", + "abi_id": "i0246", "module": "matrix", - "name": "mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e4m3_e3m2_f32", + "name": "mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e4m3_e5m2_f32", "arguments": [ "[f32; 4]", "[u32; 4]", @@ -212631,10 +215710,10 @@ "safe": false, "must_use": true, "safe_allowlist_reason": null, - "canonical_path": "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0244", - "public_path": "cuda_intrinsics::matrix::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e4m3_e3m2_f32", + "canonical_path": "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0246", + "public_path": "cuda_intrinsics::matrix::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e4m3_e5m2_f32", "compatibility_paths": [ - "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e4m3_e3m2_f32" + "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e4m3_e5m2_f32" ] }, "dialect": { @@ -212664,7 +215743,7 @@ ] }, "llvm": { - "symbol": "llvm.nvvm.mma.sp.ordered.metadata.m16n8k64.row.col.kind.f8f6f4.f32.e4m3.e3m2.f32", + "symbol": "llvm.nvvm.mma.sp.ordered.metadata.m16n8k64.row.col.kind.f8f6f4.f32.e4m3.e5m2.f32", "arguments": [ "i32", "i32", @@ -212895,7 +215974,7 @@ "shape": "m16n8k64", "accumulator": "f32", "a_element": "e4m3", - "b_element": "e3m2", + "b_element": "e5m2", "a_layout": "row", "b_layout": "col", "overflow": "not_applicable", @@ -212920,7 +215999,7 @@ "kind::f8f6f4", "f32", "e4m3", - "e3m2", + "e5m2", "f32" ], "operands": [ @@ -212948,29 +216027,29 @@ } ] }, - "summary": "Multiplies warp-distributed sparse e4m3 A and e3m2 B fragments and adds an f32 accumulator." + "summary": "Multiplies warp-distributed sparse e4m3 A and e5m2 B fragments and adds an f32 accumulator." }, { - "id": "mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e4m3_e4m3_f32", - "operation_key": "matrix.mma.sp.m16n8k64.row.col.kind_f8f6f4.f32.e4m3.e4m3.f32.not_applicable.ordered_metadata", + "id": "mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e5m2_e2m1_f32", + "operation_key": "matrix.mma.sp.m16n8k64.row.col.kind_f8f6f4.f32.e5m2.e2m1.f32.not_applicable.ordered_metadata", "family": "sparse_mma", "source": { "kind": "llvm_imported", - "source_record": "int_nvvm_mma_sp_ordered_metadata_m16n8k64_row_col_kind_f8f6f4_f32_e4m3_e4m3_f32" + "source_record": "int_nvvm_mma_sp_ordered_metadata_m16n8k64_row_col_kind_f8f6f4_f32_e5m2_e2m1_f32" }, "selections": [ { - "source_record": "anonymous_19740", - "asm": "mma.sp::ordered_metadata.sync.aligned.m16n8k64.row.col.kind::f8f6f4.f32.e4m3.e4m3.f32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1, $rb2, $rb3}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}},\n\t\t$metadata,\n\t\t$selector;", + "source_record": "anonymous_19817", + "asm": "mma.sp::ordered_metadata.sync.aligned.m16n8k64.row.col.kind::f8f6f4.f32.e5m2.e2m1.f32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1, $rb2, $rb3}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}},\n\t\t$metadata,\n\t\t$selector;", "predicates": [ "Subtarget->hasMMABlockScale()" ] } ], "rust": { - "abi_id": "i0245", + "abi_id": "i0247", "module": "matrix", - "name": "mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e4m3_e4m3_f32", + "name": "mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e5m2_e2m1_f32", "arguments": [ "[f32; 4]", "[u32; 4]", @@ -212982,10 +216061,10 @@ "safe": false, "must_use": true, "safe_allowlist_reason": null, - "canonical_path": "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0245", - "public_path": "cuda_intrinsics::matrix::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e4m3_e4m3_f32", + "canonical_path": "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0247", + "public_path": "cuda_intrinsics::matrix::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e5m2_e2m1_f32", "compatibility_paths": [ - "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e4m3_e4m3_f32" + "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e5m2_e2m1_f32" ] }, "dialect": { @@ -213015,7 +216094,7 @@ ] }, "llvm": { - "symbol": "llvm.nvvm.mma.sp.ordered.metadata.m16n8k64.row.col.kind.f8f6f4.f32.e4m3.e4m3.f32", + "symbol": "llvm.nvvm.mma.sp.ordered.metadata.m16n8k64.row.col.kind.f8f6f4.f32.e5m2.e2m1.f32", "arguments": [ "i32", "i32", @@ -213245,8 +216324,8 @@ "sparse_mma": { "shape": "m16n8k64", "accumulator": "f32", - "a_element": "e4m3", - "b_element": "e4m3", + "a_element": "e5m2", + "b_element": "e2m1", "a_layout": "row", "b_layout": "col", "overflow": "not_applicable", @@ -213270,8 +216349,8 @@ "col", "kind::f8f6f4", "f32", - "e4m3", - "e4m3", + "e5m2", + "e2m1", "f32" ], "operands": [ @@ -213299,29 +216378,29 @@ } ] }, - "summary": "Multiplies warp-distributed sparse e4m3 A and e4m3 B fragments and adds an f32 accumulator." + "summary": "Multiplies warp-distributed sparse e5m2 A and e2m1 B fragments and adds an f32 accumulator." }, { - "id": "mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e4m3_e5m2_f32", - "operation_key": "matrix.mma.sp.m16n8k64.row.col.kind_f8f6f4.f32.e4m3.e5m2.f32.not_applicable.ordered_metadata", + "id": "mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e5m2_e2m3_f32", + "operation_key": "matrix.mma.sp.m16n8k64.row.col.kind_f8f6f4.f32.e5m2.e2m3.f32.not_applicable.ordered_metadata", "family": "sparse_mma", "source": { "kind": "llvm_imported", - "source_record": "int_nvvm_mma_sp_ordered_metadata_m16n8k64_row_col_kind_f8f6f4_f32_e4m3_e5m2_f32" + "source_record": "int_nvvm_mma_sp_ordered_metadata_m16n8k64_row_col_kind_f8f6f4_f32_e5m2_e2m3_f32" }, "selections": [ { - "source_record": "anonymous_19749", - "asm": "mma.sp::ordered_metadata.sync.aligned.m16n8k64.row.col.kind::f8f6f4.f32.e4m3.e5m2.f32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1, $rb2, $rb3}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}},\n\t\t$metadata,\n\t\t$selector;", + "source_record": "anonymous_19809", + "asm": "mma.sp::ordered_metadata.sync.aligned.m16n8k64.row.col.kind::f8f6f4.f32.e5m2.e2m3.f32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1, $rb2, $rb3}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}},\n\t\t$metadata,\n\t\t$selector;", "predicates": [ "Subtarget->hasMMABlockScale()" ] } ], "rust": { - "abi_id": "i0246", + "abi_id": "i0248", "module": "matrix", - "name": "mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e4m3_e5m2_f32", + "name": "mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e5m2_e2m3_f32", "arguments": [ "[f32; 4]", "[u32; 4]", @@ -213333,10 +216412,10 @@ "safe": false, "must_use": true, "safe_allowlist_reason": null, - "canonical_path": "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0246", - "public_path": "cuda_intrinsics::matrix::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e4m3_e5m2_f32", + "canonical_path": "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0248", + "public_path": "cuda_intrinsics::matrix::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e5m2_e2m3_f32", "compatibility_paths": [ - "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e4m3_e5m2_f32" + "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e5m2_e2m3_f32" ] }, "dialect": { @@ -213366,7 +216445,7 @@ ] }, "llvm": { - "symbol": "llvm.nvvm.mma.sp.ordered.metadata.m16n8k64.row.col.kind.f8f6f4.f32.e4m3.e5m2.f32", + "symbol": "llvm.nvvm.mma.sp.ordered.metadata.m16n8k64.row.col.kind.f8f6f4.f32.e5m2.e2m3.f32", "arguments": [ "i32", "i32", @@ -213596,8 +216675,8 @@ "sparse_mma": { "shape": "m16n8k64", "accumulator": "f32", - "a_element": "e4m3", - "b_element": "e5m2", + "a_element": "e5m2", + "b_element": "e2m3", "a_layout": "row", "b_layout": "col", "overflow": "not_applicable", @@ -213621,8 +216700,8 @@ "col", "kind::f8f6f4", "f32", - "e4m3", "e5m2", + "e2m3", "f32" ], "operands": [ @@ -213650,29 +216729,29 @@ } ] }, - "summary": "Multiplies warp-distributed sparse e4m3 A and e5m2 B fragments and adds an f32 accumulator." + "summary": "Multiplies warp-distributed sparse e5m2 A and e2m3 B fragments and adds an f32 accumulator." }, { - "id": "mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e5m2_e2m1_f32", - "operation_key": "matrix.mma.sp.m16n8k64.row.col.kind_f8f6f4.f32.e5m2.e2m1.f32.not_applicable.ordered_metadata", + "id": "mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e5m2_e3m2_f32", + "operation_key": "matrix.mma.sp.m16n8k64.row.col.kind_f8f6f4.f32.e5m2.e3m2.f32.not_applicable.ordered_metadata", "family": "sparse_mma", "source": { "kind": "llvm_imported", - "source_record": "int_nvvm_mma_sp_ordered_metadata_m16n8k64_row_col_kind_f8f6f4_f32_e5m2_e2m1_f32" + "source_record": "int_nvvm_mma_sp_ordered_metadata_m16n8k64_row_col_kind_f8f6f4_f32_e5m2_e3m2_f32" }, "selections": [ { - "source_record": "anonymous_19817", - "asm": "mma.sp::ordered_metadata.sync.aligned.m16n8k64.row.col.kind::f8f6f4.f32.e5m2.e2m1.f32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1, $rb2, $rb3}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}},\n\t\t$metadata,\n\t\t$selector;", + "source_record": "anonymous_19801", + "asm": "mma.sp::ordered_metadata.sync.aligned.m16n8k64.row.col.kind::f8f6f4.f32.e5m2.e3m2.f32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1, $rb2, $rb3}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}},\n\t\t$metadata,\n\t\t$selector;", "predicates": [ "Subtarget->hasMMABlockScale()" ] } ], "rust": { - "abi_id": "i0247", + "abi_id": "i0249", "module": "matrix", - "name": "mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e5m2_e2m1_f32", + "name": "mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e5m2_e3m2_f32", "arguments": [ "[f32; 4]", "[u32; 4]", @@ -213684,10 +216763,10 @@ "safe": false, "must_use": true, "safe_allowlist_reason": null, - "canonical_path": "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0247", - "public_path": "cuda_intrinsics::matrix::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e5m2_e2m1_f32", + "canonical_path": "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0249", + "public_path": "cuda_intrinsics::matrix::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e5m2_e3m2_f32", "compatibility_paths": [ - "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e5m2_e2m1_f32" + "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e5m2_e3m2_f32" ] }, "dialect": { @@ -213717,7 +216796,7 @@ ] }, "llvm": { - "symbol": "llvm.nvvm.mma.sp.ordered.metadata.m16n8k64.row.col.kind.f8f6f4.f32.e5m2.e2m1.f32", + "symbol": "llvm.nvvm.mma.sp.ordered.metadata.m16n8k64.row.col.kind.f8f6f4.f32.e5m2.e3m2.f32", "arguments": [ "i32", "i32", @@ -213948,7 +217027,7 @@ "shape": "m16n8k64", "accumulator": "f32", "a_element": "e5m2", - "b_element": "e2m1", + "b_element": "e3m2", "a_layout": "row", "b_layout": "col", "overflow": "not_applicable", @@ -213973,7 +217052,7 @@ "kind::f8f6f4", "f32", "e5m2", - "e2m1", + "e3m2", "f32" ], "operands": [ @@ -214001,29 +217080,29 @@ } ] }, - "summary": "Multiplies warp-distributed sparse e5m2 A and e2m1 B fragments and adds an f32 accumulator." + "summary": "Multiplies warp-distributed sparse e5m2 A and e3m2 B fragments and adds an f32 accumulator." }, { - "id": "mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e5m2_e2m3_f32", - "operation_key": "matrix.mma.sp.m16n8k64.row.col.kind_f8f6f4.f32.e5m2.e2m3.f32.not_applicable.ordered_metadata", + "id": "mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e5m2_e4m3_f32", + "operation_key": "matrix.mma.sp.m16n8k64.row.col.kind_f8f6f4.f32.e5m2.e4m3.f32.not_applicable.ordered_metadata", "family": "sparse_mma", "source": { "kind": "llvm_imported", - "source_record": "int_nvvm_mma_sp_ordered_metadata_m16n8k64_row_col_kind_f8f6f4_f32_e5m2_e2m3_f32" + "source_record": "int_nvvm_mma_sp_ordered_metadata_m16n8k64_row_col_kind_f8f6f4_f32_e5m2_e4m3_f32" }, "selections": [ { - "source_record": "anonymous_19809", - "asm": "mma.sp::ordered_metadata.sync.aligned.m16n8k64.row.col.kind::f8f6f4.f32.e5m2.e2m3.f32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1, $rb2, $rb3}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}},\n\t\t$metadata,\n\t\t$selector;", + "source_record": "anonymous_19785", + "asm": "mma.sp::ordered_metadata.sync.aligned.m16n8k64.row.col.kind::f8f6f4.f32.e5m2.e4m3.f32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1, $rb2, $rb3}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}},\n\t\t$metadata,\n\t\t$selector;", "predicates": [ "Subtarget->hasMMABlockScale()" ] } ], "rust": { - "abi_id": "i0248", + "abi_id": "i0250", "module": "matrix", - "name": "mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e5m2_e2m3_f32", + "name": "mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e5m2_e4m3_f32", "arguments": [ "[f32; 4]", "[u32; 4]", @@ -214035,10 +217114,10 @@ "safe": false, "must_use": true, "safe_allowlist_reason": null, - "canonical_path": "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0248", - "public_path": "cuda_intrinsics::matrix::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e5m2_e2m3_f32", + "canonical_path": "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0250", + "public_path": "cuda_intrinsics::matrix::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e5m2_e4m3_f32", "compatibility_paths": [ - "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e5m2_e2m3_f32" + "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e5m2_e4m3_f32" ] }, "dialect": { @@ -214068,7 +217147,7 @@ ] }, "llvm": { - "symbol": "llvm.nvvm.mma.sp.ordered.metadata.m16n8k64.row.col.kind.f8f6f4.f32.e5m2.e2m3.f32", + "symbol": "llvm.nvvm.mma.sp.ordered.metadata.m16n8k64.row.col.kind.f8f6f4.f32.e5m2.e4m3.f32", "arguments": [ "i32", "i32", @@ -214299,7 +217378,7 @@ "shape": "m16n8k64", "accumulator": "f32", "a_element": "e5m2", - "b_element": "e2m3", + "b_element": "e4m3", "a_layout": "row", "b_layout": "col", "overflow": "not_applicable", @@ -214324,7 +217403,7 @@ "kind::f8f6f4", "f32", "e5m2", - "e2m3", + "e4m3", "f32" ], "operands": [ @@ -214352,29 +217431,29 @@ } ] }, - "summary": "Multiplies warp-distributed sparse e5m2 A and e2m3 B fragments and adds an f32 accumulator." + "summary": "Multiplies warp-distributed sparse e5m2 A and e4m3 B fragments and adds an f32 accumulator." }, { - "id": "mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e5m2_e3m2_f32", - "operation_key": "matrix.mma.sp.m16n8k64.row.col.kind_f8f6f4.f32.e5m2.e3m2.f32.not_applicable.ordered_metadata", + "id": "mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e5m2_e5m2_f32", + "operation_key": "matrix.mma.sp.m16n8k64.row.col.kind_f8f6f4.f32.e5m2.e5m2.f32.not_applicable.ordered_metadata", "family": "sparse_mma", "source": { "kind": "llvm_imported", - "source_record": "int_nvvm_mma_sp_ordered_metadata_m16n8k64_row_col_kind_f8f6f4_f32_e5m2_e3m2_f32" + "source_record": "int_nvvm_mma_sp_ordered_metadata_m16n8k64_row_col_kind_f8f6f4_f32_e5m2_e5m2_f32" }, "selections": [ { - "source_record": "anonymous_19801", - "asm": "mma.sp::ordered_metadata.sync.aligned.m16n8k64.row.col.kind::f8f6f4.f32.e5m2.e3m2.f32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1, $rb2, $rb3}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}},\n\t\t$metadata,\n\t\t$selector;", + "source_record": "anonymous_19793", + "asm": "mma.sp::ordered_metadata.sync.aligned.m16n8k64.row.col.kind::f8f6f4.f32.e5m2.e5m2.f32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1, $rb2, $rb3}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}},\n\t\t$metadata,\n\t\t$selector;", "predicates": [ "Subtarget->hasMMABlockScale()" ] } ], "rust": { - "abi_id": "i0249", + "abi_id": "i0251", "module": "matrix", - "name": "mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e5m2_e3m2_f32", + "name": "mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e5m2_e5m2_f32", "arguments": [ "[f32; 4]", "[u32; 4]", @@ -214386,10 +217465,10 @@ "safe": false, "must_use": true, "safe_allowlist_reason": null, - "canonical_path": "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0249", - "public_path": "cuda_intrinsics::matrix::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e5m2_e3m2_f32", + "canonical_path": "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0251", + "public_path": "cuda_intrinsics::matrix::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e5m2_e5m2_f32", "compatibility_paths": [ - "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e5m2_e3m2_f32" + "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e5m2_e5m2_f32" ] }, "dialect": { @@ -214419,7 +217498,7 @@ ] }, "llvm": { - "symbol": "llvm.nvvm.mma.sp.ordered.metadata.m16n8k64.row.col.kind.f8f6f4.f32.e5m2.e3m2.f32", + "symbol": "llvm.nvvm.mma.sp.ordered.metadata.m16n8k64.row.col.kind.f8f6f4.f32.e5m2.e5m2.f32", "arguments": [ "i32", "i32", @@ -214650,7 +217729,7 @@ "shape": "m16n8k64", "accumulator": "f32", "a_element": "e5m2", - "b_element": "e3m2", + "b_element": "e5m2", "a_layout": "row", "b_layout": "col", "overflow": "not_applicable", @@ -214675,7 +217754,7 @@ "kind::f8f6f4", "f32", "e5m2", - "e3m2", + "e5m2", "f32" ], "operands": [ @@ -214703,58 +217782,55 @@ } ] }, - "summary": "Multiplies warp-distributed sparse e5m2 A and e3m2 B fragments and adds an f32 accumulator." + "summary": "Multiplies warp-distributed sparse e5m2 A and e5m2 B fragments and adds an f32 accumulator." }, { - "id": "mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e5m2_e4m3_f32", - "operation_key": "matrix.mma.sp.m16n8k64.row.col.kind_f8f6f4.f32.e5m2.e4m3.f32.not_applicable.ordered_metadata", + "id": "mma_sp_ordered_metadata_m16n8k64_s32_s4", + "operation_key": "matrix.mma.sp.m16n8k64.row.col.s32.s4.s4.s32.wrapping.ordered_metadata", "family": "sparse_mma", "source": { "kind": "llvm_imported", - "source_record": "int_nvvm_mma_sp_ordered_metadata_m16n8k64_row_col_kind_f8f6f4_f32_e5m2_e4m3_f32" + "source_record": "int_nvvm_mma_sp_ordered_metadata_m16n8k64_row_col_s4" }, "selections": [ { - "source_record": "anonymous_19785", - "asm": "mma.sp::ordered_metadata.sync.aligned.m16n8k64.row.col.kind::f8f6f4.f32.e5m2.e4m3.f32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1, $rb2, $rb3}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}},\n\t\t$metadata,\n\t\t$selector;", + "source_record": "anonymous_19600", + "asm": "mma.sp::ordered_metadata.sync.aligned.m16n8k64.row.col.s32.s4.s4.s32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1}},\n\t\t{{$rb0, $rb1}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}},\n\t\t$metadata,\n\t\t$selector;", "predicates": [ - "Subtarget->hasMMABlockScale()" + "Subtarget->getSmVersion() >= 80", + "Subtarget->getPTXVersion() >= 85" ] } ], "rust": { - "abi_id": "i0250", + "abi_id": "i0195", "module": "matrix", - "name": "mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e5m2_e4m3_f32", + "name": "mma_sp_ordered_metadata_m16n8k64_s32_s4", "arguments": [ - "[f32; 4]", - "[u32; 4]", - "[u32; 4]", + "[i32; 4]", + "[u32; 2]", + "[u32; 2]", "u32", "u32" ], - "result": "[f32; 4]", + "result": "[i32; 4]", "safe": false, "must_use": true, "safe_allowlist_reason": null, - "canonical_path": "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0250", - "public_path": "cuda_intrinsics::matrix::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e5m2_e4m3_f32", + "canonical_path": "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0195", + "public_path": "cuda_intrinsics::matrix::mma_sp_ordered_metadata_m16n8k64_s32_s4", "compatibility_paths": [ - "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e5m2_e4m3_f32" + "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_s32_s4" ] }, "dialect": { "op_type": "SparseMmaOp", "op_name": "nvvm.sparse_mma", "operands": [ - "f32", - "f32", - "f32", - "f32", - "u32", - "u32", - "u32", - "u32", + "i32", + "i32", + "i32", + "i32", "u32", "u32", "u32", @@ -214763,14 +217839,14 @@ "u32" ], "results": [ - "f32", - "f32", - "f32", - "f32" + "i32", + "i32", + "i32", + "i32" ] }, "llvm": { - "symbol": "llvm.nvvm.mma.sp.ordered.metadata.m16n8k64.row.col.kind.f8f6f4.f32.e5m2.e4m3.f32", + "symbol": "llvm.nvvm.mma.sp.ordered.metadata.m16n8k64.row.col.s4", "arguments": [ "i32", "i32", @@ -214780,24 +217856,20 @@ "i32", "i32", "i32", - "f32", - "f32", - "f32", - "f32", "i32", "i32" ], "results": [ - "f32", - "f32", - "f32", - "f32" + "i32", + "i32", + "i32", + "i32" ], "properties": [ - "ImmArg", + "ImmArg", "IntrNoCallback", "IntrNoMem", - "Range" + "Range" ], "result_facts": { "no_undef": false, @@ -214811,30 +217883,18 @@ "execution_scope": "warp" }, "target": { - "minimum_ptx": "8.7", + "minimum_ptx": "8.5", "hardware": { "kind": "any_of", "alternatives": [ { - "kind": "exact_architecture", - "sm": 120 - }, - { - "kind": "family_target", - "sm": 120 - }, - { - "kind": "exact_architecture", - "sm": 121 - }, - { - "kind": "family_target", - "sm": 121 + "kind": "minimum_sm", + "sm": 80 } ] }, - "ptx_result": "[f32; 4]", - "targets": "sm_120a|sm_120f|sm_121a|sm_121f", + "ptx_result": "[i32; 4]", + "targets": "all", "ptx_isa_version": "9.3", "ptx_isa_section": "9.7.15.6.3 Multiply-and-Accumulate Instruction: mma.sp", "ptx_isa_url": "https://docs.nvidia.com/cuda/parallel-thread-execution/#warp-level-matrix-instructions-mma-sp" @@ -214845,8 +217905,8 @@ "sha256": "2e5bc688625ca7d98bca9b5f0f0d14525d2eb59e8a9842964e480df3ffd1f921", "status": "validated", "target_triple": "nvptx64-nvidia-cuda", - "gpu_target": "sm_120a", - "ptx_feature": "+ptx87" + "gpu_target": "sm_80", + "ptx_feature": "+ptx85" }, "backend_lowerings": [ { @@ -214854,25 +217914,13 @@ "mechanism": "inline_ptx", "evidence_profile": "rust-llvm-23.1.0-16696adc", "target": { - "minimum_ptx": "8.7", + "minimum_ptx": "8.5", "hardware": { "kind": "any_of", "alternatives": [ { - "kind": "exact_architecture", - "sm": 120 - }, - { - "kind": "family_target", - "sm": 120 - }, - { - "kind": "exact_architecture", - "sm": 121 - }, - { - "kind": "family_target", - "sm": 121 + "kind": "minimum_sm", + "sm": 80 } ] } @@ -214885,14 +217933,14 @@ "stages": [ { "targets": [ - "sm_120a", - "ptx87" + "sm_80", + "ptx85" ], - "representation": "convergent ordered kind::f8f6f4 F32 inline PTX in public C, A, B, metadata, selector order", + "representation": "convergent ordered sparse m16n8k64 INT4 inline PTX with selectors 0 and 1", "stage": "backend_codegen", "mechanism": "inline_ptx", "outcome": "succeeded", - "detail": "Pinned LLVM lowered the 28,839-byte all-forms source (SHA-256 5518d5dfb092f5ae3ccefe1e7e66eb4df9db7da480722e390587490c6ce8832a) to 12,015-byte PTX (SHA-256 0d93ea01d39bc512b96becf2ad799522d9d5187c17d521294eecd4e69c055e66) containing the exact 25-form matrix at sm_120a and PTX 8.7.", + "detail": "The 8,107-byte combined inline-PTX probe (SHA-256 ce31bb4c5d7f083ae8e1293a0a3e5196575482427a041d549f9ecd3862e46942) used public C, A, B, metadata, selector order and covered all eight variants with both selector values. Pinned LLVM emitted 8,453-byte PTX (SHA-256 7a8bb0261fd16c1941b47500d70f3cff95a1acb95c51e52480af15a4effc8818) with exactly 16 ordered m16n8k64 INT4 instructions. An auxiliary 6,948-byte typed LLVM comparison (SHA-256 379488c94c4e3d6b1806928d72723845b7bd329857f4dfc3caf8f74d7a5c6649) used source A, B, C, metadata, selector order and emitted 22,330-byte PTX (SHA-256 913b74cc0dba68779655073b83e5a534bcf076fa5e6a1d1d6029ef951b0fc1cd) with the same 16 forms; this record retained wrapping s4-by-s4 PTX.", "artifact_kind": null, "tool_path": null, "tool_version": null, @@ -214900,14 +217948,14 @@ }, { "targets": [ - "sm_120a", - "ptx87" + "sm_80", + "ptx85" ], - "representation": "exact-floor ordered kind::f8f6f4 F32 PTX", + "representation": "exact-floor ordered sparse m16n8k64 INT4 PTX", "stage": "ptx_assembly", "mechanism": "inline_ptx", "outcome": "succeeded", - "detail": "CUDA 13.3 ptxas produced a 12,144-byte cubin (SHA-256 7769d4fe1de8cdf6644b911bc3654ab220f4dd28cc44a83e28793a5d3f381cf3); its 38,172-byte SASS dump (SHA-256 34df448cb5d7367b36657270961981955bb76cc1dd5dd221f673f174c6e10b0a) retains 25 unique QMMA forms. PTX 8.6, sm_120, selector 1, and dynamic selectors were rejected.", + "detail": "CUDA 13.3 ptxas accepted all 16 instructions and produced a 4,008-byte cubin with SHA-256 a6df23e0492e6f26ede3da7f7fab6c9fdab2693c5c2d6bda12339948cba640ec containing exactly 16 IMMA.SP.16864 instructions. LLVM and ptxas rejected selector 2 and dynamic selectors; ptxas also rejected PTX 8.4 and sm_75.", "artifact_kind": "cubin", "tool_path": "/usr/local/cuda-13.3/bin/ptxas", "tool_version": "CUDA 13.3 V13.3.33 build cuda_13.3.r13.3/compiler.37862127_0", @@ -214920,25 +217968,13 @@ "mechanism": "inline_ptx", "evidence_profile": "cuda-13.3-libnvvm-13.3.33", "target": { - "minimum_ptx": "8.7", + "minimum_ptx": "8.5", "hardware": { "kind": "any_of", "alternatives": [ { - "kind": "exact_architecture", - "sm": 120 - }, - { - "kind": "family_target", - "sm": 120 - }, - { - "kind": "exact_architecture", - "sm": 121 - }, - { - "kind": "family_target", - "sm": 121 + "kind": "minimum_sm", + "sm": 80 } ] } @@ -214951,14 +217987,14 @@ "stages": [ { "targets": [ - "compute_120a", + "compute_80", "ptx93" ], - "representation": "convergent ordered kind::f8f6f4 F32 inline PTX in public C, A, B, metadata, selector order", + "representation": "convergent ordered sparse m16n8k64 INT4 inline PTX in the generated coverage kernel", "stage": "backend_codegen", "mechanism": "inline_ptx", "outcome": "succeeded", - "detail": "CUDA 13.3 libNVVM retained the exact 25-form matrix in 11,910-byte PTX (SHA-256 a096494f6b066927107cf222f784d1a586ed1cf3ab766669b741e429f03f4427) and produced 14,052-byte LTOIR (SHA-256 99941daa24a78884788ed0908a3764f596c527e6ab621d6085c549aea9575377).", + "detail": "The production generated_intrinsics route produced 294,949-byte compute_80 NVVM IR with SHA-256 787025e167bb7bb790fab0af002f838502536834145304ce8df3fc75227059d2 and 82,648-byte LTOIR with SHA-256 eb6516ac258f3c70d20879de097822b13ab73e00288691ae9a13e17bc7fe0d1a. All eight raw variants use selectors 0 and 1. An auxiliary 8,107-byte combined probe with SHA-256 ce31bb4c5d7f083ae8e1293a0a3e5196575482427a041d549f9ecd3862e46942 separately covered every variant with both selectors.", "artifact_kind": null, "tool_path": null, "tool_version": null, @@ -214966,29 +218002,14 @@ }, { "targets": [ - "sm_120a", - "ptx93" - ], - "representation": "libNVVM-emitted ordered kind::f8f6f4 F32 PTX", - "stage": "ptx_assembly", - "mechanism": "inline_ptx", - "outcome": "succeeded", - "detail": "CUDA 13.3 ptxas produced a 12,144-byte cubin (SHA-256 7769d4fe1de8cdf6644b911bc3654ab220f4dd28cc44a83e28793a5d3f381cf3) retaining all 25 unique QMMA forms.", - "artifact_kind": "cubin", - "tool_path": "/usr/local/cuda-13.3/bin/ptxas", - "tool_version": "CUDA 13.3 V13.3.33 build cuda_13.3.r13.3/compiler.37862127_0", - "tool_sha256": "7fdd01a4cf50e30746da98989c9272a907f491e6fd7fecfda14642e4375f88fb" - }, - { - "targets": [ - "sm_120a", + "sm_80", "ptx93" ], - "representation": "libNVVM LTOIR retaining the ordered kind::f8f6f4 F32 matrix", + "representation": "generated sparse-MMA coverage kernel with ordered m16n8k64 INT4 calls", "stage": "device_link", "mechanism": "inline_ptx", "outcome": "succeeded", - "detail": "CUDA 13.3 nvJitLink produced a 12,144-byte cubin (SHA-256 62457debbb99023b09b3701e14974a97cfc5761f931ebf9f0d9e2bada3e3a642); its 38,172-byte SASS dump (SHA-256 34df448cb5d7367b36657270961981955bb76cc1dd5dd221f673f174c6e10b0a) retains 25 unique QMMA forms.", + "detail": "nvJitLink produced a 26,600-byte cubin with SHA-256 1837a2742ce837ccf16b4900b50a72fb018a49bd1850bafe62b3a2a31f550406. Disassembly contained 50 IMMA.SP instructions in total, exactly 30 IMMA.SP.16864 instructions, and exactly 10 ordered m16n8k64 INT4 forms: all eight raw variants plus two compatibility-path calls.", "artifact_kind": "cubin", "tool_path": "/usr/local/cuda-13.3/lib64/libnvJitLink.so.13.3.33", "tool_version": "V13.3.33", @@ -214999,17 +218020,17 @@ ], "sparse_mma": { "shape": "m16n8k64", - "accumulator": "f32", - "a_element": "e5m2", - "b_element": "e4m3", + "accumulator": "s32", + "a_element": "s4", + "b_element": "s4", "a_layout": "row", "b_layout": "col", - "overflow": "not_applicable", + "overflow": "wrapping", "metadata": "ordered", - "selector": "immediate_zero", + "selector": "immediate_zero_or_one", "participation": "all_warp_lanes_same_instruction_and_qualifiers_no_exited_lanes", - "adapter": "c4_f32_a4_u32_b4_u32_metadata_u32_selector_u32_to_d4_f32", - "llvm_adapter": "a4_i32_b4_i32_c4_f32_metadata_i32_selector_i32_to_d4_f32", + "adapter": "c4_i32_a2_u32_b2_u32_metadata_u32_selector_u32_to_d4_i32", + "llvm_adapter": "a2_i32_b2_i32_c4_i32_metadata_i32_selector_i32_to_d4_i32", "compatibility_source": "generated_stub", "runtime_validation": "unexecuted" }, @@ -215023,11 +218044,10 @@ "m16n8k64", "row", "col", - "kind::f8f6f4", - "f32", - "e5m2", - "e4m3", - "f32" + "s32", + "s4", + "s4", + "s32" ], "operands": [ { @@ -215036,11 +218056,11 @@ }, { "kind": "register_list", - "length": 4 + "length": 2 }, { "kind": "register_list", - "length": 4 + "length": 2 }, { "kind": "register_list", @@ -215054,58 +218074,55 @@ } ] }, - "summary": "Multiplies warp-distributed sparse e5m2 A and e4m3 B fragments and adds an f32 accumulator." + "summary": "Multiplies warp-distributed sparse signed A and signed B INT4 fragments with ordered sparsity metadata and adds a wrapping s32 accumulator." }, { - "id": "mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e5m2_e5m2_f32", - "operation_key": "matrix.mma.sp.m16n8k64.row.col.kind_f8f6f4.f32.e5m2.e5m2.f32.not_applicable.ordered_metadata", + "id": "mma_sp_ordered_metadata_m16n8k64_s32_s4_satfinite", + "operation_key": "matrix.mma.sp.m16n8k64.row.col.s32.s4.s4.s32.satfinite.ordered_metadata", "family": "sparse_mma", "source": { "kind": "llvm_imported", - "source_record": "int_nvvm_mma_sp_ordered_metadata_m16n8k64_row_col_kind_f8f6f4_f32_e5m2_e5m2_f32" + "source_record": "int_nvvm_mma_sp_ordered_metadata_m16n8k64_row_col_satfinite_s4" }, "selections": [ { - "source_record": "anonymous_19793", - "asm": "mma.sp::ordered_metadata.sync.aligned.m16n8k64.row.col.kind::f8f6f4.f32.e5m2.e5m2.f32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1, $rb2, $rb3}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}},\n\t\t$metadata,\n\t\t$selector;", + "source_record": "anonymous_19681", + "asm": "mma.sp::ordered_metadata.sync.aligned.m16n8k64.row.col.satfinite.s32.s4.s4.s32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1}},\n\t\t{{$rb0, $rb1}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}},\n\t\t$metadata,\n\t\t$selector;", "predicates": [ - "Subtarget->hasMMABlockScale()" + "Subtarget->getSmVersion() >= 80", + "Subtarget->getPTXVersion() >= 85" ] } ], "rust": { - "abi_id": "i0251", + "abi_id": "i0199", "module": "matrix", - "name": "mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e5m2_e5m2_f32", + "name": "mma_sp_ordered_metadata_m16n8k64_s32_s4_satfinite", "arguments": [ - "[f32; 4]", - "[u32; 4]", - "[u32; 4]", + "[i32; 4]", + "[u32; 2]", + "[u32; 2]", "u32", "u32" ], - "result": "[f32; 4]", + "result": "[i32; 4]", "safe": false, "must_use": true, "safe_allowlist_reason": null, - "canonical_path": "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0251", - "public_path": "cuda_intrinsics::matrix::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e5m2_e5m2_f32", + "canonical_path": "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0199", + "public_path": "cuda_intrinsics::matrix::mma_sp_ordered_metadata_m16n8k64_s32_s4_satfinite", "compatibility_paths": [ - "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e5m2_e5m2_f32" + "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_s32_s4_satfinite" ] }, "dialect": { "op_type": "SparseMmaOp", "op_name": "nvvm.sparse_mma", "operands": [ - "f32", - "f32", - "f32", - "f32", - "u32", - "u32", - "u32", - "u32", + "i32", + "i32", + "i32", + "i32", "u32", "u32", "u32", @@ -215114,14 +218131,14 @@ "u32" ], "results": [ - "f32", - "f32", - "f32", - "f32" + "i32", + "i32", + "i32", + "i32" ] }, "llvm": { - "symbol": "llvm.nvvm.mma.sp.ordered.metadata.m16n8k64.row.col.kind.f8f6f4.f32.e5m2.e5m2.f32", + "symbol": "llvm.nvvm.mma.sp.ordered.metadata.m16n8k64.row.col.satfinite.s4", "arguments": [ "i32", "i32", @@ -215131,24 +218148,20 @@ "i32", "i32", "i32", - "f32", - "f32", - "f32", - "f32", "i32", "i32" ], "results": [ - "f32", - "f32", - "f32", - "f32" + "i32", + "i32", + "i32", + "i32" ], "properties": [ - "ImmArg", + "ImmArg", "IntrNoCallback", "IntrNoMem", - "Range" + "Range" ], "result_facts": { "no_undef": false, @@ -215162,30 +218175,18 @@ "execution_scope": "warp" }, "target": { - "minimum_ptx": "8.7", + "minimum_ptx": "8.5", "hardware": { "kind": "any_of", "alternatives": [ { - "kind": "exact_architecture", - "sm": 120 - }, - { - "kind": "family_target", - "sm": 120 - }, - { - "kind": "exact_architecture", - "sm": 121 - }, - { - "kind": "family_target", - "sm": 121 + "kind": "minimum_sm", + "sm": 80 } ] }, - "ptx_result": "[f32; 4]", - "targets": "sm_120a|sm_120f|sm_121a|sm_121f", + "ptx_result": "[i32; 4]", + "targets": "all", "ptx_isa_version": "9.3", "ptx_isa_section": "9.7.15.6.3 Multiply-and-Accumulate Instruction: mma.sp", "ptx_isa_url": "https://docs.nvidia.com/cuda/parallel-thread-execution/#warp-level-matrix-instructions-mma-sp" @@ -215196,8 +218197,8 @@ "sha256": "2e5bc688625ca7d98bca9b5f0f0d14525d2eb59e8a9842964e480df3ffd1f921", "status": "validated", "target_triple": "nvptx64-nvidia-cuda", - "gpu_target": "sm_120a", - "ptx_feature": "+ptx87" + "gpu_target": "sm_80", + "ptx_feature": "+ptx85" }, "backend_lowerings": [ { @@ -215205,25 +218206,13 @@ "mechanism": "inline_ptx", "evidence_profile": "rust-llvm-23.1.0-16696adc", "target": { - "minimum_ptx": "8.7", + "minimum_ptx": "8.5", "hardware": { "kind": "any_of", "alternatives": [ { - "kind": "exact_architecture", - "sm": 120 - }, - { - "kind": "family_target", - "sm": 120 - }, - { - "kind": "exact_architecture", - "sm": 121 - }, - { - "kind": "family_target", - "sm": 121 + "kind": "minimum_sm", + "sm": 80 } ] } @@ -215236,14 +218225,14 @@ "stages": [ { "targets": [ - "sm_120a", - "ptx87" + "sm_80", + "ptx85" ], - "representation": "convergent ordered kind::f8f6f4 F32 inline PTX in public C, A, B, metadata, selector order", + "representation": "convergent ordered sparse m16n8k64 INT4 inline PTX with selectors 0 and 1", "stage": "backend_codegen", "mechanism": "inline_ptx", "outcome": "succeeded", - "detail": "Pinned LLVM lowered the 28,839-byte all-forms source (SHA-256 5518d5dfb092f5ae3ccefe1e7e66eb4df9db7da480722e390587490c6ce8832a) to 12,015-byte PTX (SHA-256 0d93ea01d39bc512b96becf2ad799522d9d5187c17d521294eecd4e69c055e66) containing the exact 25-form matrix at sm_120a and PTX 8.7.", + "detail": "The combined inline-PTX and typed LLVM probes described by the first record each emitted all eight variants with both selector values; this record retained saturating s4-by-s4 PTX.", "artifact_kind": null, "tool_path": null, "tool_version": null, @@ -215251,14 +218240,14 @@ }, { "targets": [ - "sm_120a", - "ptx87" + "sm_80", + "ptx85" ], - "representation": "exact-floor ordered kind::f8f6f4 F32 PTX", + "representation": "exact-floor ordered sparse m16n8k64 INT4 PTX", "stage": "ptx_assembly", "mechanism": "inline_ptx", "outcome": "succeeded", - "detail": "CUDA 13.3 ptxas produced a 12,144-byte cubin (SHA-256 7769d4fe1de8cdf6644b911bc3654ab220f4dd28cc44a83e28793a5d3f381cf3); its 38,172-byte SASS dump (SHA-256 34df448cb5d7367b36657270961981955bb76cc1dd5dd221f673f174c6e10b0a) retains 25 unique QMMA forms. PTX 8.6, sm_120, selector 1, and dynamic selectors were rejected.", + "detail": "CUDA 13.3 ptxas accepted the 4,008-byte combined cubin and the selector and target negative boundaries described by the first record.", "artifact_kind": "cubin", "tool_path": "/usr/local/cuda-13.3/bin/ptxas", "tool_version": "CUDA 13.3 V13.3.33 build cuda_13.3.r13.3/compiler.37862127_0", @@ -215271,25 +218260,13 @@ "mechanism": "inline_ptx", "evidence_profile": "cuda-13.3-libnvvm-13.3.33", "target": { - "minimum_ptx": "8.7", + "minimum_ptx": "8.5", "hardware": { "kind": "any_of", "alternatives": [ { - "kind": "exact_architecture", - "sm": 120 - }, - { - "kind": "family_target", - "sm": 120 - }, - { - "kind": "exact_architecture", - "sm": 121 - }, - { - "kind": "family_target", - "sm": 121 + "kind": "minimum_sm", + "sm": 80 } ] } @@ -215302,14 +218279,14 @@ "stages": [ { "targets": [ - "compute_120a", + "compute_80", "ptx93" ], - "representation": "convergent ordered kind::f8f6f4 F32 inline PTX in public C, A, B, metadata, selector order", + "representation": "convergent ordered sparse m16n8k64 INT4 inline PTX in the generated coverage kernel", "stage": "backend_codegen", "mechanism": "inline_ptx", "outcome": "succeeded", - "detail": "CUDA 13.3 libNVVM retained the exact 25-form matrix in 11,910-byte PTX (SHA-256 a096494f6b066927107cf222f784d1a586ed1cf3ab766669b741e429f03f4427) and produced 14,052-byte LTOIR (SHA-256 99941daa24a78884788ed0908a3764f596c527e6ab621d6085c549aea9575377).", + "detail": "The production artifacts described by the first record retained saturating s4-by-s4 PTX with selector 0.", "artifact_kind": null, "tool_path": null, "tool_version": null, @@ -215317,29 +218294,14 @@ }, { "targets": [ - "sm_120a", - "ptx93" - ], - "representation": "libNVVM-emitted ordered kind::f8f6f4 F32 PTX", - "stage": "ptx_assembly", - "mechanism": "inline_ptx", - "outcome": "succeeded", - "detail": "CUDA 13.3 ptxas produced a 12,144-byte cubin (SHA-256 7769d4fe1de8cdf6644b911bc3654ab220f4dd28cc44a83e28793a5d3f381cf3) retaining all 25 unique QMMA forms.", - "artifact_kind": "cubin", - "tool_path": "/usr/local/cuda-13.3/bin/ptxas", - "tool_version": "CUDA 13.3 V13.3.33 build cuda_13.3.r13.3/compiler.37862127_0", - "tool_sha256": "7fdd01a4cf50e30746da98989c9272a907f491e6fd7fecfda14642e4375f88fb" - }, - { - "targets": [ - "sm_120a", + "sm_80", "ptx93" ], - "representation": "libNVVM LTOIR retaining the ordered kind::f8f6f4 F32 matrix", + "representation": "generated sparse-MMA coverage kernel with ordered m16n8k64 INT4 calls", "stage": "device_link", "mechanism": "inline_ptx", "outcome": "succeeded", - "detail": "CUDA 13.3 nvJitLink produced a 12,144-byte cubin (SHA-256 62457debbb99023b09b3701e14974a97cfc5761f931ebf9f0d9e2bada3e3a642); its 38,172-byte SASS dump (SHA-256 34df448cb5d7367b36657270961981955bb76cc1dd5dd221f673f174c6e10b0a) retains 25 unique QMMA forms.", + "detail": "The 26,600-byte production cubin described by the first record retained all eight raw variants and both compatibility-path calls.", "artifact_kind": "cubin", "tool_path": "/usr/local/cuda-13.3/lib64/libnvJitLink.so.13.3.33", "tool_version": "V13.3.33", @@ -215350,17 +218312,17 @@ ], "sparse_mma": { "shape": "m16n8k64", - "accumulator": "f32", - "a_element": "e5m2", - "b_element": "e5m2", + "accumulator": "s32", + "a_element": "s4", + "b_element": "s4", "a_layout": "row", "b_layout": "col", - "overflow": "not_applicable", + "overflow": "satfinite", "metadata": "ordered", - "selector": "immediate_zero", + "selector": "immediate_zero_or_one", "participation": "all_warp_lanes_same_instruction_and_qualifiers_no_exited_lanes", - "adapter": "c4_f32_a4_u32_b4_u32_metadata_u32_selector_u32_to_d4_f32", - "llvm_adapter": "a4_i32_b4_i32_c4_f32_metadata_i32_selector_i32_to_d4_f32", + "adapter": "c4_i32_a2_u32_b2_u32_metadata_u32_selector_u32_to_d4_i32", + "llvm_adapter": "a2_i32_b2_i32_c4_i32_metadata_i32_selector_i32_to_d4_i32", "compatibility_source": "generated_stub", "runtime_validation": "unexecuted" }, @@ -215374,11 +218336,11 @@ "m16n8k64", "row", "col", - "kind::f8f6f4", - "f32", - "e5m2", - "e5m2", - "f32" + "satfinite", + "s32", + "s4", + "s4", + "s32" ], "operands": [ { @@ -215387,11 +218349,11 @@ }, { "kind": "register_list", - "length": 4 + "length": 2 }, { "kind": "register_list", - "length": 4 + "length": 2 }, { "kind": "register_list", @@ -215405,20 +218367,20 @@ } ] }, - "summary": "Multiplies warp-distributed sparse e5m2 A and e5m2 B fragments and adds an f32 accumulator." + "summary": "Multiplies warp-distributed sparse signed A and signed B INT4 fragments with ordered sparsity metadata and adds a saturating s32 accumulator." }, { - "id": "mma_sp_ordered_metadata_m16n8k64_s32_s4", - "operation_key": "matrix.mma.sp.m16n8k64.row.col.s32.s4.s4.s32.wrapping.ordered_metadata", + "id": "mma_sp_ordered_metadata_m16n8k64_s32_s4_u4", + "operation_key": "matrix.mma.sp.m16n8k64.row.col.s32.s4.u4.s32.wrapping.ordered_metadata", "family": "sparse_mma", "source": { "kind": "llvm_imported", - "source_record": "int_nvvm_mma_sp_ordered_metadata_m16n8k64_row_col_s4" + "source_record": "int_nvvm_mma_sp_ordered_metadata_m16n8k64_row_col_s4_u4" }, "selections": [ { - "source_record": "anonymous_19600", - "asm": "mma.sp::ordered_metadata.sync.aligned.m16n8k64.row.col.s32.s4.s4.s32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1}},\n\t\t{{$rb0, $rb1}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}},\n\t\t$metadata,\n\t\t$selector;", + "source_record": "anonymous_19605", + "asm": "mma.sp::ordered_metadata.sync.aligned.m16n8k64.row.col.s32.s4.u4.s32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1}},\n\t\t{{$rb0, $rb1}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}},\n\t\t$metadata,\n\t\t$selector;", "predicates": [ "Subtarget->getSmVersion() >= 80", "Subtarget->getPTXVersion() >= 85" @@ -215426,9 +218388,9 @@ } ], "rust": { - "abi_id": "i0195", + "abi_id": "i0196", "module": "matrix", - "name": "mma_sp_ordered_metadata_m16n8k64_s32_s4", + "name": "mma_sp_ordered_metadata_m16n8k64_s32_s4_u4", "arguments": [ "[i32; 4]", "[u32; 2]", @@ -215440,10 +218402,10 @@ "safe": false, "must_use": true, "safe_allowlist_reason": null, - "canonical_path": "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0195", - "public_path": "cuda_intrinsics::matrix::mma_sp_ordered_metadata_m16n8k64_s32_s4", + "canonical_path": "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0196", + "public_path": "cuda_intrinsics::matrix::mma_sp_ordered_metadata_m16n8k64_s32_s4_u4", "compatibility_paths": [ - "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_s32_s4" + "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_s32_s4_u4" ] }, "dialect": { @@ -215469,7 +218431,7 @@ ] }, "llvm": { - "symbol": "llvm.nvvm.mma.sp.ordered.metadata.m16n8k64.row.col.s4", + "symbol": "llvm.nvvm.mma.sp.ordered.metadata.m16n8k64.row.col.s4.u4", "arguments": [ "i32", "i32", @@ -215563,7 +218525,7 @@ "stage": "backend_codegen", "mechanism": "inline_ptx", "outcome": "succeeded", - "detail": "The 8,107-byte combined inline-PTX probe (SHA-256 ce31bb4c5d7f083ae8e1293a0a3e5196575482427a041d549f9ecd3862e46942) used public C, A, B, metadata, selector order and covered all eight variants with both selector values. Pinned LLVM emitted 8,453-byte PTX (SHA-256 7a8bb0261fd16c1941b47500d70f3cff95a1acb95c51e52480af15a4effc8818) with exactly 16 ordered m16n8k64 INT4 instructions. An auxiliary 6,948-byte typed LLVM comparison (SHA-256 379488c94c4e3d6b1806928d72723845b7bd329857f4dfc3caf8f74d7a5c6649) used source A, B, C, metadata, selector order and emitted 22,330-byte PTX (SHA-256 913b74cc0dba68779655073b83e5a534bcf076fa5e6a1d1d6029ef951b0fc1cd) with the same 16 forms; this record retained wrapping s4-by-s4 PTX.", + "detail": "The combined inline-PTX and typed LLVM probes described by the first record each emitted all eight variants with both selector values; this record retained wrapping s4-by-u4 PTX.", "artifact_kind": null, "tool_path": null, "tool_version": null, @@ -215578,7 +218540,7 @@ "stage": "ptx_assembly", "mechanism": "inline_ptx", "outcome": "succeeded", - "detail": "CUDA 13.3 ptxas accepted all 16 instructions and produced a 4,008-byte cubin with SHA-256 a6df23e0492e6f26ede3da7f7fab6c9fdab2693c5c2d6bda12339948cba640ec containing exactly 16 IMMA.SP.16864 instructions. LLVM and ptxas rejected selector 2 and dynamic selectors; ptxas also rejected PTX 8.4 and sm_75.", + "detail": "CUDA 13.3 ptxas accepted the 4,008-byte combined cubin and the selector and target negative boundaries described by the first record.", "artifact_kind": "cubin", "tool_path": "/usr/local/cuda-13.3/bin/ptxas", "tool_version": "CUDA 13.3 V13.3.33 build cuda_13.3.r13.3/compiler.37862127_0", @@ -215617,7 +218579,7 @@ "stage": "backend_codegen", "mechanism": "inline_ptx", "outcome": "succeeded", - "detail": "The production generated_intrinsics route produced 294,949-byte compute_80 NVVM IR with SHA-256 787025e167bb7bb790fab0af002f838502536834145304ce8df3fc75227059d2 and 82,648-byte LTOIR with SHA-256 eb6516ac258f3c70d20879de097822b13ab73e00288691ae9a13e17bc7fe0d1a. All eight raw variants use selectors 0 and 1. An auxiliary 8,107-byte combined probe with SHA-256 ce31bb4c5d7f083ae8e1293a0a3e5196575482427a041d549f9ecd3862e46942 separately covered every variant with both selectors.", + "detail": "The production artifacts described by the first record retained wrapping s4-by-u4 PTX with selector 1.", "artifact_kind": null, "tool_path": null, "tool_version": null, @@ -215632,7 +218594,7 @@ "stage": "device_link", "mechanism": "inline_ptx", "outcome": "succeeded", - "detail": "nvJitLink produced a 26,600-byte cubin with SHA-256 1837a2742ce837ccf16b4900b50a72fb018a49bd1850bafe62b3a2a31f550406. Disassembly contained 50 IMMA.SP instructions in total, exactly 30 IMMA.SP.16864 instructions, and exactly 10 ordered m16n8k64 INT4 forms: all eight raw variants plus two compatibility-path calls.", + "detail": "The 26,600-byte production cubin described by the first record retained all eight raw variants and both compatibility-path calls.", "artifact_kind": "cubin", "tool_path": "/usr/local/cuda-13.3/lib64/libnvJitLink.so.13.3.33", "tool_version": "V13.3.33", @@ -215645,7 +218607,7 @@ "shape": "m16n8k64", "accumulator": "s32", "a_element": "s4", - "b_element": "s4", + "b_element": "u4", "a_layout": "row", "b_layout": "col", "overflow": "wrapping", @@ -215669,7 +218631,7 @@ "col", "s32", "s4", - "s4", + "u4", "s32" ], "operands": [ @@ -215697,20 +218659,20 @@ } ] }, - "summary": "Multiplies warp-distributed sparse signed A and signed B INT4 fragments with ordered sparsity metadata and adds a wrapping s32 accumulator." + "summary": "Multiplies warp-distributed sparse signed A and unsigned B INT4 fragments with ordered sparsity metadata and adds a wrapping s32 accumulator." }, { - "id": "mma_sp_ordered_metadata_m16n8k64_s32_s4_satfinite", - "operation_key": "matrix.mma.sp.m16n8k64.row.col.s32.s4.s4.s32.satfinite.ordered_metadata", + "id": "mma_sp_ordered_metadata_m16n8k64_s32_s4_u4_satfinite", + "operation_key": "matrix.mma.sp.m16n8k64.row.col.s32.s4.u4.s32.satfinite.ordered_metadata", "family": "sparse_mma", "source": { "kind": "llvm_imported", - "source_record": "int_nvvm_mma_sp_ordered_metadata_m16n8k64_row_col_satfinite_s4" + "source_record": "int_nvvm_mma_sp_ordered_metadata_m16n8k64_row_col_satfinite_s4_u4" }, "selections": [ { - "source_record": "anonymous_19681", - "asm": "mma.sp::ordered_metadata.sync.aligned.m16n8k64.row.col.satfinite.s32.s4.s4.s32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1}},\n\t\t{{$rb0, $rb1}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}},\n\t\t$metadata,\n\t\t$selector;", + "source_record": "anonymous_19684", + "asm": "mma.sp::ordered_metadata.sync.aligned.m16n8k64.row.col.satfinite.s32.s4.u4.s32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1}},\n\t\t{{$rb0, $rb1}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}},\n\t\t$metadata,\n\t\t$selector;", "predicates": [ "Subtarget->getSmVersion() >= 80", "Subtarget->getPTXVersion() >= 85" @@ -215718,9 +218680,9 @@ } ], "rust": { - "abi_id": "i0199", + "abi_id": "i0200", "module": "matrix", - "name": "mma_sp_ordered_metadata_m16n8k64_s32_s4_satfinite", + "name": "mma_sp_ordered_metadata_m16n8k64_s32_s4_u4_satfinite", "arguments": [ "[i32; 4]", "[u32; 2]", @@ -215732,10 +218694,10 @@ "safe": false, "must_use": true, "safe_allowlist_reason": null, - "canonical_path": "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0199", - "public_path": "cuda_intrinsics::matrix::mma_sp_ordered_metadata_m16n8k64_s32_s4_satfinite", + "canonical_path": "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0200", + "public_path": "cuda_intrinsics::matrix::mma_sp_ordered_metadata_m16n8k64_s32_s4_u4_satfinite", "compatibility_paths": [ - "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_s32_s4_satfinite" + "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_s32_s4_u4_satfinite" ] }, "dialect": { @@ -215761,7 +218723,7 @@ ] }, "llvm": { - "symbol": "llvm.nvvm.mma.sp.ordered.metadata.m16n8k64.row.col.satfinite.s4", + "symbol": "llvm.nvvm.mma.sp.ordered.metadata.m16n8k64.row.col.satfinite.s4.u4", "arguments": [ "i32", "i32", @@ -215855,7 +218817,7 @@ "stage": "backend_codegen", "mechanism": "inline_ptx", "outcome": "succeeded", - "detail": "The combined inline-PTX and typed LLVM probes described by the first record each emitted all eight variants with both selector values; this record retained saturating s4-by-s4 PTX.", + "detail": "The combined inline-PTX and typed LLVM probes described by the first record each emitted all eight variants with both selector values; this record retained saturating s4-by-u4 PTX.", "artifact_kind": null, "tool_path": null, "tool_version": null, @@ -215909,7 +218871,7 @@ "stage": "backend_codegen", "mechanism": "inline_ptx", "outcome": "succeeded", - "detail": "The production artifacts described by the first record retained saturating s4-by-s4 PTX with selector 0.", + "detail": "The production artifacts described by the first record retained saturating s4-by-u4 PTX with selector 1.", "artifact_kind": null, "tool_path": null, "tool_version": null, @@ -215937,7 +218899,7 @@ "shape": "m16n8k64", "accumulator": "s32", "a_element": "s4", - "b_element": "s4", + "b_element": "u4", "a_layout": "row", "b_layout": "col", "overflow": "satfinite", @@ -215962,7 +218924,7 @@ "satfinite", "s32", "s4", - "s4", + "u4", "s32" ], "operands": [ @@ -215990,20 +218952,20 @@ } ] }, - "summary": "Multiplies warp-distributed sparse signed A and signed B INT4 fragments with ordered sparsity metadata and adds a saturating s32 accumulator." + "summary": "Multiplies warp-distributed sparse signed A and unsigned B INT4 fragments with ordered sparsity metadata and adds a saturating s32 accumulator." }, { - "id": "mma_sp_ordered_metadata_m16n8k64_s32_s4_u4", - "operation_key": "matrix.mma.sp.m16n8k64.row.col.s32.s4.u4.s32.wrapping.ordered_metadata", + "id": "mma_sp_ordered_metadata_m16n8k64_s32_s8", + "operation_key": "matrix.mma.sp.m16n8k64.row.col.s32.s8.s8.s32.wrapping.ordered_metadata", "family": "sparse_mma", "source": { "kind": "llvm_imported", - "source_record": "int_nvvm_mma_sp_ordered_metadata_m16n8k64_row_col_s4_u4" + "source_record": "int_nvvm_mma_sp_ordered_metadata_m16n8k64_row_col_s8" }, "selections": [ { - "source_record": "anonymous_19605", - "asm": "mma.sp::ordered_metadata.sync.aligned.m16n8k64.row.col.s32.s4.u4.s32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1}},\n\t\t{{$rb0, $rb1}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}},\n\t\t$metadata,\n\t\t$selector;", + "source_record": "anonymous_19664", + "asm": "mma.sp::ordered_metadata.sync.aligned.m16n8k64.row.col.s32.s8.s8.s32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1, $rb2, $rb3}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}},\n\t\t$metadata,\n\t\t$selector;", "predicates": [ "Subtarget->getSmVersion() >= 80", "Subtarget->getPTXVersion() >= 85" @@ -216011,13 +218973,13 @@ } ], "rust": { - "abi_id": "i0196", + "abi_id": "i0179", "module": "matrix", - "name": "mma_sp_ordered_metadata_m16n8k64_s32_s4_u4", + "name": "mma_sp_ordered_metadata_m16n8k64_s32_s8", "arguments": [ "[i32; 4]", - "[u32; 2]", - "[u32; 2]", + "[u32; 4]", + "[u32; 4]", "u32", "u32" ], @@ -216025,10 +218987,10 @@ "safe": false, "must_use": true, "safe_allowlist_reason": null, - "canonical_path": "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0196", - "public_path": "cuda_intrinsics::matrix::mma_sp_ordered_metadata_m16n8k64_s32_s4_u4", + "canonical_path": "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0179", + "public_path": "cuda_intrinsics::matrix::mma_sp_ordered_metadata_m16n8k64_s32_s8", "compatibility_paths": [ - "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_s32_s4_u4" + "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_s32_s8" ] }, "dialect": { @@ -216044,294 +219006,6 @@ "u32", "u32", "u32", - "u32" - ], - "results": [ - "i32", - "i32", - "i32", - "i32" - ] - }, - "llvm": { - "symbol": "llvm.nvvm.mma.sp.ordered.metadata.m16n8k64.row.col.s4.u4", - "arguments": [ - "i32", - "i32", - "i32", - "i32", - "i32", - "i32", - "i32", - "i32", - "i32", - "i32" - ], - "results": [ - "i32", - "i32", - "i32", - "i32" - ], - "properties": [ - "ImmArg", - "IntrNoCallback", - "IntrNoMem", - "Range" - ], - "result_facts": { - "no_undef": false, - "range": null - } - }, - "semantics": { - "pure": false, - "memory": "none", - "convergent": true, - "execution_scope": "warp" - }, - "target": { - "minimum_ptx": "8.5", - "hardware": { - "kind": "any_of", - "alternatives": [ - { - "kind": "minimum_sm", - "sm": 80 - } - ] - }, - "ptx_result": "[i32; 4]", - "targets": "all", - "ptx_isa_version": "9.3", - "ptx_isa_section": "9.7.15.6.3 Multiply-and-Accumulate Instruction: mma.sp", - "ptx_isa_url": "https://docs.nvidia.com/cuda/parallel-thread-execution/#warp-level-matrix-instructions-mma-sp" - }, - "backend": { - "profile": "rust-llvm-23.1.0-16696adc", - "version": "LLVM version 23.1.0-rust-1.100.0-nightly", - "sha256": "2e5bc688625ca7d98bca9b5f0f0d14525d2eb59e8a9842964e480df3ffd1f921", - "status": "validated", - "target_triple": "nvptx64-nvidia-cuda", - "gpu_target": "sm_80", - "ptx_feature": "+ptx85" - }, - "backend_lowerings": [ - { - "backend": "llvm_nvptx", - "mechanism": "inline_ptx", - "evidence_profile": "rust-llvm-23.1.0-16696adc", - "target": { - "minimum_ptx": "8.5", - "hardware": { - "kind": "any_of", - "alternatives": [ - { - "kind": "minimum_sm", - "sm": 80 - } - ] - } - }, - "version": "LLVM version 23.1.0-rust-1.100.0-nightly", - "sha256": "2e5bc688625ca7d98bca9b5f0f0d14525d2eb59e8a9842964e480df3ffd1f921", - "artifact_path": null, - "build_id_prefix": null, - "status": "validated", - "stages": [ - { - "targets": [ - "sm_80", - "ptx85" - ], - "representation": "convergent ordered sparse m16n8k64 INT4 inline PTX with selectors 0 and 1", - "stage": "backend_codegen", - "mechanism": "inline_ptx", - "outcome": "succeeded", - "detail": "The combined inline-PTX and typed LLVM probes described by the first record each emitted all eight variants with both selector values; this record retained wrapping s4-by-u4 PTX.", - "artifact_kind": null, - "tool_path": null, - "tool_version": null, - "tool_sha256": null - }, - { - "targets": [ - "sm_80", - "ptx85" - ], - "representation": "exact-floor ordered sparse m16n8k64 INT4 PTX", - "stage": "ptx_assembly", - "mechanism": "inline_ptx", - "outcome": "succeeded", - "detail": "CUDA 13.3 ptxas accepted the 4,008-byte combined cubin and the selector and target negative boundaries described by the first record.", - "artifact_kind": "cubin", - "tool_path": "/usr/local/cuda-13.3/bin/ptxas", - "tool_version": "CUDA 13.3 V13.3.33 build cuda_13.3.r13.3/compiler.37862127_0", - "tool_sha256": "7fdd01a4cf50e30746da98989c9272a907f491e6fd7fecfda14642e4375f88fb" - } - ] - }, - { - "backend": "lib_nvvm", - "mechanism": "inline_ptx", - "evidence_profile": "cuda-13.3-libnvvm-13.3.33", - "target": { - "minimum_ptx": "8.5", - "hardware": { - "kind": "any_of", - "alternatives": [ - { - "kind": "minimum_sm", - "sm": 80 - } - ] - } - }, - "version": "CUDA toolkit 13.3; nvcc/libNVVM release V13.3.33", - "sha256": "b6a5db233133fb0ed693f8cb8aeb1d405254ce0ab10364478985292ec98cfcf0", - "artifact_path": "/usr/local/cuda-13.3/nvvm/lib64/libnvvm.so.4.0.0", - "build_id_prefix": "2330c0", - "status": "validated", - "stages": [ - { - "targets": [ - "compute_80", - "ptx93" - ], - "representation": "convergent ordered sparse m16n8k64 INT4 inline PTX in the generated coverage kernel", - "stage": "backend_codegen", - "mechanism": "inline_ptx", - "outcome": "succeeded", - "detail": "The production artifacts described by the first record retained wrapping s4-by-u4 PTX with selector 1.", - "artifact_kind": null, - "tool_path": null, - "tool_version": null, - "tool_sha256": null - }, - { - "targets": [ - "sm_80", - "ptx93" - ], - "representation": "generated sparse-MMA coverage kernel with ordered m16n8k64 INT4 calls", - "stage": "device_link", - "mechanism": "inline_ptx", - "outcome": "succeeded", - "detail": "The 26,600-byte production cubin described by the first record retained all eight raw variants and both compatibility-path calls.", - "artifact_kind": "cubin", - "tool_path": "/usr/local/cuda-13.3/lib64/libnvJitLink.so.13.3.33", - "tool_version": "V13.3.33", - "tool_sha256": "3ba1e744347cd68617b862eccfd98b125482e882b7a6319f42abc9a768513db8" - } - ] - } - ], - "sparse_mma": { - "shape": "m16n8k64", - "accumulator": "s32", - "a_element": "s4", - "b_element": "u4", - "a_layout": "row", - "b_layout": "col", - "overflow": "wrapping", - "metadata": "ordered", - "selector": "immediate_zero_or_one", - "participation": "all_warp_lanes_same_instruction_and_qualifiers_no_exited_lanes", - "adapter": "c4_i32_a2_u32_b2_u32_metadata_u32_selector_u32_to_d4_i32", - "llvm_adapter": "a2_i32_b2_i32_c4_i32_metadata_i32_selector_i32_to_d4_i32", - "compatibility_source": "generated_stub", - "runtime_validation": "unexecuted" - }, - "lowering": "generated_sparse_mma", - "expected_ptx": { - "mnemonic": "mma", - "modifiers": [ - "sp::ordered_metadata", - "sync", - "aligned", - "m16n8k64", - "row", - "col", - "s32", - "s4", - "u4", - "s32" - ], - "operands": [ - { - "kind": "register_list", - "length": 4 - }, - { - "kind": "register_list", - "length": 2 - }, - { - "kind": "register_list", - "length": 2 - }, - { - "kind": "register_list", - "length": 4 - }, - { - "kind": "register" - }, - { - "kind": "immediate" - } - ] - }, - "summary": "Multiplies warp-distributed sparse signed A and unsigned B INT4 fragments with ordered sparsity metadata and adds a wrapping s32 accumulator." - }, - { - "id": "mma_sp_ordered_metadata_m16n8k64_s32_s4_u4_satfinite", - "operation_key": "matrix.mma.sp.m16n8k64.row.col.s32.s4.u4.s32.satfinite.ordered_metadata", - "family": "sparse_mma", - "source": { - "kind": "llvm_imported", - "source_record": "int_nvvm_mma_sp_ordered_metadata_m16n8k64_row_col_satfinite_s4_u4" - }, - "selections": [ - { - "source_record": "anonymous_19684", - "asm": "mma.sp::ordered_metadata.sync.aligned.m16n8k64.row.col.satfinite.s32.s4.u4.s32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1}},\n\t\t{{$rb0, $rb1}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}},\n\t\t$metadata,\n\t\t$selector;", - "predicates": [ - "Subtarget->getSmVersion() >= 80", - "Subtarget->getPTXVersion() >= 85" - ] - } - ], - "rust": { - "abi_id": "i0200", - "module": "matrix", - "name": "mma_sp_ordered_metadata_m16n8k64_s32_s4_u4_satfinite", - "arguments": [ - "[i32; 4]", - "[u32; 2]", - "[u32; 2]", - "u32", - "u32" - ], - "result": "[i32; 4]", - "safe": false, - "must_use": true, - "safe_allowlist_reason": null, - "canonical_path": "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0200", - "public_path": "cuda_intrinsics::matrix::mma_sp_ordered_metadata_m16n8k64_s32_s4_u4_satfinite", - "compatibility_paths": [ - "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_s32_s4_u4_satfinite" - ] - }, - "dialect": { - "op_type": "SparseMmaOp", - "op_name": "nvvm.sparse_mma", - "operands": [ - "i32", - "i32", - "i32", - "i32", - "u32", "u32", "u32", "u32", @@ -216346,7 +219020,7 @@ ] }, "llvm": { - "symbol": "llvm.nvvm.mma.sp.ordered.metadata.m16n8k64.row.col.satfinite.s4.u4", + "symbol": "llvm.nvvm.mma.sp.ordered.metadata.m16n8k64.row.col.s8", "arguments": [ "i32", "i32", @@ -216357,6 +219031,10 @@ "i32", "i32", "i32", + "i32", + "i32", + "i32", + "i32", "i32" ], "results": [ @@ -216366,10 +219044,10 @@ "i32" ], "properties": [ - "ImmArg", + "ImmArg", "IntrNoCallback", "IntrNoMem", - "Range" + "Range" ], "result_facts": { "no_undef": false, @@ -216436,11 +219114,11 @@ "sm_80", "ptx85" ], - "representation": "convergent ordered sparse m16n8k64 INT4 inline PTX with selectors 0 and 1", + "representation": "convergent ordered sparse m16n8k64 signed INT8 inline PTX with selector 0", "stage": "backend_codegen", "mechanism": "inline_ptx", "outcome": "succeeded", - "detail": "The combined inline-PTX and typed LLVM probes described by the first record each emitted all eight variants with both selector values; this record retained saturating s4-by-u4 PTX.", + "detail": "The 4,779-byte combined LLVM IR probe (SHA-256 01600853ff696df81a849a3d804086265d07d61c7a2f24ebaf7b3f056753fccb) covered all eight variants. Pinned LLVM emitted 13,390-byte PTX (SHA-256 b370bcbebbe761bd65675ad2d2602230cc315189a1bb8cb1c4533c68b564a897) with exactly eight ordered m16n8k64 instructions at PTX 8.5 and sm_80; this record retained exact wrapping s8-by-s8 PTX with selector 0.", "artifact_kind": null, "tool_path": null, "tool_version": null, @@ -216451,12 +219129,12 @@ "sm_80", "ptx85" ], - "representation": "exact-floor ordered sparse m16n8k64 INT4 PTX", + "representation": "exact-floor ordered sparse m16n8k64 INT8 PTX", "stage": "ptx_assembly", "mechanism": "inline_ptx", "outcome": "succeeded", - "detail": "CUDA 13.3 ptxas accepted the 4,008-byte combined cubin and the selector and target negative boundaries described by the first record.", - "artifact_kind": "cubin", + "detail": "CUDA 13.3 ptxas accepted all eight exact instructions and produced a 1,464-byte cubin with SHA-256 6bcec1b1eab13da703fdade053704aa6ab00591a1b38dd7daf48ac0dec541df2. Because every probe function was unreferenced, ptxas removed their bodies; this proves assembly acceptance, not retained SASS.", + "artifact_kind": null, "tool_path": "/usr/local/cuda-13.3/bin/ptxas", "tool_version": "CUDA 13.3 V13.3.33 build cuda_13.3.r13.3/compiler.37862127_0", "tool_sha256": "7fdd01a4cf50e30746da98989c9272a907f491e6fd7fecfda14642e4375f88fb" @@ -216490,11 +219168,11 @@ "compute_80", "ptx93" ], - "representation": "convergent ordered sparse m16n8k64 INT4 inline PTX in the generated coverage kernel", + "representation": "convergent ordered sparse m16n8k64 signed INT8 inline PTX in the combined coverage kernel", "stage": "backend_codegen", "mechanism": "inline_ptx", "outcome": "succeeded", - "detail": "The production artifacts described by the first record retained saturating s4-by-u4 PTX with selector 1.", + "detail": "The production generated_intrinsics route produced 242,464-byte compute_80 NVVM IR with SHA-256 fcc2fe1a6200de7b5ab8a38cab847432669fe4d6ce823c81b73f9b18fa25144c and 68,600-byte LTOIR with SHA-256 aa011070e20cb91d99f0d6d41ffd3883f01031b44d171380f638e3674b2facf3. All eight raw variants use compile-time selector 0.", "artifact_kind": null, "tool_path": null, "tool_version": null, @@ -216505,11 +219183,11 @@ "sm_80", "ptx93" ], - "representation": "generated sparse-MMA coverage kernel with ordered m16n8k64 INT4 calls", + "representation": "combined sparse INT8 coverage kernel with ordered m16n8k64 calls", "stage": "device_link", "mechanism": "inline_ptx", "outcome": "succeeded", - "detail": "The 26,600-byte production cubin described by the first record retained all eight raw variants and both compatibility-path calls.", + "detail": "nvJitLink produced a 23,656-byte cubin with SHA-256 8a09455f87f3ef0c7c16adf13bf6030cbe7f0f18df7fcd91ec2a19a10de5b50d. Disassembly contained 30 IMMA.SP instructions in total and exactly 10 IMMA.SP.16864 instructions: all eight raw variants plus two compatibility-path calls.", "artifact_kind": "cubin", "tool_path": "/usr/local/cuda-13.3/lib64/libnvJitLink.so.13.3.33", "tool_version": "V13.3.33", @@ -216521,16 +219199,16 @@ "sparse_mma": { "shape": "m16n8k64", "accumulator": "s32", - "a_element": "s4", - "b_element": "u4", + "a_element": "s8", + "b_element": "s8", "a_layout": "row", "b_layout": "col", - "overflow": "satfinite", + "overflow": "wrapping", "metadata": "ordered", - "selector": "immediate_zero_or_one", + "selector": "immediate_zero", "participation": "all_warp_lanes_same_instruction_and_qualifiers_no_exited_lanes", - "adapter": "c4_i32_a2_u32_b2_u32_metadata_u32_selector_u32_to_d4_i32", - "llvm_adapter": "a2_i32_b2_i32_c4_i32_metadata_i32_selector_i32_to_d4_i32", + "adapter": "c4_i32_a4_u32_b4_u32_metadata_u32_selector_u32_to_d4_i32", + "llvm_adapter": "a4_i32_b4_i32_c4_i32_metadata_i32_selector_i32_to_d4_i32", "compatibility_source": "generated_stub", "runtime_validation": "unexecuted" }, @@ -216544,10 +219222,9 @@ "m16n8k64", "row", "col", - "satfinite", "s32", - "s4", - "u4", + "s8", + "s8", "s32" ], "operands": [ @@ -216557,11 +219234,11 @@ }, { "kind": "register_list", - "length": 2 + "length": 4 }, { "kind": "register_list", - "length": 2 + "length": 4 }, { "kind": "register_list", @@ -216575,20 +219252,20 @@ } ] }, - "summary": "Multiplies warp-distributed sparse signed A and unsigned B INT4 fragments with ordered sparsity metadata and adds a saturating s32 accumulator." + "summary": "Multiplies warp-distributed sparse signed A and signed B INT8 fragments with ordered sparsity metadata and adds a wrapping s32 accumulator." }, { - "id": "mma_sp_ordered_metadata_m16n8k64_s32_s8", - "operation_key": "matrix.mma.sp.m16n8k64.row.col.s32.s8.s8.s32.wrapping.ordered_metadata", + "id": "mma_sp_ordered_metadata_m16n8k64_s32_s8_satfinite", + "operation_key": "matrix.mma.sp.m16n8k64.row.col.s32.s8.s8.s32.satfinite.ordered_metadata", "family": "sparse_mma", "source": { "kind": "llvm_imported", - "source_record": "int_nvvm_mma_sp_ordered_metadata_m16n8k64_row_col_s8" + "source_record": "int_nvvm_mma_sp_ordered_metadata_m16n8k64_row_col_satfinite_s8" }, "selections": [ { - "source_record": "anonymous_19664", - "asm": "mma.sp::ordered_metadata.sync.aligned.m16n8k64.row.col.s32.s8.s8.s32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1, $rb2, $rb3}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}},\n\t\t$metadata,\n\t\t$selector;", + "source_record": "anonymous_19717", + "asm": "mma.sp::ordered_metadata.sync.aligned.m16n8k64.row.col.satfinite.s32.s8.s8.s32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1, $rb2, $rb3}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}},\n\t\t$metadata,\n\t\t$selector;", "predicates": [ "Subtarget->getSmVersion() >= 80", "Subtarget->getPTXVersion() >= 85" @@ -216596,9 +219273,9 @@ } ], "rust": { - "abi_id": "i0179", + "abi_id": "i0183", "module": "matrix", - "name": "mma_sp_ordered_metadata_m16n8k64_s32_s8", + "name": "mma_sp_ordered_metadata_m16n8k64_s32_s8_satfinite", "arguments": [ "[i32; 4]", "[u32; 4]", @@ -216610,10 +219287,10 @@ "safe": false, "must_use": true, "safe_allowlist_reason": null, - "canonical_path": "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0179", - "public_path": "cuda_intrinsics::matrix::mma_sp_ordered_metadata_m16n8k64_s32_s8", + "canonical_path": "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0183", + "public_path": "cuda_intrinsics::matrix::mma_sp_ordered_metadata_m16n8k64_s32_s8_satfinite", "compatibility_paths": [ - "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_s32_s8" + "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_s32_s8_satfinite" ] }, "dialect": { @@ -216643,7 +219320,7 @@ ] }, "llvm": { - "symbol": "llvm.nvvm.mma.sp.ordered.metadata.m16n8k64.row.col.s8", + "symbol": "llvm.nvvm.mma.sp.ordered.metadata.m16n8k64.row.col.satfinite.s8", "arguments": [ "i32", "i32", @@ -216737,11 +219414,11 @@ "sm_80", "ptx85" ], - "representation": "convergent ordered sparse m16n8k64 signed INT8 inline PTX with selector 0", + "representation": "convergent ordered sparse m16n8k64 signed saturating INT8 inline PTX with selector 0", "stage": "backend_codegen", "mechanism": "inline_ptx", "outcome": "succeeded", - "detail": "The 4,779-byte combined LLVM IR probe (SHA-256 01600853ff696df81a849a3d804086265d07d61c7a2f24ebaf7b3f056753fccb) covered all eight variants. Pinned LLVM emitted 13,390-byte PTX (SHA-256 b370bcbebbe761bd65675ad2d2602230cc315189a1bb8cb1c4533c68b564a897) with exactly eight ordered m16n8k64 instructions at PTX 8.5 and sm_80; this record retained exact wrapping s8-by-s8 PTX with selector 0.", + "detail": "The 4,779-byte combined LLVM IR probe (SHA-256 01600853ff696df81a849a3d804086265d07d61c7a2f24ebaf7b3f056753fccb) covered all eight variants. Pinned LLVM emitted 13,390-byte PTX (SHA-256 b370bcbebbe761bd65675ad2d2602230cc315189a1bb8cb1c4533c68b564a897) with exactly eight ordered m16n8k64 instructions at PTX 8.5 and sm_80; this record retained exact saturating s8-by-s8 PTX with selector 0.", "artifact_kind": null, "tool_path": null, "tool_version": null, @@ -216791,7 +219468,7 @@ "compute_80", "ptx93" ], - "representation": "convergent ordered sparse m16n8k64 signed INT8 inline PTX in the combined coverage kernel", + "representation": "convergent ordered sparse m16n8k64 signed saturating INT8 inline PTX in the combined coverage kernel", "stage": "backend_codegen", "mechanism": "inline_ptx", "outcome": "succeeded", @@ -216826,7 +219503,7 @@ "b_element": "s8", "a_layout": "row", "b_layout": "col", - "overflow": "wrapping", + "overflow": "satfinite", "metadata": "ordered", "selector": "immediate_zero", "participation": "all_warp_lanes_same_instruction_and_qualifiers_no_exited_lanes", @@ -216845,6 +219522,7 @@ "m16n8k64", "row", "col", + "satfinite", "s32", "s8", "s8", @@ -216875,20 +219553,20 @@ } ] }, - "summary": "Multiplies warp-distributed sparse signed A and signed B INT8 fragments with ordered sparsity metadata and adds a wrapping s32 accumulator." + "summary": "Multiplies warp-distributed sparse signed A and signed B INT8 fragments with ordered sparsity metadata and adds a saturating s32 accumulator." }, { - "id": "mma_sp_ordered_metadata_m16n8k64_s32_s8_satfinite", - "operation_key": "matrix.mma.sp.m16n8k64.row.col.s32.s8.s8.s32.satfinite.ordered_metadata", + "id": "mma_sp_ordered_metadata_m16n8k64_s32_s8_u8", + "operation_key": "matrix.mma.sp.m16n8k64.row.col.s32.s8.u8.s32.wrapping.ordered_metadata", "family": "sparse_mma", "source": { "kind": "llvm_imported", - "source_record": "int_nvvm_mma_sp_ordered_metadata_m16n8k64_row_col_satfinite_s8" + "source_record": "int_nvvm_mma_sp_ordered_metadata_m16n8k64_row_col_s8_u8" }, "selections": [ { - "source_record": "anonymous_19717", - "asm": "mma.sp::ordered_metadata.sync.aligned.m16n8k64.row.col.satfinite.s32.s8.s8.s32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1, $rb2, $rb3}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}},\n\t\t$metadata,\n\t\t$selector;", + "source_record": "anonymous_19669", + "asm": "mma.sp::ordered_metadata.sync.aligned.m16n8k64.row.col.s32.s8.u8.s32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1, $rb2, $rb3}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}},\n\t\t$metadata,\n\t\t$selector;", "predicates": [ "Subtarget->getSmVersion() >= 80", "Subtarget->getPTXVersion() >= 85" @@ -216896,9 +219574,9 @@ } ], "rust": { - "abi_id": "i0183", + "abi_id": "i0180", "module": "matrix", - "name": "mma_sp_ordered_metadata_m16n8k64_s32_s8_satfinite", + "name": "mma_sp_ordered_metadata_m16n8k64_s32_s8_u8", "arguments": [ "[i32; 4]", "[u32; 4]", @@ -216910,10 +219588,10 @@ "safe": false, "must_use": true, "safe_allowlist_reason": null, - "canonical_path": "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0183", - "public_path": "cuda_intrinsics::matrix::mma_sp_ordered_metadata_m16n8k64_s32_s8_satfinite", + "canonical_path": "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0180", + "public_path": "cuda_intrinsics::matrix::mma_sp_ordered_metadata_m16n8k64_s32_s8_u8", "compatibility_paths": [ - "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_s32_s8_satfinite" + "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_s32_s8_u8" ] }, "dialect": { @@ -216943,7 +219621,7 @@ ] }, "llvm": { - "symbol": "llvm.nvvm.mma.sp.ordered.metadata.m16n8k64.row.col.satfinite.s8", + "symbol": "llvm.nvvm.mma.sp.ordered.metadata.m16n8k64.row.col.s8.u8", "arguments": [ "i32", "i32", @@ -217037,11 +219715,11 @@ "sm_80", "ptx85" ], - "representation": "convergent ordered sparse m16n8k64 signed saturating INT8 inline PTX with selector 0", + "representation": "convergent ordered sparse m16n8k64 mixed-sign INT8 inline PTX with selector 0", "stage": "backend_codegen", "mechanism": "inline_ptx", "outcome": "succeeded", - "detail": "The 4,779-byte combined LLVM IR probe (SHA-256 01600853ff696df81a849a3d804086265d07d61c7a2f24ebaf7b3f056753fccb) covered all eight variants. Pinned LLVM emitted 13,390-byte PTX (SHA-256 b370bcbebbe761bd65675ad2d2602230cc315189a1bb8cb1c4533c68b564a897) with exactly eight ordered m16n8k64 instructions at PTX 8.5 and sm_80; this record retained exact saturating s8-by-s8 PTX with selector 0.", + "detail": "The 4,779-byte combined LLVM IR probe (SHA-256 01600853ff696df81a849a3d804086265d07d61c7a2f24ebaf7b3f056753fccb) covered all eight variants. Pinned LLVM emitted 13,390-byte PTX (SHA-256 b370bcbebbe761bd65675ad2d2602230cc315189a1bb8cb1c4533c68b564a897) with exactly eight ordered m16n8k64 instructions at PTX 8.5 and sm_80; this record retained exact wrapping s8-by-u8 PTX with selector 0.", "artifact_kind": null, "tool_path": null, "tool_version": null, @@ -217091,7 +219769,7 @@ "compute_80", "ptx93" ], - "representation": "convergent ordered sparse m16n8k64 signed saturating INT8 inline PTX in the combined coverage kernel", + "representation": "convergent ordered sparse m16n8k64 mixed-sign INT8 inline PTX in the combined coverage kernel", "stage": "backend_codegen", "mechanism": "inline_ptx", "outcome": "succeeded", @@ -217123,10 +219801,10 @@ "shape": "m16n8k64", "accumulator": "s32", "a_element": "s8", - "b_element": "s8", + "b_element": "u8", "a_layout": "row", "b_layout": "col", - "overflow": "satfinite", + "overflow": "wrapping", "metadata": "ordered", "selector": "immediate_zero", "participation": "all_warp_lanes_same_instruction_and_qualifiers_no_exited_lanes", @@ -217145,10 +219823,9 @@ "m16n8k64", "row", "col", - "satfinite", "s32", "s8", - "s8", + "u8", "s32" ], "operands": [ @@ -217176,20 +219853,20 @@ } ] }, - "summary": "Multiplies warp-distributed sparse signed A and signed B INT8 fragments with ordered sparsity metadata and adds a saturating s32 accumulator." + "summary": "Multiplies warp-distributed sparse signed A and unsigned B INT8 fragments with ordered sparsity metadata and adds a wrapping s32 accumulator." }, { - "id": "mma_sp_ordered_metadata_m16n8k64_s32_s8_u8", - "operation_key": "matrix.mma.sp.m16n8k64.row.col.s32.s8.u8.s32.wrapping.ordered_metadata", + "id": "mma_sp_ordered_metadata_m16n8k64_s32_s8_u8_satfinite", + "operation_key": "matrix.mma.sp.m16n8k64.row.col.s32.s8.u8.s32.satfinite.ordered_metadata", "family": "sparse_mma", "source": { "kind": "llvm_imported", - "source_record": "int_nvvm_mma_sp_ordered_metadata_m16n8k64_row_col_s8_u8" + "source_record": "int_nvvm_mma_sp_ordered_metadata_m16n8k64_row_col_satfinite_s8_u8" }, "selections": [ { - "source_record": "anonymous_19669", - "asm": "mma.sp::ordered_metadata.sync.aligned.m16n8k64.row.col.s32.s8.u8.s32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1, $rb2, $rb3}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}},\n\t\t$metadata,\n\t\t$selector;", + "source_record": "anonymous_19720", + "asm": "mma.sp::ordered_metadata.sync.aligned.m16n8k64.row.col.satfinite.s32.s8.u8.s32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1, $rb2, $rb3}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}},\n\t\t$metadata,\n\t\t$selector;", "predicates": [ "Subtarget->getSmVersion() >= 80", "Subtarget->getPTXVersion() >= 85" @@ -217197,9 +219874,9 @@ } ], "rust": { - "abi_id": "i0180", + "abi_id": "i0184", "module": "matrix", - "name": "mma_sp_ordered_metadata_m16n8k64_s32_s8_u8", + "name": "mma_sp_ordered_metadata_m16n8k64_s32_s8_u8_satfinite", "arguments": [ "[i32; 4]", "[u32; 4]", @@ -217211,10 +219888,10 @@ "safe": false, "must_use": true, "safe_allowlist_reason": null, - "canonical_path": "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0180", - "public_path": "cuda_intrinsics::matrix::mma_sp_ordered_metadata_m16n8k64_s32_s8_u8", + "canonical_path": "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0184", + "public_path": "cuda_intrinsics::matrix::mma_sp_ordered_metadata_m16n8k64_s32_s8_u8_satfinite", "compatibility_paths": [ - "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_s32_s8_u8" + "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_s32_s8_u8_satfinite" ] }, "dialect": { @@ -217244,7 +219921,7 @@ ] }, "llvm": { - "symbol": "llvm.nvvm.mma.sp.ordered.metadata.m16n8k64.row.col.s8.u8", + "symbol": "llvm.nvvm.mma.sp.ordered.metadata.m16n8k64.row.col.satfinite.s8.u8", "arguments": [ "i32", "i32", @@ -217338,11 +220015,11 @@ "sm_80", "ptx85" ], - "representation": "convergent ordered sparse m16n8k64 mixed-sign INT8 inline PTX with selector 0", + "representation": "convergent ordered sparse m16n8k64 mixed-sign saturating INT8 inline PTX with selector 0", "stage": "backend_codegen", "mechanism": "inline_ptx", "outcome": "succeeded", - "detail": "The 4,779-byte combined LLVM IR probe (SHA-256 01600853ff696df81a849a3d804086265d07d61c7a2f24ebaf7b3f056753fccb) covered all eight variants. Pinned LLVM emitted 13,390-byte PTX (SHA-256 b370bcbebbe761bd65675ad2d2602230cc315189a1bb8cb1c4533c68b564a897) with exactly eight ordered m16n8k64 instructions at PTX 8.5 and sm_80; this record retained exact wrapping s8-by-u8 PTX with selector 0.", + "detail": "The 4,779-byte combined LLVM IR probe (SHA-256 01600853ff696df81a849a3d804086265d07d61c7a2f24ebaf7b3f056753fccb) covered all eight variants. Pinned LLVM emitted 13,390-byte PTX (SHA-256 b370bcbebbe761bd65675ad2d2602230cc315189a1bb8cb1c4533c68b564a897) with exactly eight ordered m16n8k64 instructions at PTX 8.5 and sm_80; this record retained exact saturating s8-by-u8 PTX with selector 0.", "artifact_kind": null, "tool_path": null, "tool_version": null, @@ -217392,7 +220069,7 @@ "compute_80", "ptx93" ], - "representation": "convergent ordered sparse m16n8k64 mixed-sign INT8 inline PTX in the combined coverage kernel", + "representation": "convergent ordered sparse m16n8k64 mixed-sign saturating INT8 inline PTX in the combined coverage kernel", "stage": "backend_codegen", "mechanism": "inline_ptx", "outcome": "succeeded", @@ -217427,7 +220104,7 @@ "b_element": "u8", "a_layout": "row", "b_layout": "col", - "overflow": "wrapping", + "overflow": "satfinite", "metadata": "ordered", "selector": "immediate_zero", "participation": "all_warp_lanes_same_instruction_and_qualifiers_no_exited_lanes", @@ -217446,6 +220123,7 @@ "m16n8k64", "row", "col", + "satfinite", "s32", "s8", "u8", @@ -217476,20 +220154,20 @@ } ] }, - "summary": "Multiplies warp-distributed sparse signed A and unsigned B INT8 fragments with ordered sparsity metadata and adds a wrapping s32 accumulator." + "summary": "Multiplies warp-distributed sparse signed A and unsigned B INT8 fragments with ordered sparsity metadata and adds a saturating s32 accumulator." }, { - "id": "mma_sp_ordered_metadata_m16n8k64_s32_s8_u8_satfinite", - "operation_key": "matrix.mma.sp.m16n8k64.row.col.s32.s8.u8.s32.satfinite.ordered_metadata", + "id": "mma_sp_ordered_metadata_m16n8k64_s32_u4", + "operation_key": "matrix.mma.sp.m16n8k64.row.col.s32.u4.u4.s32.wrapping.ordered_metadata", "family": "sparse_mma", "source": { "kind": "llvm_imported", - "source_record": "int_nvvm_mma_sp_ordered_metadata_m16n8k64_row_col_satfinite_s8_u8" + "source_record": "int_nvvm_mma_sp_ordered_metadata_m16n8k64_row_col_u4" }, "selections": [ { - "source_record": "anonymous_19720", - "asm": "mma.sp::ordered_metadata.sync.aligned.m16n8k64.row.col.satfinite.s32.s8.u8.s32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1, $rb2, $rb3}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}},\n\t\t$metadata,\n\t\t$selector;", + "source_record": "anonymous_19614", + "asm": "mma.sp::ordered_metadata.sync.aligned.m16n8k64.row.col.s32.u4.u4.s32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1}},\n\t\t{{$rb0, $rb1}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}},\n\t\t$metadata,\n\t\t$selector;", "predicates": [ "Subtarget->getSmVersion() >= 80", "Subtarget->getPTXVersion() >= 85" @@ -217497,13 +220175,13 @@ } ], "rust": { - "abi_id": "i0184", + "abi_id": "i0197", "module": "matrix", - "name": "mma_sp_ordered_metadata_m16n8k64_s32_s8_u8_satfinite", + "name": "mma_sp_ordered_metadata_m16n8k64_s32_u4", "arguments": [ "[i32; 4]", - "[u32; 4]", - "[u32; 4]", + "[u32; 2]", + "[u32; 2]", "u32", "u32" ], @@ -217511,10 +220189,10 @@ "safe": false, "must_use": true, "safe_allowlist_reason": null, - "canonical_path": "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0184", - "public_path": "cuda_intrinsics::matrix::mma_sp_ordered_metadata_m16n8k64_s32_s8_u8_satfinite", + "canonical_path": "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0197", + "public_path": "cuda_intrinsics::matrix::mma_sp_ordered_metadata_m16n8k64_s32_u4", "compatibility_paths": [ - "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_s32_s8_u8_satfinite" + "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_s32_u4" ] }, "dialect": { @@ -217530,10 +220208,6 @@ "u32", "u32", "u32", - "u32", - "u32", - "u32", - "u32", "u32" ], "results": [ @@ -217544,7 +220218,7 @@ ] }, "llvm": { - "symbol": "llvm.nvvm.mma.sp.ordered.metadata.m16n8k64.row.col.satfinite.s8.u8", + "symbol": "llvm.nvvm.mma.sp.ordered.metadata.m16n8k64.row.col.u4", "arguments": [ "i32", "i32", @@ -217555,10 +220229,6 @@ "i32", "i32", "i32", - "i32", - "i32", - "i32", - "i32", "i32" ], "results": [ @@ -217568,10 +220238,10 @@ "i32" ], "properties": [ - "ImmArg", + "ImmArg", "IntrNoCallback", "IntrNoMem", - "Range" + "Range" ], "result_facts": { "no_undef": false, @@ -217638,11 +220308,11 @@ "sm_80", "ptx85" ], - "representation": "convergent ordered sparse m16n8k64 mixed-sign saturating INT8 inline PTX with selector 0", + "representation": "convergent ordered sparse m16n8k64 INT4 inline PTX with selectors 0 and 1", "stage": "backend_codegen", "mechanism": "inline_ptx", "outcome": "succeeded", - "detail": "The 4,779-byte combined LLVM IR probe (SHA-256 01600853ff696df81a849a3d804086265d07d61c7a2f24ebaf7b3f056753fccb) covered all eight variants. Pinned LLVM emitted 13,390-byte PTX (SHA-256 b370bcbebbe761bd65675ad2d2602230cc315189a1bb8cb1c4533c68b564a897) with exactly eight ordered m16n8k64 instructions at PTX 8.5 and sm_80; this record retained exact saturating s8-by-u8 PTX with selector 0.", + "detail": "The combined inline-PTX and typed LLVM probes described by the first record each emitted all eight variants with both selector values; this record retained wrapping u4-by-u4 PTX.", "artifact_kind": null, "tool_path": null, "tool_version": null, @@ -217653,12 +220323,12 @@ "sm_80", "ptx85" ], - "representation": "exact-floor ordered sparse m16n8k64 INT8 PTX", + "representation": "exact-floor ordered sparse m16n8k64 INT4 PTX", "stage": "ptx_assembly", "mechanism": "inline_ptx", "outcome": "succeeded", - "detail": "CUDA 13.3 ptxas accepted all eight exact instructions and produced a 1,464-byte cubin with SHA-256 6bcec1b1eab13da703fdade053704aa6ab00591a1b38dd7daf48ac0dec541df2. Because every probe function was unreferenced, ptxas removed their bodies; this proves assembly acceptance, not retained SASS.", - "artifact_kind": null, + "detail": "CUDA 13.3 ptxas accepted the 4,008-byte combined cubin and the selector and target negative boundaries described by the first record.", + "artifact_kind": "cubin", "tool_path": "/usr/local/cuda-13.3/bin/ptxas", "tool_version": "CUDA 13.3 V13.3.33 build cuda_13.3.r13.3/compiler.37862127_0", "tool_sha256": "7fdd01a4cf50e30746da98989c9272a907f491e6fd7fecfda14642e4375f88fb" @@ -217692,11 +220362,11 @@ "compute_80", "ptx93" ], - "representation": "convergent ordered sparse m16n8k64 mixed-sign saturating INT8 inline PTX in the combined coverage kernel", + "representation": "convergent ordered sparse m16n8k64 INT4 inline PTX in the generated coverage kernel", "stage": "backend_codegen", "mechanism": "inline_ptx", "outcome": "succeeded", - "detail": "The production generated_intrinsics route produced 242,464-byte compute_80 NVVM IR with SHA-256 fcc2fe1a6200de7b5ab8a38cab847432669fe4d6ce823c81b73f9b18fa25144c and 68,600-byte LTOIR with SHA-256 aa011070e20cb91d99f0d6d41ffd3883f01031b44d171380f638e3674b2facf3. All eight raw variants use compile-time selector 0.", + "detail": "The production artifacts described by the first record retained wrapping u4-by-u4 PTX with selector 0.", "artifact_kind": null, "tool_path": null, "tool_version": null, @@ -217707,11 +220377,11 @@ "sm_80", "ptx93" ], - "representation": "combined sparse INT8 coverage kernel with ordered m16n8k64 calls", + "representation": "generated sparse-MMA coverage kernel with ordered m16n8k64 INT4 calls", "stage": "device_link", "mechanism": "inline_ptx", "outcome": "succeeded", - "detail": "nvJitLink produced a 23,656-byte cubin with SHA-256 8a09455f87f3ef0c7c16adf13bf6030cbe7f0f18df7fcd91ec2a19a10de5b50d. Disassembly contained 30 IMMA.SP instructions in total and exactly 10 IMMA.SP.16864 instructions: all eight raw variants plus two compatibility-path calls.", + "detail": "The 26,600-byte production cubin described by the first record retained all eight raw variants and both compatibility-path calls.", "artifact_kind": "cubin", "tool_path": "/usr/local/cuda-13.3/lib64/libnvJitLink.so.13.3.33", "tool_version": "V13.3.33", @@ -217723,16 +220393,16 @@ "sparse_mma": { "shape": "m16n8k64", "accumulator": "s32", - "a_element": "s8", - "b_element": "u8", + "a_element": "u4", + "b_element": "u4", "a_layout": "row", "b_layout": "col", - "overflow": "satfinite", + "overflow": "wrapping", "metadata": "ordered", - "selector": "immediate_zero", + "selector": "immediate_zero_or_one", "participation": "all_warp_lanes_same_instruction_and_qualifiers_no_exited_lanes", - "adapter": "c4_i32_a4_u32_b4_u32_metadata_u32_selector_u32_to_d4_i32", - "llvm_adapter": "a4_i32_b4_i32_c4_i32_metadata_i32_selector_i32_to_d4_i32", + "adapter": "c4_i32_a2_u32_b2_u32_metadata_u32_selector_u32_to_d4_i32", + "llvm_adapter": "a2_i32_b2_i32_c4_i32_metadata_i32_selector_i32_to_d4_i32", "compatibility_source": "generated_stub", "runtime_validation": "unexecuted" }, @@ -217746,10 +220416,9 @@ "m16n8k64", "row", "col", - "satfinite", "s32", - "s8", - "u8", + "u4", + "u4", "s32" ], "operands": [ @@ -217759,11 +220428,11 @@ }, { "kind": "register_list", - "length": 4 + "length": 2 }, { "kind": "register_list", - "length": 4 + "length": 2 }, { "kind": "register_list", @@ -217777,20 +220446,20 @@ } ] }, - "summary": "Multiplies warp-distributed sparse signed A and unsigned B INT8 fragments with ordered sparsity metadata and adds a saturating s32 accumulator." + "summary": "Multiplies warp-distributed sparse unsigned A and unsigned B INT4 fragments with ordered sparsity metadata and adds a wrapping s32 accumulator." }, { - "id": "mma_sp_ordered_metadata_m16n8k64_s32_u4", - "operation_key": "matrix.mma.sp.m16n8k64.row.col.s32.u4.u4.s32.wrapping.ordered_metadata", + "id": "mma_sp_ordered_metadata_m16n8k64_s32_u4_s4", + "operation_key": "matrix.mma.sp.m16n8k64.row.col.s32.u4.s4.s32.wrapping.ordered_metadata", "family": "sparse_mma", "source": { "kind": "llvm_imported", - "source_record": "int_nvvm_mma_sp_ordered_metadata_m16n8k64_row_col_u4" + "source_record": "int_nvvm_mma_sp_ordered_metadata_m16n8k64_row_col_u4_s4" }, "selections": [ { - "source_record": "anonymous_19614", - "asm": "mma.sp::ordered_metadata.sync.aligned.m16n8k64.row.col.s32.u4.u4.s32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1}},\n\t\t{{$rb0, $rb1}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}},\n\t\t$metadata,\n\t\t$selector;", + "source_record": "anonymous_19610", + "asm": "mma.sp::ordered_metadata.sync.aligned.m16n8k64.row.col.s32.u4.s4.s32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1}},\n\t\t{{$rb0, $rb1}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}},\n\t\t$metadata,\n\t\t$selector;", "predicates": [ "Subtarget->getSmVersion() >= 80", "Subtarget->getPTXVersion() >= 85" @@ -217798,9 +220467,9 @@ } ], "rust": { - "abi_id": "i0197", + "abi_id": "i0198", "module": "matrix", - "name": "mma_sp_ordered_metadata_m16n8k64_s32_u4", + "name": "mma_sp_ordered_metadata_m16n8k64_s32_u4_s4", "arguments": [ "[i32; 4]", "[u32; 2]", @@ -217812,10 +220481,10 @@ "safe": false, "must_use": true, "safe_allowlist_reason": null, - "canonical_path": "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0197", - "public_path": "cuda_intrinsics::matrix::mma_sp_ordered_metadata_m16n8k64_s32_u4", + "canonical_path": "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0198", + "public_path": "cuda_intrinsics::matrix::mma_sp_ordered_metadata_m16n8k64_s32_u4_s4", "compatibility_paths": [ - "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_s32_u4" + "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_s32_u4_s4" ] }, "dialect": { @@ -217841,7 +220510,7 @@ ] }, "llvm": { - "symbol": "llvm.nvvm.mma.sp.ordered.metadata.m16n8k64.row.col.u4", + "symbol": "llvm.nvvm.mma.sp.ordered.metadata.m16n8k64.row.col.u4.s4", "arguments": [ "i32", "i32", @@ -217935,7 +220604,7 @@ "stage": "backend_codegen", "mechanism": "inline_ptx", "outcome": "succeeded", - "detail": "The combined inline-PTX and typed LLVM probes described by the first record each emitted all eight variants with both selector values; this record retained wrapping u4-by-u4 PTX.", + "detail": "The combined inline-PTX and typed LLVM probes described by the first record each emitted all eight variants with both selector values; this record retained wrapping u4-by-s4 PTX.", "artifact_kind": null, "tool_path": null, "tool_version": null, @@ -217989,7 +220658,7 @@ "stage": "backend_codegen", "mechanism": "inline_ptx", "outcome": "succeeded", - "detail": "The production artifacts described by the first record retained wrapping u4-by-u4 PTX with selector 0.", + "detail": "The production artifacts described by the first record retained wrapping u4-by-s4 PTX with selector 1.", "artifact_kind": null, "tool_path": null, "tool_version": null, @@ -218017,7 +220686,7 @@ "shape": "m16n8k64", "accumulator": "s32", "a_element": "u4", - "b_element": "u4", + "b_element": "s4", "a_layout": "row", "b_layout": "col", "overflow": "wrapping", @@ -218041,7 +220710,7 @@ "col", "s32", "u4", - "u4", + "s4", "s32" ], "operands": [ @@ -218069,20 +220738,20 @@ } ] }, - "summary": "Multiplies warp-distributed sparse unsigned A and unsigned B INT4 fragments with ordered sparsity metadata and adds a wrapping s32 accumulator." + "summary": "Multiplies warp-distributed sparse unsigned A and signed B INT4 fragments with ordered sparsity metadata and adds a wrapping s32 accumulator." }, { - "id": "mma_sp_ordered_metadata_m16n8k64_s32_u4_s4", - "operation_key": "matrix.mma.sp.m16n8k64.row.col.s32.u4.s4.s32.wrapping.ordered_metadata", + "id": "mma_sp_ordered_metadata_m16n8k64_s32_u4_s4_satfinite", + "operation_key": "matrix.mma.sp.m16n8k64.row.col.s32.u4.s4.s32.satfinite.ordered_metadata", "family": "sparse_mma", "source": { "kind": "llvm_imported", - "source_record": "int_nvvm_mma_sp_ordered_metadata_m16n8k64_row_col_u4_s4" + "source_record": "int_nvvm_mma_sp_ordered_metadata_m16n8k64_row_col_satfinite_u4_s4" }, "selections": [ { - "source_record": "anonymous_19610", - "asm": "mma.sp::ordered_metadata.sync.aligned.m16n8k64.row.col.s32.u4.s4.s32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1}},\n\t\t{{$rb0, $rb1}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}},\n\t\t$metadata,\n\t\t$selector;", + "source_record": "anonymous_19687", + "asm": "mma.sp::ordered_metadata.sync.aligned.m16n8k64.row.col.satfinite.s32.u4.s4.s32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1}},\n\t\t{{$rb0, $rb1}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}},\n\t\t$metadata,\n\t\t$selector;", "predicates": [ "Subtarget->getSmVersion() >= 80", "Subtarget->getPTXVersion() >= 85" @@ -218090,9 +220759,9 @@ } ], "rust": { - "abi_id": "i0198", + "abi_id": "i0202", "module": "matrix", - "name": "mma_sp_ordered_metadata_m16n8k64_s32_u4_s4", + "name": "mma_sp_ordered_metadata_m16n8k64_s32_u4_s4_satfinite", "arguments": [ "[i32; 4]", "[u32; 2]", @@ -218104,10 +220773,10 @@ "safe": false, "must_use": true, "safe_allowlist_reason": null, - "canonical_path": "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0198", - "public_path": "cuda_intrinsics::matrix::mma_sp_ordered_metadata_m16n8k64_s32_u4_s4", + "canonical_path": "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0202", + "public_path": "cuda_intrinsics::matrix::mma_sp_ordered_metadata_m16n8k64_s32_u4_s4_satfinite", "compatibility_paths": [ - "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_s32_u4_s4" + "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_s32_u4_s4_satfinite" ] }, "dialect": { @@ -218133,7 +220802,7 @@ ] }, "llvm": { - "symbol": "llvm.nvvm.mma.sp.ordered.metadata.m16n8k64.row.col.u4.s4", + "symbol": "llvm.nvvm.mma.sp.ordered.metadata.m16n8k64.row.col.satfinite.u4.s4", "arguments": [ "i32", "i32", @@ -218227,7 +220896,7 @@ "stage": "backend_codegen", "mechanism": "inline_ptx", "outcome": "succeeded", - "detail": "The combined inline-PTX and typed LLVM probes described by the first record each emitted all eight variants with both selector values; this record retained wrapping u4-by-s4 PTX.", + "detail": "The combined inline-PTX and typed LLVM probes described by the first record each emitted all eight variants with both selector values; this record retained saturating u4-by-s4 PTX.", "artifact_kind": null, "tool_path": null, "tool_version": null, @@ -218281,7 +220950,7 @@ "stage": "backend_codegen", "mechanism": "inline_ptx", "outcome": "succeeded", - "detail": "The production artifacts described by the first record retained wrapping u4-by-s4 PTX with selector 1.", + "detail": "The production artifacts described by the first record retained saturating u4-by-s4 PTX with selector 1.", "artifact_kind": null, "tool_path": null, "tool_version": null, @@ -218312,7 +220981,7 @@ "b_element": "s4", "a_layout": "row", "b_layout": "col", - "overflow": "wrapping", + "overflow": "satfinite", "metadata": "ordered", "selector": "immediate_zero_or_one", "participation": "all_warp_lanes_same_instruction_and_qualifiers_no_exited_lanes", @@ -218331,6 +221000,7 @@ "m16n8k64", "row", "col", + "satfinite", "s32", "u4", "s4", @@ -218361,20 +221031,20 @@ } ] }, - "summary": "Multiplies warp-distributed sparse unsigned A and signed B INT4 fragments with ordered sparsity metadata and adds a wrapping s32 accumulator." + "summary": "Multiplies warp-distributed sparse unsigned A and signed B INT4 fragments with ordered sparsity metadata and adds a saturating s32 accumulator." }, { - "id": "mma_sp_ordered_metadata_m16n8k64_s32_u4_s4_satfinite", - "operation_key": "matrix.mma.sp.m16n8k64.row.col.s32.u4.s4.s32.satfinite.ordered_metadata", + "id": "mma_sp_ordered_metadata_m16n8k64_s32_u4_satfinite", + "operation_key": "matrix.mma.sp.m16n8k64.row.col.s32.u4.u4.s32.satfinite.ordered_metadata", "family": "sparse_mma", "source": { "kind": "llvm_imported", - "source_record": "int_nvvm_mma_sp_ordered_metadata_m16n8k64_row_col_satfinite_u4_s4" + "source_record": "int_nvvm_mma_sp_ordered_metadata_m16n8k64_row_col_satfinite_u4" }, "selections": [ { - "source_record": "anonymous_19687", - "asm": "mma.sp::ordered_metadata.sync.aligned.m16n8k64.row.col.satfinite.s32.u4.s4.s32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1}},\n\t\t{{$rb0, $rb1}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}},\n\t\t$metadata,\n\t\t$selector;", + "source_record": "anonymous_19690", + "asm": "mma.sp::ordered_metadata.sync.aligned.m16n8k64.row.col.satfinite.s32.u4.u4.s32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1}},\n\t\t{{$rb0, $rb1}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}},\n\t\t$metadata,\n\t\t$selector;", "predicates": [ "Subtarget->getSmVersion() >= 80", "Subtarget->getPTXVersion() >= 85" @@ -218382,9 +221052,9 @@ } ], "rust": { - "abi_id": "i0202", + "abi_id": "i0201", "module": "matrix", - "name": "mma_sp_ordered_metadata_m16n8k64_s32_u4_s4_satfinite", + "name": "mma_sp_ordered_metadata_m16n8k64_s32_u4_satfinite", "arguments": [ "[i32; 4]", "[u32; 2]", @@ -218396,10 +221066,10 @@ "safe": false, "must_use": true, "safe_allowlist_reason": null, - "canonical_path": "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0202", - "public_path": "cuda_intrinsics::matrix::mma_sp_ordered_metadata_m16n8k64_s32_u4_s4_satfinite", + "canonical_path": "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0201", + "public_path": "cuda_intrinsics::matrix::mma_sp_ordered_metadata_m16n8k64_s32_u4_satfinite", "compatibility_paths": [ - "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_s32_u4_s4_satfinite" + "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_s32_u4_satfinite" ] }, "dialect": { @@ -218425,7 +221095,7 @@ ] }, "llvm": { - "symbol": "llvm.nvvm.mma.sp.ordered.metadata.m16n8k64.row.col.satfinite.u4.s4", + "symbol": "llvm.nvvm.mma.sp.ordered.metadata.m16n8k64.row.col.satfinite.u4", "arguments": [ "i32", "i32", @@ -218519,7 +221189,7 @@ "stage": "backend_codegen", "mechanism": "inline_ptx", "outcome": "succeeded", - "detail": "The combined inline-PTX and typed LLVM probes described by the first record each emitted all eight variants with both selector values; this record retained saturating u4-by-s4 PTX.", + "detail": "The combined inline-PTX and typed LLVM probes described by the first record each emitted all eight variants with both selector values; this record retained saturating u4-by-u4 PTX.", "artifact_kind": null, "tool_path": null, "tool_version": null, @@ -218573,7 +221243,7 @@ "stage": "backend_codegen", "mechanism": "inline_ptx", "outcome": "succeeded", - "detail": "The production artifacts described by the first record retained saturating u4-by-s4 PTX with selector 1.", + "detail": "The production artifacts described by the first record retained saturating u4-by-u4 PTX with selector 0.", "artifact_kind": null, "tool_path": null, "tool_version": null, @@ -218601,7 +221271,7 @@ "shape": "m16n8k64", "accumulator": "s32", "a_element": "u4", - "b_element": "s4", + "b_element": "u4", "a_layout": "row", "b_layout": "col", "overflow": "satfinite", @@ -218626,7 +221296,7 @@ "satfinite", "s32", "u4", - "s4", + "u4", "s32" ], "operands": [ @@ -218654,20 +221324,20 @@ } ] }, - "summary": "Multiplies warp-distributed sparse unsigned A and signed B INT4 fragments with ordered sparsity metadata and adds a saturating s32 accumulator." + "summary": "Multiplies warp-distributed sparse unsigned A and unsigned B INT4 fragments with ordered sparsity metadata and adds a saturating s32 accumulator." }, { - "id": "mma_sp_ordered_metadata_m16n8k64_s32_u4_satfinite", - "operation_key": "matrix.mma.sp.m16n8k64.row.col.s32.u4.u4.s32.satfinite.ordered_metadata", + "id": "mma_sp_ordered_metadata_m16n8k64_s32_u8", + "operation_key": "matrix.mma.sp.m16n8k64.row.col.s32.u8.u8.s32.wrapping.ordered_metadata", "family": "sparse_mma", "source": { "kind": "llvm_imported", - "source_record": "int_nvvm_mma_sp_ordered_metadata_m16n8k64_row_col_satfinite_u4" + "source_record": "int_nvvm_mma_sp_ordered_metadata_m16n8k64_row_col_u8" }, "selections": [ { - "source_record": "anonymous_19690", - "asm": "mma.sp::ordered_metadata.sync.aligned.m16n8k64.row.col.satfinite.s32.u4.u4.s32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1}},\n\t\t{{$rb0, $rb1}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}},\n\t\t$metadata,\n\t\t$selector;", + "source_record": "anonymous_19678", + "asm": "mma.sp::ordered_metadata.sync.aligned.m16n8k64.row.col.s32.u8.u8.s32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1, $rb2, $rb3}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}},\n\t\t$metadata,\n\t\t$selector;", "predicates": [ "Subtarget->getSmVersion() >= 80", "Subtarget->getPTXVersion() >= 85" @@ -218675,13 +221345,13 @@ } ], "rust": { - "abi_id": "i0201", + "abi_id": "i0181", "module": "matrix", - "name": "mma_sp_ordered_metadata_m16n8k64_s32_u4_satfinite", + "name": "mma_sp_ordered_metadata_m16n8k64_s32_u8", "arguments": [ "[i32; 4]", - "[u32; 2]", - "[u32; 2]", + "[u32; 4]", + "[u32; 4]", "u32", "u32" ], @@ -218689,10 +221359,10 @@ "safe": false, "must_use": true, "safe_allowlist_reason": null, - "canonical_path": "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0201", - "public_path": "cuda_intrinsics::matrix::mma_sp_ordered_metadata_m16n8k64_s32_u4_satfinite", + "canonical_path": "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0181", + "public_path": "cuda_intrinsics::matrix::mma_sp_ordered_metadata_m16n8k64_s32_u8", "compatibility_paths": [ - "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_s32_u4_satfinite" + "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_s32_u8" ] }, "dialect": { @@ -218708,6 +221378,10 @@ "u32", "u32", "u32", + "u32", + "u32", + "u32", + "u32", "u32" ], "results": [ @@ -218718,7 +221392,7 @@ ] }, "llvm": { - "symbol": "llvm.nvvm.mma.sp.ordered.metadata.m16n8k64.row.col.satfinite.u4", + "symbol": "llvm.nvvm.mma.sp.ordered.metadata.m16n8k64.row.col.u8", "arguments": [ "i32", "i32", @@ -218729,6 +221403,10 @@ "i32", "i32", "i32", + "i32", + "i32", + "i32", + "i32", "i32" ], "results": [ @@ -218738,10 +221416,10 @@ "i32" ], "properties": [ - "ImmArg", + "ImmArg", "IntrNoCallback", "IntrNoMem", - "Range" + "Range" ], "result_facts": { "no_undef": false, @@ -218808,11 +221486,11 @@ "sm_80", "ptx85" ], - "representation": "convergent ordered sparse m16n8k64 INT4 inline PTX with selectors 0 and 1", + "representation": "convergent ordered sparse m16n8k64 unsigned INT8 inline PTX with selector 0", "stage": "backend_codegen", "mechanism": "inline_ptx", "outcome": "succeeded", - "detail": "The combined inline-PTX and typed LLVM probes described by the first record each emitted all eight variants with both selector values; this record retained saturating u4-by-u4 PTX.", + "detail": "The 4,779-byte combined LLVM IR probe (SHA-256 01600853ff696df81a849a3d804086265d07d61c7a2f24ebaf7b3f056753fccb) covered all eight variants. Pinned LLVM emitted 13,390-byte PTX (SHA-256 b370bcbebbe761bd65675ad2d2602230cc315189a1bb8cb1c4533c68b564a897) with exactly eight ordered m16n8k64 instructions at PTX 8.5 and sm_80; this record retained exact wrapping u8-by-u8 PTX with selector 0.", "artifact_kind": null, "tool_path": null, "tool_version": null, @@ -218823,12 +221501,12 @@ "sm_80", "ptx85" ], - "representation": "exact-floor ordered sparse m16n8k64 INT4 PTX", + "representation": "exact-floor ordered sparse m16n8k64 INT8 PTX", "stage": "ptx_assembly", "mechanism": "inline_ptx", "outcome": "succeeded", - "detail": "CUDA 13.3 ptxas accepted the 4,008-byte combined cubin and the selector and target negative boundaries described by the first record.", - "artifact_kind": "cubin", + "detail": "CUDA 13.3 ptxas accepted all eight exact instructions and produced a 1,464-byte cubin with SHA-256 6bcec1b1eab13da703fdade053704aa6ab00591a1b38dd7daf48ac0dec541df2. Because every probe function was unreferenced, ptxas removed their bodies; this proves assembly acceptance, not retained SASS.", + "artifact_kind": null, "tool_path": "/usr/local/cuda-13.3/bin/ptxas", "tool_version": "CUDA 13.3 V13.3.33 build cuda_13.3.r13.3/compiler.37862127_0", "tool_sha256": "7fdd01a4cf50e30746da98989c9272a907f491e6fd7fecfda14642e4375f88fb" @@ -218862,11 +221540,11 @@ "compute_80", "ptx93" ], - "representation": "convergent ordered sparse m16n8k64 INT4 inline PTX in the generated coverage kernel", + "representation": "convergent ordered sparse m16n8k64 unsigned INT8 inline PTX in the combined coverage kernel", "stage": "backend_codegen", "mechanism": "inline_ptx", "outcome": "succeeded", - "detail": "The production artifacts described by the first record retained saturating u4-by-u4 PTX with selector 0.", + "detail": "The production generated_intrinsics route produced 242,464-byte compute_80 NVVM IR with SHA-256 fcc2fe1a6200de7b5ab8a38cab847432669fe4d6ce823c81b73f9b18fa25144c and 68,600-byte LTOIR with SHA-256 aa011070e20cb91d99f0d6d41ffd3883f01031b44d171380f638e3674b2facf3. All eight raw variants use compile-time selector 0.", "artifact_kind": null, "tool_path": null, "tool_version": null, @@ -218877,11 +221555,11 @@ "sm_80", "ptx93" ], - "representation": "generated sparse-MMA coverage kernel with ordered m16n8k64 INT4 calls", + "representation": "combined sparse INT8 coverage kernel with ordered m16n8k64 calls", "stage": "device_link", "mechanism": "inline_ptx", "outcome": "succeeded", - "detail": "The 26,600-byte production cubin described by the first record retained all eight raw variants and both compatibility-path calls.", + "detail": "nvJitLink produced a 23,656-byte cubin with SHA-256 8a09455f87f3ef0c7c16adf13bf6030cbe7f0f18df7fcd91ec2a19a10de5b50d. Disassembly contained 30 IMMA.SP instructions in total and exactly 10 IMMA.SP.16864 instructions: all eight raw variants plus two compatibility-path calls.", "artifact_kind": "cubin", "tool_path": "/usr/local/cuda-13.3/lib64/libnvJitLink.so.13.3.33", "tool_version": "V13.3.33", @@ -218893,16 +221571,16 @@ "sparse_mma": { "shape": "m16n8k64", "accumulator": "s32", - "a_element": "u4", - "b_element": "u4", + "a_element": "u8", + "b_element": "u8", "a_layout": "row", "b_layout": "col", - "overflow": "satfinite", + "overflow": "wrapping", "metadata": "ordered", - "selector": "immediate_zero_or_one", + "selector": "immediate_zero", "participation": "all_warp_lanes_same_instruction_and_qualifiers_no_exited_lanes", - "adapter": "c4_i32_a2_u32_b2_u32_metadata_u32_selector_u32_to_d4_i32", - "llvm_adapter": "a2_i32_b2_i32_c4_i32_metadata_i32_selector_i32_to_d4_i32", + "adapter": "c4_i32_a4_u32_b4_u32_metadata_u32_selector_u32_to_d4_i32", + "llvm_adapter": "a4_i32_b4_i32_c4_i32_metadata_i32_selector_i32_to_d4_i32", "compatibility_source": "generated_stub", "runtime_validation": "unexecuted" }, @@ -218916,10 +221594,9 @@ "m16n8k64", "row", "col", - "satfinite", "s32", - "u4", - "u4", + "u8", + "u8", "s32" ], "operands": [ @@ -218929,11 +221606,11 @@ }, { "kind": "register_list", - "length": 2 + "length": 4 }, { "kind": "register_list", - "length": 2 + "length": 4 }, { "kind": "register_list", @@ -218947,20 +221624,20 @@ } ] }, - "summary": "Multiplies warp-distributed sparse unsigned A and unsigned B INT4 fragments with ordered sparsity metadata and adds a saturating s32 accumulator." + "summary": "Multiplies warp-distributed sparse unsigned A and unsigned B INT8 fragments with ordered sparsity metadata and adds a wrapping s32 accumulator." }, { - "id": "mma_sp_ordered_metadata_m16n8k64_s32_u8", - "operation_key": "matrix.mma.sp.m16n8k64.row.col.s32.u8.u8.s32.wrapping.ordered_metadata", + "id": "mma_sp_ordered_metadata_m16n8k64_s32_u8_s8", + "operation_key": "matrix.mma.sp.m16n8k64.row.col.s32.u8.s8.s32.wrapping.ordered_metadata", "family": "sparse_mma", "source": { "kind": "llvm_imported", - "source_record": "int_nvvm_mma_sp_ordered_metadata_m16n8k64_row_col_u8" + "source_record": "int_nvvm_mma_sp_ordered_metadata_m16n8k64_row_col_u8_s8" }, "selections": [ { - "source_record": "anonymous_19678", - "asm": "mma.sp::ordered_metadata.sync.aligned.m16n8k64.row.col.s32.u8.u8.s32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1, $rb2, $rb3}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}},\n\t\t$metadata,\n\t\t$selector;", + "source_record": "anonymous_19674", + "asm": "mma.sp::ordered_metadata.sync.aligned.m16n8k64.row.col.s32.u8.s8.s32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1, $rb2, $rb3}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}},\n\t\t$metadata,\n\t\t$selector;", "predicates": [ "Subtarget->getSmVersion() >= 80", "Subtarget->getPTXVersion() >= 85" @@ -218968,9 +221645,9 @@ } ], "rust": { - "abi_id": "i0181", + "abi_id": "i0182", "module": "matrix", - "name": "mma_sp_ordered_metadata_m16n8k64_s32_u8", + "name": "mma_sp_ordered_metadata_m16n8k64_s32_u8_s8", "arguments": [ "[i32; 4]", "[u32; 4]", @@ -218982,10 +221659,10 @@ "safe": false, "must_use": true, "safe_allowlist_reason": null, - "canonical_path": "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0181", - "public_path": "cuda_intrinsics::matrix::mma_sp_ordered_metadata_m16n8k64_s32_u8", + "canonical_path": "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0182", + "public_path": "cuda_intrinsics::matrix::mma_sp_ordered_metadata_m16n8k64_s32_u8_s8", "compatibility_paths": [ - "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_s32_u8" + "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_s32_u8_s8" ] }, "dialect": { @@ -219015,7 +221692,7 @@ ] }, "llvm": { - "symbol": "llvm.nvvm.mma.sp.ordered.metadata.m16n8k64.row.col.u8", + "symbol": "llvm.nvvm.mma.sp.ordered.metadata.m16n8k64.row.col.u8.s8", "arguments": [ "i32", "i32", @@ -219109,11 +221786,11 @@ "sm_80", "ptx85" ], - "representation": "convergent ordered sparse m16n8k64 unsigned INT8 inline PTX with selector 0", + "representation": "convergent ordered sparse m16n8k64 mixed-sign INT8 inline PTX with selector 0", "stage": "backend_codegen", "mechanism": "inline_ptx", "outcome": "succeeded", - "detail": "The 4,779-byte combined LLVM IR probe (SHA-256 01600853ff696df81a849a3d804086265d07d61c7a2f24ebaf7b3f056753fccb) covered all eight variants. Pinned LLVM emitted 13,390-byte PTX (SHA-256 b370bcbebbe761bd65675ad2d2602230cc315189a1bb8cb1c4533c68b564a897) with exactly eight ordered m16n8k64 instructions at PTX 8.5 and sm_80; this record retained exact wrapping u8-by-u8 PTX with selector 0.", + "detail": "The 4,779-byte combined LLVM IR probe (SHA-256 01600853ff696df81a849a3d804086265d07d61c7a2f24ebaf7b3f056753fccb) covered all eight variants. Pinned LLVM emitted 13,390-byte PTX (SHA-256 b370bcbebbe761bd65675ad2d2602230cc315189a1bb8cb1c4533c68b564a897) with exactly eight ordered m16n8k64 instructions at PTX 8.5 and sm_80; this record retained exact wrapping u8-by-s8 PTX with selector 0.", "artifact_kind": null, "tool_path": null, "tool_version": null, @@ -219163,7 +221840,7 @@ "compute_80", "ptx93" ], - "representation": "convergent ordered sparse m16n8k64 unsigned INT8 inline PTX in the combined coverage kernel", + "representation": "convergent ordered sparse m16n8k64 mixed-sign INT8 inline PTX in the combined coverage kernel", "stage": "backend_codegen", "mechanism": "inline_ptx", "outcome": "succeeded", @@ -219195,7 +221872,7 @@ "shape": "m16n8k64", "accumulator": "s32", "a_element": "u8", - "b_element": "u8", + "b_element": "s8", "a_layout": "row", "b_layout": "col", "overflow": "wrapping", @@ -219219,7 +221896,7 @@ "col", "s32", "u8", - "u8", + "s8", "s32" ], "operands": [ @@ -219247,20 +221924,20 @@ } ] }, - "summary": "Multiplies warp-distributed sparse unsigned A and unsigned B INT8 fragments with ordered sparsity metadata and adds a wrapping s32 accumulator." + "summary": "Multiplies warp-distributed sparse unsigned A and signed B INT8 fragments with ordered sparsity metadata and adds a wrapping s32 accumulator." }, { - "id": "mma_sp_ordered_metadata_m16n8k64_s32_u8_s8", - "operation_key": "matrix.mma.sp.m16n8k64.row.col.s32.u8.s8.s32.wrapping.ordered_metadata", + "id": "mma_sp_ordered_metadata_m16n8k64_s32_u8_s8_satfinite", + "operation_key": "matrix.mma.sp.m16n8k64.row.col.s32.u8.s8.s32.satfinite.ordered_metadata", "family": "sparse_mma", "source": { "kind": "llvm_imported", - "source_record": "int_nvvm_mma_sp_ordered_metadata_m16n8k64_row_col_u8_s8" + "source_record": "int_nvvm_mma_sp_ordered_metadata_m16n8k64_row_col_satfinite_u8_s8" }, "selections": [ { - "source_record": "anonymous_19674", - "asm": "mma.sp::ordered_metadata.sync.aligned.m16n8k64.row.col.s32.u8.s8.s32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1, $rb2, $rb3}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}},\n\t\t$metadata,\n\t\t$selector;", + "source_record": "anonymous_19723", + "asm": "mma.sp::ordered_metadata.sync.aligned.m16n8k64.row.col.satfinite.s32.u8.s8.s32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1, $rb2, $rb3}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}},\n\t\t$metadata,\n\t\t$selector;", "predicates": [ "Subtarget->getSmVersion() >= 80", "Subtarget->getPTXVersion() >= 85" @@ -219268,9 +221945,9 @@ } ], "rust": { - "abi_id": "i0182", + "abi_id": "i0186", "module": "matrix", - "name": "mma_sp_ordered_metadata_m16n8k64_s32_u8_s8", + "name": "mma_sp_ordered_metadata_m16n8k64_s32_u8_s8_satfinite", "arguments": [ "[i32; 4]", "[u32; 4]", @@ -219282,10 +221959,10 @@ "safe": false, "must_use": true, "safe_allowlist_reason": null, - "canonical_path": "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0182", - "public_path": "cuda_intrinsics::matrix::mma_sp_ordered_metadata_m16n8k64_s32_u8_s8", + "canonical_path": "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0186", + "public_path": "cuda_intrinsics::matrix::mma_sp_ordered_metadata_m16n8k64_s32_u8_s8_satfinite", "compatibility_paths": [ - "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_s32_u8_s8" + "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_s32_u8_s8_satfinite" ] }, "dialect": { @@ -219315,7 +221992,7 @@ ] }, "llvm": { - "symbol": "llvm.nvvm.mma.sp.ordered.metadata.m16n8k64.row.col.u8.s8", + "symbol": "llvm.nvvm.mma.sp.ordered.metadata.m16n8k64.row.col.satfinite.u8.s8", "arguments": [ "i32", "i32", @@ -219409,11 +222086,11 @@ "sm_80", "ptx85" ], - "representation": "convergent ordered sparse m16n8k64 mixed-sign INT8 inline PTX with selector 0", + "representation": "convergent ordered sparse m16n8k64 mixed-sign saturating INT8 inline PTX with selector 0", "stage": "backend_codegen", "mechanism": "inline_ptx", "outcome": "succeeded", - "detail": "The 4,779-byte combined LLVM IR probe (SHA-256 01600853ff696df81a849a3d804086265d07d61c7a2f24ebaf7b3f056753fccb) covered all eight variants. Pinned LLVM emitted 13,390-byte PTX (SHA-256 b370bcbebbe761bd65675ad2d2602230cc315189a1bb8cb1c4533c68b564a897) with exactly eight ordered m16n8k64 instructions at PTX 8.5 and sm_80; this record retained exact wrapping u8-by-s8 PTX with selector 0.", + "detail": "The 4,779-byte combined LLVM IR probe (SHA-256 01600853ff696df81a849a3d804086265d07d61c7a2f24ebaf7b3f056753fccb) covered all eight variants. Pinned LLVM emitted 13,390-byte PTX (SHA-256 b370bcbebbe761bd65675ad2d2602230cc315189a1bb8cb1c4533c68b564a897) with exactly eight ordered m16n8k64 instructions at PTX 8.5 and sm_80; this record retained exact saturating u8-by-s8 PTX with selector 0.", "artifact_kind": null, "tool_path": null, "tool_version": null, @@ -219463,7 +222140,7 @@ "compute_80", "ptx93" ], - "representation": "convergent ordered sparse m16n8k64 mixed-sign INT8 inline PTX in the combined coverage kernel", + "representation": "convergent ordered sparse m16n8k64 mixed-sign saturating INT8 inline PTX in the combined coverage kernel", "stage": "backend_codegen", "mechanism": "inline_ptx", "outcome": "succeeded", @@ -219498,7 +222175,7 @@ "b_element": "s8", "a_layout": "row", "b_layout": "col", - "overflow": "wrapping", + "overflow": "satfinite", "metadata": "ordered", "selector": "immediate_zero", "participation": "all_warp_lanes_same_instruction_and_qualifiers_no_exited_lanes", @@ -219517,6 +222194,7 @@ "m16n8k64", "row", "col", + "satfinite", "s32", "u8", "s8", @@ -219547,20 +222225,20 @@ } ] }, - "summary": "Multiplies warp-distributed sparse unsigned A and signed B INT8 fragments with ordered sparsity metadata and adds a wrapping s32 accumulator." + "summary": "Multiplies warp-distributed sparse unsigned A and signed B INT8 fragments with ordered sparsity metadata and adds a saturating s32 accumulator." }, { - "id": "mma_sp_ordered_metadata_m16n8k64_s32_u8_s8_satfinite", - "operation_key": "matrix.mma.sp.m16n8k64.row.col.s32.u8.s8.s32.satfinite.ordered_metadata", + "id": "mma_sp_ordered_metadata_m16n8k64_s32_u8_satfinite", + "operation_key": "matrix.mma.sp.m16n8k64.row.col.s32.u8.u8.s32.satfinite.ordered_metadata", "family": "sparse_mma", "source": { "kind": "llvm_imported", - "source_record": "int_nvvm_mma_sp_ordered_metadata_m16n8k64_row_col_satfinite_u8_s8" + "source_record": "int_nvvm_mma_sp_ordered_metadata_m16n8k64_row_col_satfinite_u8" }, "selections": [ { - "source_record": "anonymous_19723", - "asm": "mma.sp::ordered_metadata.sync.aligned.m16n8k64.row.col.satfinite.s32.u8.s8.s32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1, $rb2, $rb3}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}},\n\t\t$metadata,\n\t\t$selector;", + "source_record": "anonymous_19726", + "asm": "mma.sp::ordered_metadata.sync.aligned.m16n8k64.row.col.satfinite.s32.u8.u8.s32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1, $rb2, $rb3}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}},\n\t\t$metadata,\n\t\t$selector;", "predicates": [ "Subtarget->getSmVersion() >= 80", "Subtarget->getPTXVersion() >= 85" @@ -219568,9 +222246,9 @@ } ], "rust": { - "abi_id": "i0186", + "abi_id": "i0185", "module": "matrix", - "name": "mma_sp_ordered_metadata_m16n8k64_s32_u8_s8_satfinite", + "name": "mma_sp_ordered_metadata_m16n8k64_s32_u8_satfinite", "arguments": [ "[i32; 4]", "[u32; 4]", @@ -219582,10 +222260,10 @@ "safe": false, "must_use": true, "safe_allowlist_reason": null, - "canonical_path": "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0186", - "public_path": "cuda_intrinsics::matrix::mma_sp_ordered_metadata_m16n8k64_s32_u8_s8_satfinite", + "canonical_path": "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0185", + "public_path": "cuda_intrinsics::matrix::mma_sp_ordered_metadata_m16n8k64_s32_u8_satfinite", "compatibility_paths": [ - "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_s32_u8_s8_satfinite" + "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_s32_u8_satfinite" ] }, "dialect": { @@ -219615,7 +222293,7 @@ ] }, "llvm": { - "symbol": "llvm.nvvm.mma.sp.ordered.metadata.m16n8k64.row.col.satfinite.u8.s8", + "symbol": "llvm.nvvm.mma.sp.ordered.metadata.m16n8k64.row.col.satfinite.u8", "arguments": [ "i32", "i32", @@ -219709,11 +222387,11 @@ "sm_80", "ptx85" ], - "representation": "convergent ordered sparse m16n8k64 mixed-sign saturating INT8 inline PTX with selector 0", + "representation": "convergent ordered sparse m16n8k64 unsigned saturating INT8 inline PTX with selector 0", "stage": "backend_codegen", "mechanism": "inline_ptx", "outcome": "succeeded", - "detail": "The 4,779-byte combined LLVM IR probe (SHA-256 01600853ff696df81a849a3d804086265d07d61c7a2f24ebaf7b3f056753fccb) covered all eight variants. Pinned LLVM emitted 13,390-byte PTX (SHA-256 b370bcbebbe761bd65675ad2d2602230cc315189a1bb8cb1c4533c68b564a897) with exactly eight ordered m16n8k64 instructions at PTX 8.5 and sm_80; this record retained exact saturating u8-by-s8 PTX with selector 0.", + "detail": "The 4,779-byte combined LLVM IR probe (SHA-256 01600853ff696df81a849a3d804086265d07d61c7a2f24ebaf7b3f056753fccb) covered all eight variants. Pinned LLVM emitted 13,390-byte PTX (SHA-256 b370bcbebbe761bd65675ad2d2602230cc315189a1bb8cb1c4533c68b564a897) with exactly eight ordered m16n8k64 instructions at PTX 8.5 and sm_80; this record retained exact saturating u8-by-u8 PTX with selector 0.", "artifact_kind": null, "tool_path": null, "tool_version": null, @@ -219763,7 +222441,7 @@ "compute_80", "ptx93" ], - "representation": "convergent ordered sparse m16n8k64 mixed-sign saturating INT8 inline PTX in the combined coverage kernel", + "representation": "convergent ordered sparse m16n8k64 unsigned saturating INT8 inline PTX in the combined coverage kernel", "stage": "backend_codegen", "mechanism": "inline_ptx", "outcome": "succeeded", @@ -219795,7 +222473,7 @@ "shape": "m16n8k64", "accumulator": "s32", "a_element": "u8", - "b_element": "s8", + "b_element": "u8", "a_layout": "row", "b_layout": "col", "overflow": "satfinite", @@ -219820,7 +222498,7 @@ "satfinite", "s32", "u8", - "s8", + "u8", "s32" ], "operands": [ @@ -219848,20 +222526,20 @@ } ] }, - "summary": "Multiplies warp-distributed sparse unsigned A and signed B INT8 fragments with ordered sparsity metadata and adds a saturating s32 accumulator." + "summary": "Multiplies warp-distributed sparse unsigned A and unsigned B INT8 fragments with ordered sparsity metadata and adds a saturating s32 accumulator." }, { - "id": "mma_sp_ordered_metadata_m16n8k64_s32_u8_satfinite", - "operation_key": "matrix.mma.sp.m16n8k64.row.col.s32.u8.u8.s32.satfinite.ordered_metadata", + "id": "mma_sp_ordered_metadata_m16n8k8_f32_tf32", + "operation_key": "matrix.mma.sp.m16n8k8.row.col.f32.tf32.tf32.f32.not_applicable.ordered_metadata", "family": "sparse_mma", "source": { "kind": "llvm_imported", - "source_record": "int_nvvm_mma_sp_ordered_metadata_m16n8k64_row_col_satfinite_u8" + "source_record": "int_nvvm_mma_sp_ordered_metadata_m16n8k8_row_col_tf32" }, "selections": [ { - "source_record": "anonymous_19726", - "asm": "mma.sp::ordered_metadata.sync.aligned.m16n8k64.row.col.satfinite.s32.u8.u8.s32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1, $ra2, $ra3}},\n\t\t{{$rb0, $rb1, $rb2, $rb3}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}},\n\t\t$metadata,\n\t\t$selector;", + "source_record": "anonymous_19540", + "asm": "mma.sp::ordered_metadata.sync.aligned.m16n8k8.row.col.f32.tf32.tf32.f32\n\t\t{{$rd0, $rd1, $rd2, $rd3}},\n\t\t{{$ra0, $ra1}},\n\t\t{{$rb0, $rb1}},\n\t\t{{$rc0, $rc1, $rc2, $rc3}},\n\t\t$metadata,\n\t\t$selector;", "predicates": [ "Subtarget->getSmVersion() >= 80", "Subtarget->getPTXVersion() >= 85" @@ -219869,38 +222547,34 @@ } ], "rust": { - "abi_id": "i0185", + "abi_id": "i1018", "module": "matrix", - "name": "mma_sp_ordered_metadata_m16n8k64_s32_u8_satfinite", + "name": "mma_sp_ordered_metadata_m16n8k8_f32_tf32", "arguments": [ - "[i32; 4]", - "[u32; 4]", - "[u32; 4]", + "[f32; 4]", + "[u32; 2]", + "[u32; 2]", "u32", "u32" ], - "result": "[i32; 4]", + "result": "[f32; 4]", "safe": false, "must_use": true, "safe_allowlist_reason": null, - "canonical_path": "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0185", - "public_path": "cuda_intrinsics::matrix::mma_sp_ordered_metadata_m16n8k64_s32_u8_satfinite", + "canonical_path": "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i1018", + "public_path": "cuda_intrinsics::matrix::mma_sp_ordered_metadata_m16n8k8_f32_tf32", "compatibility_paths": [ - "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_s32_u8_satfinite" + "cuda_device::wmma::mma_sp_ordered_metadata_m16n8k8_f32_tf32" ] }, "dialect": { "op_type": "SparseMmaOp", "op_name": "nvvm.sparse_mma", "operands": [ - "i32", - "i32", - "i32", - "i32", - "u32", - "u32", - "u32", - "u32", + "f32", + "f32", + "f32", + "f32", "u32", "u32", "u32", @@ -219909,41 +222583,37 @@ "u32" ], "results": [ - "i32", - "i32", - "i32", - "i32" + "f32", + "f32", + "f32", + "f32" ] }, "llvm": { - "symbol": "llvm.nvvm.mma.sp.ordered.metadata.m16n8k64.row.col.satfinite.u8", + "symbol": "llvm.nvvm.mma.sp.ordered.metadata.m16n8k8.row.col.tf32", "arguments": [ "i32", "i32", "i32", "i32", - "i32", - "i32", - "i32", - "i32", - "i32", - "i32", - "i32", - "i32", + "f32", + "f32", + "f32", + "f32", "i32", "i32" ], "results": [ - "i32", - "i32", - "i32", - "i32" + "f32", + "f32", + "f32", + "f32" ], "properties": [ - "ImmArg", + "ImmArg", "IntrNoCallback", "IntrNoMem", - "Range" + "Range" ], "result_facts": { "no_undef": false, @@ -219967,7 +222637,7 @@ } ] }, - "ptx_result": "[i32; 4]", + "ptx_result": "[f32; 4]", "targets": "all", "ptx_isa_version": "9.3", "ptx_isa_section": "9.7.15.6.3 Multiply-and-Accumulate Instruction: mma.sp", @@ -219977,7 +222647,7 @@ "profile": "rust-llvm-23.1.0-16696adc", "version": "LLVM version 23.1.0-rust-1.100.0-nightly", "sha256": "2e5bc688625ca7d98bca9b5f0f0d14525d2eb59e8a9842964e480df3ffd1f921", - "status": "validated", + "status": "executed", "target_triple": "nvptx64-nvidia-cuda", "gpu_target": "sm_80", "ptx_feature": "+ptx85" @@ -220003,18 +222673,18 @@ "sha256": "2e5bc688625ca7d98bca9b5f0f0d14525d2eb59e8a9842964e480df3ffd1f921", "artifact_path": null, "build_id_prefix": null, - "status": "validated", + "status": "executed", "stages": [ { "targets": [ "sm_80", "ptx85" ], - "representation": "convergent ordered sparse m16n8k64 unsigned saturating INT8 inline PTX with selector 0", + "representation": "eight committed per-intrinsic convergent inline-PTX probe fixtures covering every selector immediate", "stage": "backend_codegen", "mechanism": "inline_ptx", "outcome": "succeeded", - "detail": "The 4,779-byte combined LLVM IR probe (SHA-256 01600853ff696df81a849a3d804086265d07d61c7a2f24ebaf7b3f056753fccb) covered all eight variants. Pinned LLVM emitted 13,390-byte PTX (SHA-256 b370bcbebbe761bd65675ad2d2602230cc315189a1bb8cb1c4533c68b564a897) with exactly eight ordered m16n8k64 instructions at PTX 8.5 and sm_80; this record retained exact saturating u8-by-u8 PTX with selector 0.", + "detail": "Pinned LLVM 23.1.0-rust lowered the eight per-intrinsic probe fixtures at sm_80/+ptx85 into 59,900 bytes of PTX across eight files; their concatenation in lexicographic id order has SHA-256 2eaae1b352ef07684549050756eba1ae0eb57318cfa329a9f103f086296f81dc, and every fixture retains one unguarded exact ordered-metadata instruction per selector immediate (24 across the family). Typed declarations of all eight intrinsics fail selection at sm_75/+ptx85 and sm_80/+ptx80, and select at sm_80, sm_86, sm_89, and sm_90/+ptx85 plus sm_100/+ptx86.", "artifact_kind": null, "tool_path": null, "tool_version": null, @@ -220025,15 +222695,30 @@ "sm_80", "ptx85" ], - "representation": "exact-floor ordered sparse m16n8k64 INT8 PTX", + "representation": "exact-floor per-intrinsic probe PTX containing all eight ordered sparse floating MMA forms", "stage": "ptx_assembly", "mechanism": "inline_ptx", "outcome": "succeeded", - "detail": "CUDA 13.3 ptxas accepted all eight exact instructions and produced a 1,464-byte cubin with SHA-256 6bcec1b1eab13da703fdade053704aa6ab00591a1b38dd7daf48ac0dec541df2. Because every probe function was unreferenced, ptxas removed their bodies; this proves assembly acceptance, not retained SASS.", - "artifact_kind": null, + "detail": "CUDA 13.3 ptxas accepted every selector form of all eight ordered-metadata sparse floating variants at PTX 8.5 and sm_80.", + "artifact_kind": "cubin", "tool_path": "/usr/local/cuda-13.3/bin/ptxas", "tool_version": "CUDA 13.3 V13.3.33 build cuda_13.3.r13.3/compiler.37862127_0", "tool_sha256": "7fdd01a4cf50e30746da98989c9272a907f491e6fd7fecfda14642e4375f88fb" + }, + { + "targets": [ + "sm_120", + "ptx85" + ], + "representation": "all eight generated ordered sparse floating MMA APIs checked across all 32 lanes and four logical accumulators per lane against an independent host GEMM oracle", + "stage": "runtime", + "mechanism": "inline_ptx", + "outcome": "succeeded", + "detail": "Re-measured with the asymmetric oracle on NVIDIA GeForce RTX 5090 (compute capability 12.0), NVIDIA driver 580.173.02, CUDA toolkit 13.3 V13.3.33. Command: cargo oxide run sparse_mma_ordered_float. Result: exit code 0; SUCCESS: all 8 variants; all 32 lanes and 4 logical accumulators/lane match host GEMM; positionally distinct A/B/C, all six ordered metadata codes (tf32: both), and a nonzero selector per selector domain executed; compute-sanitizer memcheck reports 0 errors.", + "artifact_kind": null, + "tool_path": null, + "tool_version": null, + "tool_sha256": null } ] }, @@ -220057,18 +222742,18 @@ "sha256": "b6a5db233133fb0ed693f8cb8aeb1d405254ce0ab10364478985292ec98cfcf0", "artifact_path": "/usr/local/cuda-13.3/nvvm/lib64/libnvvm.so.4.0.0", "build_id_prefix": "2330c0", - "status": "validated", + "status": "executed", "stages": [ { "targets": [ "compute_80", "ptx93" ], - "representation": "convergent ordered sparse m16n8k64 unsigned saturating INT8 inline PTX in the combined coverage kernel", + "representation": "eight convergent side-effecting ordered-metadata sparse floating inline PTX calls in the sparse_mma_ordered_float coverage kernel", "stage": "backend_codegen", "mechanism": "inline_ptx", "outcome": "succeeded", - "detail": "The production generated_intrinsics route produced 242,464-byte compute_80 NVVM IR with SHA-256 fcc2fe1a6200de7b5ab8a38cab847432669fe4d6ce823c81b73f9b18fa25144c and 68,600-byte LTOIR with SHA-256 aa011070e20cb91d99f0d6d41ffd3883f01031b44d171380f638e3674b2facf3. All eight raw variants use compile-time selector 0.", + "detail": "The production emit-ltoir route (cargo oxide emit-ltoir sparse_mma_ordered_float --arch sm_80) produced 159,170-byte compute_80 NVVM IR with SHA-256 b338c017795f39f98f756f1d87dc202d1db274479c6619fef9797cb5a95f7613, and CUDA 13.3 libNVVM -gen-lto compiled it to 37,468-byte LTOIR with SHA-256 ac6d8317ba99d9c4332a0ce8777024bc066a7304c6ed4b64c341f4248f6b6100; both artifacts are byte-identical across repeated runs, and the module carries all eight ordered raw calls with one compile-time selector per variant.", "artifact_kind": null, "tool_path": null, "tool_version": null, @@ -220079,34 +222764,64 @@ "sm_80", "ptx93" ], - "representation": "combined sparse INT8 coverage kernel with ordered m16n8k64 calls", + "representation": "nvJitLink PTX containing all eight ordered sparse floating MMA forms", + "stage": "ptx_assembly", + "mechanism": "inline_ptx", + "outcome": "succeeded", + "detail": "nvJitLink rendered the LTOIR as 83,805-byte PTX 9.3 for sm_80 (SHA-256 4a92814b0579bf19a0ab8aa4c8b2114ec2170c87711831b2a17a31d579bf6e87) retaining all eight ordered forms, and CUDA 13.3 ptxas assembled it into a 41,896-byte cubin with SHA-256 26aa4d2f38132bc6a219ec7b22655a77b412176f464fe93d6c8ae81ea1b9e88b.", + "artifact_kind": "cubin", + "tool_path": "/usr/local/cuda-13.3/bin/ptxas", + "tool_version": "CUDA 13.3 V13.3.33 build cuda_13.3.r13.3/compiler.37862127_0", + "tool_sha256": "7fdd01a4cf50e30746da98989c9272a907f491e6fd7fecfda14642e4375f88fb" + }, + { + "targets": [ + "sm_80", + "ptx93" + ], + "representation": "the 37,468-byte all-variant libNVVM LTOIR linked for sm_80", "stage": "device_link", "mechanism": "inline_ptx", "outcome": "succeeded", - "detail": "nvJitLink produced a 23,656-byte cubin with SHA-256 8a09455f87f3ef0c7c16adf13bf6030cbe7f0f18df7fcd91ec2a19a10de5b50d. Disassembly contained 30 IMMA.SP instructions in total and exactly 10 IMMA.SP.16864 instructions: all eight raw variants plus two compatibility-path calls.", + "detail": "nvJitLink linked the real libNVVM LTOIR into a 41,896-byte sm_80 cubin with SHA-256 99aa489c3c80ed1414df0c6fe073cff99dcb66a55fd0057729322b54790ac1bf; its cuobjdump SASS contains exactly eight HMMA.SP instructions, one per variant: 1688.F32.TF32, 16816.F32.TF32, 16816.F32.BF16, 16816.F32, 16816.F16, 16832.F32.BF16, 16832.F32, and 16832.F16.", "artifact_kind": "cubin", "tool_path": "/usr/local/cuda-13.3/lib64/libnvJitLink.so.13.3.33", "tool_version": "V13.3.33", "tool_sha256": "3ba1e744347cd68617b862eccfd98b125482e882b7a6319f42abc9a768513db8" + }, + { + "targets": [ + "sm_120", + "ptx93" + ], + "representation": "all eight generated ordered sparse floating MMA APIs checked across all 32 lanes and four logical accumulators per lane against an independent host GEMM oracle", + "stage": "runtime", + "mechanism": "inline_ptx", + "outcome": "succeeded", + "detail": "Executed through the libNVVM route (NVVM IR materialized by libNVVM plus nvJitLink at load time) on NVIDIA GeForce RTX 5090 (compute capability 12.0), NVIDIA driver 580.173.02, CUDA toolkit 13.3 V13.3.33. Command: cargo oxide run sparse_mma_ordered_float --emit-nvvm-ir --arch sm_120. Result: exit code 0; SUCCESS: all 8 variants; all 32 lanes and 4 logical accumulators/lane match host GEMM; positionally distinct A/B/C, all six ordered metadata codes (tf32: both), and a nonzero selector per selector domain executed; compute-sanitizer memcheck reports 0 errors.", + "artifact_kind": null, + "tool_path": null, + "tool_version": null, + "tool_sha256": null } ] } ], "sparse_mma": { - "shape": "m16n8k64", - "accumulator": "s32", - "a_element": "u8", - "b_element": "u8", + "shape": "m16n8k8", + "accumulator": "f32", + "a_element": "tf32", + "b_element": "tf32", "a_layout": "row", "b_layout": "col", - "overflow": "satfinite", + "overflow": "not_applicable", "metadata": "ordered", - "selector": "immediate_zero", + "selector": "immediate_zero_through_three", "participation": "all_warp_lanes_same_instruction_and_qualifiers_no_exited_lanes", - "adapter": "c4_i32_a4_u32_b4_u32_metadata_u32_selector_u32_to_d4_i32", - "llvm_adapter": "a4_i32_b4_i32_c4_i32_metadata_i32_selector_i32_to_d4_i32", + "adapter": "c4_f32_a2_u32_b2_u32_metadata_u32_selector_u32_to_d4_f32", + "llvm_adapter": "a2_i32_b2_i32_c4_f32_metadata_i32_selector_i32_to_d4_f32", "compatibility_source": "generated_stub", - "runtime_validation": "unexecuted" + "runtime_validation": "executed" }, "lowering": "generated_sparse_mma", "expected_ptx": { @@ -220115,14 +222830,13 @@ "sp::ordered_metadata", "sync", "aligned", - "m16n8k64", + "m16n8k8", "row", "col", - "satfinite", - "s32", - "u8", - "u8", - "s32" + "f32", + "tf32", + "tf32", + "f32" ], "operands": [ { @@ -220131,11 +222845,11 @@ }, { "kind": "register_list", - "length": 4 + "length": 2 }, { "kind": "register_list", - "length": 4 + "length": 2 }, { "kind": "register_list", @@ -220149,7 +222863,7 @@ } ] }, - "summary": "Multiplies warp-distributed sparse unsigned A and unsigned B INT8 fragments with ordered sparsity metadata and adds a saturating s32 accumulator." + "summary": "Multiplies warp-distributed ordered sparse tf32 A and B fragments and adds a f32 accumulator." }, { "id": "movmatrix_trans_b16", diff --git a/intrinsics/evidence/cuda-13.3-libnvvm-13.3.33-sparse-mma-ordered-ampere-float.json b/intrinsics/evidence/cuda-13.3-libnvvm-13.3.33-sparse-mma-ordered-ampere-float.json new file mode 100644 index 0000000000..3f013f78b2 --- /dev/null +++ b/intrinsics/evidence/cuda-13.3-libnvvm-13.3.33-sparse-mma-ordered-ampere-float.json @@ -0,0 +1,33 @@ +{ + "schema": 6, + "backend_profile": "cuda-13.3-libnvvm-13.3.33", + "backend_kind": "lib_nvvm", + "llvm_revision": "not-applicable-libnvvm-ir-2.0", + "backend_version": "CUDA toolkit 13.3; nvcc/libNVVM release V13.3.33", + "backend_sha256": "b6a5db233133fb0ed693f8cb8aeb1d405254ce0ab10364478985292ec98cfcf0", + "artifact_path": "/usr/local/cuda-13.3/nvvm/lib64/libnvvm.so.4.0.0", + "build_id_prefix": "2330c0", + "nvvm_ir_version": "2.0", + "debug_ir_version": "3.2", + "defaults": {"target_triple":"nvptx64-nvidia-cuda","gpu_target":"compute_80","ptx_feature":"PTX ISA 8.5 minimum; CUDA 13.3 emits PTX 9.3","status":"executed","runtime_validation":"executed"}, + "fixtures": [{ + "id": "ordered_ampere_float_all", + "coverage_count": 8, + "stages": [ + {"targets":["compute_80","ptx93"],"representation":"eight convergent side-effecting ordered-metadata sparse floating inline PTX calls in the sparse_mma_ordered_float coverage kernel","stage":"backend_codegen","mechanism":"inline_ptx","outcome":"succeeded","detail":"The production emit-ltoir route (cargo oxide emit-ltoir sparse_mma_ordered_float --arch sm_80) produced 159,170-byte compute_80 NVVM IR with SHA-256 b338c017795f39f98f756f1d87dc202d1db274479c6619fef9797cb5a95f7613, and CUDA 13.3 libNVVM -gen-lto compiled it to 37,468-byte LTOIR with SHA-256 ac6d8317ba99d9c4332a0ce8777024bc066a7304c6ed4b64c341f4248f6b6100; both artifacts are byte-identical across repeated runs, and the module carries all eight ordered raw calls with one compile-time selector per variant."}, + {"targets":["sm_80","ptx93"],"representation":"nvJitLink PTX containing all eight ordered sparse floating MMA forms","stage":"ptx_assembly","mechanism":"inline_ptx","outcome":"succeeded","artifact_kind":"cubin","detail":"nvJitLink rendered the LTOIR as 83,805-byte PTX 9.3 for sm_80 (SHA-256 4a92814b0579bf19a0ab8aa4c8b2114ec2170c87711831b2a17a31d579bf6e87) retaining all eight ordered forms, and CUDA 13.3 ptxas assembled it into a 41,896-byte cubin with SHA-256 26aa4d2f38132bc6a219ec7b22655a77b412176f464fe93d6c8ae81ea1b9e88b.","tool_path":"/usr/local/cuda-13.3/bin/ptxas","tool_version":"CUDA 13.3 V13.3.33 build cuda_13.3.r13.3/compiler.37862127_0","tool_sha256":"7fdd01a4cf50e30746da98989c9272a907f491e6fd7fecfda14642e4375f88fb"}, + {"targets":["sm_80","ptx93"],"representation":"the 37,468-byte all-variant libNVVM LTOIR linked for sm_80","stage":"device_link","mechanism":"inline_ptx","outcome":"succeeded","artifact_kind":"cubin","detail":"nvJitLink linked the real libNVVM LTOIR into a 41,896-byte sm_80 cubin with SHA-256 99aa489c3c80ed1414df0c6fe073cff99dcb66a55fd0057729322b54790ac1bf; its cuobjdump SASS contains exactly eight HMMA.SP instructions, one per variant: 1688.F32.TF32, 16816.F32.TF32, 16816.F32.BF16, 16816.F32, 16816.F16, 16832.F32.BF16, 16832.F32, and 16832.F16.","tool_path":"/usr/local/cuda-13.3/lib64/libnvJitLink.so.13.3.33","tool_version":"V13.3.33","tool_sha256":"3ba1e744347cd68617b862eccfd98b125482e882b7a6319f42abc9a768513db8"}, + {"targets":["sm_120","ptx93"],"representation":"all eight generated ordered sparse floating MMA APIs checked across all 32 lanes and four logical accumulators per lane against an independent host GEMM oracle","stage":"runtime","mechanism":"inline_ptx","outcome":"succeeded","detail":"Executed through the libNVVM route (NVVM IR materialized by libNVVM plus nvJitLink at load time) on NVIDIA GeForce RTX 5090 (compute capability 12.0), NVIDIA driver 580.173.02, CUDA toolkit 13.3 V13.3.33. Command: cargo oxide run sparse_mma_ordered_float --emit-nvvm-ir --arch sm_120. Result: exit code 0; SUCCESS: all 8 variants; all 32 lanes and 4 logical accumulators/lane match host GEMM; positionally distinct A/B/C, all six ordered metadata codes (tf32: both), and a nonzero selector per selector domain executed; compute-sanitizer memcheck reports 0 errors."} + ] + }], + "matrices": [ + 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{"axes":[{"name":"variant","values":["mma_sp_ordered_metadata_m16n8k32_f32_bf16"]}],"product_count":1,"fixtures":["ordered_ampere_float_all"],"template":{"id":"${variant}","source_record":"int_nvvm_mma_sp_ordered_metadata_m16n8k32_row_col_bf16","llvm_symbol":"llvm.nvvm.mma.sp.ordered.metadata.m16n8k32.row.col.bf16","expected_ptx":{"mnemonic":"mma","modifiers":["sp::ordered_metadata","sync","aligned","m16n8k32","row","col","f32","bf16","bf16","f32"],"operands":[{"kind":"register_list","length":4},{"kind":"register_list","length":4},{"kind":"register_list","length":4},{"kind":"register_list","length":4},{"kind":"register"},{"kind":"immediate"}]},"facts":{"llvm_arguments":["i32","i32","i32","i32","i32","i32","i32","i32","f32","f32","f32","f32","i32","i32"],"llvm_results":["f32","f32","f32","f32"]}}}, + {"axes":[{"name":"variant","values":["mma_sp_ordered_metadata_m16n8k32_f16_f16"]}],"product_count":1,"fixtures":["ordered_ampere_float_all"],"template":{"id":"${variant}","source_record":"int_nvvm_mma_sp_ordered_metadata_m16n8k32_row_col_f16_f16","llvm_symbol":"llvm.nvvm.mma.sp.ordered.metadata.m16n8k32.row.col.f16.f16","expected_ptx":{"mnemonic":"mma","modifiers":["sp::ordered_metadata","sync","aligned","m16n8k32","row","col","f16","f16","f16","f16"],"operands":[{"kind":"register_list","length":2},{"kind":"register_list","length":4},{"kind":"register_list","length":4},{"kind":"register_list","length":2},{"kind":"register"},{"kind":"immediate"}]},"facts":{"llvm_arguments":["v2f16","v2f16","v2f16","v2f16","v2f16","v2f16","v2f16","v2f16","v2f16","v2f16","i32","i32"],"llvm_results":["v2f16","v2f16"]}}}, + {"axes":[{"name":"variant","values":["mma_sp_ordered_metadata_m16n8k32_f32_f16"]}],"product_count":1,"fixtures":["ordered_ampere_float_all"],"template":{"id":"${variant}","source_record":"int_nvvm_mma_sp_ordered_metadata_m16n8k32_row_col_f32_f32","llvm_symbol":"llvm.nvvm.mma.sp.ordered.metadata.m16n8k32.row.col.f32.f32","expected_ptx":{"mnemonic":"mma","modifiers":["sp::ordered_metadata","sync","aligned","m16n8k32","row","col","f32","f16","f16","f32"],"operands":[{"kind":"register_list","length":4},{"kind":"register_list","length":4},{"kind":"register_list","length":4},{"kind":"register_list","length":4},{"kind":"register"},{"kind":"immediate"}]},"facts":{"llvm_arguments":["v2f16","v2f16","v2f16","v2f16","v2f16","v2f16","v2f16","v2f16","f32","f32","f32","f32","i32","i32"],"llvm_results":["f32","f32","f32","f32"]}}} + ] +} diff --git a/intrinsics/evidence/rust-llvm-23.1.0-16696adc-sparse-mma-ordered-ampere-float.json b/intrinsics/evidence/rust-llvm-23.1.0-16696adc-sparse-mma-ordered-ampere-float.json new file mode 100644 index 0000000000..df9e933659 --- /dev/null +++ b/intrinsics/evidence/rust-llvm-23.1.0-16696adc-sparse-mma-ordered-ampere-float.json @@ -0,0 +1,28 @@ +{ + "schema": 6, + "backend_profile": "rust-llvm-23.1.0-16696adc", + "backend_kind": "llvm_nvptx", + "llvm_revision": "16696adcd119e6ba9cc175207d984d7021211acb", + "backend_version": "LLVM version 23.1.0-rust-1.100.0-nightly", + "backend_sha256": "2e5bc688625ca7d98bca9b5f0f0d14525d2eb59e8a9842964e480df3ffd1f921", + "defaults": {"target_triple":"nvptx64-nvidia-cuda","gpu_target":"sm_80","ptx_feature":"+ptx85","status":"executed","runtime_validation":"executed"}, + "fixtures": [{ + "id": "ordered_ampere_float_all", + "coverage_count": 8, + "stages": [ + {"targets":["sm_80","ptx85"],"representation":"eight committed per-intrinsic convergent inline-PTX probe fixtures covering every selector immediate","stage":"backend_codegen","mechanism":"inline_ptx","outcome":"succeeded","detail":"Pinned LLVM 23.1.0-rust lowered the eight per-intrinsic probe fixtures at sm_80/+ptx85 into 59,900 bytes of PTX across eight files; their concatenation in lexicographic id order has SHA-256 2eaae1b352ef07684549050756eba1ae0eb57318cfa329a9f103f086296f81dc, and every fixture retains one unguarded exact ordered-metadata instruction per selector immediate (24 across the family). Typed declarations of all eight intrinsics fail selection at sm_75/+ptx85 and sm_80/+ptx80, and select at sm_80, sm_86, sm_89, and sm_90/+ptx85 plus sm_100/+ptx86."}, + {"targets":["sm_80","ptx85"],"representation":"exact-floor per-intrinsic probe PTX containing all eight ordered sparse floating MMA forms","stage":"ptx_assembly","mechanism":"inline_ptx","outcome":"succeeded","artifact_kind":"cubin","detail":"CUDA 13.3 ptxas accepted every selector form of all eight ordered-metadata sparse floating variants at PTX 8.5 and sm_80.","tool_path":"/usr/local/cuda-13.3/bin/ptxas","tool_version":"CUDA 13.3 V13.3.33 build cuda_13.3.r13.3/compiler.37862127_0","tool_sha256":"7fdd01a4cf50e30746da98989c9272a907f491e6fd7fecfda14642e4375f88fb"}, + {"targets":["sm_120","ptx85"],"representation":"all eight generated ordered sparse floating MMA APIs checked across all 32 lanes and four logical accumulators per lane against an independent host GEMM oracle","stage":"runtime","mechanism":"inline_ptx","outcome":"succeeded","detail":"Re-measured with the asymmetric oracle on NVIDIA GeForce RTX 5090 (compute capability 12.0), NVIDIA driver 580.173.02, CUDA toolkit 13.3 V13.3.33. Command: cargo oxide run sparse_mma_ordered_float. Result: exit code 0; SUCCESS: all 8 variants; all 32 lanes and 4 logical accumulators/lane match host GEMM; positionally distinct A/B/C, all six ordered metadata codes (tf32: both), and a nonzero selector per selector domain executed; compute-sanitizer memcheck reports 0 errors."} + ] + }], + "matrices": [ + {"axes":[{"name":"variant","values":["mma_sp_ordered_metadata_m16n8k8_f32_tf32"]}],"product_count":1,"fixtures":["ordered_ampere_float_all"],"template":{"id":"${variant}","source_record":"int_nvvm_mma_sp_ordered_metadata_m16n8k8_row_col_tf32","llvm_symbol":"llvm.nvvm.mma.sp.ordered.metadata.m16n8k8.row.col.tf32","expected_ptx":{"mnemonic":"mma","modifiers":["sp::ordered_metadata","sync","aligned","m16n8k8","row","col","f32","tf32","tf32","f32"],"operands":[{"kind":"register_list","length":4},{"kind":"register_list","length":2},{"kind":"register_list","length":2},{"kind":"register_list","length":4},{"kind":"register"},{"kind":"immediate"}]},"facts":{"llvm_arguments":["i32","i32","i32","i32","f32","f32","f32","f32","i32","i32"],"llvm_results":["f32","f32","f32","f32"]}}}, + {"axes":[{"name":"variant","values":["mma_sp_ordered_metadata_m16n8k16_f32_tf32"]}],"product_count":1,"fixtures":["ordered_ampere_float_all"],"template":{"id":"${variant}","source_record":"int_nvvm_mma_sp_ordered_metadata_m16n8k16_row_col_tf32","llvm_symbol":"llvm.nvvm.mma.sp.ordered.metadata.m16n8k16.row.col.tf32","expected_ptx":{"mnemonic":"mma","modifiers":["sp::ordered_metadata","sync","aligned","m16n8k16","row","col","f32","tf32","tf32","f32"],"operands":[{"kind":"register_list","length":4},{"kind":"register_list","length":4},{"kind":"register_list","length":4},{"kind":"register_list","length":4},{"kind":"register"},{"kind":"immediate"}]},"facts":{"llvm_arguments":["i32","i32","i32","i32","i32","i32","i32","i32","f32","f32","f32","f32","i32","i32"],"llvm_results":["f32","f32","f32","f32"]}}}, + {"axes":[{"name":"variant","values":["mma_sp_ordered_metadata_m16n8k16_f32_bf16"]}],"product_count":1,"fixtures":["ordered_ampere_float_all"],"template":{"id":"${variant}","source_record":"int_nvvm_mma_sp_ordered_metadata_m16n8k16_row_col_bf16","llvm_symbol":"llvm.nvvm.mma.sp.ordered.metadata.m16n8k16.row.col.bf16","expected_ptx":{"mnemonic":"mma","modifiers":["sp::ordered_metadata","sync","aligned","m16n8k16","row","col","f32","bf16","bf16","f32"],"operands":[{"kind":"register_list","length":4},{"kind":"register_list","length":2},{"kind":"register_list","length":2},{"kind":"register_list","length":4},{"kind":"register"},{"kind":"immediate"}]},"facts":{"llvm_arguments":["i32","i32","i32","i32","f32","f32","f32","f32","i32","i32"],"llvm_results":["f32","f32","f32","f32"]}}}, + {"axes":[{"name":"variant","values":["mma_sp_ordered_metadata_m16n8k16_f16_f16"]}],"product_count":1,"fixtures":["ordered_ampere_float_all"],"template":{"id":"${variant}","source_record":"int_nvvm_mma_sp_ordered_metadata_m16n8k16_row_col_f16_f16","llvm_symbol":"llvm.nvvm.mma.sp.ordered.metadata.m16n8k16.row.col.f16.f16","expected_ptx":{"mnemonic":"mma","modifiers":["sp::ordered_metadata","sync","aligned","m16n8k16","row","col","f16","f16","f16","f16"],"operands":[{"kind":"register_list","length":2},{"kind":"register_list","length":2},{"kind":"register_list","length":2},{"kind":"register_list","length":2},{"kind":"register"},{"kind":"immediate"}]},"facts":{"llvm_arguments":["v2f16","v2f16","v2f16","v2f16","v2f16","v2f16","i32","i32"],"llvm_results":["v2f16","v2f16"]}}}, + {"axes":[{"name":"variant","values":["mma_sp_ordered_metadata_m16n8k16_f32_f16"]}],"product_count":1,"fixtures":["ordered_ampere_float_all"],"template":{"id":"${variant}","source_record":"int_nvvm_mma_sp_ordered_metadata_m16n8k16_row_col_f32_f32","llvm_symbol":"llvm.nvvm.mma.sp.ordered.metadata.m16n8k16.row.col.f32.f32","expected_ptx":{"mnemonic":"mma","modifiers":["sp::ordered_metadata","sync","aligned","m16n8k16","row","col","f32","f16","f16","f32"],"operands":[{"kind":"register_list","length":4},{"kind":"register_list","length":2},{"kind":"register_list","length":2},{"kind":"register_list","length":4},{"kind":"register"},{"kind":"immediate"}]},"facts":{"llvm_arguments":["v2f16","v2f16","v2f16","v2f16","f32","f32","f32","f32","i32","i32"],"llvm_results":["f32","f32","f32","f32"]}}}, + {"axes":[{"name":"variant","values":["mma_sp_ordered_metadata_m16n8k32_f32_bf16"]}],"product_count":1,"fixtures":["ordered_ampere_float_all"],"template":{"id":"${variant}","source_record":"int_nvvm_mma_sp_ordered_metadata_m16n8k32_row_col_bf16","llvm_symbol":"llvm.nvvm.mma.sp.ordered.metadata.m16n8k32.row.col.bf16","expected_ptx":{"mnemonic":"mma","modifiers":["sp::ordered_metadata","sync","aligned","m16n8k32","row","col","f32","bf16","bf16","f32"],"operands":[{"kind":"register_list","length":4},{"kind":"register_list","length":4},{"kind":"register_list","length":4},{"kind":"register_list","length":4},{"kind":"register"},{"kind":"immediate"}]},"facts":{"llvm_arguments":["i32","i32","i32","i32","i32","i32","i32","i32","f32","f32","f32","f32","i32","i32"],"llvm_results":["f32","f32","f32","f32"]}}}, + {"axes":[{"name":"variant","values":["mma_sp_ordered_metadata_m16n8k32_f16_f16"]}],"product_count":1,"fixtures":["ordered_ampere_float_all"],"template":{"id":"${variant}","source_record":"int_nvvm_mma_sp_ordered_metadata_m16n8k32_row_col_f16_f16","llvm_symbol":"llvm.nvvm.mma.sp.ordered.metadata.m16n8k32.row.col.f16.f16","expected_ptx":{"mnemonic":"mma","modifiers":["sp::ordered_metadata","sync","aligned","m16n8k32","row","col","f16","f16","f16","f16"],"operands":[{"kind":"register_list","length":2},{"kind":"register_list","length":4},{"kind":"register_list","length":4},{"kind":"register_list","length":2},{"kind":"register"},{"kind":"immediate"}]},"facts":{"llvm_arguments":["v2f16","v2f16","v2f16","v2f16","v2f16","v2f16","v2f16","v2f16","v2f16","v2f16","i32","i32"],"llvm_results":["v2f16","v2f16"]}}}, + {"axes":[{"name":"variant","values":["mma_sp_ordered_metadata_m16n8k32_f32_f16"]}],"product_count":1,"fixtures":["ordered_ampere_float_all"],"template":{"id":"${variant}","source_record":"int_nvvm_mma_sp_ordered_metadata_m16n8k32_row_col_f32_f32","llvm_symbol":"llvm.nvvm.mma.sp.ordered.metadata.m16n8k32.row.col.f32.f32","expected_ptx":{"mnemonic":"mma","modifiers":["sp::ordered_metadata","sync","aligned","m16n8k32","row","col","f32","f16","f16","f32"],"operands":[{"kind":"register_list","length":4},{"kind":"register_list","length":4},{"kind":"register_list","length":4},{"kind":"register_list","length":4},{"kind":"register"},{"kind":"immediate"}]},"facts":{"llvm_arguments":["v2f16","v2f16","v2f16","v2f16","v2f16","v2f16","v2f16","v2f16","f32","f32","f32","f32","i32","i32"],"llvm_results":["f32","f32","f32","f32"]}}} + ] +} diff --git a/intrinsics/generated-reference.md b/intrinsics/generated-reference.md index 7c04c6d845..b3ce1c8484 100644 --- a/intrinsics/generated-reference.md +++ b/intrinsics/generated-reference.md @@ -2,7 +2,7 @@ SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. SPDX-License-Identifier: Apache-2.0 @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. --> @@ -590,6 +590,13 @@ This table is generated from the resolved catalog. Evidence stages below disting | `cuda_intrinsics::matrix::mma_sp_ordered_metadata_m16n8k128_s32_u4_s4` | `nvvm.sparse_mma` | LLVM `llvm.nvvm.mma.sp.ordered.metadata.m16n8k128.row.col.u4.s4` from `int_nvvm_mma_sp_ordered_metadata_m16n8k128_row_col_u4_s4` | unsafe; scope warp; impure; memory none; convergent true | PTX 8.5 on sm_80+ ([PTX ISA 9.3, 9.7.15.6.3 Multiply-and-Accumulate Instruction: mma.sp](https://docs.nvidia.com/cuda/parallel-thread-execution/#warp-level-matrix-instructions-mma-sp)) | validated on `rust-llvm-23.1.0-16696adc`; expects `mma.sp::ordered_metadata.sync.aligned.m16n8k128.row.col.s32.u4.s4.s32 , , , , , ;` (`LLVM version 23.1.0-rust-1.100.0-nightly`, SHA-256 `2e5bc688625ca7d98bca9b5f0f0d14525d2eb59e8a9842964e480df3ffd1f921`) | | `cuda_intrinsics::matrix::mma_sp_ordered_metadata_m16n8k128_s32_u4_s4_satfinite` | `nvvm.sparse_mma` | LLVM `llvm.nvvm.mma.sp.ordered.metadata.m16n8k128.row.col.satfinite.u4.s4` from `int_nvvm_mma_sp_ordered_metadata_m16n8k128_row_col_satfinite_u4_s4` | unsafe; scope warp; impure; memory none; convergent true | PTX 8.5 on sm_80+ ([PTX ISA 9.3, 9.7.15.6.3 Multiply-and-Accumulate Instruction: mma.sp](https://docs.nvidia.com/cuda/parallel-thread-execution/#warp-level-matrix-instructions-mma-sp)) | validated on `rust-llvm-23.1.0-16696adc`; expects `mma.sp::ordered_metadata.sync.aligned.m16n8k128.row.col.satfinite.s32.u4.s4.s32 , , , , , ;` (`LLVM version 23.1.0-rust-1.100.0-nightly`, SHA-256 `2e5bc688625ca7d98bca9b5f0f0d14525d2eb59e8a9842964e480df3ffd1f921`) | | `cuda_intrinsics::matrix::mma_sp_ordered_metadata_m16n8k128_s32_u4_satfinite` | `nvvm.sparse_mma` | LLVM `llvm.nvvm.mma.sp.ordered.metadata.m16n8k128.row.col.satfinite.u4` from `int_nvvm_mma_sp_ordered_metadata_m16n8k128_row_col_satfinite_u4` | unsafe; scope warp; impure; memory none; convergent true | PTX 8.5 on sm_80+ ([PTX ISA 9.3, 9.7.15.6.3 Multiply-and-Accumulate Instruction: mma.sp](https://docs.nvidia.com/cuda/parallel-thread-execution/#warp-level-matrix-instructions-mma-sp)) | validated on `rust-llvm-23.1.0-16696adc`; expects `mma.sp::ordered_metadata.sync.aligned.m16n8k128.row.col.satfinite.s32.u4.u4.s32 , , , , , ;` (`LLVM version 23.1.0-rust-1.100.0-nightly`, SHA-256 `2e5bc688625ca7d98bca9b5f0f0d14525d2eb59e8a9842964e480df3ffd1f921`) | +| `cuda_intrinsics::matrix::mma_sp_ordered_metadata_m16n8k16_f16_f16` | `nvvm.sparse_mma` | LLVM `llvm.nvvm.mma.sp.ordered.metadata.m16n8k16.row.col.f16.f16` from `int_nvvm_mma_sp_ordered_metadata_m16n8k16_row_col_f16_f16` | unsafe; scope warp; impure; memory none; convergent true | PTX 8.5 on sm_80+ ([PTX ISA 9.3, 9.7.15.6.3 Multiply-and-Accumulate Instruction: mma.sp](https://docs.nvidia.com/cuda/parallel-thread-execution/#warp-level-matrix-instructions-mma-sp)) | executed on `rust-llvm-23.1.0-16696adc`; expects `mma.sp::ordered_metadata.sync.aligned.m16n8k16.row.col.f16.f16.f16.f16 , , , , , ;` (`LLVM version 23.1.0-rust-1.100.0-nightly`, SHA-256 `2e5bc688625ca7d98bca9b5f0f0d14525d2eb59e8a9842964e480df3ffd1f921`) | +| `cuda_intrinsics::matrix::mma_sp_ordered_metadata_m16n8k16_f32_bf16` | `nvvm.sparse_mma` | LLVM `llvm.nvvm.mma.sp.ordered.metadata.m16n8k16.row.col.bf16` from `int_nvvm_mma_sp_ordered_metadata_m16n8k16_row_col_bf16` | unsafe; scope warp; impure; memory none; convergent true | PTX 8.5 on sm_80+ ([PTX ISA 9.3, 9.7.15.6.3 Multiply-and-Accumulate Instruction: mma.sp](https://docs.nvidia.com/cuda/parallel-thread-execution/#warp-level-matrix-instructions-mma-sp)) | executed on `rust-llvm-23.1.0-16696adc`; expects `mma.sp::ordered_metadata.sync.aligned.m16n8k16.row.col.f32.bf16.bf16.f32 , , , , , ;` (`LLVM version 23.1.0-rust-1.100.0-nightly`, SHA-256 `2e5bc688625ca7d98bca9b5f0f0d14525d2eb59e8a9842964e480df3ffd1f921`) | +| `cuda_intrinsics::matrix::mma_sp_ordered_metadata_m16n8k16_f32_f16` | `nvvm.sparse_mma` | LLVM `llvm.nvvm.mma.sp.ordered.metadata.m16n8k16.row.col.f32.f32` from `int_nvvm_mma_sp_ordered_metadata_m16n8k16_row_col_f32_f32` | unsafe; scope warp; impure; memory none; convergent true | PTX 8.5 on sm_80+ ([PTX ISA 9.3, 9.7.15.6.3 Multiply-and-Accumulate Instruction: mma.sp](https://docs.nvidia.com/cuda/parallel-thread-execution/#warp-level-matrix-instructions-mma-sp)) | executed on `rust-llvm-23.1.0-16696adc`; expects `mma.sp::ordered_metadata.sync.aligned.m16n8k16.row.col.f32.f16.f16.f32 , , , , , ;` (`LLVM version 23.1.0-rust-1.100.0-nightly`, SHA-256 `2e5bc688625ca7d98bca9b5f0f0d14525d2eb59e8a9842964e480df3ffd1f921`) | +| `cuda_intrinsics::matrix::mma_sp_ordered_metadata_m16n8k16_f32_tf32` | `nvvm.sparse_mma` | LLVM `llvm.nvvm.mma.sp.ordered.metadata.m16n8k16.row.col.tf32` from `int_nvvm_mma_sp_ordered_metadata_m16n8k16_row_col_tf32` | unsafe; scope warp; impure; memory none; convergent true | PTX 8.5 on sm_80+ ([PTX ISA 9.3, 9.7.15.6.3 Multiply-and-Accumulate Instruction: mma.sp](https://docs.nvidia.com/cuda/parallel-thread-execution/#warp-level-matrix-instructions-mma-sp)) | executed on `rust-llvm-23.1.0-16696adc`; expects `mma.sp::ordered_metadata.sync.aligned.m16n8k16.row.col.f32.tf32.tf32.f32 , , , , , ;` (`LLVM version 23.1.0-rust-1.100.0-nightly`, SHA-256 `2e5bc688625ca7d98bca9b5f0f0d14525d2eb59e8a9842964e480df3ffd1f921`) | +| `cuda_intrinsics::matrix::mma_sp_ordered_metadata_m16n8k32_f16_f16` | `nvvm.sparse_mma` | LLVM `llvm.nvvm.mma.sp.ordered.metadata.m16n8k32.row.col.f16.f16` from `int_nvvm_mma_sp_ordered_metadata_m16n8k32_row_col_f16_f16` | unsafe; scope warp; impure; memory none; convergent true | PTX 8.5 on sm_80+ ([PTX ISA 9.3, 9.7.15.6.3 Multiply-and-Accumulate Instruction: mma.sp](https://docs.nvidia.com/cuda/parallel-thread-execution/#warp-level-matrix-instructions-mma-sp)) | executed on `rust-llvm-23.1.0-16696adc`; expects `mma.sp::ordered_metadata.sync.aligned.m16n8k32.row.col.f16.f16.f16.f16 , , , , , ;` (`LLVM version 23.1.0-rust-1.100.0-nightly`, SHA-256 `2e5bc688625ca7d98bca9b5f0f0d14525d2eb59e8a9842964e480df3ffd1f921`) | +| `cuda_intrinsics::matrix::mma_sp_ordered_metadata_m16n8k32_f32_bf16` | `nvvm.sparse_mma` | LLVM `llvm.nvvm.mma.sp.ordered.metadata.m16n8k32.row.col.bf16` from `int_nvvm_mma_sp_ordered_metadata_m16n8k32_row_col_bf16` | unsafe; scope warp; impure; memory none; convergent true | PTX 8.5 on sm_80+ ([PTX ISA 9.3, 9.7.15.6.3 Multiply-and-Accumulate Instruction: mma.sp](https://docs.nvidia.com/cuda/parallel-thread-execution/#warp-level-matrix-instructions-mma-sp)) | executed on `rust-llvm-23.1.0-16696adc`; expects `mma.sp::ordered_metadata.sync.aligned.m16n8k32.row.col.f32.bf16.bf16.f32 , , , , , ;` (`LLVM version 23.1.0-rust-1.100.0-nightly`, SHA-256 `2e5bc688625ca7d98bca9b5f0f0d14525d2eb59e8a9842964e480df3ffd1f921`) | +| `cuda_intrinsics::matrix::mma_sp_ordered_metadata_m16n8k32_f32_f16` | `nvvm.sparse_mma` | LLVM `llvm.nvvm.mma.sp.ordered.metadata.m16n8k32.row.col.f32.f32` from `int_nvvm_mma_sp_ordered_metadata_m16n8k32_row_col_f32_f32` | unsafe; scope warp; impure; memory none; convergent true | PTX 8.5 on sm_80+ ([PTX ISA 9.3, 9.7.15.6.3 Multiply-and-Accumulate Instruction: mma.sp](https://docs.nvidia.com/cuda/parallel-thread-execution/#warp-level-matrix-instructions-mma-sp)) | executed on `rust-llvm-23.1.0-16696adc`; expects `mma.sp::ordered_metadata.sync.aligned.m16n8k32.row.col.f32.f16.f16.f32 , , , , , ;` (`LLVM version 23.1.0-rust-1.100.0-nightly`, SHA-256 `2e5bc688625ca7d98bca9b5f0f0d14525d2eb59e8a9842964e480df3ffd1f921`) | | `cuda_intrinsics::matrix::mma_sp_ordered_metadata_m16n8k32_s32_s8` | `nvvm.sparse_mma` | LLVM `llvm.nvvm.mma.sp.ordered.metadata.m16n8k32.row.col.s8` from `int_nvvm_mma_sp_ordered_metadata_m16n8k32_row_col_s8` | unsafe; scope warp; impure; memory none; convergent true | PTX 8.5 on sm_80+ ([PTX ISA 9.3, 9.7.15.6.3 Multiply-and-Accumulate Instruction: mma.sp](https://docs.nvidia.com/cuda/parallel-thread-execution/#warp-level-matrix-instructions-mma-sp)) | validated on `rust-llvm-23.1.0-16696adc`; expects `mma.sp::ordered_metadata.sync.aligned.m16n8k32.row.col.s32.s8.s8.s32 , , , , , ;` (`LLVM version 23.1.0-rust-1.100.0-nightly`, SHA-256 `2e5bc688625ca7d98bca9b5f0f0d14525d2eb59e8a9842964e480df3ffd1f921`) | | `cuda_intrinsics::matrix::mma_sp_ordered_metadata_m16n8k32_s32_s8_satfinite` | `nvvm.sparse_mma` | LLVM `llvm.nvvm.mma.sp.ordered.metadata.m16n8k32.row.col.satfinite.s8` from `int_nvvm_mma_sp_ordered_metadata_m16n8k32_row_col_satfinite_s8` | unsafe; scope warp; impure; memory none; convergent true | PTX 8.5 on sm_80+ ([PTX ISA 9.3, 9.7.15.6.3 Multiply-and-Accumulate Instruction: mma.sp](https://docs.nvidia.com/cuda/parallel-thread-execution/#warp-level-matrix-instructions-mma-sp)) | validated on `rust-llvm-23.1.0-16696adc`; expects `mma.sp::ordered_metadata.sync.aligned.m16n8k32.row.col.satfinite.s32.s8.s8.s32 , , , , , ;` (`LLVM version 23.1.0-rust-1.100.0-nightly`, SHA-256 `2e5bc688625ca7d98bca9b5f0f0d14525d2eb59e8a9842964e480df3ffd1f921`) | | `cuda_intrinsics::matrix::mma_sp_ordered_metadata_m16n8k32_s32_s8_u8` | `nvvm.sparse_mma` | LLVM `llvm.nvvm.mma.sp.ordered.metadata.m16n8k32.row.col.s8.u8` from `int_nvvm_mma_sp_ordered_metadata_m16n8k32_row_col_s8_u8` | unsafe; scope warp; impure; memory none; convergent true | PTX 8.5 on sm_80+ ([PTX ISA 9.3, 9.7.15.6.3 Multiply-and-Accumulate Instruction: mma.sp](https://docs.nvidia.com/cuda/parallel-thread-execution/#warp-level-matrix-instructions-mma-sp)) | validated on `rust-llvm-23.1.0-16696adc`; expects `mma.sp::ordered_metadata.sync.aligned.m16n8k32.row.col.s32.s8.u8.s32 , , , , , ;` (`LLVM version 23.1.0-rust-1.100.0-nightly`, SHA-256 `2e5bc688625ca7d98bca9b5f0f0d14525d2eb59e8a9842964e480df3ffd1f921`) | @@ -664,6 +671,7 @@ This table is generated from the resolved catalog. Evidence stages below disting | `cuda_intrinsics::matrix::mma_sp_ordered_metadata_m16n8k64_s32_u8_s8` | `nvvm.sparse_mma` | LLVM `llvm.nvvm.mma.sp.ordered.metadata.m16n8k64.row.col.u8.s8` from `int_nvvm_mma_sp_ordered_metadata_m16n8k64_row_col_u8_s8` | unsafe; scope warp; impure; memory none; convergent true | PTX 8.5 on sm_80+ ([PTX ISA 9.3, 9.7.15.6.3 Multiply-and-Accumulate Instruction: mma.sp](https://docs.nvidia.com/cuda/parallel-thread-execution/#warp-level-matrix-instructions-mma-sp)) | validated on `rust-llvm-23.1.0-16696adc`; expects `mma.sp::ordered_metadata.sync.aligned.m16n8k64.row.col.s32.u8.s8.s32 , , , , , ;` (`LLVM version 23.1.0-rust-1.100.0-nightly`, SHA-256 `2e5bc688625ca7d98bca9b5f0f0d14525d2eb59e8a9842964e480df3ffd1f921`) | | `cuda_intrinsics::matrix::mma_sp_ordered_metadata_m16n8k64_s32_u8_s8_satfinite` | `nvvm.sparse_mma` | LLVM `llvm.nvvm.mma.sp.ordered.metadata.m16n8k64.row.col.satfinite.u8.s8` from `int_nvvm_mma_sp_ordered_metadata_m16n8k64_row_col_satfinite_u8_s8` | unsafe; scope warp; impure; memory none; convergent true | PTX 8.5 on sm_80+ ([PTX ISA 9.3, 9.7.15.6.3 Multiply-and-Accumulate Instruction: mma.sp](https://docs.nvidia.com/cuda/parallel-thread-execution/#warp-level-matrix-instructions-mma-sp)) | validated on `rust-llvm-23.1.0-16696adc`; expects `mma.sp::ordered_metadata.sync.aligned.m16n8k64.row.col.satfinite.s32.u8.s8.s32 , , , , , ;` (`LLVM version 23.1.0-rust-1.100.0-nightly`, SHA-256 `2e5bc688625ca7d98bca9b5f0f0d14525d2eb59e8a9842964e480df3ffd1f921`) | | `cuda_intrinsics::matrix::mma_sp_ordered_metadata_m16n8k64_s32_u8_satfinite` | `nvvm.sparse_mma` | LLVM `llvm.nvvm.mma.sp.ordered.metadata.m16n8k64.row.col.satfinite.u8` from `int_nvvm_mma_sp_ordered_metadata_m16n8k64_row_col_satfinite_u8` | unsafe; scope warp; impure; memory none; convergent true | PTX 8.5 on sm_80+ ([PTX ISA 9.3, 9.7.15.6.3 Multiply-and-Accumulate Instruction: mma.sp](https://docs.nvidia.com/cuda/parallel-thread-execution/#warp-level-matrix-instructions-mma-sp)) | validated on `rust-llvm-23.1.0-16696adc`; expects `mma.sp::ordered_metadata.sync.aligned.m16n8k64.row.col.satfinite.s32.u8.u8.s32 , , , , , ;` (`LLVM version 23.1.0-rust-1.100.0-nightly`, SHA-256 `2e5bc688625ca7d98bca9b5f0f0d14525d2eb59e8a9842964e480df3ffd1f921`) | +| `cuda_intrinsics::matrix::mma_sp_ordered_metadata_m16n8k8_f32_tf32` | `nvvm.sparse_mma` | LLVM `llvm.nvvm.mma.sp.ordered.metadata.m16n8k8.row.col.tf32` from `int_nvvm_mma_sp_ordered_metadata_m16n8k8_row_col_tf32` | unsafe; scope warp; impure; memory none; convergent true | PTX 8.5 on sm_80+ ([PTX ISA 9.3, 9.7.15.6.3 Multiply-and-Accumulate Instruction: mma.sp](https://docs.nvidia.com/cuda/parallel-thread-execution/#warp-level-matrix-instructions-mma-sp)) | executed on `rust-llvm-23.1.0-16696adc`; expects `mma.sp::ordered_metadata.sync.aligned.m16n8k8.row.col.f32.tf32.tf32.f32 , , , , , ;` (`LLVM version 23.1.0-rust-1.100.0-nightly`, SHA-256 `2e5bc688625ca7d98bca9b5f0f0d14525d2eb59e8a9842964e480df3ffd1f921`) | | `cuda_intrinsics::matrix::movmatrix_trans_b16` | `nvvm.movmatrix_trans_b16` | PTX-native `movmatrix.sync.aligned.m8n8.trans.b16` | unsafe; scope warp; impure; memory inaccessible_read_write; convergent true | PTX 7.8 on sm_75+ ([PTX ISA 9.3, 9.7.15.5.17 Warp-level matrix transpose instruction: movmatrix](https://docs.nvidia.com/cuda/parallel-thread-execution/#warp-level-matrix-instructions-movmatrix)) | validated on `rust-llvm-23.1.0-16696adc`; expects `movmatrix.sync.aligned.m8n8.trans.b16 , ;` (`LLVM version 23.1.0-rust-1.100.0-nightly`, SHA-256 `2e5bc688625ca7d98bca9b5f0f0d14525d2eb59e8a9842964e480df3ffd1f921`) | | `cuda_intrinsics::bf16x2::mul_bf16x2` | `nvvm.mul_bf16x2` | PTX-native `mul.rn.bf16x2` | safe; scope thread; pure; memory none; convergent false | PTX 7.8 on sm_90+ ([PTX ISA 9.3, 9.7.4.3 Half Precision Floating Point Instructions: mul](https://docs.nvidia.com/cuda/parallel-thread-execution/#half-precision-floating-point-instructions-mul)) | validated on `rust-llvm-23.1.0-16696adc`; expects `mul.rn.bf16x2 , , ;` (`LLVM version 23.1.0-rust-1.100.0-nightly`, SHA-256 `2e5bc688625ca7d98bca9b5f0f0d14525d2eb59e8a9842964e480df3ffd1f921`) | | `cuda_intrinsics::f16x2::mul_f16x2` | `nvvm.mul_f16x2` | PTX-native `mul.rn.f16x2` | safe; scope thread; pure; memory none; convergent false | PTX 4.2 on sm_70+ ([PTX ISA 9.3, 9.7.4.3 Half Precision Floating Point Instructions: mul](https://docs.nvidia.com/cuda/parallel-thread-execution/#half-precision-floating-point-instructions-mul)) | validated on `rust-llvm-23.1.0-16696adc`; expects `mul.rn.f16x2 , , ;` (`LLVM version 23.1.0-rust-1.100.0-nightly`, SHA-256 `2e5bc688625ca7d98bca9b5f0f0d14525d2eb59e8a9842964e480df3ffd1f921`) | @@ -3343,6 +3351,34 @@ This table is generated from the resolved catalog. Evidence stages below disting - canonical compiler path: `cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0209` - public source path: `cuda_intrinsics::matrix::mma_sp_ordered_metadata_m16n8k128_s32_u4_satfinite` - compatibility compiler path: `cuda_device::wmma::mma_sp_ordered_metadata_m16n8k128_s32_u4_satfinite` +- `mma_sp_ordered_metadata_m16n8k16_f16_f16` (`i1021`) + - canonical compiler path: `cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i1021` + - public source path: `cuda_intrinsics::matrix::mma_sp_ordered_metadata_m16n8k16_f16_f16` + - compatibility compiler path: `cuda_device::wmma::mma_sp_ordered_metadata_m16n8k16_f16_f16` +- `mma_sp_ordered_metadata_m16n8k16_f32_bf16` (`i1020`) + - canonical compiler path: `cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i1020` + - public source path: `cuda_intrinsics::matrix::mma_sp_ordered_metadata_m16n8k16_f32_bf16` + - compatibility compiler path: `cuda_device::wmma::mma_sp_ordered_metadata_m16n8k16_f32_bf16` +- `mma_sp_ordered_metadata_m16n8k16_f32_f16` (`i1022`) + - canonical compiler path: `cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i1022` + - public source path: `cuda_intrinsics::matrix::mma_sp_ordered_metadata_m16n8k16_f32_f16` + - compatibility compiler path: `cuda_device::wmma::mma_sp_ordered_metadata_m16n8k16_f32_f16` +- `mma_sp_ordered_metadata_m16n8k16_f32_tf32` (`i1019`) + - canonical compiler path: `cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i1019` + - public source path: `cuda_intrinsics::matrix::mma_sp_ordered_metadata_m16n8k16_f32_tf32` + - compatibility compiler path: `cuda_device::wmma::mma_sp_ordered_metadata_m16n8k16_f32_tf32` +- `mma_sp_ordered_metadata_m16n8k32_f16_f16` (`i1024`) + - canonical compiler path: `cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i1024` + - public source path: `cuda_intrinsics::matrix::mma_sp_ordered_metadata_m16n8k32_f16_f16` + - compatibility compiler path: `cuda_device::wmma::mma_sp_ordered_metadata_m16n8k32_f16_f16` +- `mma_sp_ordered_metadata_m16n8k32_f32_bf16` (`i1023`) + - canonical compiler path: `cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i1023` + - public source path: `cuda_intrinsics::matrix::mma_sp_ordered_metadata_m16n8k32_f32_bf16` + - compatibility compiler path: `cuda_device::wmma::mma_sp_ordered_metadata_m16n8k32_f32_bf16` +- `mma_sp_ordered_metadata_m16n8k32_f32_f16` (`i1025`) + - canonical compiler path: `cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i1025` + - public source path: `cuda_intrinsics::matrix::mma_sp_ordered_metadata_m16n8k32_f32_f16` + - compatibility compiler path: `cuda_device::wmma::mma_sp_ordered_metadata_m16n8k32_f32_f16` - `mma_sp_ordered_metadata_m16n8k32_s32_s8` (`i0171`) - canonical compiler path: `cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0171` - public source path: `cuda_intrinsics::matrix::mma_sp_ordered_metadata_m16n8k32_s32_s8` @@ -3639,6 +3675,10 @@ This table is generated from the resolved catalog. Evidence stages below disting - canonical compiler path: `cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0185` - public source path: `cuda_intrinsics::matrix::mma_sp_ordered_metadata_m16n8k64_s32_u8_satfinite` - compatibility compiler path: `cuda_device::wmma::mma_sp_ordered_metadata_m16n8k64_s32_u8_satfinite` +- `mma_sp_ordered_metadata_m16n8k8_f32_tf32` (`i1018`) + - canonical compiler path: `cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i1018` + - public source path: `cuda_intrinsics::matrix::mma_sp_ordered_metadata_m16n8k8_f32_tf32` + - compatibility compiler path: `cuda_device::wmma::mma_sp_ordered_metadata_m16n8k8_f32_tf32` - `movmatrix_trans_b16` (`i0305`) - canonical compiler path: `cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0305` - public source path: `cuda_intrinsics::matrix::movmatrix_trans_b16` @@ -5307,6 +5347,13 @@ This table is generated from the resolved catalog. Evidence stages below disting - `mma_sp_ordered_metadata_m16n8k128_s32_u4_s4` takes fragments in C, A, B, metadata, selector order and lowers to one convergent, register-only `mma.sp::ordered_metadata.sync.aligned.m16n8k128.row.col.s32.u4.s4.s32` instruction. Its LLVM source record uses A, B, C, metadata, selector order. The selector must be the compile-time constant `0`. Every non-exited warp lane must execute the same instruction and qualifiers. Every 4-bit metadata group must be `0x4`, `0x8`, `0x9`, `0xc`, `0xd`, or `0xe`; any other value is undefined behavior. Integer overflow wraps. Runtime validation is not executed on a GPU. - `mma_sp_ordered_metadata_m16n8k128_s32_u4_s4_satfinite` takes fragments in C, A, B, metadata, selector order and lowers to one convergent, register-only `mma.sp::ordered_metadata.sync.aligned.m16n8k128.row.col.satfinite.s32.u4.s4.s32` instruction. Its LLVM source record uses A, B, C, metadata, selector order. The selector must be the compile-time constant `0`. Every non-exited warp lane must execute the same instruction and qualifiers. Every 4-bit metadata group must be `0x4`, `0x8`, `0x9`, `0xc`, `0xd`, or `0xe`; any other value is undefined behavior. Integer overflow uses finite saturation. Runtime validation is not executed on a GPU. - `mma_sp_ordered_metadata_m16n8k128_s32_u4_satfinite` takes fragments in C, A, B, metadata, selector order and lowers to one convergent, register-only `mma.sp::ordered_metadata.sync.aligned.m16n8k128.row.col.satfinite.s32.u4.u4.s32` instruction. Its LLVM source record uses A, B, C, metadata, selector order. The selector must be the compile-time constant `0`. Every non-exited warp lane must execute the same instruction and qualifiers. Every 4-bit metadata group must be `0x4`, `0x8`, `0x9`, `0xc`, `0xd`, or `0xe`; any other value is undefined behavior. Integer overflow uses finite saturation. Runtime validation is not executed on a GPU. +- `mma_sp_ordered_metadata_m16n8k16_f16_f16` takes fragments in C, A, B, metadata, selector order and lowers to one convergent, register-only `mma.sp::ordered_metadata.sync.aligned.m16n8k16.row.col.f16.f16.f16.f16` instruction. Its LLVM source record uses A, B, C, metadata, selector order. The selector must be the compile-time constant `0`, `1`, `2`, or `3`. Every non-exited warp lane must execute the same instruction and qualifiers. Every 4-bit metadata group must be `0x4`, `0x8`, `0x9`, `0xc`, `0xd`, or `0xe`; any other value is undefined behavior. Overflow mode is not applicable. Runtime validation is executed on a GPU. +- `mma_sp_ordered_metadata_m16n8k16_f32_bf16` takes fragments in C, A, B, metadata, selector order and lowers to one convergent, register-only `mma.sp::ordered_metadata.sync.aligned.m16n8k16.row.col.f32.bf16.bf16.f32` instruction. Its LLVM source record uses A, B, C, metadata, selector order. The selector must be the compile-time constant `0`, `1`, `2`, or `3`. Every non-exited warp lane must execute the same instruction and qualifiers. Every 4-bit metadata group must be `0x4`, `0x8`, `0x9`, `0xc`, `0xd`, or `0xe`; any other value is undefined behavior. Overflow mode is not applicable. Runtime validation is executed on a GPU. +- `mma_sp_ordered_metadata_m16n8k16_f32_f16` takes fragments in C, A, B, metadata, selector order and lowers to one convergent, register-only `mma.sp::ordered_metadata.sync.aligned.m16n8k16.row.col.f32.f16.f16.f32` instruction. Its LLVM source record uses A, B, C, metadata, selector order. The selector must be the compile-time constant `0`, `1`, `2`, or `3`. Every non-exited warp lane must execute the same instruction and qualifiers. Every 4-bit metadata group must be `0x4`, `0x8`, `0x9`, `0xc`, `0xd`, or `0xe`; any other value is undefined behavior. Overflow mode is not applicable. Runtime validation is executed on a GPU. +- `mma_sp_ordered_metadata_m16n8k16_f32_tf32` takes fragments in C, A, B, metadata, selector order and lowers to one convergent, register-only `mma.sp::ordered_metadata.sync.aligned.m16n8k16.row.col.f32.tf32.tf32.f32` instruction. Its LLVM source record uses A, B, C, metadata, selector order. The selector must be the compile-time constant `0` or `1`. Every non-exited warp lane must execute the same instruction and qualifiers. Every 4-bit metadata group must be `0x4` or `0xe`; any other value is undefined behavior. Overflow mode is not applicable. Runtime validation is executed on a GPU. +- `mma_sp_ordered_metadata_m16n8k32_f16_f16` takes fragments in C, A, B, metadata, selector order and lowers to one convergent, register-only `mma.sp::ordered_metadata.sync.aligned.m16n8k32.row.col.f16.f16.f16.f16` instruction. Its LLVM source record uses A, B, C, metadata, selector order. The selector must be the compile-time constant `0` or `1`. Every non-exited warp lane must execute the same instruction and qualifiers. Every 4-bit metadata group must be `0x4`, `0x8`, `0x9`, `0xc`, `0xd`, or `0xe`; any other value is undefined behavior. Overflow mode is not applicable. Runtime validation is executed on a GPU. +- `mma_sp_ordered_metadata_m16n8k32_f32_bf16` takes fragments in C, A, B, metadata, selector order and lowers to one convergent, register-only `mma.sp::ordered_metadata.sync.aligned.m16n8k32.row.col.f32.bf16.bf16.f32` instruction. Its LLVM source record uses A, B, C, metadata, selector order. The selector must be the compile-time constant `0` or `1`. Every non-exited warp lane must execute the same instruction and qualifiers. Every 4-bit metadata group must be `0x4`, `0x8`, `0x9`, `0xc`, `0xd`, or `0xe`; any other value is undefined behavior. Overflow mode is not applicable. Runtime validation is executed on a GPU. +- `mma_sp_ordered_metadata_m16n8k32_f32_f16` takes fragments in C, A, B, metadata, selector order and lowers to one convergent, register-only `mma.sp::ordered_metadata.sync.aligned.m16n8k32.row.col.f32.f16.f16.f32` instruction. Its LLVM source record uses A, B, C, metadata, selector order. The selector must be the compile-time constant `0` or `1`. Every non-exited warp lane must execute the same instruction and qualifiers. Every 4-bit metadata group must be `0x4`, `0x8`, `0x9`, `0xc`, `0xd`, or `0xe`; any other value is undefined behavior. Overflow mode is not applicable. Runtime validation is executed on a GPU. - `mma_sp_ordered_metadata_m16n8k32_s32_s8` takes fragments in C, A, B, metadata, selector order and lowers to one convergent, register-only `mma.sp::ordered_metadata.sync.aligned.m16n8k32.row.col.s32.s8.s8.s32` instruction. Its LLVM source record uses A, B, C, metadata, selector order. The selector must be the compile-time constant `0` or `1`. Every non-exited warp lane must execute the same instruction and qualifiers. Every 4-bit metadata group must be `0x4`, `0x8`, `0x9`, `0xc`, `0xd`, or `0xe`; any other value is undefined behavior. Integer overflow wraps. Runtime validation is not executed on a GPU. - `mma_sp_ordered_metadata_m16n8k32_s32_s8_satfinite` takes fragments in C, A, B, metadata, selector order and lowers to one convergent, register-only `mma.sp::ordered_metadata.sync.aligned.m16n8k32.row.col.satfinite.s32.s8.s8.s32` instruction. Its LLVM source record uses A, B, C, metadata, selector order. The selector must be the compile-time constant `0` or `1`. Every non-exited warp lane must execute the same instruction and qualifiers. Every 4-bit metadata group must be `0x4`, `0x8`, `0x9`, `0xc`, `0xd`, or `0xe`; any other value is undefined behavior. Integer overflow uses finite saturation. Runtime validation is not executed on a GPU. - `mma_sp_ordered_metadata_m16n8k32_s32_s8_u8` takes fragments in C, A, B, metadata, selector order and lowers to one convergent, register-only `mma.sp::ordered_metadata.sync.aligned.m16n8k32.row.col.s32.s8.u8.s32` instruction. Its LLVM source record uses A, B, C, metadata, selector order. The selector must be the compile-time constant `0` or `1`. Every non-exited warp lane must execute the same instruction and qualifiers. Every 4-bit metadata group must be `0x4`, `0x8`, `0x9`, `0xc`, `0xd`, or `0xe`; any other value is undefined behavior. Integer overflow wraps. Runtime validation is not executed on a GPU. @@ -5381,6 +5428,7 @@ This table is generated from the resolved catalog. Evidence stages below disting - `mma_sp_ordered_metadata_m16n8k64_s32_u8_s8` takes fragments in C, A, B, metadata, selector order and lowers to one convergent, register-only `mma.sp::ordered_metadata.sync.aligned.m16n8k64.row.col.s32.u8.s8.s32` instruction. Its LLVM source record uses A, B, C, metadata, selector order. The selector must be the compile-time constant `0`. Every non-exited warp lane must execute the same instruction and qualifiers. Every 4-bit metadata group must be `0x4`, `0x8`, `0x9`, `0xc`, `0xd`, or `0xe`; any other value is undefined behavior. Integer overflow wraps. Runtime validation is not executed on a GPU. - `mma_sp_ordered_metadata_m16n8k64_s32_u8_s8_satfinite` takes fragments in C, A, B, metadata, selector order and lowers to one convergent, register-only `mma.sp::ordered_metadata.sync.aligned.m16n8k64.row.col.satfinite.s32.u8.s8.s32` instruction. Its LLVM source record uses A, B, C, metadata, selector order. The selector must be the compile-time constant `0`. Every non-exited warp lane must execute the same instruction and qualifiers. Every 4-bit metadata group must be `0x4`, `0x8`, `0x9`, `0xc`, `0xd`, or `0xe`; any other value is undefined behavior. Integer overflow uses finite saturation. Runtime validation is not executed on a GPU. - `mma_sp_ordered_metadata_m16n8k64_s32_u8_satfinite` takes fragments in C, A, B, metadata, selector order and lowers to one convergent, register-only `mma.sp::ordered_metadata.sync.aligned.m16n8k64.row.col.satfinite.s32.u8.u8.s32` instruction. Its LLVM source record uses A, B, C, metadata, selector order. The selector must be the compile-time constant `0`. Every non-exited warp lane must execute the same instruction and qualifiers. Every 4-bit metadata group must be `0x4`, `0x8`, `0x9`, `0xc`, `0xd`, or `0xe`; any other value is undefined behavior. Integer overflow uses finite saturation. Runtime validation is not executed on a GPU. +- `mma_sp_ordered_metadata_m16n8k8_f32_tf32` takes fragments in C, A, B, metadata, selector order and lowers to one convergent, register-only `mma.sp::ordered_metadata.sync.aligned.m16n8k8.row.col.f32.tf32.tf32.f32` instruction. Its LLVM source record uses A, B, C, metadata, selector order. The selector must be the compile-time constant `0`, `1`, `2`, or `3`. Every non-exited warp lane must execute the same instruction and qualifiers. Every 4-bit metadata group must be `0x4` or `0xe`; any other value is undefined behavior. Overflow mode is not applicable. Runtime validation is executed on a GPU. ## Packed-atomic contracts @@ -6218,6 +6266,13 @@ This table is generated from the resolved catalog. Evidence stages below disting - `mma_sp_ordered_metadata_m16n8k128_s32_u4_s4`: properties `ImmArg`, `IntrNoCallback`, `IntrNoMem`, `Range`; result `NoUndef` false; half-open result range `none`; selection records `anonymous_19632`; selection predicates `Subtarget->getPTXVersion() >= 85`, `Subtarget->getSmVersion() >= 80` - `mma_sp_ordered_metadata_m16n8k128_s32_u4_s4_satfinite`: properties `ImmArg`, `IntrNoCallback`, `IntrNoMem`, `Range`; result `NoUndef` false; half-open result range `none`; selection records `anonymous_19699`; selection predicates `Subtarget->getPTXVersion() >= 85`, `Subtarget->getSmVersion() >= 80` - `mma_sp_ordered_metadata_m16n8k128_s32_u4_satfinite`: properties `ImmArg`, `IntrNoCallback`, `IntrNoMem`, `Range`; result `NoUndef` false; half-open result range `none`; selection records `anonymous_19702`; selection predicates `Subtarget->getPTXVersion() >= 85`, `Subtarget->getSmVersion() >= 80` +- `mma_sp_ordered_metadata_m16n8k16_f16_f16`: properties `ImmArg`, `IntrNoCallback`, `IntrNoMem`, `Range`; result `NoUndef` false; half-open result range `none`; selection records `anonymous_19554`; selection predicates `Subtarget->getPTXVersion() >= 85`, `Subtarget->getSmVersion() >= 80` +- `mma_sp_ordered_metadata_m16n8k16_f32_bf16`: properties `ImmArg`, `IntrNoCallback`, `IntrNoMem`, `Range`; result `NoUndef` false; half-open result range `none`; selection records `anonymous_19524`; selection predicates `Subtarget->getPTXVersion() >= 85`, `Subtarget->getSmVersion() >= 80` +- `mma_sp_ordered_metadata_m16n8k16_f32_f16`: properties `ImmArg`, `IntrNoCallback`, `IntrNoMem`, `Range`; result `NoUndef` false; half-open result range `none`; selection records `anonymous_19558`; selection predicates `Subtarget->getPTXVersion() >= 85`, `Subtarget->getSmVersion() >= 80` +- `mma_sp_ordered_metadata_m16n8k16_f32_tf32`: properties `ImmArg`, `IntrNoCallback`, `IntrNoMem`, `Range`; result `NoUndef` false; half-open result range `none`; selection records `anonymous_19546`; selection predicates `Subtarget->getPTXVersion() >= 85`, `Subtarget->getSmVersion() >= 80` +- `mma_sp_ordered_metadata_m16n8k32_f16_f16`: properties `ImmArg`, `IntrNoCallback`, `IntrNoMem`, `Range`; result `NoUndef` false; half-open result range `none`; selection records `anonymous_19566`; selection predicates `Subtarget->getPTXVersion() >= 85`, `Subtarget->getSmVersion() >= 80` +- `mma_sp_ordered_metadata_m16n8k32_f32_bf16`: properties `ImmArg`, `IntrNoCallback`, `IntrNoMem`, `Range`; result `NoUndef` false; half-open result range `none`; selection records `anonymous_19532`; selection predicates `Subtarget->getPTXVersion() >= 85`, `Subtarget->getSmVersion() >= 80` +- `mma_sp_ordered_metadata_m16n8k32_f32_f16`: properties `ImmArg`, `IntrNoCallback`, `IntrNoMem`, `Range`; result `NoUndef` false; half-open result range `none`; selection records `anonymous_19570`; selection predicates `Subtarget->getPTXVersion() >= 85`, `Subtarget->getSmVersion() >= 80` - `mma_sp_ordered_metadata_m16n8k32_s32_s8`: properties `ImmArg`, `IntrNoCallback`, `IntrNoMem`, `Range`; result `NoUndef` false; half-open result range `none`; selection records `anonymous_19644`; selection predicates `Subtarget->getPTXVersion() >= 85`, `Subtarget->getSmVersion() >= 80` - `mma_sp_ordered_metadata_m16n8k32_s32_s8_satfinite`: properties `ImmArg`, `IntrNoCallback`, `IntrNoMem`, `Range`; result `NoUndef` false; half-open result range `none`; selection records `anonymous_19705`; selection predicates `Subtarget->getPTXVersion() >= 85`, `Subtarget->getSmVersion() >= 80` - `mma_sp_ordered_metadata_m16n8k32_s32_s8_u8`: properties `ImmArg`, `IntrNoCallback`, `IntrNoMem`, `Range`; result `NoUndef` false; half-open result range `none`; selection records `anonymous_19649`; selection predicates `Subtarget->getPTXVersion() >= 85`, `Subtarget->getSmVersion() >= 80` @@ -6292,6 +6347,7 @@ This table is generated from the resolved catalog. Evidence stages below disting - `mma_sp_ordered_metadata_m16n8k64_s32_u8_s8`: properties `ImmArg`, `IntrNoCallback`, `IntrNoMem`, `Range`; result `NoUndef` false; half-open result range `none`; selection records `anonymous_19674`; selection predicates `Subtarget->getPTXVersion() >= 85`, `Subtarget->getSmVersion() >= 80` - `mma_sp_ordered_metadata_m16n8k64_s32_u8_s8_satfinite`: properties `ImmArg`, `IntrNoCallback`, `IntrNoMem`, `Range`; result `NoUndef` false; half-open result range `none`; selection records `anonymous_19723`; selection predicates `Subtarget->getPTXVersion() >= 85`, `Subtarget->getSmVersion() >= 80` - `mma_sp_ordered_metadata_m16n8k64_s32_u8_satfinite`: properties `ImmArg`, `IntrNoCallback`, `IntrNoMem`, `Range`; result `NoUndef` false; half-open result range `none`; selection records `anonymous_19726`; selection predicates `Subtarget->getPTXVersion() >= 85`, `Subtarget->getSmVersion() >= 80` +- `mma_sp_ordered_metadata_m16n8k8_f32_tf32`: properties `ImmArg`, `IntrNoCallback`, `IntrNoMem`, `Range`; result `NoUndef` false; half-open result range `none`; selection records `anonymous_19540`; selection predicates `Subtarget->getPTXVersion() >= 85`, `Subtarget->getSmVersion() >= 80` - `movmatrix_trans_b16`: PTX-native source; no LLVM record, symbol, properties, or selection facts. - `mul_bf16x2`: PTX-native source; no LLVM record, symbol, properties, or selection facts. - `mul_f16x2`: PTX-native source; no LLVM record, symbol, properties, or selection facts. @@ -13411,6 +13467,76 @@ This table is generated from the resolved catalog. Evidence stages below disting - `lib_nvvm` uses `inline_ptx` from profile `cuda-13.3-libnvvm-13.3.33` at PTX 8.5 / sm_80+: status `validated` (`CUDA toolkit 13.3; nvcc/libNVVM release V13.3.33`, SHA-256 `b6a5db233133fb0ed693f8cb8aeb1d405254ce0ab10364478985292ec98cfcf0`) - backend codegen on `compute_80, ptx93`: `succeeded` — The production artifacts described by the first record retained saturating u4-by-u4 PTX with selector 0. - device link on `sm_80, ptx93`: `succeeded` — The 27,880-byte production cubin described by the first record retained all eight raw variants and both compatibility-path calls. Tool `/usr/local/cuda-13.3/lib64/libnvJitLink.so.13.3.33` reports `V13.3.33` (SHA-256 `3ba1e744347cd68617b862eccfd98b125482e882b7a6319f42abc9a768513db8`). Artifact `cubin`. +- `mma_sp_ordered_metadata_m16n8k16_f16_f16`: runtime `executed` + - `llvm_nvptx` uses `inline_ptx` from profile `rust-llvm-23.1.0-16696adc` at PTX 8.5 / sm_80+: status `executed` (`LLVM version 23.1.0-rust-1.100.0-nightly`, SHA-256 `2e5bc688625ca7d98bca9b5f0f0d14525d2eb59e8a9842964e480df3ffd1f921`) + - backend codegen on `sm_80, ptx85`: `succeeded` — Pinned LLVM 23.1.0-rust lowered the eight per-intrinsic probe fixtures at sm_80/+ptx85 into 59,900 bytes of PTX across eight files; their concatenation in lexicographic id order has SHA-256 2eaae1b352ef07684549050756eba1ae0eb57318cfa329a9f103f086296f81dc, and every fixture retains one unguarded exact ordered-metadata instruction per selector immediate (24 across the family). Typed declarations of all eight intrinsics fail selection at sm_75/+ptx85 and sm_80/+ptx80, and select at sm_80, sm_86, sm_89, and sm_90/+ptx85 plus sm_100/+ptx86. + - PTX assembly on `sm_80, ptx85`: `succeeded` — CUDA 13.3 ptxas accepted every selector form of all eight ordered-metadata sparse floating variants at PTX 8.5 and sm_80. Tool `/usr/local/cuda-13.3/bin/ptxas` reports `CUDA 13.3 V13.3.33 build cuda_13.3.r13.3/compiler.37862127_0` (SHA-256 `7fdd01a4cf50e30746da98989c9272a907f491e6fd7fecfda14642e4375f88fb`). Artifact `cubin`. + - runtime on `sm_120, ptx85`: `succeeded` — Re-measured with the asymmetric oracle on NVIDIA GeForce RTX 5090 (compute capability 12.0), NVIDIA driver 580.173.02, CUDA toolkit 13.3 V13.3.33. Command: cargo oxide run sparse_mma_ordered_float. Result: exit code 0; SUCCESS: all 8 variants; all 32 lanes and 4 logical accumulators/lane match host GEMM; positionally distinct A/B/C, all six ordered metadata codes (tf32: both), and a nonzero selector per selector domain executed; compute-sanitizer memcheck reports 0 errors. + - `lib_nvvm` uses `inline_ptx` from profile `cuda-13.3-libnvvm-13.3.33` at PTX 8.5 / sm_80+: status `executed` (`CUDA toolkit 13.3; nvcc/libNVVM release V13.3.33`, SHA-256 `b6a5db233133fb0ed693f8cb8aeb1d405254ce0ab10364478985292ec98cfcf0`) + - backend codegen on `compute_80, ptx93`: `succeeded` — The production emit-ltoir route (cargo oxide emit-ltoir sparse_mma_ordered_float --arch sm_80) produced 159,170-byte compute_80 NVVM IR with SHA-256 b338c017795f39f98f756f1d87dc202d1db274479c6619fef9797cb5a95f7613, and CUDA 13.3 libNVVM -gen-lto compiled it to 37,468-byte LTOIR with SHA-256 ac6d8317ba99d9c4332a0ce8777024bc066a7304c6ed4b64c341f4248f6b6100; both artifacts are byte-identical across repeated runs, and the module carries all eight ordered raw calls with one compile-time selector per variant. + - PTX assembly on `sm_80, ptx93`: `succeeded` — nvJitLink rendered the LTOIR as 83,805-byte PTX 9.3 for sm_80 (SHA-256 4a92814b0579bf19a0ab8aa4c8b2114ec2170c87711831b2a17a31d579bf6e87) retaining all eight ordered forms, and CUDA 13.3 ptxas assembled it into a 41,896-byte cubin with SHA-256 26aa4d2f38132bc6a219ec7b22655a77b412176f464fe93d6c8ae81ea1b9e88b. Tool `/usr/local/cuda-13.3/bin/ptxas` reports `CUDA 13.3 V13.3.33 build cuda_13.3.r13.3/compiler.37862127_0` (SHA-256 `7fdd01a4cf50e30746da98989c9272a907f491e6fd7fecfda14642e4375f88fb`). Artifact `cubin`. + - device link on `sm_80, ptx93`: `succeeded` — nvJitLink linked the real libNVVM LTOIR into a 41,896-byte sm_80 cubin with SHA-256 99aa489c3c80ed1414df0c6fe073cff99dcb66a55fd0057729322b54790ac1bf; its cuobjdump SASS contains exactly eight HMMA.SP instructions, one per variant: 1688.F32.TF32, 16816.F32.TF32, 16816.F32.BF16, 16816.F32, 16816.F16, 16832.F32.BF16, 16832.F32, and 16832.F16. Tool `/usr/local/cuda-13.3/lib64/libnvJitLink.so.13.3.33` reports `V13.3.33` (SHA-256 `3ba1e744347cd68617b862eccfd98b125482e882b7a6319f42abc9a768513db8`). Artifact `cubin`. + - runtime on `sm_120, ptx93`: `succeeded` — Executed through the libNVVM route (NVVM IR materialized by libNVVM plus nvJitLink at load time) on NVIDIA GeForce RTX 5090 (compute capability 12.0), NVIDIA driver 580.173.02, CUDA toolkit 13.3 V13.3.33. Command: cargo oxide run sparse_mma_ordered_float --emit-nvvm-ir --arch sm_120. Result: exit code 0; SUCCESS: all 8 variants; all 32 lanes and 4 logical accumulators/lane match host GEMM; positionally distinct A/B/C, all six ordered metadata codes (tf32: both), and a nonzero selector per selector domain executed; compute-sanitizer memcheck reports 0 errors. +- `mma_sp_ordered_metadata_m16n8k16_f32_bf16`: runtime `executed` + - `llvm_nvptx` uses `inline_ptx` from profile `rust-llvm-23.1.0-16696adc` at PTX 8.5 / sm_80+: status `executed` (`LLVM version 23.1.0-rust-1.100.0-nightly`, SHA-256 `2e5bc688625ca7d98bca9b5f0f0d14525d2eb59e8a9842964e480df3ffd1f921`) + - backend codegen on `sm_80, ptx85`: `succeeded` — Pinned LLVM 23.1.0-rust lowered the eight per-intrinsic probe fixtures at sm_80/+ptx85 into 59,900 bytes of PTX across eight files; their concatenation in lexicographic id order has SHA-256 2eaae1b352ef07684549050756eba1ae0eb57318cfa329a9f103f086296f81dc, and every fixture retains one unguarded exact ordered-metadata instruction per selector immediate (24 across the family). Typed declarations of all eight intrinsics fail selection at sm_75/+ptx85 and sm_80/+ptx80, and select at sm_80, sm_86, sm_89, and sm_90/+ptx85 plus sm_100/+ptx86. + - PTX assembly on `sm_80, ptx85`: `succeeded` — CUDA 13.3 ptxas accepted every selector form of all eight ordered-metadata sparse floating variants at PTX 8.5 and sm_80. Tool `/usr/local/cuda-13.3/bin/ptxas` reports `CUDA 13.3 V13.3.33 build cuda_13.3.r13.3/compiler.37862127_0` (SHA-256 `7fdd01a4cf50e30746da98989c9272a907f491e6fd7fecfda14642e4375f88fb`). Artifact `cubin`. + - runtime on `sm_120, ptx85`: `succeeded` — Re-measured with the asymmetric oracle on NVIDIA GeForce RTX 5090 (compute capability 12.0), NVIDIA driver 580.173.02, CUDA toolkit 13.3 V13.3.33. Command: cargo oxide run sparse_mma_ordered_float. Result: exit code 0; SUCCESS: all 8 variants; all 32 lanes and 4 logical accumulators/lane match host GEMM; positionally distinct A/B/C, all six ordered metadata codes (tf32: both), and a nonzero selector per selector domain executed; compute-sanitizer memcheck reports 0 errors. + - `lib_nvvm` uses `inline_ptx` from profile `cuda-13.3-libnvvm-13.3.33` at PTX 8.5 / sm_80+: status `executed` (`CUDA toolkit 13.3; nvcc/libNVVM release V13.3.33`, SHA-256 `b6a5db233133fb0ed693f8cb8aeb1d405254ce0ab10364478985292ec98cfcf0`) + - backend codegen on `compute_80, ptx93`: `succeeded` — The production emit-ltoir route (cargo oxide emit-ltoir sparse_mma_ordered_float --arch sm_80) produced 159,170-byte compute_80 NVVM IR with SHA-256 b338c017795f39f98f756f1d87dc202d1db274479c6619fef9797cb5a95f7613, and CUDA 13.3 libNVVM -gen-lto compiled it to 37,468-byte LTOIR with SHA-256 ac6d8317ba99d9c4332a0ce8777024bc066a7304c6ed4b64c341f4248f6b6100; both artifacts are byte-identical across repeated runs, and the module carries all eight ordered raw calls with one compile-time selector per variant. + - PTX assembly on `sm_80, ptx93`: `succeeded` — nvJitLink rendered the LTOIR as 83,805-byte PTX 9.3 for sm_80 (SHA-256 4a92814b0579bf19a0ab8aa4c8b2114ec2170c87711831b2a17a31d579bf6e87) retaining all eight ordered forms, and CUDA 13.3 ptxas assembled it into a 41,896-byte cubin with SHA-256 26aa4d2f38132bc6a219ec7b22655a77b412176f464fe93d6c8ae81ea1b9e88b. Tool `/usr/local/cuda-13.3/bin/ptxas` reports `CUDA 13.3 V13.3.33 build cuda_13.3.r13.3/compiler.37862127_0` (SHA-256 `7fdd01a4cf50e30746da98989c9272a907f491e6fd7fecfda14642e4375f88fb`). Artifact `cubin`. + - device link on `sm_80, ptx93`: `succeeded` — nvJitLink linked the real libNVVM LTOIR into a 41,896-byte sm_80 cubin with SHA-256 99aa489c3c80ed1414df0c6fe073cff99dcb66a55fd0057729322b54790ac1bf; its cuobjdump SASS contains exactly eight HMMA.SP instructions, one per variant: 1688.F32.TF32, 16816.F32.TF32, 16816.F32.BF16, 16816.F32, 16816.F16, 16832.F32.BF16, 16832.F32, and 16832.F16. Tool `/usr/local/cuda-13.3/lib64/libnvJitLink.so.13.3.33` reports `V13.3.33` (SHA-256 `3ba1e744347cd68617b862eccfd98b125482e882b7a6319f42abc9a768513db8`). Artifact `cubin`. + - runtime on `sm_120, ptx93`: `succeeded` — Executed through the libNVVM route (NVVM IR materialized by libNVVM plus nvJitLink at load time) on NVIDIA GeForce RTX 5090 (compute capability 12.0), NVIDIA driver 580.173.02, CUDA toolkit 13.3 V13.3.33. Command: cargo oxide run sparse_mma_ordered_float --emit-nvvm-ir --arch sm_120. Result: exit code 0; SUCCESS: all 8 variants; all 32 lanes and 4 logical accumulators/lane match host GEMM; positionally distinct A/B/C, all six ordered metadata codes (tf32: both), and a nonzero selector per selector domain executed; compute-sanitizer memcheck reports 0 errors. +- `mma_sp_ordered_metadata_m16n8k16_f32_f16`: runtime `executed` + - `llvm_nvptx` uses `inline_ptx` from profile `rust-llvm-23.1.0-16696adc` at PTX 8.5 / sm_80+: status `executed` (`LLVM version 23.1.0-rust-1.100.0-nightly`, SHA-256 `2e5bc688625ca7d98bca9b5f0f0d14525d2eb59e8a9842964e480df3ffd1f921`) + - backend codegen on `sm_80, ptx85`: `succeeded` — Pinned LLVM 23.1.0-rust lowered the eight per-intrinsic probe fixtures at sm_80/+ptx85 into 59,900 bytes of PTX across eight files; their concatenation in lexicographic id order has SHA-256 2eaae1b352ef07684549050756eba1ae0eb57318cfa329a9f103f086296f81dc, and every fixture retains one unguarded exact ordered-metadata instruction per selector immediate (24 across the family). Typed declarations of all eight intrinsics fail selection at sm_75/+ptx85 and sm_80/+ptx80, and select at sm_80, sm_86, sm_89, and sm_90/+ptx85 plus sm_100/+ptx86. + - PTX assembly on `sm_80, ptx85`: `succeeded` — CUDA 13.3 ptxas accepted every selector form of all eight ordered-metadata sparse floating variants at PTX 8.5 and sm_80. Tool `/usr/local/cuda-13.3/bin/ptxas` reports `CUDA 13.3 V13.3.33 build cuda_13.3.r13.3/compiler.37862127_0` (SHA-256 `7fdd01a4cf50e30746da98989c9272a907f491e6fd7fecfda14642e4375f88fb`). Artifact `cubin`. + - runtime on `sm_120, ptx85`: `succeeded` — Re-measured with the asymmetric oracle on NVIDIA GeForce RTX 5090 (compute capability 12.0), NVIDIA driver 580.173.02, CUDA toolkit 13.3 V13.3.33. Command: cargo oxide run sparse_mma_ordered_float. Result: exit code 0; SUCCESS: all 8 variants; all 32 lanes and 4 logical accumulators/lane match host GEMM; positionally distinct A/B/C, all six ordered metadata codes (tf32: both), and a nonzero selector per selector domain executed; compute-sanitizer memcheck reports 0 errors. + - `lib_nvvm` uses `inline_ptx` from profile `cuda-13.3-libnvvm-13.3.33` at PTX 8.5 / sm_80+: status `executed` (`CUDA toolkit 13.3; nvcc/libNVVM release V13.3.33`, SHA-256 `b6a5db233133fb0ed693f8cb8aeb1d405254ce0ab10364478985292ec98cfcf0`) + - backend codegen on `compute_80, ptx93`: `succeeded` — The production emit-ltoir route (cargo oxide emit-ltoir sparse_mma_ordered_float --arch sm_80) produced 159,170-byte compute_80 NVVM IR with SHA-256 b338c017795f39f98f756f1d87dc202d1db274479c6619fef9797cb5a95f7613, and CUDA 13.3 libNVVM -gen-lto compiled it to 37,468-byte LTOIR with SHA-256 ac6d8317ba99d9c4332a0ce8777024bc066a7304c6ed4b64c341f4248f6b6100; both artifacts are byte-identical across repeated runs, and the module carries all eight ordered raw calls with one compile-time selector per variant. + - PTX assembly on `sm_80, ptx93`: `succeeded` — nvJitLink rendered the LTOIR as 83,805-byte PTX 9.3 for sm_80 (SHA-256 4a92814b0579bf19a0ab8aa4c8b2114ec2170c87711831b2a17a31d579bf6e87) retaining all eight ordered forms, and CUDA 13.3 ptxas assembled it into a 41,896-byte cubin with SHA-256 26aa4d2f38132bc6a219ec7b22655a77b412176f464fe93d6c8ae81ea1b9e88b. Tool `/usr/local/cuda-13.3/bin/ptxas` reports `CUDA 13.3 V13.3.33 build cuda_13.3.r13.3/compiler.37862127_0` (SHA-256 `7fdd01a4cf50e30746da98989c9272a907f491e6fd7fecfda14642e4375f88fb`). Artifact `cubin`. + - device link on `sm_80, ptx93`: `succeeded` — nvJitLink linked the real libNVVM LTOIR into a 41,896-byte sm_80 cubin with SHA-256 99aa489c3c80ed1414df0c6fe073cff99dcb66a55fd0057729322b54790ac1bf; its cuobjdump SASS contains exactly eight HMMA.SP instructions, one per variant: 1688.F32.TF32, 16816.F32.TF32, 16816.F32.BF16, 16816.F32, 16816.F16, 16832.F32.BF16, 16832.F32, and 16832.F16. Tool `/usr/local/cuda-13.3/lib64/libnvJitLink.so.13.3.33` reports `V13.3.33` (SHA-256 `3ba1e744347cd68617b862eccfd98b125482e882b7a6319f42abc9a768513db8`). Artifact `cubin`. + - runtime on `sm_120, ptx93`: `succeeded` — Executed through the libNVVM route (NVVM IR materialized by libNVVM plus nvJitLink at load time) on NVIDIA GeForce RTX 5090 (compute capability 12.0), NVIDIA driver 580.173.02, CUDA toolkit 13.3 V13.3.33. Command: cargo oxide run sparse_mma_ordered_float --emit-nvvm-ir --arch sm_120. Result: exit code 0; SUCCESS: all 8 variants; all 32 lanes and 4 logical accumulators/lane match host GEMM; positionally distinct A/B/C, all six ordered metadata codes (tf32: both), and a nonzero selector per selector domain executed; compute-sanitizer memcheck reports 0 errors. +- `mma_sp_ordered_metadata_m16n8k16_f32_tf32`: runtime `executed` + - `llvm_nvptx` uses `inline_ptx` from profile `rust-llvm-23.1.0-16696adc` at PTX 8.5 / sm_80+: status `executed` (`LLVM version 23.1.0-rust-1.100.0-nightly`, SHA-256 `2e5bc688625ca7d98bca9b5f0f0d14525d2eb59e8a9842964e480df3ffd1f921`) + - backend codegen on `sm_80, ptx85`: `succeeded` — Pinned LLVM 23.1.0-rust lowered the eight per-intrinsic probe fixtures at sm_80/+ptx85 into 59,900 bytes of PTX across eight files; their concatenation in lexicographic id order has SHA-256 2eaae1b352ef07684549050756eba1ae0eb57318cfa329a9f103f086296f81dc, and every fixture retains one unguarded exact ordered-metadata instruction per selector immediate (24 across the family). Typed declarations of all eight intrinsics fail selection at sm_75/+ptx85 and sm_80/+ptx80, and select at sm_80, sm_86, sm_89, and sm_90/+ptx85 plus sm_100/+ptx86. + - PTX assembly on `sm_80, ptx85`: `succeeded` — CUDA 13.3 ptxas accepted every selector form of all eight ordered-metadata sparse floating variants at PTX 8.5 and sm_80. Tool `/usr/local/cuda-13.3/bin/ptxas` reports `CUDA 13.3 V13.3.33 build cuda_13.3.r13.3/compiler.37862127_0` (SHA-256 `7fdd01a4cf50e30746da98989c9272a907f491e6fd7fecfda14642e4375f88fb`). Artifact `cubin`. + - runtime on `sm_120, ptx85`: `succeeded` — Re-measured with the asymmetric oracle on NVIDIA GeForce RTX 5090 (compute capability 12.0), NVIDIA driver 580.173.02, CUDA toolkit 13.3 V13.3.33. Command: cargo oxide run sparse_mma_ordered_float. Result: exit code 0; SUCCESS: all 8 variants; all 32 lanes and 4 logical accumulators/lane match host GEMM; positionally distinct A/B/C, all six ordered metadata codes (tf32: both), and a nonzero selector per selector domain executed; compute-sanitizer memcheck reports 0 errors. + - `lib_nvvm` uses `inline_ptx` from profile `cuda-13.3-libnvvm-13.3.33` at PTX 8.5 / sm_80+: status `executed` (`CUDA toolkit 13.3; nvcc/libNVVM release V13.3.33`, SHA-256 `b6a5db233133fb0ed693f8cb8aeb1d405254ce0ab10364478985292ec98cfcf0`) + - backend codegen on `compute_80, ptx93`: `succeeded` — The production emit-ltoir route (cargo oxide emit-ltoir sparse_mma_ordered_float --arch sm_80) produced 159,170-byte compute_80 NVVM IR with SHA-256 b338c017795f39f98f756f1d87dc202d1db274479c6619fef9797cb5a95f7613, and CUDA 13.3 libNVVM -gen-lto compiled it to 37,468-byte LTOIR with SHA-256 ac6d8317ba99d9c4332a0ce8777024bc066a7304c6ed4b64c341f4248f6b6100; both artifacts are byte-identical across repeated runs, and the module carries all eight ordered raw calls with one compile-time selector per variant. + - PTX assembly on `sm_80, ptx93`: `succeeded` — nvJitLink rendered the LTOIR as 83,805-byte PTX 9.3 for sm_80 (SHA-256 4a92814b0579bf19a0ab8aa4c8b2114ec2170c87711831b2a17a31d579bf6e87) retaining all eight ordered forms, and CUDA 13.3 ptxas assembled it into a 41,896-byte cubin with SHA-256 26aa4d2f38132bc6a219ec7b22655a77b412176f464fe93d6c8ae81ea1b9e88b. Tool `/usr/local/cuda-13.3/bin/ptxas` reports `CUDA 13.3 V13.3.33 build cuda_13.3.r13.3/compiler.37862127_0` (SHA-256 `7fdd01a4cf50e30746da98989c9272a907f491e6fd7fecfda14642e4375f88fb`). Artifact `cubin`. + - device link on `sm_80, ptx93`: `succeeded` — nvJitLink linked the real libNVVM LTOIR into a 41,896-byte sm_80 cubin with SHA-256 99aa489c3c80ed1414df0c6fe073cff99dcb66a55fd0057729322b54790ac1bf; its cuobjdump SASS contains exactly eight HMMA.SP instructions, one per variant: 1688.F32.TF32, 16816.F32.TF32, 16816.F32.BF16, 16816.F32, 16816.F16, 16832.F32.BF16, 16832.F32, and 16832.F16. Tool `/usr/local/cuda-13.3/lib64/libnvJitLink.so.13.3.33` reports `V13.3.33` (SHA-256 `3ba1e744347cd68617b862eccfd98b125482e882b7a6319f42abc9a768513db8`). Artifact `cubin`. + - runtime on `sm_120, ptx93`: `succeeded` — Executed through the libNVVM route (NVVM IR materialized by libNVVM plus nvJitLink at load time) on NVIDIA GeForce RTX 5090 (compute capability 12.0), NVIDIA driver 580.173.02, CUDA toolkit 13.3 V13.3.33. Command: cargo oxide run sparse_mma_ordered_float --emit-nvvm-ir --arch sm_120. Result: exit code 0; SUCCESS: all 8 variants; all 32 lanes and 4 logical accumulators/lane match host GEMM; positionally distinct A/B/C, all six ordered metadata codes (tf32: both), and a nonzero selector per selector domain executed; compute-sanitizer memcheck reports 0 errors. +- `mma_sp_ordered_metadata_m16n8k32_f16_f16`: runtime `executed` + - `llvm_nvptx` uses `inline_ptx` from profile `rust-llvm-23.1.0-16696adc` at PTX 8.5 / sm_80+: status `executed` (`LLVM version 23.1.0-rust-1.100.0-nightly`, SHA-256 `2e5bc688625ca7d98bca9b5f0f0d14525d2eb59e8a9842964e480df3ffd1f921`) + - backend codegen on `sm_80, ptx85`: `succeeded` — Pinned LLVM 23.1.0-rust lowered the eight per-intrinsic probe fixtures at sm_80/+ptx85 into 59,900 bytes of PTX across eight files; their concatenation in lexicographic id order has SHA-256 2eaae1b352ef07684549050756eba1ae0eb57318cfa329a9f103f086296f81dc, and every fixture retains one unguarded exact ordered-metadata instruction per selector immediate (24 across the family). Typed declarations of all eight intrinsics fail selection at sm_75/+ptx85 and sm_80/+ptx80, and select at sm_80, sm_86, sm_89, and sm_90/+ptx85 plus sm_100/+ptx86. + - PTX assembly on `sm_80, ptx85`: `succeeded` — CUDA 13.3 ptxas accepted every selector form of all eight ordered-metadata sparse floating variants at PTX 8.5 and sm_80. Tool `/usr/local/cuda-13.3/bin/ptxas` reports `CUDA 13.3 V13.3.33 build cuda_13.3.r13.3/compiler.37862127_0` (SHA-256 `7fdd01a4cf50e30746da98989c9272a907f491e6fd7fecfda14642e4375f88fb`). Artifact `cubin`. + - runtime on `sm_120, ptx85`: `succeeded` — Re-measured with the asymmetric oracle on NVIDIA GeForce RTX 5090 (compute capability 12.0), NVIDIA driver 580.173.02, CUDA toolkit 13.3 V13.3.33. Command: cargo oxide run sparse_mma_ordered_float. Result: exit code 0; SUCCESS: all 8 variants; all 32 lanes and 4 logical accumulators/lane match host GEMM; positionally distinct A/B/C, all six ordered metadata codes (tf32: both), and a nonzero selector per selector domain executed; compute-sanitizer memcheck reports 0 errors. + - `lib_nvvm` uses `inline_ptx` from profile `cuda-13.3-libnvvm-13.3.33` at PTX 8.5 / sm_80+: status `executed` (`CUDA toolkit 13.3; nvcc/libNVVM release V13.3.33`, SHA-256 `b6a5db233133fb0ed693f8cb8aeb1d405254ce0ab10364478985292ec98cfcf0`) + - backend codegen on `compute_80, ptx93`: `succeeded` — The production emit-ltoir route (cargo oxide emit-ltoir sparse_mma_ordered_float --arch sm_80) produced 159,170-byte compute_80 NVVM IR with SHA-256 b338c017795f39f98f756f1d87dc202d1db274479c6619fef9797cb5a95f7613, and CUDA 13.3 libNVVM -gen-lto compiled it to 37,468-byte LTOIR with SHA-256 ac6d8317ba99d9c4332a0ce8777024bc066a7304c6ed4b64c341f4248f6b6100; both artifacts are byte-identical across repeated runs, and the module carries all eight ordered raw calls with one compile-time selector per variant. + - PTX assembly on `sm_80, ptx93`: `succeeded` — nvJitLink rendered the LTOIR as 83,805-byte PTX 9.3 for sm_80 (SHA-256 4a92814b0579bf19a0ab8aa4c8b2114ec2170c87711831b2a17a31d579bf6e87) retaining all eight ordered forms, and CUDA 13.3 ptxas assembled it into a 41,896-byte cubin with SHA-256 26aa4d2f38132bc6a219ec7b22655a77b412176f464fe93d6c8ae81ea1b9e88b. Tool `/usr/local/cuda-13.3/bin/ptxas` reports `CUDA 13.3 V13.3.33 build cuda_13.3.r13.3/compiler.37862127_0` (SHA-256 `7fdd01a4cf50e30746da98989c9272a907f491e6fd7fecfda14642e4375f88fb`). Artifact `cubin`. + - device link on `sm_80, ptx93`: `succeeded` — nvJitLink linked the real libNVVM LTOIR into a 41,896-byte sm_80 cubin with SHA-256 99aa489c3c80ed1414df0c6fe073cff99dcb66a55fd0057729322b54790ac1bf; its cuobjdump SASS contains exactly eight HMMA.SP instructions, one per variant: 1688.F32.TF32, 16816.F32.TF32, 16816.F32.BF16, 16816.F32, 16816.F16, 16832.F32.BF16, 16832.F32, and 16832.F16. Tool `/usr/local/cuda-13.3/lib64/libnvJitLink.so.13.3.33` reports `V13.3.33` (SHA-256 `3ba1e744347cd68617b862eccfd98b125482e882b7a6319f42abc9a768513db8`). Artifact `cubin`. + - runtime on `sm_120, ptx93`: `succeeded` — Executed through the libNVVM route (NVVM IR materialized by libNVVM plus nvJitLink at load time) on NVIDIA GeForce RTX 5090 (compute capability 12.0), NVIDIA driver 580.173.02, CUDA toolkit 13.3 V13.3.33. Command: cargo oxide run sparse_mma_ordered_float --emit-nvvm-ir --arch sm_120. Result: exit code 0; SUCCESS: all 8 variants; all 32 lanes and 4 logical accumulators/lane match host GEMM; positionally distinct A/B/C, all six ordered metadata codes (tf32: both), and a nonzero selector per selector domain executed; compute-sanitizer memcheck reports 0 errors. +- `mma_sp_ordered_metadata_m16n8k32_f32_bf16`: runtime `executed` + - `llvm_nvptx` uses `inline_ptx` from profile `rust-llvm-23.1.0-16696adc` at PTX 8.5 / sm_80+: status `executed` (`LLVM version 23.1.0-rust-1.100.0-nightly`, SHA-256 `2e5bc688625ca7d98bca9b5f0f0d14525d2eb59e8a9842964e480df3ffd1f921`) + - backend codegen on `sm_80, ptx85`: `succeeded` — Pinned LLVM 23.1.0-rust lowered the eight per-intrinsic probe fixtures at sm_80/+ptx85 into 59,900 bytes of PTX across eight files; their concatenation in lexicographic id order has SHA-256 2eaae1b352ef07684549050756eba1ae0eb57318cfa329a9f103f086296f81dc, and every fixture retains one unguarded exact ordered-metadata instruction per selector immediate (24 across the family). Typed declarations of all eight intrinsics fail selection at sm_75/+ptx85 and sm_80/+ptx80, and select at sm_80, sm_86, sm_89, and sm_90/+ptx85 plus sm_100/+ptx86. + - PTX assembly on `sm_80, ptx85`: `succeeded` — CUDA 13.3 ptxas accepted every selector form of all eight ordered-metadata sparse floating variants at PTX 8.5 and sm_80. Tool `/usr/local/cuda-13.3/bin/ptxas` reports `CUDA 13.3 V13.3.33 build cuda_13.3.r13.3/compiler.37862127_0` (SHA-256 `7fdd01a4cf50e30746da98989c9272a907f491e6fd7fecfda14642e4375f88fb`). Artifact `cubin`. + - runtime on `sm_120, ptx85`: `succeeded` — Re-measured with the asymmetric oracle on NVIDIA GeForce RTX 5090 (compute capability 12.0), NVIDIA driver 580.173.02, CUDA toolkit 13.3 V13.3.33. Command: cargo oxide run sparse_mma_ordered_float. Result: exit code 0; SUCCESS: all 8 variants; all 32 lanes and 4 logical accumulators/lane match host GEMM; positionally distinct A/B/C, all six ordered metadata codes (tf32: both), and a nonzero selector per selector domain executed; compute-sanitizer memcheck reports 0 errors. + - `lib_nvvm` uses `inline_ptx` from profile `cuda-13.3-libnvvm-13.3.33` at PTX 8.5 / sm_80+: status `executed` (`CUDA toolkit 13.3; nvcc/libNVVM release V13.3.33`, SHA-256 `b6a5db233133fb0ed693f8cb8aeb1d405254ce0ab10364478985292ec98cfcf0`) + - backend codegen on `compute_80, ptx93`: `succeeded` — The production emit-ltoir route (cargo oxide emit-ltoir sparse_mma_ordered_float --arch sm_80) produced 159,170-byte compute_80 NVVM IR with SHA-256 b338c017795f39f98f756f1d87dc202d1db274479c6619fef9797cb5a95f7613, and CUDA 13.3 libNVVM -gen-lto compiled it to 37,468-byte LTOIR with SHA-256 ac6d8317ba99d9c4332a0ce8777024bc066a7304c6ed4b64c341f4248f6b6100; both artifacts are byte-identical across repeated runs, and the module carries all eight ordered raw calls with one compile-time selector per variant. + - PTX assembly on `sm_80, ptx93`: `succeeded` — nvJitLink rendered the LTOIR as 83,805-byte PTX 9.3 for sm_80 (SHA-256 4a92814b0579bf19a0ab8aa4c8b2114ec2170c87711831b2a17a31d579bf6e87) retaining all eight ordered forms, and CUDA 13.3 ptxas assembled it into a 41,896-byte cubin with SHA-256 26aa4d2f38132bc6a219ec7b22655a77b412176f464fe93d6c8ae81ea1b9e88b. Tool `/usr/local/cuda-13.3/bin/ptxas` reports `CUDA 13.3 V13.3.33 build cuda_13.3.r13.3/compiler.37862127_0` (SHA-256 `7fdd01a4cf50e30746da98989c9272a907f491e6fd7fecfda14642e4375f88fb`). Artifact `cubin`. + - device link on `sm_80, ptx93`: `succeeded` — nvJitLink linked the real libNVVM LTOIR into a 41,896-byte sm_80 cubin with SHA-256 99aa489c3c80ed1414df0c6fe073cff99dcb66a55fd0057729322b54790ac1bf; its cuobjdump SASS contains exactly eight HMMA.SP instructions, one per variant: 1688.F32.TF32, 16816.F32.TF32, 16816.F32.BF16, 16816.F32, 16816.F16, 16832.F32.BF16, 16832.F32, and 16832.F16. Tool `/usr/local/cuda-13.3/lib64/libnvJitLink.so.13.3.33` reports `V13.3.33` (SHA-256 `3ba1e744347cd68617b862eccfd98b125482e882b7a6319f42abc9a768513db8`). Artifact `cubin`. + - runtime on `sm_120, ptx93`: `succeeded` — Executed through the libNVVM route (NVVM IR materialized by libNVVM plus nvJitLink at load time) on NVIDIA GeForce RTX 5090 (compute capability 12.0), NVIDIA driver 580.173.02, CUDA toolkit 13.3 V13.3.33. Command: cargo oxide run sparse_mma_ordered_float --emit-nvvm-ir --arch sm_120. Result: exit code 0; SUCCESS: all 8 variants; all 32 lanes and 4 logical accumulators/lane match host GEMM; positionally distinct A/B/C, all six ordered metadata codes (tf32: both), and a nonzero selector per selector domain executed; compute-sanitizer memcheck reports 0 errors. +- `mma_sp_ordered_metadata_m16n8k32_f32_f16`: runtime `executed` + - `llvm_nvptx` uses `inline_ptx` from profile `rust-llvm-23.1.0-16696adc` at PTX 8.5 / sm_80+: status `executed` (`LLVM version 23.1.0-rust-1.100.0-nightly`, SHA-256 `2e5bc688625ca7d98bca9b5f0f0d14525d2eb59e8a9842964e480df3ffd1f921`) + - backend codegen on `sm_80, ptx85`: `succeeded` — Pinned LLVM 23.1.0-rust lowered the eight per-intrinsic probe fixtures at sm_80/+ptx85 into 59,900 bytes of PTX across eight files; their concatenation in lexicographic id order has SHA-256 2eaae1b352ef07684549050756eba1ae0eb57318cfa329a9f103f086296f81dc, and every fixture retains one unguarded exact ordered-metadata instruction per selector immediate (24 across the family). Typed declarations of all eight intrinsics fail selection at sm_75/+ptx85 and sm_80/+ptx80, and select at sm_80, sm_86, sm_89, and sm_90/+ptx85 plus sm_100/+ptx86. + - PTX assembly on `sm_80, ptx85`: `succeeded` — CUDA 13.3 ptxas accepted every selector form of all eight ordered-metadata sparse floating variants at PTX 8.5 and sm_80. Tool `/usr/local/cuda-13.3/bin/ptxas` reports `CUDA 13.3 V13.3.33 build cuda_13.3.r13.3/compiler.37862127_0` (SHA-256 `7fdd01a4cf50e30746da98989c9272a907f491e6fd7fecfda14642e4375f88fb`). Artifact `cubin`. + - runtime on `sm_120, ptx85`: `succeeded` — Re-measured with the asymmetric oracle on NVIDIA GeForce RTX 5090 (compute capability 12.0), NVIDIA driver 580.173.02, CUDA toolkit 13.3 V13.3.33. Command: cargo oxide run sparse_mma_ordered_float. Result: exit code 0; SUCCESS: all 8 variants; all 32 lanes and 4 logical accumulators/lane match host GEMM; positionally distinct A/B/C, all six ordered metadata codes (tf32: both), and a nonzero selector per selector domain executed; compute-sanitizer memcheck reports 0 errors. + - `lib_nvvm` uses `inline_ptx` from profile `cuda-13.3-libnvvm-13.3.33` at PTX 8.5 / sm_80+: status `executed` (`CUDA toolkit 13.3; nvcc/libNVVM release V13.3.33`, SHA-256 `b6a5db233133fb0ed693f8cb8aeb1d405254ce0ab10364478985292ec98cfcf0`) + - backend codegen on `compute_80, ptx93`: `succeeded` — The production emit-ltoir route (cargo oxide emit-ltoir sparse_mma_ordered_float --arch sm_80) produced 159,170-byte compute_80 NVVM IR with SHA-256 b338c017795f39f98f756f1d87dc202d1db274479c6619fef9797cb5a95f7613, and CUDA 13.3 libNVVM -gen-lto compiled it to 37,468-byte LTOIR with SHA-256 ac6d8317ba99d9c4332a0ce8777024bc066a7304c6ed4b64c341f4248f6b6100; both artifacts are byte-identical across repeated runs, and the module carries all eight ordered raw calls with one compile-time selector per variant. + - PTX assembly on `sm_80, ptx93`: `succeeded` — nvJitLink rendered the LTOIR as 83,805-byte PTX 9.3 for sm_80 (SHA-256 4a92814b0579bf19a0ab8aa4c8b2114ec2170c87711831b2a17a31d579bf6e87) retaining all eight ordered forms, and CUDA 13.3 ptxas assembled it into a 41,896-byte cubin with SHA-256 26aa4d2f38132bc6a219ec7b22655a77b412176f464fe93d6c8ae81ea1b9e88b. Tool `/usr/local/cuda-13.3/bin/ptxas` reports `CUDA 13.3 V13.3.33 build cuda_13.3.r13.3/compiler.37862127_0` (SHA-256 `7fdd01a4cf50e30746da98989c9272a907f491e6fd7fecfda14642e4375f88fb`). Artifact `cubin`. + - device link on `sm_80, ptx93`: `succeeded` — nvJitLink linked the real libNVVM LTOIR into a 41,896-byte sm_80 cubin with SHA-256 99aa489c3c80ed1414df0c6fe073cff99dcb66a55fd0057729322b54790ac1bf; its cuobjdump SASS contains exactly eight HMMA.SP instructions, one per variant: 1688.F32.TF32, 16816.F32.TF32, 16816.F32.BF16, 16816.F32, 16816.F16, 16832.F32.BF16, 16832.F32, and 16832.F16. Tool `/usr/local/cuda-13.3/lib64/libnvJitLink.so.13.3.33` reports `V13.3.33` (SHA-256 `3ba1e744347cd68617b862eccfd98b125482e882b7a6319f42abc9a768513db8`). Artifact `cubin`. + - runtime on `sm_120, ptx93`: `succeeded` — Executed through the libNVVM route (NVVM IR materialized by libNVVM plus nvJitLink at load time) on NVIDIA GeForce RTX 5090 (compute capability 12.0), NVIDIA driver 580.173.02, CUDA toolkit 13.3 V13.3.33. Command: cargo oxide run sparse_mma_ordered_float --emit-nvvm-ir --arch sm_120. Result: exit code 0; SUCCESS: all 8 variants; all 32 lanes and 4 logical accumulators/lane match host GEMM; positionally distinct A/B/C, all six ordered metadata codes (tf32: both), and a nonzero selector per selector domain executed; compute-sanitizer memcheck reports 0 errors. - `mma_sp_ordered_metadata_m16n8k32_s32_s8`: runtime `unexecuted` - `llvm_nvptx` uses `inline_ptx` from profile `rust-llvm-23.1.0-16696adc` at PTX 8.5 / sm_80+: status `validated` (`LLVM version 23.1.0-rust-1.100.0-nightly`, SHA-256 `2e5bc688625ca7d98bca9b5f0f0d14525d2eb59e8a9842964e480df3ffd1f921`) - backend codegen on `sm_80, ptx85`: `succeeded` — The selected LLVM 22 probe retained exactly two unguarded ordered-metadata instructions, one for each selector, at PTX 8.5 and sm_80. @@ -14379,6 +14505,16 @@ This table is generated from the resolved catalog. Evidence stages below disting - `lib_nvvm` uses `inline_ptx` from profile `cuda-13.3-libnvvm-13.3.33` at PTX 8.5 / sm_80+: status `validated` (`CUDA toolkit 13.3; nvcc/libNVVM release V13.3.33`, SHA-256 `b6a5db233133fb0ed693f8cb8aeb1d405254ce0ab10364478985292ec98cfcf0`) - backend codegen on `compute_80, ptx93`: `succeeded` — The production generated_intrinsics route produced 242,464-byte compute_80 NVVM IR with SHA-256 fcc2fe1a6200de7b5ab8a38cab847432669fe4d6ce823c81b73f9b18fa25144c and 68,600-byte LTOIR with SHA-256 aa011070e20cb91d99f0d6d41ffd3883f01031b44d171380f638e3674b2facf3. All eight raw variants use compile-time selector 0. - device link on `sm_80, ptx93`: `succeeded` — nvJitLink produced a 23,656-byte cubin with SHA-256 8a09455f87f3ef0c7c16adf13bf6030cbe7f0f18df7fcd91ec2a19a10de5b50d. Disassembly contained 30 IMMA.SP instructions in total and exactly 10 IMMA.SP.16864 instructions: all eight raw variants plus two compatibility-path calls. Tool `/usr/local/cuda-13.3/lib64/libnvJitLink.so.13.3.33` reports `V13.3.33` (SHA-256 `3ba1e744347cd68617b862eccfd98b125482e882b7a6319f42abc9a768513db8`). Artifact `cubin`. +- `mma_sp_ordered_metadata_m16n8k8_f32_tf32`: runtime `executed` + - `llvm_nvptx` uses `inline_ptx` from profile `rust-llvm-23.1.0-16696adc` at PTX 8.5 / sm_80+: status `executed` (`LLVM version 23.1.0-rust-1.100.0-nightly`, SHA-256 `2e5bc688625ca7d98bca9b5f0f0d14525d2eb59e8a9842964e480df3ffd1f921`) + - backend codegen on `sm_80, ptx85`: `succeeded` — Pinned LLVM 23.1.0-rust lowered the eight per-intrinsic probe fixtures at sm_80/+ptx85 into 59,900 bytes of PTX across eight files; their concatenation in lexicographic id order has SHA-256 2eaae1b352ef07684549050756eba1ae0eb57318cfa329a9f103f086296f81dc, and every fixture retains one unguarded exact ordered-metadata instruction per selector immediate (24 across the family). Typed declarations of all eight intrinsics fail selection at sm_75/+ptx85 and sm_80/+ptx80, and select at sm_80, sm_86, sm_89, and sm_90/+ptx85 plus sm_100/+ptx86. + - PTX assembly on `sm_80, ptx85`: `succeeded` — CUDA 13.3 ptxas accepted every selector form of all eight ordered-metadata sparse floating variants at PTX 8.5 and sm_80. Tool `/usr/local/cuda-13.3/bin/ptxas` reports `CUDA 13.3 V13.3.33 build cuda_13.3.r13.3/compiler.37862127_0` (SHA-256 `7fdd01a4cf50e30746da98989c9272a907f491e6fd7fecfda14642e4375f88fb`). Artifact `cubin`. + - runtime on `sm_120, ptx85`: `succeeded` — Re-measured with the asymmetric oracle on NVIDIA GeForce RTX 5090 (compute capability 12.0), NVIDIA driver 580.173.02, CUDA toolkit 13.3 V13.3.33. Command: cargo oxide run sparse_mma_ordered_float. Result: exit code 0; SUCCESS: all 8 variants; all 32 lanes and 4 logical accumulators/lane match host GEMM; positionally distinct A/B/C, all six ordered metadata codes (tf32: both), and a nonzero selector per selector domain executed; compute-sanitizer memcheck reports 0 errors. + - `lib_nvvm` uses `inline_ptx` from profile `cuda-13.3-libnvvm-13.3.33` at PTX 8.5 / sm_80+: status `executed` (`CUDA toolkit 13.3; nvcc/libNVVM release V13.3.33`, SHA-256 `b6a5db233133fb0ed693f8cb8aeb1d405254ce0ab10364478985292ec98cfcf0`) + - backend codegen on `compute_80, ptx93`: `succeeded` — The production emit-ltoir route (cargo oxide emit-ltoir sparse_mma_ordered_float --arch sm_80) produced 159,170-byte compute_80 NVVM IR with SHA-256 b338c017795f39f98f756f1d87dc202d1db274479c6619fef9797cb5a95f7613, and CUDA 13.3 libNVVM -gen-lto compiled it to 37,468-byte LTOIR with SHA-256 ac6d8317ba99d9c4332a0ce8777024bc066a7304c6ed4b64c341f4248f6b6100; both artifacts are byte-identical across repeated runs, and the module carries all eight ordered raw calls with one compile-time selector per variant. + - PTX assembly on `sm_80, ptx93`: `succeeded` — nvJitLink rendered the LTOIR as 83,805-byte PTX 9.3 for sm_80 (SHA-256 4a92814b0579bf19a0ab8aa4c8b2114ec2170c87711831b2a17a31d579bf6e87) retaining all eight ordered forms, and CUDA 13.3 ptxas assembled it into a 41,896-byte cubin with SHA-256 26aa4d2f38132bc6a219ec7b22655a77b412176f464fe93d6c8ae81ea1b9e88b. Tool `/usr/local/cuda-13.3/bin/ptxas` reports `CUDA 13.3 V13.3.33 build cuda_13.3.r13.3/compiler.37862127_0` (SHA-256 `7fdd01a4cf50e30746da98989c9272a907f491e6fd7fecfda14642e4375f88fb`). Artifact `cubin`. + - device link on `sm_80, ptx93`: `succeeded` — nvJitLink linked the real libNVVM LTOIR into a 41,896-byte sm_80 cubin with SHA-256 99aa489c3c80ed1414df0c6fe073cff99dcb66a55fd0057729322b54790ac1bf; its cuobjdump SASS contains exactly eight HMMA.SP instructions, one per variant: 1688.F32.TF32, 16816.F32.TF32, 16816.F32.BF16, 16816.F32, 16816.F16, 16832.F32.BF16, 16832.F32, and 16832.F16. Tool `/usr/local/cuda-13.3/lib64/libnvJitLink.so.13.3.33` reports `V13.3.33` (SHA-256 `3ba1e744347cd68617b862eccfd98b125482e882b7a6319f42abc9a768513db8`). Artifact `cubin`. + - runtime on `sm_120, ptx93`: `succeeded` — Executed through the libNVVM route (NVVM IR materialized by libNVVM plus nvJitLink at load time) on NVIDIA GeForce RTX 5090 (compute capability 12.0), NVIDIA driver 580.173.02, CUDA toolkit 13.3 V13.3.33. Command: cargo oxide run sparse_mma_ordered_float --emit-nvvm-ir --arch sm_120. Result: exit code 0; SUCCESS: all 8 variants; all 32 lanes and 4 logical accumulators/lane match host GEMM; positionally distinct A/B/C, all six ordered metadata codes (tf32: both), and a nonzero selector per selector domain executed; compute-sanitizer memcheck reports 0 errors. - `movmatrix_trans_b16`: runtime `unexecuted` - `llvm_nvptx` uses `inline_ptx` from profile `rust-llvm-23.1.0-16696adc` at PTX 7.8 / sm_75+: status `validated` (`LLVM version 23.1.0-rust-1.100.0-nightly`, SHA-256 `2e5bc688625ca7d98bca9b5f0f0d14525d2eb59e8a9842964e480df3ffd1f921`) - backend codegen on `sm_75, ptx78`: `succeeded` — Pinned Rust LLVM emitted one exact movmatrix instruction; source SHA-256 b8776ed95d8c8e451deea02d8851a238cfcfe570e286a92c94e5971bf06db963, bitcode SHA-256 caf25ab44ed893d449343707f06af85395e86f41852c32ec1b577be184365aee, and PTX SHA-256 f1e1b7d8ad879abd120d6cb32a5999925af0ed77b3a7144a7dfd8db76ea18246. diff --git a/intrinsics/overlay.toml b/intrinsics/overlay.toml index 35e5442674..17d0d32670 100644 --- a/intrinsics/overlay.toml +++ b/intrinsics/overlay.toml @@ -48,6 +48,7 @@ shards = [ "overlay/sparse_mma_int4_m16n8k64.toml", "overlay/sparse_mma_int8.toml", "overlay/sparse_mma_int8_m16n8k64.toml", + "overlay/sparse_mma_ordered_ampere_float.toml", "overlay/sparse_mma_ordered_f8f6f4_f16.toml", "overlay/sparse_mma_ordered_f8f6f4_f32.toml", "overlay/sparse_mma_ordered_int4_m16n8k128.toml", diff --git a/intrinsics/overlay/sparse_mma_ordered_ampere_float.toml b/intrinsics/overlay/sparse_mma_ordered_ampere_float.toml new file mode 100644 index 0000000000..81c3e6a775 --- /dev/null +++ b/intrinsics/overlay/sparse_mma_ordered_ampere_float.toml @@ -0,0 +1,49 @@ +# Reviewed ordered-metadata sparse Ampere floating-point register-MMA family. + +schema = 63 +family = "sparse_mma" + +[sparse_mma_ordered_ampere_float] +llvm_evidence_profile = "rust-llvm-23.1.0-16696adc" +libnvvm_evidence_profile = "cuda-13.3-libnvvm-13.3.33" +runtime_validation = "executed" + +[[sparse_mma_ordered_ampere_float.variant]] +shape = "m16n8k8" +accumulator = "f32" +element = "tf32" + +[[sparse_mma_ordered_ampere_float.variant]] +shape = "m16n8k16" +accumulator = "f32" +element = "tf32" + +[[sparse_mma_ordered_ampere_float.variant]] +shape = "m16n8k16" +accumulator = "f32" +element = "bf16" + +[[sparse_mma_ordered_ampere_float.variant]] +shape = "m16n8k16" +accumulator = "f16" +element = "f16" + +[[sparse_mma_ordered_ampere_float.variant]] +shape = "m16n8k16" +accumulator = "f32" +element = "f16" + +[[sparse_mma_ordered_ampere_float.variant]] +shape = "m16n8k32" +accumulator = "f32" +element = "bf16" + +[[sparse_mma_ordered_ampere_float.variant]] +shape = "m16n8k32" +accumulator = "f16" +element = "f16" + +[[sparse_mma_ordered_ampere_float.variant]] +shape = "m16n8k32" +accumulator = "f32" +element = "f16" diff --git a/intrinsics/probes/abs_bf16x2.ll b/intrinsics/probes/abs_bf16x2.ll index c609f08856..cca4b2352b 100644 --- a/intrinsics/probes/abs_bf16x2.ll +++ b/intrinsics/probes/abs_bf16x2.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/abs_f16x2.ll b/intrinsics/probes/abs_f16x2.ll index 5b01c2f2cb..5257ea88ea 100644 --- a/intrinsics/probes/abs_f16x2.ll +++ b/intrinsics/probes/abs_f16x2.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/active_mask.ll b/intrinsics/probes/active_mask.ll index c462dc93c7..7393bdb5b4 100644 --- a/intrinsics/probes/active_mask.ll +++ b/intrinsics/probes/active_mask.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/add_bf16x2.ll b/intrinsics/probes/add_bf16x2.ll index 1fcf71988d..d91c24235e 100644 --- a/intrinsics/probes/add_bf16x2.ll +++ b/intrinsics/probes/add_bf16x2.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/add_f16x2.ll b/intrinsics/probes/add_f16x2.ll index 1d7cce592c..bf5a4a2b96 100644 --- a/intrinsics/probes/add_f16x2.ll +++ b/intrinsics/probes/add_f16x2.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/add_f32x2.ll b/intrinsics/probes/add_f32x2.ll index a583f42e50..f6ed708f36 100644 --- a/intrinsics/probes/add_f32x2.ll +++ b/intrinsics/probes/add_f32x2.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/add_ftz_f32x2.ll b/intrinsics/probes/add_ftz_f32x2.ll index 31d1648795..552dc288fc 100644 --- a/intrinsics/probes/add_ftz_f32x2.ll +++ b/intrinsics/probes/add_ftz_f32x2.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/add_rm_f32.ll b/intrinsics/probes/add_rm_f32.ll index f847d0de52..b397872077 100644 --- a/intrinsics/probes/add_rm_f32.ll +++ b/intrinsics/probes/add_rm_f32.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/add_rm_f64.ll b/intrinsics/probes/add_rm_f64.ll index 837c73c6a4..8ab4dc25a0 100644 --- a/intrinsics/probes/add_rm_f64.ll +++ b/intrinsics/probes/add_rm_f64.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/add_rm_ftz_f32.ll b/intrinsics/probes/add_rm_ftz_f32.ll index 48f384ea4f..58d0504338 100644 --- a/intrinsics/probes/add_rm_ftz_f32.ll +++ b/intrinsics/probes/add_rm_ftz_f32.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/add_rm_ftz_sat_f32.ll b/intrinsics/probes/add_rm_ftz_sat_f32.ll index a301888f47..79e548b8fc 100644 --- a/intrinsics/probes/add_rm_ftz_sat_f32.ll +++ b/intrinsics/probes/add_rm_ftz_sat_f32.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/add_rm_sat_f32.ll b/intrinsics/probes/add_rm_sat_f32.ll index 11559b2c52..1564a8c5b8 100644 --- a/intrinsics/probes/add_rm_sat_f32.ll +++ b/intrinsics/probes/add_rm_sat_f32.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/add_rn_f32.ll b/intrinsics/probes/add_rn_f32.ll index 377c6252fe..629ede57e5 100644 --- a/intrinsics/probes/add_rn_f32.ll +++ b/intrinsics/probes/add_rn_f32.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/add_rn_f64.ll b/intrinsics/probes/add_rn_f64.ll index c6cb6c8066..7fdfc9629f 100644 --- a/intrinsics/probes/add_rn_f64.ll +++ b/intrinsics/probes/add_rn_f64.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/add_rn_ftz_f32.ll b/intrinsics/probes/add_rn_ftz_f32.ll index b701d3c1a1..0aad5deade 100644 --- a/intrinsics/probes/add_rn_ftz_f32.ll +++ b/intrinsics/probes/add_rn_ftz_f32.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/add_rn_ftz_sat_f32.ll b/intrinsics/probes/add_rn_ftz_sat_f32.ll index b7b3f15786..4a2046a0c2 100644 --- a/intrinsics/probes/add_rn_ftz_sat_f32.ll +++ b/intrinsics/probes/add_rn_ftz_sat_f32.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/add_rn_sat_f32.ll b/intrinsics/probes/add_rn_sat_f32.ll index b2cb1169fc..dc1f5ba356 100644 --- a/intrinsics/probes/add_rn_sat_f32.ll +++ b/intrinsics/probes/add_rn_sat_f32.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/add_rp_f32.ll b/intrinsics/probes/add_rp_f32.ll index 8ce809d19b..b36320a766 100644 --- a/intrinsics/probes/add_rp_f32.ll +++ b/intrinsics/probes/add_rp_f32.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/add_rp_f64.ll b/intrinsics/probes/add_rp_f64.ll index d5f1b66bb7..8be59631c3 100644 --- a/intrinsics/probes/add_rp_f64.ll +++ b/intrinsics/probes/add_rp_f64.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/add_rp_ftz_f32.ll b/intrinsics/probes/add_rp_ftz_f32.ll index 4f933d1c0e..816ee74904 100644 --- a/intrinsics/probes/add_rp_ftz_f32.ll +++ b/intrinsics/probes/add_rp_ftz_f32.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/add_rp_ftz_sat_f32.ll b/intrinsics/probes/add_rp_ftz_sat_f32.ll index a80f4cf60a..0729db523d 100644 --- a/intrinsics/probes/add_rp_ftz_sat_f32.ll +++ b/intrinsics/probes/add_rp_ftz_sat_f32.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/add_rp_sat_f32.ll b/intrinsics/probes/add_rp_sat_f32.ll index 0f801e00df..41752a0384 100644 --- a/intrinsics/probes/add_rp_sat_f32.ll +++ b/intrinsics/probes/add_rp_sat_f32.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/add_rz_f32.ll b/intrinsics/probes/add_rz_f32.ll index c3f0794599..747c0e7aaf 100644 --- a/intrinsics/probes/add_rz_f32.ll +++ b/intrinsics/probes/add_rz_f32.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/add_rz_f64.ll b/intrinsics/probes/add_rz_f64.ll index a1b9ce5981..c2625461a0 100644 --- a/intrinsics/probes/add_rz_f64.ll +++ b/intrinsics/probes/add_rz_f64.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/add_rz_ftz_f32.ll b/intrinsics/probes/add_rz_ftz_f32.ll index 7334a58b3c..f4bcc91f95 100644 --- a/intrinsics/probes/add_rz_ftz_f32.ll +++ b/intrinsics/probes/add_rz_ftz_f32.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/add_rz_ftz_sat_f32.ll b/intrinsics/probes/add_rz_ftz_sat_f32.ll index 6d3a5f85a1..3e93f354e9 100644 --- a/intrinsics/probes/add_rz_ftz_sat_f32.ll +++ b/intrinsics/probes/add_rz_ftz_sat_f32.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/add_rz_sat_f32.ll b/intrinsics/probes/add_rz_sat_f32.ll index d683d1a1b6..883195d6ba 100644 --- a/intrinsics/probes/add_rz_sat_f32.ll +++ b/intrinsics/probes/add_rz_sat_f32.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/all_sync.ll b/intrinsics/probes/all_sync.ll index fc4a337c42..1c42857b82 100644 --- a/intrinsics/probes/all_sync.ll +++ b/intrinsics/probes/all_sync.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/any_sync.ll b/intrinsics/probes/any_sync.ll index dd72595874..3704797990 100644 --- a/intrinsics/probes/any_sync.ll +++ b/intrinsics/probes/any_sync.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/ballot_sync.ll b/intrinsics/probes/ballot_sync.ll index 885c4ac11d..99d0586848 100644 --- a/intrinsics/probes/ballot_sync.ll +++ b/intrinsics/probes/ballot_sync.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/barrier_cluster_arrive.ll b/intrinsics/probes/barrier_cluster_arrive.ll index da78bf131f..743baeef9e 100644 --- a/intrinsics/probes/barrier_cluster_arrive.ll +++ b/intrinsics/probes/barrier_cluster_arrive.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/barrier_cluster_arrive_aligned.ll b/intrinsics/probes/barrier_cluster_arrive_aligned.ll index 968e64f5f7..03f401248b 100644 --- a/intrinsics/probes/barrier_cluster_arrive_aligned.ll +++ b/intrinsics/probes/barrier_cluster_arrive_aligned.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/barrier_cluster_arrive_relaxed.ll b/intrinsics/probes/barrier_cluster_arrive_relaxed.ll index 5e930acc57..833a76d4a9 100644 --- a/intrinsics/probes/barrier_cluster_arrive_relaxed.ll +++ b/intrinsics/probes/barrier_cluster_arrive_relaxed.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/barrier_cluster_arrive_relaxed_aligned.ll b/intrinsics/probes/barrier_cluster_arrive_relaxed_aligned.ll index 68ea041c48..1782465c0b 100644 --- a/intrinsics/probes/barrier_cluster_arrive_relaxed_aligned.ll +++ b/intrinsics/probes/barrier_cluster_arrive_relaxed_aligned.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/barrier_cluster_wait.ll b/intrinsics/probes/barrier_cluster_wait.ll index 7722ee5ad8..42056b0818 100644 --- a/intrinsics/probes/barrier_cluster_wait.ll +++ b/intrinsics/probes/barrier_cluster_wait.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/barrier_cluster_wait_aligned.ll b/intrinsics/probes/barrier_cluster_wait_aligned.ll index 4120531c5d..9c2cd52d56 100644 --- a/intrinsics/probes/barrier_cluster_wait_aligned.ll +++ b/intrinsics/probes/barrier_cluster_wait_aligned.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/barrier_cta_arrive.ll b/intrinsics/probes/barrier_cta_arrive.ll index 77c28a6bee..988f6b8d89 100644 --- a/intrinsics/probes/barrier_cta_arrive.ll +++ b/intrinsics/probes/barrier_cta_arrive.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/barrier_cta_arrive_aligned.ll b/intrinsics/probes/barrier_cta_arrive_aligned.ll index 144450182b..debb9bf116 100644 --- a/intrinsics/probes/barrier_cta_arrive_aligned.ll +++ b/intrinsics/probes/barrier_cta_arrive_aligned.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/barrier_cta_sync.ll b/intrinsics/probes/barrier_cta_sync.ll index b93383f842..92934260d7 100644 --- a/intrinsics/probes/barrier_cta_sync.ll +++ b/intrinsics/probes/barrier_cta_sync.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/barrier_cta_sync_aligned.ll b/intrinsics/probes/barrier_cta_sync_aligned.ll index 86d4d3593b..40a46ab9ba 100644 --- a/intrinsics/probes/barrier_cta_sync_aligned.ll +++ b/intrinsics/probes/barrier_cta_sync_aligned.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/block_dim_x.ll b/intrinsics/probes/block_dim_x.ll index 22767fa7a2..389be3a4bc 100644 --- a/intrinsics/probes/block_dim_x.ll +++ b/intrinsics/probes/block_dim_x.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/block_dim_y.ll b/intrinsics/probes/block_dim_y.ll index d67f7d50f6..d04aa863f9 100644 --- a/intrinsics/probes/block_dim_y.ll +++ b/intrinsics/probes/block_dim_y.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/block_dim_z.ll b/intrinsics/probes/block_dim_z.ll index 1ca99d2015..f16acaaf82 100644 --- a/intrinsics/probes/block_dim_z.ll +++ b/intrinsics/probes/block_dim_z.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/block_idx_x.ll b/intrinsics/probes/block_idx_x.ll index ea65bb2a7f..b3a7f09cbd 100644 --- a/intrinsics/probes/block_idx_x.ll +++ b/intrinsics/probes/block_idx_x.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/block_idx_y.ll b/intrinsics/probes/block_idx_y.ll index f233092981..271522a744 100644 --- a/intrinsics/probes/block_idx_y.ll +++ b/intrinsics/probes/block_idx_y.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/block_idx_z.ll b/intrinsics/probes/block_idx_z.ll index 8783453823..84a4733b04 100644 --- a/intrinsics/probes/block_idx_z.ll +++ b/intrinsics/probes/block_idx_z.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/breakpoint.ll b/intrinsics/probes/breakpoint.ll index 87edd4a5fe..c9ac46ff33 100644 --- a/intrinsics/probes/breakpoint.ll +++ b/intrinsics/probes/breakpoint.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/clc_query_get_first_ctaid_x.ll b/intrinsics/probes/clc_query_get_first_ctaid_x.ll index bc38ab2916..5d701fb60f 100644 --- a/intrinsics/probes/clc_query_get_first_ctaid_x.ll +++ b/intrinsics/probes/clc_query_get_first_ctaid_x.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/clc_query_get_first_ctaid_y.ll b/intrinsics/probes/clc_query_get_first_ctaid_y.ll index 3c9bafc97c..710f5ef24d 100644 --- a/intrinsics/probes/clc_query_get_first_ctaid_y.ll +++ b/intrinsics/probes/clc_query_get_first_ctaid_y.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/clc_query_get_first_ctaid_z.ll b/intrinsics/probes/clc_query_get_first_ctaid_z.ll index 8b15e08330..6f149e0642 100644 --- a/intrinsics/probes/clc_query_get_first_ctaid_z.ll +++ b/intrinsics/probes/clc_query_get_first_ctaid_z.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/clc_query_is_canceled.ll b/intrinsics/probes/clc_query_is_canceled.ll index fdf07c347e..bbbc09bdda 100644 --- a/intrinsics/probes/clc_query_is_canceled.ll +++ b/intrinsics/probes/clc_query_is_canceled.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/clc_try_cancel.ll b/intrinsics/probes/clc_try_cancel.ll index f9dbd5eab5..8ba877db67 100644 --- a/intrinsics/probes/clc_try_cancel.ll +++ b/intrinsics/probes/clc_try_cancel.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/clc_try_cancel_multicast.ll b/intrinsics/probes/clc_try_cancel_multicast.ll index bc1b6a5ea6..32cf2bc606 100644 --- a/intrinsics/probes/clc_try_cancel_multicast.ll +++ b/intrinsics/probes/clc_try_cancel_multicast.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/clock.lib_nvvm.ll b/intrinsics/probes/clock.lib_nvvm.ll index f4c2a27adf..aae6c3c3a9 100644 --- a/intrinsics/probes/clock.lib_nvvm.ll +++ b/intrinsics/probes/clock.lib_nvvm.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/clock.llvm_nvptx.ll b/intrinsics/probes/clock.llvm_nvptx.ll index 6231ca318b..020875e1e8 100644 --- a/intrinsics/probes/clock.llvm_nvptx.ll +++ b/intrinsics/probes/clock.llvm_nvptx.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/clock64.lib_nvvm.ll b/intrinsics/probes/clock64.lib_nvvm.ll index 9c108521f9..9d6b8baa09 100644 --- a/intrinsics/probes/clock64.lib_nvvm.ll +++ b/intrinsics/probes/clock64.lib_nvvm.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/clock64.llvm_nvptx.ll b/intrinsics/probes/clock64.llvm_nvptx.ll index 1328081ef9..9efb8e8d5f 100644 --- a/intrinsics/probes/clock64.llvm_nvptx.ll +++ b/intrinsics/probes/clock64.llvm_nvptx.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/cluster_block_count.ll b/intrinsics/probes/cluster_block_count.ll index ce46b23d32..43aeccd980 100644 --- a/intrinsics/probes/cluster_block_count.ll +++ b/intrinsics/probes/cluster_block_count.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/cluster_block_idx_x.ll b/intrinsics/probes/cluster_block_idx_x.ll index 208670cbcc..3efe7e160e 100644 --- a/intrinsics/probes/cluster_block_idx_x.ll +++ b/intrinsics/probes/cluster_block_idx_x.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/cluster_block_idx_y.ll b/intrinsics/probes/cluster_block_idx_y.ll index 5872b943af..16f4f35bf8 100644 --- a/intrinsics/probes/cluster_block_idx_y.ll +++ b/intrinsics/probes/cluster_block_idx_y.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/cluster_block_idx_z.ll b/intrinsics/probes/cluster_block_idx_z.ll index d79ec42141..e3635a723d 100644 --- a/intrinsics/probes/cluster_block_idx_z.ll +++ b/intrinsics/probes/cluster_block_idx_z.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/cluster_block_rank.ll b/intrinsics/probes/cluster_block_rank.ll index cc1a1a2218..2c955fc29e 100644 --- a/intrinsics/probes/cluster_block_rank.ll +++ b/intrinsics/probes/cluster_block_rank.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/cluster_dim_x.ll b/intrinsics/probes/cluster_dim_x.ll index 8ffdd4b85a..0ac9225804 100644 --- a/intrinsics/probes/cluster_dim_x.ll +++ b/intrinsics/probes/cluster_dim_x.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/cluster_dim_y.ll b/intrinsics/probes/cluster_dim_y.ll index 5ca3c379a1..4dfcb783b2 100644 --- a/intrinsics/probes/cluster_dim_y.ll +++ b/intrinsics/probes/cluster_dim_y.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/cluster_dim_z.ll b/intrinsics/probes/cluster_dim_z.ll index c4918dc583..df49c87680 100644 --- a/intrinsics/probes/cluster_dim_z.ll +++ b/intrinsics/probes/cluster_dim_z.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/cluster_grid_dim_x.ll b/intrinsics/probes/cluster_grid_dim_x.ll index 0c225deb07..9165f36c52 100644 --- a/intrinsics/probes/cluster_grid_dim_x.ll +++ b/intrinsics/probes/cluster_grid_dim_x.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/cluster_grid_dim_y.ll b/intrinsics/probes/cluster_grid_dim_y.ll index ef37682575..ee21d3a29d 100644 --- a/intrinsics/probes/cluster_grid_dim_y.ll +++ b/intrinsics/probes/cluster_grid_dim_y.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/cluster_grid_dim_z.ll b/intrinsics/probes/cluster_grid_dim_z.ll index 0fb7ccc8da..e6babc2b38 100644 --- a/intrinsics/probes/cluster_grid_dim_z.ll +++ b/intrinsics/probes/cluster_grid_dim_z.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/cluster_idx_x.ll b/intrinsics/probes/cluster_idx_x.ll index de25dd6bf9..4cb2a0e1a4 100644 --- a/intrinsics/probes/cluster_idx_x.ll +++ b/intrinsics/probes/cluster_idx_x.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/cluster_idx_y.ll b/intrinsics/probes/cluster_idx_y.ll index a0fc38c789..32d751d8c5 100644 --- a/intrinsics/probes/cluster_idx_y.ll +++ b/intrinsics/probes/cluster_idx_y.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/cluster_idx_z.ll b/intrinsics/probes/cluster_idx_z.ll index c217bd9135..d06c5d5579 100644 --- a/intrinsics/probes/cluster_idx_z.ll +++ b/intrinsics/probes/cluster_idx_z.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/cos_approx_f32.ll b/intrinsics/probes/cos_approx_f32.ll index 20726c20c7..8095f354e9 100644 --- a/intrinsics/probes/cos_approx_f32.ll +++ b/intrinsics/probes/cos_approx_f32.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/cos_approx_ftz_f32.ll b/intrinsics/probes/cos_approx_ftz_f32.ll index 48cfbdd385..870001a86f 100644 --- a/intrinsics/probes/cos_approx_ftz_f32.ll +++ b/intrinsics/probes/cos_approx_ftz_f32.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/cp_async_bulk_commit_group.ll b/intrinsics/probes/cp_async_bulk_commit_group.ll index da90cd24fc..83caabdf53 100644 --- a/intrinsics/probes/cp_async_bulk_commit_group.ll +++ b/intrinsics/probes/cp_async_bulk_commit_group.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/cp_async_bulk_prefetch_tensor_1d_l2.ll b/intrinsics/probes/cp_async_bulk_prefetch_tensor_1d_l2.ll index 9a8d24d738..4149de9ff1 100644 --- a/intrinsics/probes/cp_async_bulk_prefetch_tensor_1d_l2.ll +++ b/intrinsics/probes/cp_async_bulk_prefetch_tensor_1d_l2.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/cp_async_bulk_prefetch_tensor_1d_l2_cache_hint.ll b/intrinsics/probes/cp_async_bulk_prefetch_tensor_1d_l2_cache_hint.ll index 31eaa9f5e8..f5f951df6b 100644 --- a/intrinsics/probes/cp_async_bulk_prefetch_tensor_1d_l2_cache_hint.ll +++ b/intrinsics/probes/cp_async_bulk_prefetch_tensor_1d_l2_cache_hint.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/cp_async_bulk_prefetch_tensor_2d_l2.ll b/intrinsics/probes/cp_async_bulk_prefetch_tensor_2d_l2.ll index ba7646bd29..2ac7032b2f 100644 --- a/intrinsics/probes/cp_async_bulk_prefetch_tensor_2d_l2.ll +++ b/intrinsics/probes/cp_async_bulk_prefetch_tensor_2d_l2.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/cp_async_bulk_prefetch_tensor_2d_l2_cache_hint.ll b/intrinsics/probes/cp_async_bulk_prefetch_tensor_2d_l2_cache_hint.ll index f62085cc31..30d87e686a 100644 --- a/intrinsics/probes/cp_async_bulk_prefetch_tensor_2d_l2_cache_hint.ll +++ b/intrinsics/probes/cp_async_bulk_prefetch_tensor_2d_l2_cache_hint.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/cp_async_bulk_prefetch_tensor_3d_l2.ll b/intrinsics/probes/cp_async_bulk_prefetch_tensor_3d_l2.ll index 597fc28485..fa98fec890 100644 --- a/intrinsics/probes/cp_async_bulk_prefetch_tensor_3d_l2.ll +++ b/intrinsics/probes/cp_async_bulk_prefetch_tensor_3d_l2.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/cp_async_bulk_prefetch_tensor_3d_l2_cache_hint.ll b/intrinsics/probes/cp_async_bulk_prefetch_tensor_3d_l2_cache_hint.ll index b2cc839435..b43473833f 100644 --- a/intrinsics/probes/cp_async_bulk_prefetch_tensor_3d_l2_cache_hint.ll +++ b/intrinsics/probes/cp_async_bulk_prefetch_tensor_3d_l2_cache_hint.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/cp_async_bulk_prefetch_tensor_4d_l2.ll b/intrinsics/probes/cp_async_bulk_prefetch_tensor_4d_l2.ll index ad18034413..ed65100bcd 100644 --- a/intrinsics/probes/cp_async_bulk_prefetch_tensor_4d_l2.ll +++ b/intrinsics/probes/cp_async_bulk_prefetch_tensor_4d_l2.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/cp_async_bulk_prefetch_tensor_4d_l2_cache_hint.ll b/intrinsics/probes/cp_async_bulk_prefetch_tensor_4d_l2_cache_hint.ll index 9f364700fd..7cafc37242 100644 --- a/intrinsics/probes/cp_async_bulk_prefetch_tensor_4d_l2_cache_hint.ll +++ b/intrinsics/probes/cp_async_bulk_prefetch_tensor_4d_l2_cache_hint.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/cp_async_bulk_prefetch_tensor_5d_l2.ll b/intrinsics/probes/cp_async_bulk_prefetch_tensor_5d_l2.ll index caf984c31e..2cc5b3be6a 100644 --- a/intrinsics/probes/cp_async_bulk_prefetch_tensor_5d_l2.ll +++ b/intrinsics/probes/cp_async_bulk_prefetch_tensor_5d_l2.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/cp_async_bulk_prefetch_tensor_5d_l2_cache_hint.ll b/intrinsics/probes/cp_async_bulk_prefetch_tensor_5d_l2_cache_hint.ll index 1fa945b326..fee338a705 100644 --- a/intrinsics/probes/cp_async_bulk_prefetch_tensor_5d_l2_cache_hint.ll +++ b/intrinsics/probes/cp_async_bulk_prefetch_tensor_5d_l2_cache_hint.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/cp_async_bulk_prefetch_tensor_gather4_2d_l2.ll b/intrinsics/probes/cp_async_bulk_prefetch_tensor_gather4_2d_l2.ll index 61551e3af0..a0e2984077 100644 --- a/intrinsics/probes/cp_async_bulk_prefetch_tensor_gather4_2d_l2.ll +++ b/intrinsics/probes/cp_async_bulk_prefetch_tensor_gather4_2d_l2.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/cp_async_bulk_prefetch_tensor_gather4_2d_l2_cache_hint.ll b/intrinsics/probes/cp_async_bulk_prefetch_tensor_gather4_2d_l2_cache_hint.ll index ab34a8093e..a2b275543a 100644 --- a/intrinsics/probes/cp_async_bulk_prefetch_tensor_gather4_2d_l2_cache_hint.ll +++ b/intrinsics/probes/cp_async_bulk_prefetch_tensor_gather4_2d_l2_cache_hint.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/cp_async_bulk_tensor_1d_g2s.ll b/intrinsics/probes/cp_async_bulk_tensor_1d_g2s.ll index 8068b26188..f63568de2b 100644 --- a/intrinsics/probes/cp_async_bulk_tensor_1d_g2s.ll +++ b/intrinsics/probes/cp_async_bulk_tensor_1d_g2s.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/cp_async_bulk_tensor_1d_s2g.ll b/intrinsics/probes/cp_async_bulk_tensor_1d_s2g.ll index d2eccf6ab9..b6b9c039b0 100644 --- a/intrinsics/probes/cp_async_bulk_tensor_1d_s2g.ll +++ b/intrinsics/probes/cp_async_bulk_tensor_1d_s2g.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/cp_async_bulk_tensor_2d_g2s.ll b/intrinsics/probes/cp_async_bulk_tensor_2d_g2s.ll index 85b228a3bd..b7afdbb71a 100644 --- a/intrinsics/probes/cp_async_bulk_tensor_2d_g2s.ll +++ b/intrinsics/probes/cp_async_bulk_tensor_2d_g2s.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/cp_async_bulk_tensor_2d_g2s_multicast.ll b/intrinsics/probes/cp_async_bulk_tensor_2d_g2s_multicast.ll index 6ba27d69f8..3554e77b88 100644 --- a/intrinsics/probes/cp_async_bulk_tensor_2d_g2s_multicast.ll +++ b/intrinsics/probes/cp_async_bulk_tensor_2d_g2s_multicast.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/cp_async_bulk_tensor_2d_g2s_multicast_cg2.ll b/intrinsics/probes/cp_async_bulk_tensor_2d_g2s_multicast_cg2.ll index b9c6f18b45..3190b17287 100644 --- a/intrinsics/probes/cp_async_bulk_tensor_2d_g2s_multicast_cg2.ll +++ b/intrinsics/probes/cp_async_bulk_tensor_2d_g2s_multicast_cg2.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/cp_async_bulk_tensor_2d_s2g.ll b/intrinsics/probes/cp_async_bulk_tensor_2d_s2g.ll index a8c1119bfb..06f5cd4274 100644 --- a/intrinsics/probes/cp_async_bulk_tensor_2d_s2g.ll +++ b/intrinsics/probes/cp_async_bulk_tensor_2d_s2g.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/cp_async_bulk_tensor_3d_g2s.ll b/intrinsics/probes/cp_async_bulk_tensor_3d_g2s.ll index 59c4103cce..dc79faf428 100644 --- a/intrinsics/probes/cp_async_bulk_tensor_3d_g2s.ll +++ b/intrinsics/probes/cp_async_bulk_tensor_3d_g2s.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/cp_async_bulk_tensor_3d_s2g.ll b/intrinsics/probes/cp_async_bulk_tensor_3d_s2g.ll index d527c74295..776c20f2e9 100644 --- a/intrinsics/probes/cp_async_bulk_tensor_3d_s2g.ll +++ b/intrinsics/probes/cp_async_bulk_tensor_3d_s2g.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/cp_async_bulk_tensor_4d_g2s.ll b/intrinsics/probes/cp_async_bulk_tensor_4d_g2s.ll index 535f27f5e6..02c55b4481 100644 --- a/intrinsics/probes/cp_async_bulk_tensor_4d_g2s.ll +++ b/intrinsics/probes/cp_async_bulk_tensor_4d_g2s.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/cp_async_bulk_tensor_4d_s2g.ll b/intrinsics/probes/cp_async_bulk_tensor_4d_s2g.ll index cfc2ecaaf0..7dbeb4e088 100644 --- a/intrinsics/probes/cp_async_bulk_tensor_4d_s2g.ll +++ b/intrinsics/probes/cp_async_bulk_tensor_4d_s2g.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/cp_async_bulk_tensor_5d_g2s.ll b/intrinsics/probes/cp_async_bulk_tensor_5d_g2s.ll index fa33493022..d64d54d8ed 100644 --- a/intrinsics/probes/cp_async_bulk_tensor_5d_g2s.ll +++ b/intrinsics/probes/cp_async_bulk_tensor_5d_g2s.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/cp_async_bulk_tensor_5d_s2g.ll b/intrinsics/probes/cp_async_bulk_tensor_5d_s2g.ll index d391d1f663..1eed033c7a 100644 --- a/intrinsics/probes/cp_async_bulk_tensor_5d_s2g.ll +++ b/intrinsics/probes/cp_async_bulk_tensor_5d_s2g.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/cp_async_bulk_tensor_reduce_add_im2col_3d.ll b/intrinsics/probes/cp_async_bulk_tensor_reduce_add_im2col_3d.ll index ae2bd9beb4..e5116ba977 100644 --- a/intrinsics/probes/cp_async_bulk_tensor_reduce_add_im2col_3d.ll +++ b/intrinsics/probes/cp_async_bulk_tensor_reduce_add_im2col_3d.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/cp_async_bulk_tensor_reduce_add_im2col_4d.ll b/intrinsics/probes/cp_async_bulk_tensor_reduce_add_im2col_4d.ll index 85727e2413..38fd954c13 100644 --- a/intrinsics/probes/cp_async_bulk_tensor_reduce_add_im2col_4d.ll +++ b/intrinsics/probes/cp_async_bulk_tensor_reduce_add_im2col_4d.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/cp_async_bulk_tensor_reduce_add_im2col_5d.ll b/intrinsics/probes/cp_async_bulk_tensor_reduce_add_im2col_5d.ll index cfef6b45af..1a50a05a94 100644 --- a/intrinsics/probes/cp_async_bulk_tensor_reduce_add_im2col_5d.ll +++ b/intrinsics/probes/cp_async_bulk_tensor_reduce_add_im2col_5d.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/cp_async_bulk_tensor_reduce_add_tile_1d.ll b/intrinsics/probes/cp_async_bulk_tensor_reduce_add_tile_1d.ll index 858b12b1a9..347d6b578e 100644 --- a/intrinsics/probes/cp_async_bulk_tensor_reduce_add_tile_1d.ll +++ b/intrinsics/probes/cp_async_bulk_tensor_reduce_add_tile_1d.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/cp_async_bulk_tensor_reduce_add_tile_2d.ll b/intrinsics/probes/cp_async_bulk_tensor_reduce_add_tile_2d.ll index 3306e8bd43..75fb12b45a 100644 --- a/intrinsics/probes/cp_async_bulk_tensor_reduce_add_tile_2d.ll +++ b/intrinsics/probes/cp_async_bulk_tensor_reduce_add_tile_2d.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/cp_async_bulk_tensor_reduce_add_tile_3d.ll b/intrinsics/probes/cp_async_bulk_tensor_reduce_add_tile_3d.ll index c0d73c7098..69562915f7 100644 --- a/intrinsics/probes/cp_async_bulk_tensor_reduce_add_tile_3d.ll +++ b/intrinsics/probes/cp_async_bulk_tensor_reduce_add_tile_3d.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/cp_async_bulk_tensor_reduce_add_tile_4d.ll b/intrinsics/probes/cp_async_bulk_tensor_reduce_add_tile_4d.ll index fbf0e301fc..88cf1dab36 100644 --- a/intrinsics/probes/cp_async_bulk_tensor_reduce_add_tile_4d.ll +++ b/intrinsics/probes/cp_async_bulk_tensor_reduce_add_tile_4d.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/cp_async_bulk_tensor_reduce_add_tile_5d.ll b/intrinsics/probes/cp_async_bulk_tensor_reduce_add_tile_5d.ll index e9102488f1..6ec0df9f0d 100644 --- a/intrinsics/probes/cp_async_bulk_tensor_reduce_add_tile_5d.ll +++ b/intrinsics/probes/cp_async_bulk_tensor_reduce_add_tile_5d.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/cp_async_bulk_tensor_reduce_and_im2col_3d.ll b/intrinsics/probes/cp_async_bulk_tensor_reduce_and_im2col_3d.ll index 7e176b2040..3555e2d7bd 100644 --- a/intrinsics/probes/cp_async_bulk_tensor_reduce_and_im2col_3d.ll +++ b/intrinsics/probes/cp_async_bulk_tensor_reduce_and_im2col_3d.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/cp_async_bulk_tensor_reduce_and_im2col_4d.ll b/intrinsics/probes/cp_async_bulk_tensor_reduce_and_im2col_4d.ll index b2b1efca45..07f5958404 100644 --- a/intrinsics/probes/cp_async_bulk_tensor_reduce_and_im2col_4d.ll +++ b/intrinsics/probes/cp_async_bulk_tensor_reduce_and_im2col_4d.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/cp_async_bulk_tensor_reduce_and_im2col_5d.ll b/intrinsics/probes/cp_async_bulk_tensor_reduce_and_im2col_5d.ll index b10cdd45bd..8eecec3e78 100644 --- a/intrinsics/probes/cp_async_bulk_tensor_reduce_and_im2col_5d.ll +++ b/intrinsics/probes/cp_async_bulk_tensor_reduce_and_im2col_5d.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/cp_async_bulk_tensor_reduce_and_tile_1d.ll b/intrinsics/probes/cp_async_bulk_tensor_reduce_and_tile_1d.ll index 0de93f765b..68ac1820de 100644 --- a/intrinsics/probes/cp_async_bulk_tensor_reduce_and_tile_1d.ll +++ b/intrinsics/probes/cp_async_bulk_tensor_reduce_and_tile_1d.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/cp_async_bulk_tensor_reduce_and_tile_2d.ll b/intrinsics/probes/cp_async_bulk_tensor_reduce_and_tile_2d.ll index ce6850c01b..73c6d01035 100644 --- a/intrinsics/probes/cp_async_bulk_tensor_reduce_and_tile_2d.ll +++ b/intrinsics/probes/cp_async_bulk_tensor_reduce_and_tile_2d.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/cp_async_bulk_tensor_reduce_and_tile_3d.ll b/intrinsics/probes/cp_async_bulk_tensor_reduce_and_tile_3d.ll index 03746f3ab4..7280799ab4 100644 --- a/intrinsics/probes/cp_async_bulk_tensor_reduce_and_tile_3d.ll +++ b/intrinsics/probes/cp_async_bulk_tensor_reduce_and_tile_3d.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/cp_async_bulk_tensor_reduce_and_tile_4d.ll b/intrinsics/probes/cp_async_bulk_tensor_reduce_and_tile_4d.ll index 9d6edbbd1f..c35d9a444a 100644 --- a/intrinsics/probes/cp_async_bulk_tensor_reduce_and_tile_4d.ll +++ b/intrinsics/probes/cp_async_bulk_tensor_reduce_and_tile_4d.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/cp_async_bulk_tensor_reduce_and_tile_5d.ll b/intrinsics/probes/cp_async_bulk_tensor_reduce_and_tile_5d.ll index dcaada8af6..615fadbb6d 100644 --- a/intrinsics/probes/cp_async_bulk_tensor_reduce_and_tile_5d.ll +++ b/intrinsics/probes/cp_async_bulk_tensor_reduce_and_tile_5d.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/cp_async_bulk_tensor_reduce_dec_im2col_3d.ll b/intrinsics/probes/cp_async_bulk_tensor_reduce_dec_im2col_3d.ll index 3013990ce0..2546e4bcc9 100644 --- a/intrinsics/probes/cp_async_bulk_tensor_reduce_dec_im2col_3d.ll +++ b/intrinsics/probes/cp_async_bulk_tensor_reduce_dec_im2col_3d.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/cp_async_bulk_tensor_reduce_dec_im2col_4d.ll b/intrinsics/probes/cp_async_bulk_tensor_reduce_dec_im2col_4d.ll index b07955a9a2..c69fa290ae 100644 --- a/intrinsics/probes/cp_async_bulk_tensor_reduce_dec_im2col_4d.ll +++ b/intrinsics/probes/cp_async_bulk_tensor_reduce_dec_im2col_4d.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/cp_async_bulk_tensor_reduce_dec_im2col_5d.ll b/intrinsics/probes/cp_async_bulk_tensor_reduce_dec_im2col_5d.ll index 163952b2a7..1fe5b505a3 100644 --- a/intrinsics/probes/cp_async_bulk_tensor_reduce_dec_im2col_5d.ll +++ b/intrinsics/probes/cp_async_bulk_tensor_reduce_dec_im2col_5d.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/cp_async_bulk_tensor_reduce_dec_tile_1d.ll b/intrinsics/probes/cp_async_bulk_tensor_reduce_dec_tile_1d.ll index 0e23d44490..18be88b009 100644 --- a/intrinsics/probes/cp_async_bulk_tensor_reduce_dec_tile_1d.ll +++ b/intrinsics/probes/cp_async_bulk_tensor_reduce_dec_tile_1d.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/cp_async_bulk_tensor_reduce_dec_tile_2d.ll b/intrinsics/probes/cp_async_bulk_tensor_reduce_dec_tile_2d.ll index f4c74595ee..ae0ff1759c 100644 --- a/intrinsics/probes/cp_async_bulk_tensor_reduce_dec_tile_2d.ll +++ b/intrinsics/probes/cp_async_bulk_tensor_reduce_dec_tile_2d.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/cp_async_bulk_tensor_reduce_dec_tile_3d.ll b/intrinsics/probes/cp_async_bulk_tensor_reduce_dec_tile_3d.ll index 9c8e2245e8..7b7d41dbdf 100644 --- a/intrinsics/probes/cp_async_bulk_tensor_reduce_dec_tile_3d.ll +++ b/intrinsics/probes/cp_async_bulk_tensor_reduce_dec_tile_3d.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/cp_async_bulk_tensor_reduce_dec_tile_4d.ll b/intrinsics/probes/cp_async_bulk_tensor_reduce_dec_tile_4d.ll index 3abf8af43c..ca36e04ca7 100644 --- a/intrinsics/probes/cp_async_bulk_tensor_reduce_dec_tile_4d.ll +++ b/intrinsics/probes/cp_async_bulk_tensor_reduce_dec_tile_4d.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/cp_async_bulk_tensor_reduce_dec_tile_5d.ll b/intrinsics/probes/cp_async_bulk_tensor_reduce_dec_tile_5d.ll index 19de09c905..a052ce7d6c 100644 --- a/intrinsics/probes/cp_async_bulk_tensor_reduce_dec_tile_5d.ll +++ b/intrinsics/probes/cp_async_bulk_tensor_reduce_dec_tile_5d.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/cp_async_bulk_tensor_reduce_inc_im2col_3d.ll b/intrinsics/probes/cp_async_bulk_tensor_reduce_inc_im2col_3d.ll index 5725fa6a7b..b8a443624b 100644 --- a/intrinsics/probes/cp_async_bulk_tensor_reduce_inc_im2col_3d.ll +++ b/intrinsics/probes/cp_async_bulk_tensor_reduce_inc_im2col_3d.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/cp_async_bulk_tensor_reduce_inc_im2col_4d.ll b/intrinsics/probes/cp_async_bulk_tensor_reduce_inc_im2col_4d.ll index 5a520b3f4c..32e63b7d74 100644 --- a/intrinsics/probes/cp_async_bulk_tensor_reduce_inc_im2col_4d.ll +++ b/intrinsics/probes/cp_async_bulk_tensor_reduce_inc_im2col_4d.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/cp_async_bulk_tensor_reduce_inc_im2col_5d.ll b/intrinsics/probes/cp_async_bulk_tensor_reduce_inc_im2col_5d.ll index 391159dc59..d8e57c64ba 100644 --- a/intrinsics/probes/cp_async_bulk_tensor_reduce_inc_im2col_5d.ll +++ b/intrinsics/probes/cp_async_bulk_tensor_reduce_inc_im2col_5d.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/cp_async_bulk_tensor_reduce_inc_tile_1d.ll b/intrinsics/probes/cp_async_bulk_tensor_reduce_inc_tile_1d.ll index 52527a786b..23c3c50a6b 100644 --- a/intrinsics/probes/cp_async_bulk_tensor_reduce_inc_tile_1d.ll +++ b/intrinsics/probes/cp_async_bulk_tensor_reduce_inc_tile_1d.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/cp_async_bulk_tensor_reduce_inc_tile_2d.ll b/intrinsics/probes/cp_async_bulk_tensor_reduce_inc_tile_2d.ll index f8f13f03f9..842a7fffa0 100644 --- a/intrinsics/probes/cp_async_bulk_tensor_reduce_inc_tile_2d.ll +++ b/intrinsics/probes/cp_async_bulk_tensor_reduce_inc_tile_2d.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/cp_async_bulk_tensor_reduce_inc_tile_3d.ll b/intrinsics/probes/cp_async_bulk_tensor_reduce_inc_tile_3d.ll index a0c3cc6eff..3406875aa8 100644 --- a/intrinsics/probes/cp_async_bulk_tensor_reduce_inc_tile_3d.ll +++ b/intrinsics/probes/cp_async_bulk_tensor_reduce_inc_tile_3d.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/cp_async_bulk_tensor_reduce_inc_tile_4d.ll b/intrinsics/probes/cp_async_bulk_tensor_reduce_inc_tile_4d.ll index 2ea1d68278..43519c10b2 100644 --- a/intrinsics/probes/cp_async_bulk_tensor_reduce_inc_tile_4d.ll +++ b/intrinsics/probes/cp_async_bulk_tensor_reduce_inc_tile_4d.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/cp_async_bulk_tensor_reduce_inc_tile_5d.ll b/intrinsics/probes/cp_async_bulk_tensor_reduce_inc_tile_5d.ll index a73a26eab4..bf9d49c9ca 100644 --- a/intrinsics/probes/cp_async_bulk_tensor_reduce_inc_tile_5d.ll +++ b/intrinsics/probes/cp_async_bulk_tensor_reduce_inc_tile_5d.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/cp_async_bulk_tensor_reduce_max_im2col_3d.ll b/intrinsics/probes/cp_async_bulk_tensor_reduce_max_im2col_3d.ll index 74bda6e5fb..81abfdb266 100644 --- a/intrinsics/probes/cp_async_bulk_tensor_reduce_max_im2col_3d.ll +++ b/intrinsics/probes/cp_async_bulk_tensor_reduce_max_im2col_3d.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/cp_async_bulk_tensor_reduce_max_im2col_4d.ll b/intrinsics/probes/cp_async_bulk_tensor_reduce_max_im2col_4d.ll index ed67d9e5df..4c364caab9 100644 --- a/intrinsics/probes/cp_async_bulk_tensor_reduce_max_im2col_4d.ll +++ b/intrinsics/probes/cp_async_bulk_tensor_reduce_max_im2col_4d.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/cp_async_bulk_tensor_reduce_max_im2col_5d.ll b/intrinsics/probes/cp_async_bulk_tensor_reduce_max_im2col_5d.ll index 3ba8314de6..3689864a12 100644 --- a/intrinsics/probes/cp_async_bulk_tensor_reduce_max_im2col_5d.ll +++ b/intrinsics/probes/cp_async_bulk_tensor_reduce_max_im2col_5d.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/cp_async_bulk_tensor_reduce_max_tile_1d.ll b/intrinsics/probes/cp_async_bulk_tensor_reduce_max_tile_1d.ll index 196b7451af..6fe4380095 100644 --- a/intrinsics/probes/cp_async_bulk_tensor_reduce_max_tile_1d.ll +++ b/intrinsics/probes/cp_async_bulk_tensor_reduce_max_tile_1d.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/cp_async_bulk_tensor_reduce_max_tile_2d.ll b/intrinsics/probes/cp_async_bulk_tensor_reduce_max_tile_2d.ll index 3154708184..571b0d5d9c 100644 --- a/intrinsics/probes/cp_async_bulk_tensor_reduce_max_tile_2d.ll +++ b/intrinsics/probes/cp_async_bulk_tensor_reduce_max_tile_2d.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/cp_async_bulk_tensor_reduce_max_tile_3d.ll b/intrinsics/probes/cp_async_bulk_tensor_reduce_max_tile_3d.ll index c6f8e41a00..4834e84b46 100644 --- a/intrinsics/probes/cp_async_bulk_tensor_reduce_max_tile_3d.ll +++ b/intrinsics/probes/cp_async_bulk_tensor_reduce_max_tile_3d.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/cp_async_bulk_tensor_reduce_max_tile_4d.ll b/intrinsics/probes/cp_async_bulk_tensor_reduce_max_tile_4d.ll index 8c94c3fbb8..e1cb79960b 100644 --- a/intrinsics/probes/cp_async_bulk_tensor_reduce_max_tile_4d.ll +++ b/intrinsics/probes/cp_async_bulk_tensor_reduce_max_tile_4d.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/cp_async_bulk_tensor_reduce_max_tile_5d.ll b/intrinsics/probes/cp_async_bulk_tensor_reduce_max_tile_5d.ll index 7ed456fcc7..29d126e9af 100644 --- a/intrinsics/probes/cp_async_bulk_tensor_reduce_max_tile_5d.ll +++ b/intrinsics/probes/cp_async_bulk_tensor_reduce_max_tile_5d.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/cp_async_bulk_tensor_reduce_min_im2col_3d.ll b/intrinsics/probes/cp_async_bulk_tensor_reduce_min_im2col_3d.ll index f0e8afabe5..a9eb159f9d 100644 --- a/intrinsics/probes/cp_async_bulk_tensor_reduce_min_im2col_3d.ll +++ b/intrinsics/probes/cp_async_bulk_tensor_reduce_min_im2col_3d.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/cp_async_bulk_tensor_reduce_min_im2col_4d.ll b/intrinsics/probes/cp_async_bulk_tensor_reduce_min_im2col_4d.ll index c8a55af1bb..3f4b16f305 100644 --- a/intrinsics/probes/cp_async_bulk_tensor_reduce_min_im2col_4d.ll +++ b/intrinsics/probes/cp_async_bulk_tensor_reduce_min_im2col_4d.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/cp_async_bulk_tensor_reduce_min_im2col_5d.ll b/intrinsics/probes/cp_async_bulk_tensor_reduce_min_im2col_5d.ll index d4fc9f1e95..d22f56bab4 100644 --- a/intrinsics/probes/cp_async_bulk_tensor_reduce_min_im2col_5d.ll +++ b/intrinsics/probes/cp_async_bulk_tensor_reduce_min_im2col_5d.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/cp_async_bulk_tensor_reduce_min_tile_1d.ll b/intrinsics/probes/cp_async_bulk_tensor_reduce_min_tile_1d.ll index d10d9799d9..64ee98ea26 100644 --- a/intrinsics/probes/cp_async_bulk_tensor_reduce_min_tile_1d.ll +++ b/intrinsics/probes/cp_async_bulk_tensor_reduce_min_tile_1d.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/cp_async_bulk_tensor_reduce_min_tile_2d.ll b/intrinsics/probes/cp_async_bulk_tensor_reduce_min_tile_2d.ll index f3a9431031..1c5e985782 100644 --- a/intrinsics/probes/cp_async_bulk_tensor_reduce_min_tile_2d.ll +++ b/intrinsics/probes/cp_async_bulk_tensor_reduce_min_tile_2d.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/cp_async_bulk_tensor_reduce_min_tile_3d.ll b/intrinsics/probes/cp_async_bulk_tensor_reduce_min_tile_3d.ll index e21f985e63..bb547ee7f7 100644 --- a/intrinsics/probes/cp_async_bulk_tensor_reduce_min_tile_3d.ll +++ b/intrinsics/probes/cp_async_bulk_tensor_reduce_min_tile_3d.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/cp_async_bulk_tensor_reduce_min_tile_4d.ll b/intrinsics/probes/cp_async_bulk_tensor_reduce_min_tile_4d.ll index 9785182c30..56d1e95d1f 100644 --- a/intrinsics/probes/cp_async_bulk_tensor_reduce_min_tile_4d.ll +++ b/intrinsics/probes/cp_async_bulk_tensor_reduce_min_tile_4d.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/cp_async_bulk_tensor_reduce_min_tile_5d.ll b/intrinsics/probes/cp_async_bulk_tensor_reduce_min_tile_5d.ll index 7ee8b90337..11359be09c 100644 --- a/intrinsics/probes/cp_async_bulk_tensor_reduce_min_tile_5d.ll +++ b/intrinsics/probes/cp_async_bulk_tensor_reduce_min_tile_5d.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/cp_async_bulk_tensor_reduce_or_im2col_3d.ll b/intrinsics/probes/cp_async_bulk_tensor_reduce_or_im2col_3d.ll index d05e05aba2..26bd86da22 100644 --- a/intrinsics/probes/cp_async_bulk_tensor_reduce_or_im2col_3d.ll +++ b/intrinsics/probes/cp_async_bulk_tensor_reduce_or_im2col_3d.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/cp_async_bulk_tensor_reduce_or_im2col_4d.ll b/intrinsics/probes/cp_async_bulk_tensor_reduce_or_im2col_4d.ll index 1ca10352e0..a9bbc60a73 100644 --- a/intrinsics/probes/cp_async_bulk_tensor_reduce_or_im2col_4d.ll +++ b/intrinsics/probes/cp_async_bulk_tensor_reduce_or_im2col_4d.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/cp_async_bulk_tensor_reduce_or_im2col_5d.ll b/intrinsics/probes/cp_async_bulk_tensor_reduce_or_im2col_5d.ll index 875b3d012a..a3dd3be9f6 100644 --- a/intrinsics/probes/cp_async_bulk_tensor_reduce_or_im2col_5d.ll +++ b/intrinsics/probes/cp_async_bulk_tensor_reduce_or_im2col_5d.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/cp_async_bulk_tensor_reduce_or_tile_1d.ll b/intrinsics/probes/cp_async_bulk_tensor_reduce_or_tile_1d.ll index 9afc5c53f7..cb14c02075 100644 --- a/intrinsics/probes/cp_async_bulk_tensor_reduce_or_tile_1d.ll +++ b/intrinsics/probes/cp_async_bulk_tensor_reduce_or_tile_1d.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/cp_async_bulk_tensor_reduce_or_tile_2d.ll b/intrinsics/probes/cp_async_bulk_tensor_reduce_or_tile_2d.ll index 09c9d9ecf1..052dfb42c4 100644 --- a/intrinsics/probes/cp_async_bulk_tensor_reduce_or_tile_2d.ll +++ b/intrinsics/probes/cp_async_bulk_tensor_reduce_or_tile_2d.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/cp_async_bulk_tensor_reduce_or_tile_3d.ll b/intrinsics/probes/cp_async_bulk_tensor_reduce_or_tile_3d.ll index 839e1cd889..2d5b830501 100644 --- a/intrinsics/probes/cp_async_bulk_tensor_reduce_or_tile_3d.ll +++ b/intrinsics/probes/cp_async_bulk_tensor_reduce_or_tile_3d.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/cp_async_bulk_tensor_reduce_or_tile_4d.ll b/intrinsics/probes/cp_async_bulk_tensor_reduce_or_tile_4d.ll index 4ddf3ae90e..f90cdb00d1 100644 --- a/intrinsics/probes/cp_async_bulk_tensor_reduce_or_tile_4d.ll +++ b/intrinsics/probes/cp_async_bulk_tensor_reduce_or_tile_4d.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/cp_async_bulk_tensor_reduce_or_tile_5d.ll b/intrinsics/probes/cp_async_bulk_tensor_reduce_or_tile_5d.ll index d2c961edff..8286cd5c30 100644 --- a/intrinsics/probes/cp_async_bulk_tensor_reduce_or_tile_5d.ll +++ b/intrinsics/probes/cp_async_bulk_tensor_reduce_or_tile_5d.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/cp_async_bulk_tensor_reduce_xor_im2col_3d.ll b/intrinsics/probes/cp_async_bulk_tensor_reduce_xor_im2col_3d.ll index 26788f2e9b..0701e6f4fd 100644 --- a/intrinsics/probes/cp_async_bulk_tensor_reduce_xor_im2col_3d.ll +++ b/intrinsics/probes/cp_async_bulk_tensor_reduce_xor_im2col_3d.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/cp_async_bulk_tensor_reduce_xor_im2col_4d.ll b/intrinsics/probes/cp_async_bulk_tensor_reduce_xor_im2col_4d.ll index 24a43f49c7..d0e5629c47 100644 --- a/intrinsics/probes/cp_async_bulk_tensor_reduce_xor_im2col_4d.ll +++ b/intrinsics/probes/cp_async_bulk_tensor_reduce_xor_im2col_4d.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/cp_async_bulk_tensor_reduce_xor_im2col_5d.ll b/intrinsics/probes/cp_async_bulk_tensor_reduce_xor_im2col_5d.ll index 4d73fbb2cc..8d0036ba00 100644 --- a/intrinsics/probes/cp_async_bulk_tensor_reduce_xor_im2col_5d.ll +++ b/intrinsics/probes/cp_async_bulk_tensor_reduce_xor_im2col_5d.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/cp_async_bulk_tensor_reduce_xor_tile_1d.ll b/intrinsics/probes/cp_async_bulk_tensor_reduce_xor_tile_1d.ll index e97b90efc1..a25538e69d 100644 --- a/intrinsics/probes/cp_async_bulk_tensor_reduce_xor_tile_1d.ll +++ b/intrinsics/probes/cp_async_bulk_tensor_reduce_xor_tile_1d.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/cp_async_bulk_tensor_reduce_xor_tile_2d.ll b/intrinsics/probes/cp_async_bulk_tensor_reduce_xor_tile_2d.ll index b90fe9fca4..67c3bda50a 100644 --- a/intrinsics/probes/cp_async_bulk_tensor_reduce_xor_tile_2d.ll +++ b/intrinsics/probes/cp_async_bulk_tensor_reduce_xor_tile_2d.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/cp_async_bulk_tensor_reduce_xor_tile_3d.ll b/intrinsics/probes/cp_async_bulk_tensor_reduce_xor_tile_3d.ll index fb16fb27ac..0692eef51e 100644 --- a/intrinsics/probes/cp_async_bulk_tensor_reduce_xor_tile_3d.ll +++ b/intrinsics/probes/cp_async_bulk_tensor_reduce_xor_tile_3d.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/cp_async_bulk_tensor_reduce_xor_tile_4d.ll b/intrinsics/probes/cp_async_bulk_tensor_reduce_xor_tile_4d.ll index ee0a56ec7d..96c21c2446 100644 --- a/intrinsics/probes/cp_async_bulk_tensor_reduce_xor_tile_4d.ll +++ b/intrinsics/probes/cp_async_bulk_tensor_reduce_xor_tile_4d.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/cp_async_bulk_tensor_reduce_xor_tile_5d.ll b/intrinsics/probes/cp_async_bulk_tensor_reduce_xor_tile_5d.ll index db63970f08..0ff1a1d0e2 100644 --- a/intrinsics/probes/cp_async_bulk_tensor_reduce_xor_tile_5d.ll +++ b/intrinsics/probes/cp_async_bulk_tensor_reduce_xor_tile_5d.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/cp_async_bulk_wait_group.ll b/intrinsics/probes/cp_async_bulk_wait_group.ll index 39867e1031..817a849f54 100644 --- a/intrinsics/probes/cp_async_bulk_wait_group.ll +++ b/intrinsics/probes/cp_async_bulk_wait_group.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/cp_async_bulk_wait_group_read.ll b/intrinsics/probes/cp_async_bulk_wait_group_read.ll index c9cc649e1b..3de9ad917b 100644 --- a/intrinsics/probes/cp_async_bulk_wait_group_read.ll +++ b/intrinsics/probes/cp_async_bulk_wait_group_read.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/cp_async_ca_16.ll b/intrinsics/probes/cp_async_ca_16.ll index 649959d046..8a155688fb 100644 --- a/intrinsics/probes/cp_async_ca_16.ll +++ b/intrinsics/probes/cp_async_ca_16.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/cp_async_ca_4.ll b/intrinsics/probes/cp_async_ca_4.ll index ea4da94141..87f9692f2a 100644 --- a/intrinsics/probes/cp_async_ca_4.ll +++ b/intrinsics/probes/cp_async_ca_4.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/cp_async_ca_8.ll b/intrinsics/probes/cp_async_ca_8.ll index 9c41c6cbae..4a2dceea26 100644 --- a/intrinsics/probes/cp_async_ca_8.ll +++ b/intrinsics/probes/cp_async_ca_8.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/cp_async_ca_zfill_16.ll b/intrinsics/probes/cp_async_ca_zfill_16.ll index 435cbbabb8..32b51c54ad 100644 --- a/intrinsics/probes/cp_async_ca_zfill_16.ll +++ b/intrinsics/probes/cp_async_ca_zfill_16.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/cp_async_ca_zfill_4.ll b/intrinsics/probes/cp_async_ca_zfill_4.ll index 1ad3cb8d26..ed3852f884 100644 --- a/intrinsics/probes/cp_async_ca_zfill_4.ll +++ b/intrinsics/probes/cp_async_ca_zfill_4.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/cp_async_ca_zfill_8.ll b/intrinsics/probes/cp_async_ca_zfill_8.ll index b7b0473e83..00b2b03731 100644 --- a/intrinsics/probes/cp_async_ca_zfill_8.ll +++ b/intrinsics/probes/cp_async_ca_zfill_8.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/cp_async_cg_16.ll b/intrinsics/probes/cp_async_cg_16.ll index fdea5cebdb..4e29b9f426 100644 --- a/intrinsics/probes/cp_async_cg_16.ll +++ b/intrinsics/probes/cp_async_cg_16.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/cp_async_cg_zfill_16.ll b/intrinsics/probes/cp_async_cg_zfill_16.ll index 8084d956ae..6402a4ff1f 100644 --- a/intrinsics/probes/cp_async_cg_zfill_16.ll +++ b/intrinsics/probes/cp_async_cg_zfill_16.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/cp_async_commit_group.ll b/intrinsics/probes/cp_async_commit_group.ll index 9372fd9a7a..a98968e898 100644 --- a/intrinsics/probes/cp_async_commit_group.ll +++ b/intrinsics/probes/cp_async_commit_group.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/cp_async_mbarrier_arrive.ll b/intrinsics/probes/cp_async_mbarrier_arrive.ll index da646f4dda..7bcd301844 100644 --- a/intrinsics/probes/cp_async_mbarrier_arrive.ll +++ b/intrinsics/probes/cp_async_mbarrier_arrive.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/cp_async_mbarrier_arrive_noinc.ll b/intrinsics/probes/cp_async_mbarrier_arrive_noinc.ll index dc6cbdbaea..242fa43511 100644 --- a/intrinsics/probes/cp_async_mbarrier_arrive_noinc.ll +++ b/intrinsics/probes/cp_async_mbarrier_arrive_noinc.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/cp_async_mbarrier_arrive_noinc_shared.ll b/intrinsics/probes/cp_async_mbarrier_arrive_noinc_shared.ll index 0922391948..c9380091fc 100644 --- a/intrinsics/probes/cp_async_mbarrier_arrive_noinc_shared.ll +++ b/intrinsics/probes/cp_async_mbarrier_arrive_noinc_shared.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/cp_async_mbarrier_arrive_shared.ll b/intrinsics/probes/cp_async_mbarrier_arrive_shared.ll index 3554e7e809..0e1adc8f8d 100644 --- a/intrinsics/probes/cp_async_mbarrier_arrive_shared.ll +++ b/intrinsics/probes/cp_async_mbarrier_arrive_shared.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/cp_async_wait_all.ll b/intrinsics/probes/cp_async_wait_all.ll index ca072fc33b..dc7fe535b9 100644 --- a/intrinsics/probes/cp_async_wait_all.ll +++ b/intrinsics/probes/cp_async_wait_all.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/cp_async_wait_group.ll b/intrinsics/probes/cp_async_wait_group.ll index f4818ca983..b1a4100831 100644 --- a/intrinsics/probes/cp_async_wait_group.ll +++ b/intrinsics/probes/cp_async_wait_group.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/cvt_f16x2_f32.ll b/intrinsics/probes/cvt_f16x2_f32.ll index c6e0b02680..8f8aa60d6d 100644 --- a/intrinsics/probes/cvt_f16x2_f32.ll +++ b/intrinsics/probes/cvt_f16x2_f32.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/cvt_f32x2_bf16x2.ll b/intrinsics/probes/cvt_f32x2_bf16x2.ll index bb6745d2a8..e6c5af4b3f 100644 --- a/intrinsics/probes/cvt_f32x2_bf16x2.ll +++ b/intrinsics/probes/cvt_f32x2_bf16x2.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/cvt_rn_f16x2_e4m3x2.ll b/intrinsics/probes/cvt_rn_f16x2_e4m3x2.ll index 5b1c2418c2..84af74c4c1 100644 --- a/intrinsics/probes/cvt_rn_f16x2_e4m3x2.ll +++ b/intrinsics/probes/cvt_rn_f16x2_e4m3x2.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/cvt_rn_f16x2_e5m2x2.ll b/intrinsics/probes/cvt_rn_f16x2_e5m2x2.ll index a39b5264d1..f3102bf9ec 100644 --- a/intrinsics/probes/cvt_rn_f16x2_e5m2x2.ll +++ b/intrinsics/probes/cvt_rn_f16x2_e5m2x2.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/cvt_rn_relu_bf16x2_f32.ll b/intrinsics/probes/cvt_rn_relu_bf16x2_f32.ll index 6c3952878d..9d0e665e7d 100644 --- a/intrinsics/probes/cvt_rn_relu_bf16x2_f32.ll +++ b/intrinsics/probes/cvt_rn_relu_bf16x2_f32.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/cvt_rn_relu_f16x2_e4m3x2.ll b/intrinsics/probes/cvt_rn_relu_f16x2_e4m3x2.ll index c5449d4450..4a978825e7 100644 --- a/intrinsics/probes/cvt_rn_relu_f16x2_e4m3x2.ll +++ b/intrinsics/probes/cvt_rn_relu_f16x2_e4m3x2.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/cvt_rn_relu_f16x2_e5m2x2.ll b/intrinsics/probes/cvt_rn_relu_f16x2_e5m2x2.ll index 958c35bb04..bd0b18f534 100644 --- a/intrinsics/probes/cvt_rn_relu_f16x2_e5m2x2.ll +++ b/intrinsics/probes/cvt_rn_relu_f16x2_e5m2x2.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/cvt_rn_relu_f16x2_f32.ll b/intrinsics/probes/cvt_rn_relu_f16x2_f32.ll index 1cdc7426c4..d29096fb6e 100644 --- a/intrinsics/probes/cvt_rn_relu_f16x2_f32.ll +++ b/intrinsics/probes/cvt_rn_relu_f16x2_f32.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/cvt_rn_relu_satfinite_tf32_f32.ll b/intrinsics/probes/cvt_rn_relu_satfinite_tf32_f32.ll index 014ac9f206..bea101b8a2 100644 --- a/intrinsics/probes/cvt_rn_relu_satfinite_tf32_f32.ll +++ b/intrinsics/probes/cvt_rn_relu_satfinite_tf32_f32.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/cvt_rn_relu_tf32_f32.ll b/intrinsics/probes/cvt_rn_relu_tf32_f32.ll index f37c53b87c..42244d6514 100644 --- a/intrinsics/probes/cvt_rn_relu_tf32_f32.ll +++ b/intrinsics/probes/cvt_rn_relu_tf32_f32.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/cvt_rn_satfinite_e4m3x2_f16x2.ll b/intrinsics/probes/cvt_rn_satfinite_e4m3x2_f16x2.ll index d3063de384..24aaa12ab5 100644 --- a/intrinsics/probes/cvt_rn_satfinite_e4m3x2_f16x2.ll +++ b/intrinsics/probes/cvt_rn_satfinite_e4m3x2_f16x2.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/cvt_rn_satfinite_e4m3x2_f32.ll b/intrinsics/probes/cvt_rn_satfinite_e4m3x2_f32.ll index 9dad331b13..0fed1a3da3 100644 --- a/intrinsics/probes/cvt_rn_satfinite_e4m3x2_f32.ll +++ b/intrinsics/probes/cvt_rn_satfinite_e4m3x2_f32.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/cvt_rn_satfinite_e5m2x2_f16x2.ll b/intrinsics/probes/cvt_rn_satfinite_e5m2x2_f16x2.ll index ec3857e44a..8d2972f890 100644 --- a/intrinsics/probes/cvt_rn_satfinite_e5m2x2_f16x2.ll +++ b/intrinsics/probes/cvt_rn_satfinite_e5m2x2_f16x2.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/cvt_rn_satfinite_e5m2x2_f32.ll b/intrinsics/probes/cvt_rn_satfinite_e5m2x2_f32.ll index 3839d96a2a..ba660340cb 100644 --- a/intrinsics/probes/cvt_rn_satfinite_e5m2x2_f32.ll +++ b/intrinsics/probes/cvt_rn_satfinite_e5m2x2_f32.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/cvt_rn_satfinite_relu_e4m3x2_f16x2.ll b/intrinsics/probes/cvt_rn_satfinite_relu_e4m3x2_f16x2.ll index 6f92240dce..ce44fe8b23 100644 --- a/intrinsics/probes/cvt_rn_satfinite_relu_e4m3x2_f16x2.ll +++ b/intrinsics/probes/cvt_rn_satfinite_relu_e4m3x2_f16x2.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/cvt_rn_satfinite_relu_e4m3x2_f32.ll b/intrinsics/probes/cvt_rn_satfinite_relu_e4m3x2_f32.ll index 186d361845..b19072a683 100644 --- a/intrinsics/probes/cvt_rn_satfinite_relu_e4m3x2_f32.ll +++ b/intrinsics/probes/cvt_rn_satfinite_relu_e4m3x2_f32.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/cvt_rn_satfinite_relu_e5m2x2_f16x2.ll b/intrinsics/probes/cvt_rn_satfinite_relu_e5m2x2_f16x2.ll index 6b7a922ef4..d96d378cb6 100644 --- a/intrinsics/probes/cvt_rn_satfinite_relu_e5m2x2_f16x2.ll +++ b/intrinsics/probes/cvt_rn_satfinite_relu_e5m2x2_f16x2.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/cvt_rn_satfinite_relu_e5m2x2_f32.ll b/intrinsics/probes/cvt_rn_satfinite_relu_e5m2x2_f32.ll index 8af268b1cb..49552a30da 100644 --- a/intrinsics/probes/cvt_rn_satfinite_relu_e5m2x2_f32.ll +++ b/intrinsics/probes/cvt_rn_satfinite_relu_e5m2x2_f32.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/cvt_rn_satfinite_tf32_f32.ll b/intrinsics/probes/cvt_rn_satfinite_tf32_f32.ll index 881cc88083..0a81e4342a 100644 --- a/intrinsics/probes/cvt_rn_satfinite_tf32_f32.ll +++ b/intrinsics/probes/cvt_rn_satfinite_tf32_f32.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/cvt_rn_tf32_f32.ll b/intrinsics/probes/cvt_rn_tf32_f32.ll index 923ce07299..351069ffb9 100644 --- a/intrinsics/probes/cvt_rn_tf32_f32.ll +++ b/intrinsics/probes/cvt_rn_tf32_f32.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/cvt_rna_satfinite_tf32_f32.ll b/intrinsics/probes/cvt_rna_satfinite_tf32_f32.ll index 29d1a7452c..a27afe7854 100644 --- a/intrinsics/probes/cvt_rna_satfinite_tf32_f32.ll +++ b/intrinsics/probes/cvt_rna_satfinite_tf32_f32.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/cvt_rna_tf32_f32.ll b/intrinsics/probes/cvt_rna_tf32_f32.ll index 8f4feb6e78..8035806371 100644 --- a/intrinsics/probes/cvt_rna_tf32_f32.ll +++ b/intrinsics/probes/cvt_rna_tf32_f32.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/cvt_rz_bf16x2_f32.ll b/intrinsics/probes/cvt_rz_bf16x2_f32.ll index ca7a297ced..24a369bcf9 100644 --- a/intrinsics/probes/cvt_rz_bf16x2_f32.ll +++ b/intrinsics/probes/cvt_rz_bf16x2_f32.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/cvt_rz_f16x2_f32.ll b/intrinsics/probes/cvt_rz_f16x2_f32.ll index 1751aeb0ad..0d404ec155 100644 --- a/intrinsics/probes/cvt_rz_f16x2_f32.ll +++ b/intrinsics/probes/cvt_rz_f16x2_f32.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/cvt_rz_relu_satfinite_tf32_f32.ll b/intrinsics/probes/cvt_rz_relu_satfinite_tf32_f32.ll index 5f9a7ce60d..d8585acdad 100644 --- a/intrinsics/probes/cvt_rz_relu_satfinite_tf32_f32.ll +++ b/intrinsics/probes/cvt_rz_relu_satfinite_tf32_f32.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/cvt_rz_relu_tf32_f32.ll b/intrinsics/probes/cvt_rz_relu_tf32_f32.ll index 3bdeb48f4e..27c5c235f7 100644 --- a/intrinsics/probes/cvt_rz_relu_tf32_f32.ll +++ b/intrinsics/probes/cvt_rz_relu_tf32_f32.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/cvt_rz_satfinite_tf32_f32.ll b/intrinsics/probes/cvt_rz_satfinite_tf32_f32.ll index 0ba8ee73e8..a4bda0c5c2 100644 --- a/intrinsics/probes/cvt_rz_satfinite_tf32_f32.ll +++ b/intrinsics/probes/cvt_rz_satfinite_tf32_f32.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/cvt_rz_tf32_f32.ll b/intrinsics/probes/cvt_rz_tf32_f32.ll index 7aab20e673..a9ab57a6af 100644 --- a/intrinsics/probes/cvt_rz_tf32_f32.ll +++ b/intrinsics/probes/cvt_rz_tf32_f32.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/div_rm_f32.ll b/intrinsics/probes/div_rm_f32.ll index 5646870571..a0bc8ecfcb 100644 --- a/intrinsics/probes/div_rm_f32.ll +++ b/intrinsics/probes/div_rm_f32.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/div_rm_f64.ll b/intrinsics/probes/div_rm_f64.ll index 9c947d780a..aea691adce 100644 --- a/intrinsics/probes/div_rm_f64.ll +++ b/intrinsics/probes/div_rm_f64.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/div_rm_ftz_f32.ll b/intrinsics/probes/div_rm_ftz_f32.ll index 094c5829eb..4ef89b2b38 100644 --- a/intrinsics/probes/div_rm_ftz_f32.ll +++ b/intrinsics/probes/div_rm_ftz_f32.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/div_rn_f32.ll b/intrinsics/probes/div_rn_f32.ll index 1e0832a11f..187ff42cd5 100644 --- a/intrinsics/probes/div_rn_f32.ll +++ b/intrinsics/probes/div_rn_f32.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/div_rn_f64.ll b/intrinsics/probes/div_rn_f64.ll index 6148ffe124..5f613b977f 100644 --- a/intrinsics/probes/div_rn_f64.ll +++ b/intrinsics/probes/div_rn_f64.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/div_rn_ftz_f32.ll b/intrinsics/probes/div_rn_ftz_f32.ll index 1536b1dbda..4a0e5253d2 100644 --- a/intrinsics/probes/div_rn_ftz_f32.ll +++ b/intrinsics/probes/div_rn_ftz_f32.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/div_rp_f32.ll b/intrinsics/probes/div_rp_f32.ll index 0f8b84dc31..5d1a20c704 100644 --- a/intrinsics/probes/div_rp_f32.ll +++ b/intrinsics/probes/div_rp_f32.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/div_rp_f64.ll b/intrinsics/probes/div_rp_f64.ll index 6ce41e4e4b..eed39dc0cf 100644 --- a/intrinsics/probes/div_rp_f64.ll +++ b/intrinsics/probes/div_rp_f64.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/div_rp_ftz_f32.ll b/intrinsics/probes/div_rp_ftz_f32.ll index dca31aa350..7399ccfd19 100644 --- a/intrinsics/probes/div_rp_ftz_f32.ll +++ b/intrinsics/probes/div_rp_ftz_f32.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/div_rz_f32.ll b/intrinsics/probes/div_rz_f32.ll index dc0338e2a3..afab7aa756 100644 --- a/intrinsics/probes/div_rz_f32.ll +++ b/intrinsics/probes/div_rz_f32.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/div_rz_f64.ll b/intrinsics/probes/div_rz_f64.ll index 38cee68728..5e135e77ed 100644 --- a/intrinsics/probes/div_rz_f64.ll +++ b/intrinsics/probes/div_rz_f64.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/div_rz_ftz_f32.ll b/intrinsics/probes/div_rz_ftz_f32.ll index 19fbdad954..3c2155e031 100644 --- a/intrinsics/probes/div_rz_ftz_f32.ll +++ b/intrinsics/probes/div_rz_ftz_f32.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/dp2a_s32.ll b/intrinsics/probes/dp2a_s32.ll index 5e3e28347f..07aa29a29f 100644 --- a/intrinsics/probes/dp2a_s32.ll +++ b/intrinsics/probes/dp2a_s32.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/dp2a_u32.ll b/intrinsics/probes/dp2a_u32.ll index 66cefe047e..93a160c924 100644 --- a/intrinsics/probes/dp2a_u32.ll +++ b/intrinsics/probes/dp2a_u32.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/dp4a_s32.ll b/intrinsics/probes/dp4a_s32.ll index 642347dffb..886c3c8d99 100644 --- a/intrinsics/probes/dp4a_s32.ll +++ b/intrinsics/probes/dp4a_s32.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/dp4a_u32.ll b/intrinsics/probes/dp4a_u32.ll index 239581854a..7fd82e566f 100644 --- a/intrinsics/probes/dp4a_u32.ll +++ b/intrinsics/probes/dp4a_u32.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/dsmem_read_u32.ll b/intrinsics/probes/dsmem_read_u32.ll index 219550cdba..368f67ccdc 100644 --- a/intrinsics/probes/dsmem_read_u32.ll +++ b/intrinsics/probes/dsmem_read_u32.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/dynamic_smem_size.lib_nvvm.ll b/intrinsics/probes/dynamic_smem_size.lib_nvvm.ll index 2ebad858c2..6a827c5447 100644 --- a/intrinsics/probes/dynamic_smem_size.lib_nvvm.ll +++ b/intrinsics/probes/dynamic_smem_size.lib_nvvm.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/dynamic_smem_size.llvm_nvptx.ll b/intrinsics/probes/dynamic_smem_size.llvm_nvptx.ll index b499bcb58f..866d4c9319 100644 --- a/intrinsics/probes/dynamic_smem_size.llvm_nvptx.ll +++ b/intrinsics/probes/dynamic_smem_size.llvm_nvptx.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/elect_sync.lib_nvvm.ll b/intrinsics/probes/elect_sync.lib_nvvm.ll index 7aa298db1c..dcc9fa9f01 100644 --- a/intrinsics/probes/elect_sync.lib_nvvm.ll +++ b/intrinsics/probes/elect_sync.lib_nvvm.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/elect_sync.llvm_nvptx.ll b/intrinsics/probes/elect_sync.llvm_nvptx.ll index 1984124ff6..d4234e2016 100644 --- a/intrinsics/probes/elect_sync.llvm_nvptx.ll +++ b/intrinsics/probes/elect_sync.llvm_nvptx.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/envreg1.lib_nvvm.ll b/intrinsics/probes/envreg1.lib_nvvm.ll index e28e28049a..0b4d1d662e 100644 --- a/intrinsics/probes/envreg1.lib_nvvm.ll +++ b/intrinsics/probes/envreg1.lib_nvvm.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/envreg1.llvm_nvptx.ll b/intrinsics/probes/envreg1.llvm_nvptx.ll index 172f3c0322..d4544b29dc 100644 --- a/intrinsics/probes/envreg1.llvm_nvptx.ll +++ b/intrinsics/probes/envreg1.llvm_nvptx.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/envreg2.lib_nvvm.ll b/intrinsics/probes/envreg2.lib_nvvm.ll index c8ab24246d..00a1a731f4 100644 --- a/intrinsics/probes/envreg2.lib_nvvm.ll +++ b/intrinsics/probes/envreg2.lib_nvvm.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/envreg2.llvm_nvptx.ll b/intrinsics/probes/envreg2.llvm_nvptx.ll index 5830dbe9f6..30778c758e 100644 --- a/intrinsics/probes/envreg2.llvm_nvptx.ll +++ b/intrinsics/probes/envreg2.llvm_nvptx.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/ex2_approx_f16.ll b/intrinsics/probes/ex2_approx_f16.ll index 283e9292f8..cfb96594ae 100644 --- a/intrinsics/probes/ex2_approx_f16.ll +++ b/intrinsics/probes/ex2_approx_f16.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/ex2_approx_f32.ll b/intrinsics/probes/ex2_approx_f32.ll index a17fcbbdfa..cf2487ade1 100644 --- a/intrinsics/probes/ex2_approx_f32.ll +++ b/intrinsics/probes/ex2_approx_f32.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/ex2_approx_ftz_f32.ll b/intrinsics/probes/ex2_approx_ftz_f32.ll index 1eec14b71e..3a8d7d2a2d 100644 --- a/intrinsics/probes/ex2_approx_ftz_f32.ll +++ b/intrinsics/probes/ex2_approx_ftz_f32.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/fence_mbarrier_init_release_cluster.ll b/intrinsics/probes/fence_mbarrier_init_release_cluster.ll index 86ddce7285..eab4479362 100644 --- a/intrinsics/probes/fence_mbarrier_init_release_cluster.ll +++ b/intrinsics/probes/fence_mbarrier_init_release_cluster.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/fence_proxy_async_generic_acquire_shared_cluster_cluster.ll b/intrinsics/probes/fence_proxy_async_generic_acquire_shared_cluster_cluster.ll index ee14c9dafa..d476c5d004 100644 --- a/intrinsics/probes/fence_proxy_async_generic_acquire_shared_cluster_cluster.ll +++ b/intrinsics/probes/fence_proxy_async_generic_acquire_shared_cluster_cluster.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/fence_proxy_async_generic_release_shared_cta_cluster.ll b/intrinsics/probes/fence_proxy_async_generic_release_shared_cta_cluster.ll index 6d14f6fc8c..a71788d7a9 100644 --- a/intrinsics/probes/fence_proxy_async_generic_release_shared_cta_cluster.ll +++ b/intrinsics/probes/fence_proxy_async_generic_release_shared_cta_cluster.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/fence_proxy_async_shared_cta.ll b/intrinsics/probes/fence_proxy_async_shared_cta.ll index 2ab7e57c45..40d57a2800 100644 --- a/intrinsics/probes/fence_proxy_async_shared_cta.ll +++ b/intrinsics/probes/fence_proxy_async_shared_cta.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/fence_proxy_tensormap_generic_acquire_cluster.ll b/intrinsics/probes/fence_proxy_tensormap_generic_acquire_cluster.ll index 9aebcca04a..c55e31cd69 100644 --- a/intrinsics/probes/fence_proxy_tensormap_generic_acquire_cluster.ll +++ b/intrinsics/probes/fence_proxy_tensormap_generic_acquire_cluster.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/fence_proxy_tensormap_generic_acquire_cta.ll b/intrinsics/probes/fence_proxy_tensormap_generic_acquire_cta.ll index cba4b3b19e..635c774de4 100644 --- a/intrinsics/probes/fence_proxy_tensormap_generic_acquire_cta.ll +++ b/intrinsics/probes/fence_proxy_tensormap_generic_acquire_cta.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/fence_proxy_tensormap_generic_acquire_gpu.ll b/intrinsics/probes/fence_proxy_tensormap_generic_acquire_gpu.ll index ca57cf9904..9854fb9677 100644 --- a/intrinsics/probes/fence_proxy_tensormap_generic_acquire_gpu.ll +++ b/intrinsics/probes/fence_proxy_tensormap_generic_acquire_gpu.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/fence_proxy_tensormap_generic_acquire_system.ll b/intrinsics/probes/fence_proxy_tensormap_generic_acquire_system.ll index 4ed9b268c3..0f5d021b1a 100644 --- a/intrinsics/probes/fence_proxy_tensormap_generic_acquire_system.ll +++ b/intrinsics/probes/fence_proxy_tensormap_generic_acquire_system.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/fence_proxy_tensormap_generic_release_cluster.ll b/intrinsics/probes/fence_proxy_tensormap_generic_release_cluster.ll index d0a3afd54d..00d2671a0b 100644 --- a/intrinsics/probes/fence_proxy_tensormap_generic_release_cluster.ll +++ b/intrinsics/probes/fence_proxy_tensormap_generic_release_cluster.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/fence_proxy_tensormap_generic_release_cta.ll b/intrinsics/probes/fence_proxy_tensormap_generic_release_cta.ll index 444e5fc733..6d95441e19 100644 --- a/intrinsics/probes/fence_proxy_tensormap_generic_release_cta.ll +++ b/intrinsics/probes/fence_proxy_tensormap_generic_release_cta.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/fence_proxy_tensormap_generic_release_gpu.ll b/intrinsics/probes/fence_proxy_tensormap_generic_release_gpu.ll index 12dc46d280..81fb5d11d9 100644 --- a/intrinsics/probes/fence_proxy_tensormap_generic_release_gpu.ll +++ b/intrinsics/probes/fence_proxy_tensormap_generic_release_gpu.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/fence_proxy_tensormap_generic_release_system.ll b/intrinsics/probes/fence_proxy_tensormap_generic_release_system.ll index 0802f25363..55be8c9857 100644 --- a/intrinsics/probes/fence_proxy_tensormap_generic_release_system.ll +++ b/intrinsics/probes/fence_proxy_tensormap_generic_release_system.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/fma_bf16x2.ll b/intrinsics/probes/fma_bf16x2.ll index 9bcd0d8136..cd2c0f1f63 100644 --- a/intrinsics/probes/fma_bf16x2.ll +++ b/intrinsics/probes/fma_bf16x2.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/fma_f16x2.ll b/intrinsics/probes/fma_f16x2.ll index 7d816eba48..25def71a0e 100644 --- a/intrinsics/probes/fma_f16x2.ll +++ b/intrinsics/probes/fma_f16x2.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/fma_f32x2.ll b/intrinsics/probes/fma_f32x2.ll index e880febb53..6f0136b006 100644 --- a/intrinsics/probes/fma_f32x2.ll +++ b/intrinsics/probes/fma_f32x2.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/fma_ftz_f16x2.ll b/intrinsics/probes/fma_ftz_f16x2.ll index fd97f79de2..47d4872763 100644 --- a/intrinsics/probes/fma_ftz_f16x2.ll +++ b/intrinsics/probes/fma_ftz_f16x2.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/fma_ftz_f32x2.ll b/intrinsics/probes/fma_ftz_f32x2.ll index 110354f1ca..b678d0225a 100644 --- a/intrinsics/probes/fma_ftz_f32x2.ll +++ b/intrinsics/probes/fma_ftz_f32x2.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/fma_ftz_relu_f16x2.ll b/intrinsics/probes/fma_ftz_relu_f16x2.ll index e3bec8f4de..abbd6dfbe1 100644 --- a/intrinsics/probes/fma_ftz_relu_f16x2.ll +++ b/intrinsics/probes/fma_ftz_relu_f16x2.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/fma_ftz_sat_f16x2.ll b/intrinsics/probes/fma_ftz_sat_f16x2.ll index 377c01190c..c11c1a2c7a 100644 --- a/intrinsics/probes/fma_ftz_sat_f16x2.ll +++ b/intrinsics/probes/fma_ftz_sat_f16x2.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/fma_relu_bf16x2.ll b/intrinsics/probes/fma_relu_bf16x2.ll index 40dee20a33..ec89e21721 100644 --- a/intrinsics/probes/fma_relu_bf16x2.ll +++ b/intrinsics/probes/fma_relu_bf16x2.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/fma_relu_f16x2.ll b/intrinsics/probes/fma_relu_f16x2.ll index 190d0e9ebd..00f15ff50d 100644 --- a/intrinsics/probes/fma_relu_f16x2.ll +++ b/intrinsics/probes/fma_relu_f16x2.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/fma_rm_f32.ll b/intrinsics/probes/fma_rm_f32.ll index 6b97f5383d..df54fdaef7 100644 --- a/intrinsics/probes/fma_rm_f32.ll +++ b/intrinsics/probes/fma_rm_f32.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/fma_rm_f64.ll b/intrinsics/probes/fma_rm_f64.ll index c32d9e952c..25d4dadba7 100644 --- a/intrinsics/probes/fma_rm_f64.ll +++ b/intrinsics/probes/fma_rm_f64.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/fma_rm_ftz_f32.ll b/intrinsics/probes/fma_rm_ftz_f32.ll index 9012e3def0..97695c4d9c 100644 --- a/intrinsics/probes/fma_rm_ftz_f32.ll +++ b/intrinsics/probes/fma_rm_ftz_f32.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/fma_rm_ftz_sat_f32.ll b/intrinsics/probes/fma_rm_ftz_sat_f32.ll index c3e4737996..a760385561 100644 --- a/intrinsics/probes/fma_rm_ftz_sat_f32.ll +++ b/intrinsics/probes/fma_rm_ftz_sat_f32.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/fma_rm_sat_f32.ll b/intrinsics/probes/fma_rm_sat_f32.ll index d466ec458c..4efeed7d02 100644 --- a/intrinsics/probes/fma_rm_sat_f32.ll +++ b/intrinsics/probes/fma_rm_sat_f32.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/fma_rn_f32.ll b/intrinsics/probes/fma_rn_f32.ll index bf1ff8b737..3ea157d358 100644 --- a/intrinsics/probes/fma_rn_f32.ll +++ b/intrinsics/probes/fma_rn_f32.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/fma_rn_f64.ll b/intrinsics/probes/fma_rn_f64.ll index fa5e645127..3df3aad47a 100644 --- a/intrinsics/probes/fma_rn_f64.ll +++ b/intrinsics/probes/fma_rn_f64.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/fma_rn_ftz_f32.ll b/intrinsics/probes/fma_rn_ftz_f32.ll index 85b61f6ab1..4e016b9bc9 100644 --- a/intrinsics/probes/fma_rn_ftz_f32.ll +++ b/intrinsics/probes/fma_rn_ftz_f32.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/fma_rn_ftz_sat_f32.ll b/intrinsics/probes/fma_rn_ftz_sat_f32.ll index c4e876057f..1049e5f876 100644 --- a/intrinsics/probes/fma_rn_ftz_sat_f32.ll +++ b/intrinsics/probes/fma_rn_ftz_sat_f32.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/fma_rn_sat_f32.ll b/intrinsics/probes/fma_rn_sat_f32.ll index 24365d3b7c..f5c8691eac 100644 --- a/intrinsics/probes/fma_rn_sat_f32.ll +++ b/intrinsics/probes/fma_rn_sat_f32.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/fma_rp_f32.ll b/intrinsics/probes/fma_rp_f32.ll index 0d09e77855..c7c20a0da9 100644 --- a/intrinsics/probes/fma_rp_f32.ll +++ b/intrinsics/probes/fma_rp_f32.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/fma_rp_f64.ll b/intrinsics/probes/fma_rp_f64.ll index 53d6f0e2f5..bad73b74e7 100644 --- a/intrinsics/probes/fma_rp_f64.ll +++ b/intrinsics/probes/fma_rp_f64.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/fma_rp_ftz_f32.ll b/intrinsics/probes/fma_rp_ftz_f32.ll index 2b2a96ca9e..25e7838dc6 100644 --- a/intrinsics/probes/fma_rp_ftz_f32.ll +++ b/intrinsics/probes/fma_rp_ftz_f32.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/fma_rp_ftz_sat_f32.ll b/intrinsics/probes/fma_rp_ftz_sat_f32.ll index ac2b5b6583..f37264abcc 100644 --- a/intrinsics/probes/fma_rp_ftz_sat_f32.ll +++ b/intrinsics/probes/fma_rp_ftz_sat_f32.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/fma_rp_sat_f32.ll b/intrinsics/probes/fma_rp_sat_f32.ll index 2a9b1edaf7..481af1e93c 100644 --- a/intrinsics/probes/fma_rp_sat_f32.ll +++ b/intrinsics/probes/fma_rp_sat_f32.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/fma_rz_f32.ll b/intrinsics/probes/fma_rz_f32.ll index 704b6cf308..0d53e36f4d 100644 --- a/intrinsics/probes/fma_rz_f32.ll +++ b/intrinsics/probes/fma_rz_f32.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/fma_rz_f64.ll b/intrinsics/probes/fma_rz_f64.ll index 5c358f1c79..f226fd67c1 100644 --- a/intrinsics/probes/fma_rz_f64.ll +++ b/intrinsics/probes/fma_rz_f64.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/fma_rz_ftz_f32.ll b/intrinsics/probes/fma_rz_ftz_f32.ll index 8aab1d33a7..f4f19b603e 100644 --- a/intrinsics/probes/fma_rz_ftz_f32.ll +++ b/intrinsics/probes/fma_rz_ftz_f32.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/fma_rz_ftz_sat_f32.ll b/intrinsics/probes/fma_rz_ftz_sat_f32.ll index 97e746464d..63e3b8a1e5 100644 --- a/intrinsics/probes/fma_rz_ftz_sat_f32.ll +++ b/intrinsics/probes/fma_rz_ftz_sat_f32.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/fma_rz_sat_f32.ll b/intrinsics/probes/fma_rz_sat_f32.ll index eca9a7f161..d00bbfe40d 100644 --- a/intrinsics/probes/fma_rz_sat_f32.ll +++ b/intrinsics/probes/fma_rz_sat_f32.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/fma_sat_f16x2.ll b/intrinsics/probes/fma_sat_f16x2.ll index 0c7b497977..af6a7f1adb 100644 --- a/intrinsics/probes/fma_sat_f16x2.ll +++ b/intrinsics/probes/fma_sat_f16x2.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/globaltimer.lib_nvvm.ll b/intrinsics/probes/globaltimer.lib_nvvm.ll index b76765bb00..d3e7036faf 100644 --- a/intrinsics/probes/globaltimer.lib_nvvm.ll +++ b/intrinsics/probes/globaltimer.lib_nvvm.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/globaltimer.llvm_nvptx.ll b/intrinsics/probes/globaltimer.llvm_nvptx.ll index 957bc8a908..f4ccb9310d 100644 --- a/intrinsics/probes/globaltimer.llvm_nvptx.ll +++ b/intrinsics/probes/globaltimer.llvm_nvptx.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/grid_dependency_launch_dependents.ll b/intrinsics/probes/grid_dependency_launch_dependents.ll index 21222cee8c..38d97c83ca 100644 --- a/intrinsics/probes/grid_dependency_launch_dependents.ll +++ b/intrinsics/probes/grid_dependency_launch_dependents.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/grid_dependency_wait.ll b/intrinsics/probes/grid_dependency_wait.ll index 4a49bb0113..5dbb5a9e30 100644 --- a/intrinsics/probes/grid_dependency_wait.ll +++ b/intrinsics/probes/grid_dependency_wait.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/grid_dim_x.ll b/intrinsics/probes/grid_dim_x.ll index 264e61eee8..daff37a567 100644 --- a/intrinsics/probes/grid_dim_x.ll +++ b/intrinsics/probes/grid_dim_x.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/grid_dim_y.ll b/intrinsics/probes/grid_dim_y.ll index 5f88f0deea..d742d7d164 100644 --- a/intrinsics/probes/grid_dim_y.ll +++ b/intrinsics/probes/grid_dim_y.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/grid_dim_z.ll b/intrinsics/probes/grid_dim_z.ll index 774aa415bb..74ce5f2984 100644 --- a/intrinsics/probes/grid_dim_z.ll +++ b/intrinsics/probes/grid_dim_z.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/gridid.lib_nvvm.ll b/intrinsics/probes/gridid.lib_nvvm.ll index 5b9c351ada..f36fb0bee7 100644 --- a/intrinsics/probes/gridid.lib_nvvm.ll +++ b/intrinsics/probes/gridid.lib_nvvm.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/gridid.llvm_nvptx.ll b/intrinsics/probes/gridid.llvm_nvptx.ll index f20a91fa8c..58d62e5c70 100644 --- a/intrinsics/probes/gridid.llvm_nvptx.ll +++ b/intrinsics/probes/gridid.llvm_nvptx.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/lane_id.ll b/intrinsics/probes/lane_id.ll index 56247b6bbb..ecb7bb05c8 100644 --- a/intrinsics/probes/lane_id.ll +++ b/intrinsics/probes/lane_id.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/lanemask_eq.ll b/intrinsics/probes/lanemask_eq.ll index f31fbcfb35..fae8db32a8 100644 --- a/intrinsics/probes/lanemask_eq.ll +++ b/intrinsics/probes/lanemask_eq.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/lanemask_ge.ll b/intrinsics/probes/lanemask_ge.ll index bd5fd9d608..3bf66a4643 100644 --- a/intrinsics/probes/lanemask_ge.ll +++ b/intrinsics/probes/lanemask_ge.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/lanemask_gt.ll b/intrinsics/probes/lanemask_gt.ll index a2448e97cd..f7d6f97010 100644 --- a/intrinsics/probes/lanemask_gt.ll +++ b/intrinsics/probes/lanemask_gt.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/lanemask_le.ll b/intrinsics/probes/lanemask_le.ll index bd780159d4..6452c39568 100644 --- a/intrinsics/probes/lanemask_le.ll +++ b/intrinsics/probes/lanemask_le.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/lanemask_lt.ll b/intrinsics/probes/lanemask_lt.ll index 91e9398eaa..8741ac148e 100644 --- a/intrinsics/probes/lanemask_lt.ll +++ b/intrinsics/probes/lanemask_lt.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/ldmatrix_m16n16_x1_trans_b8.ll b/intrinsics/probes/ldmatrix_m16n16_x1_trans_b8.ll index 547cfbfb75..4eaada91b2 100644 --- a/intrinsics/probes/ldmatrix_m16n16_x1_trans_b8.ll +++ b/intrinsics/probes/ldmatrix_m16n16_x1_trans_b8.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/ldmatrix_m16n16_x1_trans_b8x16_b4x16_p64.ll b/intrinsics/probes/ldmatrix_m16n16_x1_trans_b8x16_b4x16_p64.ll index 3d7a478b1c..c56c415315 100644 --- a/intrinsics/probes/ldmatrix_m16n16_x1_trans_b8x16_b4x16_p64.ll +++ b/intrinsics/probes/ldmatrix_m16n16_x1_trans_b8x16_b4x16_p64.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/ldmatrix_m16n16_x1_trans_b8x16_b6x16_p32.ll b/intrinsics/probes/ldmatrix_m16n16_x1_trans_b8x16_b6x16_p32.ll index 21d7ec00a6..55f6170314 100644 --- a/intrinsics/probes/ldmatrix_m16n16_x1_trans_b8x16_b6x16_p32.ll +++ b/intrinsics/probes/ldmatrix_m16n16_x1_trans_b8x16_b6x16_p32.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/ldmatrix_m16n16_x2_trans_b8.ll b/intrinsics/probes/ldmatrix_m16n16_x2_trans_b8.ll index 57b0895867..e15bd0d126 100644 --- a/intrinsics/probes/ldmatrix_m16n16_x2_trans_b8.ll +++ b/intrinsics/probes/ldmatrix_m16n16_x2_trans_b8.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/ldmatrix_m16n16_x2_trans_b8x16_b4x16_p64.ll b/intrinsics/probes/ldmatrix_m16n16_x2_trans_b8x16_b4x16_p64.ll index 3189f598aa..dcea5e45f0 100644 --- a/intrinsics/probes/ldmatrix_m16n16_x2_trans_b8x16_b4x16_p64.ll +++ b/intrinsics/probes/ldmatrix_m16n16_x2_trans_b8x16_b4x16_p64.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/ldmatrix_m16n16_x2_trans_b8x16_b6x16_p32.ll b/intrinsics/probes/ldmatrix_m16n16_x2_trans_b8x16_b6x16_p32.ll index 53fba898fd..7a596c0f24 100644 --- a/intrinsics/probes/ldmatrix_m16n16_x2_trans_b8x16_b6x16_p32.ll +++ b/intrinsics/probes/ldmatrix_m16n16_x2_trans_b8x16_b6x16_p32.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/ldmatrix_m8n16_x1_b8x16_b4x16_p64.ll b/intrinsics/probes/ldmatrix_m8n16_x1_b8x16_b4x16_p64.ll index 0367165383..c43ccdf237 100644 --- a/intrinsics/probes/ldmatrix_m8n16_x1_b8x16_b4x16_p64.ll +++ b/intrinsics/probes/ldmatrix_m8n16_x1_b8x16_b4x16_p64.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/ldmatrix_m8n16_x1_b8x16_b6x16_p32.ll b/intrinsics/probes/ldmatrix_m8n16_x1_b8x16_b6x16_p32.ll index 8ba0304a09..0d621e78fb 100644 --- a/intrinsics/probes/ldmatrix_m8n16_x1_b8x16_b6x16_p32.ll +++ b/intrinsics/probes/ldmatrix_m8n16_x1_b8x16_b6x16_p32.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/ldmatrix_m8n16_x2_b8x16_b4x16_p64.ll b/intrinsics/probes/ldmatrix_m8n16_x2_b8x16_b4x16_p64.ll index 88865d6e1b..fbce379068 100644 --- a/intrinsics/probes/ldmatrix_m8n16_x2_b8x16_b4x16_p64.ll +++ b/intrinsics/probes/ldmatrix_m8n16_x2_b8x16_b4x16_p64.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/ldmatrix_m8n16_x2_b8x16_b6x16_p32.ll b/intrinsics/probes/ldmatrix_m8n16_x2_b8x16_b6x16_p32.ll index e243dd0b70..ba3ab2f1ce 100644 --- a/intrinsics/probes/ldmatrix_m8n16_x2_b8x16_b6x16_p32.ll +++ b/intrinsics/probes/ldmatrix_m8n16_x2_b8x16_b6x16_p32.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/ldmatrix_m8n16_x4_b8x16_b4x16_p64.ll b/intrinsics/probes/ldmatrix_m8n16_x4_b8x16_b4x16_p64.ll index ff83cfd7cd..dadfa02ff5 100644 --- a/intrinsics/probes/ldmatrix_m8n16_x4_b8x16_b4x16_p64.ll +++ b/intrinsics/probes/ldmatrix_m8n16_x4_b8x16_b4x16_p64.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/ldmatrix_m8n16_x4_b8x16_b6x16_p32.ll b/intrinsics/probes/ldmatrix_m8n16_x4_b8x16_b6x16_p32.ll index 598932370b..c41bed1d36 100644 --- a/intrinsics/probes/ldmatrix_m8n16_x4_b8x16_b6x16_p32.ll +++ b/intrinsics/probes/ldmatrix_m8n16_x4_b8x16_b6x16_p32.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/ldmatrix_m8n8_x1_b16.ll b/intrinsics/probes/ldmatrix_m8n8_x1_b16.ll index 49d113b240..9f623a2ffa 100644 --- a/intrinsics/probes/ldmatrix_m8n8_x1_b16.ll +++ b/intrinsics/probes/ldmatrix_m8n8_x1_b16.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/ldmatrix_m8n8_x1_trans_b16.ll b/intrinsics/probes/ldmatrix_m8n8_x1_trans_b16.ll index f3fe9a27b5..ab298da0a1 100644 --- a/intrinsics/probes/ldmatrix_m8n8_x1_trans_b16.ll +++ b/intrinsics/probes/ldmatrix_m8n8_x1_trans_b16.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/ldmatrix_m8n8_x2_b16.ll b/intrinsics/probes/ldmatrix_m8n8_x2_b16.ll index 534efabea1..626f997489 100644 --- a/intrinsics/probes/ldmatrix_m8n8_x2_b16.ll +++ b/intrinsics/probes/ldmatrix_m8n8_x2_b16.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/ldmatrix_m8n8_x2_trans_b16.ll b/intrinsics/probes/ldmatrix_m8n8_x2_trans_b16.ll index 8d74261dac..452927808a 100644 --- a/intrinsics/probes/ldmatrix_m8n8_x2_trans_b16.ll +++ b/intrinsics/probes/ldmatrix_m8n8_x2_trans_b16.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/ldmatrix_m8n8_x4_b16.ll b/intrinsics/probes/ldmatrix_m8n8_x4_b16.ll index c62a9eb389..5236d52e6d 100644 --- a/intrinsics/probes/ldmatrix_m8n8_x4_b16.ll +++ b/intrinsics/probes/ldmatrix_m8n8_x4_b16.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/ldmatrix_m8n8_x4_trans_b16.ll b/intrinsics/probes/ldmatrix_m8n8_x4_trans_b16.ll index da24fafefd..97e71f9b73 100644 --- a/intrinsics/probes/ldmatrix_m8n8_x4_trans_b16.ll +++ b/intrinsics/probes/ldmatrix_m8n8_x4_trans_b16.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/lg2_approx_f32.ll b/intrinsics/probes/lg2_approx_f32.ll index cdb01e87a6..9170f17d9f 100644 --- a/intrinsics/probes/lg2_approx_f32.ll +++ b/intrinsics/probes/lg2_approx_f32.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/lg2_approx_ftz_f32.ll b/intrinsics/probes/lg2_approx_ftz_f32.ll index 06a9adb60e..71f66ee8fa 100644 --- a/intrinsics/probes/lg2_approx_ftz_f32.ll +++ b/intrinsics/probes/lg2_approx_ftz_f32.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/map_shared_rank.ll b/intrinsics/probes/map_shared_rank.ll index 2023b25190..b3e15fce57 100644 --- a/intrinsics/probes/map_shared_rank.ll +++ b/intrinsics/probes/map_shared_rank.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/match_all_i64_sync.ll b/intrinsics/probes/match_all_i64_sync.ll index ae34c5c418..4bcc97ba1e 100644 --- a/intrinsics/probes/match_all_i64_sync.ll +++ b/intrinsics/probes/match_all_i64_sync.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/match_all_sync.ll b/intrinsics/probes/match_all_sync.ll index dc48f658b4..e791e077bb 100644 --- a/intrinsics/probes/match_all_sync.ll +++ b/intrinsics/probes/match_all_sync.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/match_any_i64_sync.ll b/intrinsics/probes/match_any_i64_sync.ll index 428a68e780..1c8fa728e3 100644 --- a/intrinsics/probes/match_any_i64_sync.ll +++ b/intrinsics/probes/match_any_i64_sync.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/match_any_sync.ll b/intrinsics/probes/match_any_sync.ll index a7bcdad922..676678b4a9 100644 --- a/intrinsics/probes/match_any_sync.ll +++ b/intrinsics/probes/match_any_sync.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/max_bf16.ll b/intrinsics/probes/max_bf16.ll index 4e5f4bcb1b..07e15cd2c2 100644 --- a/intrinsics/probes/max_bf16.ll +++ b/intrinsics/probes/max_bf16.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/max_bf16x2.ll b/intrinsics/probes/max_bf16x2.ll index 7b5610f3a4..ab8684db82 100644 --- a/intrinsics/probes/max_bf16x2.ll +++ b/intrinsics/probes/max_bf16x2.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/max_f16.ll b/intrinsics/probes/max_f16.ll index 86b4782a78..50468af526 100644 --- a/intrinsics/probes/max_f16.ll +++ b/intrinsics/probes/max_f16.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/max_f16x2.ll b/intrinsics/probes/max_f16x2.ll index 60116846aa..26e521e3bb 100644 --- a/intrinsics/probes/max_f16x2.ll +++ b/intrinsics/probes/max_f16x2.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/max_ftz_f16.ll b/intrinsics/probes/max_ftz_f16.ll index 1459040e77..1c1431ab92 100644 --- a/intrinsics/probes/max_ftz_f16.ll +++ b/intrinsics/probes/max_ftz_f16.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/max_ftz_f16x2.ll b/intrinsics/probes/max_ftz_f16x2.ll index eddf1f0078..32198f04f9 100644 --- a/intrinsics/probes/max_ftz_f16x2.ll +++ b/intrinsics/probes/max_ftz_f16x2.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/max_ftz_nan_f16.ll b/intrinsics/probes/max_ftz_nan_f16.ll index e8faf4e523..77f6e2c767 100644 --- a/intrinsics/probes/max_ftz_nan_f16.ll +++ b/intrinsics/probes/max_ftz_nan_f16.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/max_ftz_nan_f16x2.ll b/intrinsics/probes/max_ftz_nan_f16x2.ll index ea8cc566ab..1907aa8796 100644 --- a/intrinsics/probes/max_ftz_nan_f16x2.ll +++ b/intrinsics/probes/max_ftz_nan_f16x2.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/max_ftz_nan_xorsign_abs_f16.ll b/intrinsics/probes/max_ftz_nan_xorsign_abs_f16.ll index c226c99fca..b87ac47290 100644 --- a/intrinsics/probes/max_ftz_nan_xorsign_abs_f16.ll +++ b/intrinsics/probes/max_ftz_nan_xorsign_abs_f16.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/max_ftz_nan_xorsign_abs_f16x2.ll b/intrinsics/probes/max_ftz_nan_xorsign_abs_f16x2.ll index f4fdd657ba..4ce87c7abd 100644 --- a/intrinsics/probes/max_ftz_nan_xorsign_abs_f16x2.ll +++ b/intrinsics/probes/max_ftz_nan_xorsign_abs_f16x2.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/max_ftz_nan_xorsign_abs_f32.ll b/intrinsics/probes/max_ftz_nan_xorsign_abs_f32.ll index edcee2f4a6..0a0b9bebad 100644 --- a/intrinsics/probes/max_ftz_nan_xorsign_abs_f32.ll +++ b/intrinsics/probes/max_ftz_nan_xorsign_abs_f32.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/max_ftz_xorsign_abs_f16.ll b/intrinsics/probes/max_ftz_xorsign_abs_f16.ll index fb9651c772..b5cc016894 100644 --- a/intrinsics/probes/max_ftz_xorsign_abs_f16.ll +++ b/intrinsics/probes/max_ftz_xorsign_abs_f16.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/max_ftz_xorsign_abs_f16x2.ll b/intrinsics/probes/max_ftz_xorsign_abs_f16x2.ll index be71d0de0f..01b4d8859d 100644 --- a/intrinsics/probes/max_ftz_xorsign_abs_f16x2.ll +++ b/intrinsics/probes/max_ftz_xorsign_abs_f16x2.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/max_ftz_xorsign_abs_f32.ll b/intrinsics/probes/max_ftz_xorsign_abs_f32.ll index 1988d832b5..cab064ac52 100644 --- a/intrinsics/probes/max_ftz_xorsign_abs_f32.ll +++ b/intrinsics/probes/max_ftz_xorsign_abs_f32.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/max_nan_bf16.ll b/intrinsics/probes/max_nan_bf16.ll index 7754a763de..90400600ec 100644 --- a/intrinsics/probes/max_nan_bf16.ll +++ b/intrinsics/probes/max_nan_bf16.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/max_nan_bf16x2.ll b/intrinsics/probes/max_nan_bf16x2.ll index 1633a5fd41..11e9f8af0a 100644 --- a/intrinsics/probes/max_nan_bf16x2.ll +++ b/intrinsics/probes/max_nan_bf16x2.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/max_nan_f16.ll b/intrinsics/probes/max_nan_f16.ll index 97821295b0..40127a880c 100644 --- a/intrinsics/probes/max_nan_f16.ll +++ b/intrinsics/probes/max_nan_f16.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/max_nan_f16x2.ll b/intrinsics/probes/max_nan_f16x2.ll index 86f8040a76..4db5cbb3ef 100644 --- a/intrinsics/probes/max_nan_f16x2.ll +++ b/intrinsics/probes/max_nan_f16x2.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/max_nan_xorsign_abs_bf16.ll b/intrinsics/probes/max_nan_xorsign_abs_bf16.ll index d234cdd80f..f70b9ac565 100644 --- a/intrinsics/probes/max_nan_xorsign_abs_bf16.ll +++ b/intrinsics/probes/max_nan_xorsign_abs_bf16.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/max_nan_xorsign_abs_bf16x2.ll b/intrinsics/probes/max_nan_xorsign_abs_bf16x2.ll index 577750d66f..e741e25a9f 100644 --- a/intrinsics/probes/max_nan_xorsign_abs_bf16x2.ll +++ b/intrinsics/probes/max_nan_xorsign_abs_bf16x2.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/max_nan_xorsign_abs_f16.ll b/intrinsics/probes/max_nan_xorsign_abs_f16.ll index 3f5554fcac..439c641684 100644 --- a/intrinsics/probes/max_nan_xorsign_abs_f16.ll +++ b/intrinsics/probes/max_nan_xorsign_abs_f16.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/max_nan_xorsign_abs_f16x2.ll b/intrinsics/probes/max_nan_xorsign_abs_f16x2.ll index 2c2fd2ffab..7184557be9 100644 --- a/intrinsics/probes/max_nan_xorsign_abs_f16x2.ll +++ b/intrinsics/probes/max_nan_xorsign_abs_f16x2.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/max_nan_xorsign_abs_f32.ll b/intrinsics/probes/max_nan_xorsign_abs_f32.ll index 0b46af8a1d..60c34ac71b 100644 --- a/intrinsics/probes/max_nan_xorsign_abs_f32.ll +++ b/intrinsics/probes/max_nan_xorsign_abs_f32.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/max_relu_s16x2.ll b/intrinsics/probes/max_relu_s16x2.ll index bcb81d3d32..2fdeb747f2 100644 --- a/intrinsics/probes/max_relu_s16x2.ll +++ b/intrinsics/probes/max_relu_s16x2.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/max_relu_s32.ll b/intrinsics/probes/max_relu_s32.ll index a4dd6a7d9c..38a6710db1 100644 --- a/intrinsics/probes/max_relu_s32.ll +++ b/intrinsics/probes/max_relu_s32.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/max_s16x2.ll b/intrinsics/probes/max_s16x2.ll index 0d285b85c0..09dbf72b0a 100644 --- a/intrinsics/probes/max_s16x2.ll +++ b/intrinsics/probes/max_s16x2.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/max_u16x2.ll b/intrinsics/probes/max_u16x2.ll index 57ff674c73..9a2ac229b5 100644 --- a/intrinsics/probes/max_u16x2.ll +++ b/intrinsics/probes/max_u16x2.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/max_xorsign_abs_bf16.ll b/intrinsics/probes/max_xorsign_abs_bf16.ll index dae7dda805..16080c95e2 100644 --- a/intrinsics/probes/max_xorsign_abs_bf16.ll +++ b/intrinsics/probes/max_xorsign_abs_bf16.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/max_xorsign_abs_bf16x2.ll b/intrinsics/probes/max_xorsign_abs_bf16x2.ll index 0d272bd25d..aa6005b0d9 100644 --- a/intrinsics/probes/max_xorsign_abs_bf16x2.ll +++ b/intrinsics/probes/max_xorsign_abs_bf16x2.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/max_xorsign_abs_f16.ll b/intrinsics/probes/max_xorsign_abs_f16.ll index f64c731b74..08011b55ce 100644 --- a/intrinsics/probes/max_xorsign_abs_f16.ll +++ b/intrinsics/probes/max_xorsign_abs_f16.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/max_xorsign_abs_f16x2.ll b/intrinsics/probes/max_xorsign_abs_f16x2.ll index 4c7f116529..5c9d51caf4 100644 --- a/intrinsics/probes/max_xorsign_abs_f16x2.ll +++ b/intrinsics/probes/max_xorsign_abs_f16x2.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/max_xorsign_abs_f32.ll b/intrinsics/probes/max_xorsign_abs_f32.ll index 2f8feeb538..3d35de4938 100644 --- a/intrinsics/probes/max_xorsign_abs_f32.ll +++ b/intrinsics/probes/max_xorsign_abs_f32.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mbarrier_arrive.ll b/intrinsics/probes/mbarrier_arrive.ll index f3e1f198be..bb8efce651 100644 --- a/intrinsics/probes/mbarrier_arrive.ll +++ b/intrinsics/probes/mbarrier_arrive.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mbarrier_arrive_cluster.ll b/intrinsics/probes/mbarrier_arrive_cluster.ll index 3de24f144d..b30debcb58 100644 --- a/intrinsics/probes/mbarrier_arrive_cluster.ll +++ b/intrinsics/probes/mbarrier_arrive_cluster.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mbarrier_arrive_expect_tx.ll b/intrinsics/probes/mbarrier_arrive_expect_tx.ll index f34db05bd7..b493a3dca3 100644 --- a/intrinsics/probes/mbarrier_arrive_expect_tx.ll +++ b/intrinsics/probes/mbarrier_arrive_expect_tx.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mbarrier_arrive_expect_tx_cluster.ll b/intrinsics/probes/mbarrier_arrive_expect_tx_cluster.ll index c3cd2fc876..8d46ebb491 100644 --- a/intrinsics/probes/mbarrier_arrive_expect_tx_cluster.ll +++ b/intrinsics/probes/mbarrier_arrive_expect_tx_cluster.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mbarrier_arrive_no_complete.ll b/intrinsics/probes/mbarrier_arrive_no_complete.ll index 24c50ba4f1..c2818f55c4 100644 --- a/intrinsics/probes/mbarrier_arrive_no_complete.ll +++ b/intrinsics/probes/mbarrier_arrive_no_complete.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mbarrier_init.ll b/intrinsics/probes/mbarrier_init.ll index 84593aeed3..19148dc3d5 100644 --- a/intrinsics/probes/mbarrier_init.ll +++ b/intrinsics/probes/mbarrier_init.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mbarrier_inval.ll b/intrinsics/probes/mbarrier_inval.ll index 4fbac6ad42..d72b97e12d 100644 --- a/intrinsics/probes/mbarrier_inval.ll +++ b/intrinsics/probes/mbarrier_inval.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mbarrier_test_wait.ll b/intrinsics/probes/mbarrier_test_wait.ll index 65043b5984..27aba5b27e 100644 --- a/intrinsics/probes/mbarrier_test_wait.ll +++ b/intrinsics/probes/mbarrier_test_wait.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mbarrier_try_wait.ll b/intrinsics/probes/mbarrier_try_wait.ll index 66f8c221a9..ab651c2967 100644 --- a/intrinsics/probes/mbarrier_try_wait.ll +++ b/intrinsics/probes/mbarrier_try_wait.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mbarrier_try_wait_parity.ll b/intrinsics/probes/mbarrier_try_wait_parity.ll index d3929dfe32..a7806759b7 100644 --- a/intrinsics/probes/mbarrier_try_wait_parity.ll +++ b/intrinsics/probes/mbarrier_try_wait_parity.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mbarrier_try_wait_parity_cluster.ll b/intrinsics/probes/mbarrier_try_wait_parity_cluster.ll index d65385ff4c..dbd9d48124 100644 --- a/intrinsics/probes/mbarrier_try_wait_parity_cluster.ll +++ b/intrinsics/probes/mbarrier_try_wait_parity_cluster.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/min_bf16.ll b/intrinsics/probes/min_bf16.ll index 3c5956b8ac..adc77f1ccd 100644 --- a/intrinsics/probes/min_bf16.ll +++ b/intrinsics/probes/min_bf16.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/min_bf16x2.ll b/intrinsics/probes/min_bf16x2.ll index 5e18509936..0f0782353e 100644 --- a/intrinsics/probes/min_bf16x2.ll +++ b/intrinsics/probes/min_bf16x2.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/min_f16.ll b/intrinsics/probes/min_f16.ll index cea5a4b238..2362d1c099 100644 --- a/intrinsics/probes/min_f16.ll +++ b/intrinsics/probes/min_f16.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/min_f16x2.ll b/intrinsics/probes/min_f16x2.ll index 4c43cbb417..5718325208 100644 --- a/intrinsics/probes/min_f16x2.ll +++ b/intrinsics/probes/min_f16x2.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/min_ftz_f16.ll b/intrinsics/probes/min_ftz_f16.ll index 8d0c9f1d4c..8a943f00a7 100644 --- a/intrinsics/probes/min_ftz_f16.ll +++ b/intrinsics/probes/min_ftz_f16.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/min_ftz_f16x2.ll b/intrinsics/probes/min_ftz_f16x2.ll index 51088531e1..4f5c2e2c9f 100644 --- a/intrinsics/probes/min_ftz_f16x2.ll +++ b/intrinsics/probes/min_ftz_f16x2.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/min_ftz_nan_f16.ll b/intrinsics/probes/min_ftz_nan_f16.ll index f8152a0610..2a70fc2b62 100644 --- a/intrinsics/probes/min_ftz_nan_f16.ll +++ b/intrinsics/probes/min_ftz_nan_f16.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/min_ftz_nan_f16x2.ll b/intrinsics/probes/min_ftz_nan_f16x2.ll index c52f2ed909..48ce739e1f 100644 --- a/intrinsics/probes/min_ftz_nan_f16x2.ll +++ b/intrinsics/probes/min_ftz_nan_f16x2.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/min_ftz_nan_xorsign_abs_f16.ll b/intrinsics/probes/min_ftz_nan_xorsign_abs_f16.ll index 412c81c0e8..f0ca6e0b0c 100644 --- a/intrinsics/probes/min_ftz_nan_xorsign_abs_f16.ll +++ b/intrinsics/probes/min_ftz_nan_xorsign_abs_f16.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/min_ftz_nan_xorsign_abs_f16x2.ll b/intrinsics/probes/min_ftz_nan_xorsign_abs_f16x2.ll index f5a94ac5ba..6842176d81 100644 --- a/intrinsics/probes/min_ftz_nan_xorsign_abs_f16x2.ll +++ b/intrinsics/probes/min_ftz_nan_xorsign_abs_f16x2.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/min_ftz_nan_xorsign_abs_f32.ll b/intrinsics/probes/min_ftz_nan_xorsign_abs_f32.ll index a719bb2615..bbe262cd41 100644 --- a/intrinsics/probes/min_ftz_nan_xorsign_abs_f32.ll +++ b/intrinsics/probes/min_ftz_nan_xorsign_abs_f32.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/min_ftz_xorsign_abs_f16.ll b/intrinsics/probes/min_ftz_xorsign_abs_f16.ll index a7fe507e1a..789677565f 100644 --- a/intrinsics/probes/min_ftz_xorsign_abs_f16.ll +++ b/intrinsics/probes/min_ftz_xorsign_abs_f16.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/min_ftz_xorsign_abs_f16x2.ll b/intrinsics/probes/min_ftz_xorsign_abs_f16x2.ll index 12717ef548..5c6c55c658 100644 --- a/intrinsics/probes/min_ftz_xorsign_abs_f16x2.ll +++ b/intrinsics/probes/min_ftz_xorsign_abs_f16x2.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/min_ftz_xorsign_abs_f32.ll b/intrinsics/probes/min_ftz_xorsign_abs_f32.ll index b1741490be..1932ff1032 100644 --- a/intrinsics/probes/min_ftz_xorsign_abs_f32.ll +++ b/intrinsics/probes/min_ftz_xorsign_abs_f32.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/min_nan_bf16.ll b/intrinsics/probes/min_nan_bf16.ll index 82f9b2d0a5..eba5743100 100644 --- a/intrinsics/probes/min_nan_bf16.ll +++ b/intrinsics/probes/min_nan_bf16.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/min_nan_bf16x2.ll b/intrinsics/probes/min_nan_bf16x2.ll index 8fab9390e6..832cb7e985 100644 --- a/intrinsics/probes/min_nan_bf16x2.ll +++ b/intrinsics/probes/min_nan_bf16x2.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/min_nan_f16.ll b/intrinsics/probes/min_nan_f16.ll index d9bf905963..b5e781d5f7 100644 --- a/intrinsics/probes/min_nan_f16.ll +++ b/intrinsics/probes/min_nan_f16.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/min_nan_f16x2.ll b/intrinsics/probes/min_nan_f16x2.ll index bb696ba895..f7080249d0 100644 --- a/intrinsics/probes/min_nan_f16x2.ll +++ b/intrinsics/probes/min_nan_f16x2.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/min_nan_xorsign_abs_bf16.ll b/intrinsics/probes/min_nan_xorsign_abs_bf16.ll index 4543ec9b47..15f5215252 100644 --- a/intrinsics/probes/min_nan_xorsign_abs_bf16.ll +++ b/intrinsics/probes/min_nan_xorsign_abs_bf16.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/min_nan_xorsign_abs_bf16x2.ll b/intrinsics/probes/min_nan_xorsign_abs_bf16x2.ll index 2ac7870aea..aa7fb7b2c7 100644 --- a/intrinsics/probes/min_nan_xorsign_abs_bf16x2.ll +++ b/intrinsics/probes/min_nan_xorsign_abs_bf16x2.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/min_nan_xorsign_abs_f16.ll b/intrinsics/probes/min_nan_xorsign_abs_f16.ll index f7c77059ca..71c31046e8 100644 --- a/intrinsics/probes/min_nan_xorsign_abs_f16.ll +++ b/intrinsics/probes/min_nan_xorsign_abs_f16.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/min_nan_xorsign_abs_f16x2.ll b/intrinsics/probes/min_nan_xorsign_abs_f16x2.ll index 4bdfa24872..873c55ac41 100644 --- a/intrinsics/probes/min_nan_xorsign_abs_f16x2.ll +++ b/intrinsics/probes/min_nan_xorsign_abs_f16x2.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/min_nan_xorsign_abs_f32.ll b/intrinsics/probes/min_nan_xorsign_abs_f32.ll index 925cfec7b3..a5c2d06856 100644 --- a/intrinsics/probes/min_nan_xorsign_abs_f32.ll +++ b/intrinsics/probes/min_nan_xorsign_abs_f32.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/min_relu_s16x2.ll b/intrinsics/probes/min_relu_s16x2.ll index a8693a1070..ad98adbdff 100644 --- a/intrinsics/probes/min_relu_s16x2.ll +++ b/intrinsics/probes/min_relu_s16x2.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/min_relu_s32.ll b/intrinsics/probes/min_relu_s32.ll index 8b7f438edc..90e4cca9cb 100644 --- a/intrinsics/probes/min_relu_s32.ll +++ b/intrinsics/probes/min_relu_s32.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/min_s16x2.ll b/intrinsics/probes/min_s16x2.ll index 7a619d4d86..b91cc42b20 100644 --- a/intrinsics/probes/min_s16x2.ll +++ b/intrinsics/probes/min_s16x2.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/min_u16x2.ll b/intrinsics/probes/min_u16x2.ll index 8625ce6120..c01ccf44e8 100644 --- a/intrinsics/probes/min_u16x2.ll +++ b/intrinsics/probes/min_u16x2.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/min_xorsign_abs_bf16.ll b/intrinsics/probes/min_xorsign_abs_bf16.ll index d6edc380c7..0cb9e99ddc 100644 --- a/intrinsics/probes/min_xorsign_abs_bf16.ll +++ b/intrinsics/probes/min_xorsign_abs_bf16.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/min_xorsign_abs_bf16x2.ll b/intrinsics/probes/min_xorsign_abs_bf16x2.ll index 351c82fcd1..5ef9192701 100644 --- a/intrinsics/probes/min_xorsign_abs_bf16x2.ll +++ b/intrinsics/probes/min_xorsign_abs_bf16x2.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/min_xorsign_abs_f16.ll b/intrinsics/probes/min_xorsign_abs_f16.ll index f2b471cf33..9dfdd0cf38 100644 --- a/intrinsics/probes/min_xorsign_abs_f16.ll +++ b/intrinsics/probes/min_xorsign_abs_f16.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/min_xorsign_abs_f16x2.ll b/intrinsics/probes/min_xorsign_abs_f16x2.ll index 4e79f2ad4d..e2ce392b50 100644 --- a/intrinsics/probes/min_xorsign_abs_f16x2.ll +++ b/intrinsics/probes/min_xorsign_abs_f16x2.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/min_xorsign_abs_f32.ll b/intrinsics/probes/min_xorsign_abs_f32.ll index c2bdf6f91e..2cf2a9117d 100644 --- a/intrinsics/probes/min_xorsign_abs_f32.ll +++ b/intrinsics/probes/min_xorsign_abs_f32.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_m16n8k128_s32_b1_and_popc.ll b/intrinsics/probes/mma_m16n8k128_s32_b1_and_popc.ll index 2fede10f8d..0c88b29308 100644 --- a/intrinsics/probes/mma_m16n8k128_s32_b1_and_popc.ll +++ b/intrinsics/probes/mma_m16n8k128_s32_b1_and_popc.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_m16n8k128_s32_b1_xor_popc.ll b/intrinsics/probes/mma_m16n8k128_s32_b1_xor_popc.ll index c04cef586e..13e16f0f71 100644 --- a/intrinsics/probes/mma_m16n8k128_s32_b1_xor_popc.ll +++ b/intrinsics/probes/mma_m16n8k128_s32_b1_xor_popc.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_m16n8k16_f16_f16.ll b/intrinsics/probes/mma_m16n8k16_f16_f16.ll index 0b1eeeae3a..63d662ba96 100644 --- a/intrinsics/probes/mma_m16n8k16_f16_f16.ll +++ b/intrinsics/probes/mma_m16n8k16_f16_f16.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_m16n8k16_f32_bf16.ll b/intrinsics/probes/mma_m16n8k16_f32_bf16.ll index 40bb59ebd4..e87f5df968 100644 --- a/intrinsics/probes/mma_m16n8k16_f32_bf16.ll +++ b/intrinsics/probes/mma_m16n8k16_f32_bf16.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_m16n8k16_f32_f16.ll b/intrinsics/probes/mma_m16n8k16_f32_f16.ll index 8a707b82b8..c2ecdf04fa 100644 --- a/intrinsics/probes/mma_m16n8k16_f32_f16.ll +++ b/intrinsics/probes/mma_m16n8k16_f32_f16.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_m16n8k16_fp8_f16_e4m3_e4m3.ll b/intrinsics/probes/mma_m16n8k16_fp8_f16_e4m3_e4m3.ll index 61bed3629e..a3178bfa5e 100644 --- a/intrinsics/probes/mma_m16n8k16_fp8_f16_e4m3_e4m3.ll +++ b/intrinsics/probes/mma_m16n8k16_fp8_f16_e4m3_e4m3.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_m16n8k16_fp8_f16_e4m3_e5m2.ll b/intrinsics/probes/mma_m16n8k16_fp8_f16_e4m3_e5m2.ll index b774a42906..a4cc6fa341 100644 --- a/intrinsics/probes/mma_m16n8k16_fp8_f16_e4m3_e5m2.ll +++ b/intrinsics/probes/mma_m16n8k16_fp8_f16_e4m3_e5m2.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_m16n8k16_fp8_f16_e5m2_e4m3.ll b/intrinsics/probes/mma_m16n8k16_fp8_f16_e5m2_e4m3.ll index f897a9b239..5a63b630b1 100644 --- a/intrinsics/probes/mma_m16n8k16_fp8_f16_e5m2_e4m3.ll +++ b/intrinsics/probes/mma_m16n8k16_fp8_f16_e5m2_e4m3.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_m16n8k16_fp8_f16_e5m2_e5m2.ll b/intrinsics/probes/mma_m16n8k16_fp8_f16_e5m2_e5m2.ll index 61fa2ca4f0..7650c4295c 100644 --- a/intrinsics/probes/mma_m16n8k16_fp8_f16_e5m2_e5m2.ll +++ b/intrinsics/probes/mma_m16n8k16_fp8_f16_e5m2_e5m2.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_m16n8k16_fp8_f32_e4m3_e4m3.ll b/intrinsics/probes/mma_m16n8k16_fp8_f32_e4m3_e4m3.ll index c6d5899825..6196154cca 100644 --- a/intrinsics/probes/mma_m16n8k16_fp8_f32_e4m3_e4m3.ll +++ b/intrinsics/probes/mma_m16n8k16_fp8_f32_e4m3_e4m3.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_m16n8k16_fp8_f32_e4m3_e5m2.ll b/intrinsics/probes/mma_m16n8k16_fp8_f32_e4m3_e5m2.ll index a1857c69b0..09b3ea2c18 100644 --- a/intrinsics/probes/mma_m16n8k16_fp8_f32_e4m3_e5m2.ll +++ b/intrinsics/probes/mma_m16n8k16_fp8_f32_e4m3_e5m2.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_m16n8k16_fp8_f32_e5m2_e4m3.ll b/intrinsics/probes/mma_m16n8k16_fp8_f32_e5m2_e4m3.ll index 54b57f9bf9..5c5c7aa4fb 100644 --- a/intrinsics/probes/mma_m16n8k16_fp8_f32_e5m2_e4m3.ll +++ b/intrinsics/probes/mma_m16n8k16_fp8_f32_e5m2_e4m3.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_m16n8k16_fp8_f32_e5m2_e5m2.ll b/intrinsics/probes/mma_m16n8k16_fp8_f32_e5m2_e5m2.ll index 54bbdd5398..56d08d155a 100644 --- a/intrinsics/probes/mma_m16n8k16_fp8_f32_e5m2_e5m2.ll +++ b/intrinsics/probes/mma_m16n8k16_fp8_f32_e5m2_e5m2.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_m16n8k16_s32_s8.ll b/intrinsics/probes/mma_m16n8k16_s32_s8.ll index 49acdd6baf..5e26fe58ad 100644 --- a/intrinsics/probes/mma_m16n8k16_s32_s8.ll +++ b/intrinsics/probes/mma_m16n8k16_s32_s8.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_m16n8k16_s32_s8_satfinite.ll b/intrinsics/probes/mma_m16n8k16_s32_s8_satfinite.ll index 3252adf860..0784ad648d 100644 --- a/intrinsics/probes/mma_m16n8k16_s32_s8_satfinite.ll +++ b/intrinsics/probes/mma_m16n8k16_s32_s8_satfinite.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_m16n8k16_s32_s8_u8.ll b/intrinsics/probes/mma_m16n8k16_s32_s8_u8.ll index 58d87b41ae..b3282225e0 100644 --- a/intrinsics/probes/mma_m16n8k16_s32_s8_u8.ll +++ b/intrinsics/probes/mma_m16n8k16_s32_s8_u8.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_m16n8k16_s32_s8_u8_satfinite.ll b/intrinsics/probes/mma_m16n8k16_s32_s8_u8_satfinite.ll index 9f985f3f63..d12eaffee6 100644 --- a/intrinsics/probes/mma_m16n8k16_s32_s8_u8_satfinite.ll +++ b/intrinsics/probes/mma_m16n8k16_s32_s8_u8_satfinite.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_m16n8k16_s32_u8.ll b/intrinsics/probes/mma_m16n8k16_s32_u8.ll index dc901c4f96..1d68785e58 100644 --- a/intrinsics/probes/mma_m16n8k16_s32_u8.ll +++ b/intrinsics/probes/mma_m16n8k16_s32_u8.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_m16n8k16_s32_u8_s8.ll b/intrinsics/probes/mma_m16n8k16_s32_u8_s8.ll index 2d308d8dfb..c07f7fdf1a 100644 --- a/intrinsics/probes/mma_m16n8k16_s32_u8_s8.ll +++ b/intrinsics/probes/mma_m16n8k16_s32_u8_s8.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_m16n8k16_s32_u8_s8_satfinite.ll b/intrinsics/probes/mma_m16n8k16_s32_u8_s8_satfinite.ll index cea930b165..841084135e 100644 --- a/intrinsics/probes/mma_m16n8k16_s32_u8_s8_satfinite.ll +++ b/intrinsics/probes/mma_m16n8k16_s32_u8_s8_satfinite.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_m16n8k16_s32_u8_satfinite.ll b/intrinsics/probes/mma_m16n8k16_s32_u8_satfinite.ll index 2eb72d3ab1..3ad4fbfae0 100644 --- a/intrinsics/probes/mma_m16n8k16_s32_u8_satfinite.ll +++ b/intrinsics/probes/mma_m16n8k16_s32_u8_satfinite.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_m16n8k256_s32_b1_and_popc.ll b/intrinsics/probes/mma_m16n8k256_s32_b1_and_popc.ll index 11a3b96fdc..916594335a 100644 --- a/intrinsics/probes/mma_m16n8k256_s32_b1_and_popc.ll +++ b/intrinsics/probes/mma_m16n8k256_s32_b1_and_popc.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_m16n8k256_s32_b1_xor_popc.ll b/intrinsics/probes/mma_m16n8k256_s32_b1_xor_popc.ll index ca75e4b8a8..3f2416e510 100644 --- a/intrinsics/probes/mma_m16n8k256_s32_b1_xor_popc.ll +++ b/intrinsics/probes/mma_m16n8k256_s32_b1_xor_popc.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_m16n8k32_f16_e2m1_e2m1.ll b/intrinsics/probes/mma_m16n8k32_f16_e2m1_e2m1.ll index c912116b1c..71263e38e9 100644 --- a/intrinsics/probes/mma_m16n8k32_f16_e2m1_e2m1.ll +++ b/intrinsics/probes/mma_m16n8k32_f16_e2m1_e2m1.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_m16n8k32_f16_e2m1_e2m3.ll b/intrinsics/probes/mma_m16n8k32_f16_e2m1_e2m3.ll index 979137b54d..8249de5f87 100644 --- a/intrinsics/probes/mma_m16n8k32_f16_e2m1_e2m3.ll +++ b/intrinsics/probes/mma_m16n8k32_f16_e2m1_e2m3.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_m16n8k32_f16_e2m1_e3m2.ll b/intrinsics/probes/mma_m16n8k32_f16_e2m1_e3m2.ll index 2212012149..664b9594f3 100644 --- a/intrinsics/probes/mma_m16n8k32_f16_e2m1_e3m2.ll +++ b/intrinsics/probes/mma_m16n8k32_f16_e2m1_e3m2.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_m16n8k32_f16_e2m1_e4m3.ll b/intrinsics/probes/mma_m16n8k32_f16_e2m1_e4m3.ll index 4bc6b40f9c..aa938ad781 100644 --- a/intrinsics/probes/mma_m16n8k32_f16_e2m1_e4m3.ll +++ b/intrinsics/probes/mma_m16n8k32_f16_e2m1_e4m3.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_m16n8k32_f16_e2m1_e5m2.ll b/intrinsics/probes/mma_m16n8k32_f16_e2m1_e5m2.ll index ad192ce437..5a870a66ca 100644 --- a/intrinsics/probes/mma_m16n8k32_f16_e2m1_e5m2.ll +++ b/intrinsics/probes/mma_m16n8k32_f16_e2m1_e5m2.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_m16n8k32_f16_e2m3_e2m1.ll b/intrinsics/probes/mma_m16n8k32_f16_e2m3_e2m1.ll index 9678caedcf..f2e0480634 100644 --- a/intrinsics/probes/mma_m16n8k32_f16_e2m3_e2m1.ll +++ b/intrinsics/probes/mma_m16n8k32_f16_e2m3_e2m1.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_m16n8k32_f16_e2m3_e2m3.ll b/intrinsics/probes/mma_m16n8k32_f16_e2m3_e2m3.ll index bf5ccf8437..0f731f0180 100644 --- a/intrinsics/probes/mma_m16n8k32_f16_e2m3_e2m3.ll +++ b/intrinsics/probes/mma_m16n8k32_f16_e2m3_e2m3.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_m16n8k32_f16_e2m3_e3m2.ll b/intrinsics/probes/mma_m16n8k32_f16_e2m3_e3m2.ll index 248b8151ca..bcbd1520f1 100644 --- a/intrinsics/probes/mma_m16n8k32_f16_e2m3_e3m2.ll +++ b/intrinsics/probes/mma_m16n8k32_f16_e2m3_e3m2.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_m16n8k32_f16_e2m3_e4m3.ll b/intrinsics/probes/mma_m16n8k32_f16_e2m3_e4m3.ll index fe0dc1809c..c363a03b31 100644 --- a/intrinsics/probes/mma_m16n8k32_f16_e2m3_e4m3.ll +++ b/intrinsics/probes/mma_m16n8k32_f16_e2m3_e4m3.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_m16n8k32_f16_e2m3_e5m2.ll b/intrinsics/probes/mma_m16n8k32_f16_e2m3_e5m2.ll index 51f878a55c..e7d2479ee6 100644 --- a/intrinsics/probes/mma_m16n8k32_f16_e2m3_e5m2.ll +++ b/intrinsics/probes/mma_m16n8k32_f16_e2m3_e5m2.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_m16n8k32_f16_e3m2_e2m1.ll b/intrinsics/probes/mma_m16n8k32_f16_e3m2_e2m1.ll index 69a0489763..815ad5707f 100644 --- a/intrinsics/probes/mma_m16n8k32_f16_e3m2_e2m1.ll +++ b/intrinsics/probes/mma_m16n8k32_f16_e3m2_e2m1.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_m16n8k32_f16_e3m2_e2m3.ll b/intrinsics/probes/mma_m16n8k32_f16_e3m2_e2m3.ll index e51fec2c78..feaf2a9d38 100644 --- a/intrinsics/probes/mma_m16n8k32_f16_e3m2_e2m3.ll +++ b/intrinsics/probes/mma_m16n8k32_f16_e3m2_e2m3.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_m16n8k32_f16_e3m2_e3m2.ll b/intrinsics/probes/mma_m16n8k32_f16_e3m2_e3m2.ll index 4bbc657d34..980c001dbe 100644 --- a/intrinsics/probes/mma_m16n8k32_f16_e3m2_e3m2.ll +++ b/intrinsics/probes/mma_m16n8k32_f16_e3m2_e3m2.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_m16n8k32_f16_e3m2_e4m3.ll b/intrinsics/probes/mma_m16n8k32_f16_e3m2_e4m3.ll index 7dbb91f726..afea71c569 100644 --- a/intrinsics/probes/mma_m16n8k32_f16_e3m2_e4m3.ll +++ b/intrinsics/probes/mma_m16n8k32_f16_e3m2_e4m3.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_m16n8k32_f16_e3m2_e5m2.ll b/intrinsics/probes/mma_m16n8k32_f16_e3m2_e5m2.ll index f41cbeefa9..59c7872149 100644 --- a/intrinsics/probes/mma_m16n8k32_f16_e3m2_e5m2.ll +++ b/intrinsics/probes/mma_m16n8k32_f16_e3m2_e5m2.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_m16n8k32_f16_e4m3_e2m1.ll b/intrinsics/probes/mma_m16n8k32_f16_e4m3_e2m1.ll index 38f4c90d85..b8f0351018 100644 --- a/intrinsics/probes/mma_m16n8k32_f16_e4m3_e2m1.ll +++ b/intrinsics/probes/mma_m16n8k32_f16_e4m3_e2m1.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_m16n8k32_f16_e4m3_e2m3.ll b/intrinsics/probes/mma_m16n8k32_f16_e4m3_e2m3.ll index 5ce8d4ac0b..de22423844 100644 --- a/intrinsics/probes/mma_m16n8k32_f16_e4m3_e2m3.ll +++ b/intrinsics/probes/mma_m16n8k32_f16_e4m3_e2m3.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_m16n8k32_f16_e4m3_e3m2.ll b/intrinsics/probes/mma_m16n8k32_f16_e4m3_e3m2.ll index 9bd0d013c9..30491e6068 100644 --- a/intrinsics/probes/mma_m16n8k32_f16_e4m3_e3m2.ll +++ b/intrinsics/probes/mma_m16n8k32_f16_e4m3_e3m2.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_m16n8k32_f16_e4m3_e4m3.ll b/intrinsics/probes/mma_m16n8k32_f16_e4m3_e4m3.ll index feb4a92f54..9ecb52c76d 100644 --- a/intrinsics/probes/mma_m16n8k32_f16_e4m3_e4m3.ll +++ b/intrinsics/probes/mma_m16n8k32_f16_e4m3_e4m3.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_m16n8k32_f16_e4m3_e5m2.ll b/intrinsics/probes/mma_m16n8k32_f16_e4m3_e5m2.ll index 912fce7cf5..5d59db5854 100644 --- a/intrinsics/probes/mma_m16n8k32_f16_e4m3_e5m2.ll +++ b/intrinsics/probes/mma_m16n8k32_f16_e4m3_e5m2.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_m16n8k32_f16_e5m2_e2m1.ll b/intrinsics/probes/mma_m16n8k32_f16_e5m2_e2m1.ll index 869d1f011c..dd31782a0a 100644 --- a/intrinsics/probes/mma_m16n8k32_f16_e5m2_e2m1.ll +++ b/intrinsics/probes/mma_m16n8k32_f16_e5m2_e2m1.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_m16n8k32_f16_e5m2_e2m3.ll b/intrinsics/probes/mma_m16n8k32_f16_e5m2_e2m3.ll index b647189c7a..12ae6beb6e 100644 --- a/intrinsics/probes/mma_m16n8k32_f16_e5m2_e2m3.ll +++ b/intrinsics/probes/mma_m16n8k32_f16_e5m2_e2m3.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_m16n8k32_f16_e5m2_e3m2.ll b/intrinsics/probes/mma_m16n8k32_f16_e5m2_e3m2.ll index 9d916c7ef5..a2e93aade7 100644 --- a/intrinsics/probes/mma_m16n8k32_f16_e5m2_e3m2.ll +++ b/intrinsics/probes/mma_m16n8k32_f16_e5m2_e3m2.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_m16n8k32_f16_e5m2_e4m3.ll b/intrinsics/probes/mma_m16n8k32_f16_e5m2_e4m3.ll index c971427aee..068cc94815 100644 --- a/intrinsics/probes/mma_m16n8k32_f16_e5m2_e4m3.ll +++ b/intrinsics/probes/mma_m16n8k32_f16_e5m2_e4m3.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_m16n8k32_f16_e5m2_e5m2.ll b/intrinsics/probes/mma_m16n8k32_f16_e5m2_e5m2.ll index f21a4f543a..92eb05fd47 100644 --- a/intrinsics/probes/mma_m16n8k32_f16_e5m2_e5m2.ll +++ b/intrinsics/probes/mma_m16n8k32_f16_e5m2_e5m2.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_m16n8k32_f32_e2m1_e2m1.ll b/intrinsics/probes/mma_m16n8k32_f32_e2m1_e2m1.ll index 79a4c317fc..20b0136b12 100644 --- a/intrinsics/probes/mma_m16n8k32_f32_e2m1_e2m1.ll +++ b/intrinsics/probes/mma_m16n8k32_f32_e2m1_e2m1.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_m16n8k32_f32_e2m1_e2m3.ll b/intrinsics/probes/mma_m16n8k32_f32_e2m1_e2m3.ll index df763a912a..c636de62d9 100644 --- a/intrinsics/probes/mma_m16n8k32_f32_e2m1_e2m3.ll +++ b/intrinsics/probes/mma_m16n8k32_f32_e2m1_e2m3.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_m16n8k32_f32_e2m1_e3m2.ll b/intrinsics/probes/mma_m16n8k32_f32_e2m1_e3m2.ll index 241d011ffe..34b717e7d0 100644 --- a/intrinsics/probes/mma_m16n8k32_f32_e2m1_e3m2.ll +++ b/intrinsics/probes/mma_m16n8k32_f32_e2m1_e3m2.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_m16n8k32_f32_e2m1_e4m3.ll b/intrinsics/probes/mma_m16n8k32_f32_e2m1_e4m3.ll index 9ef20cb0ad..a66c8d3339 100644 --- a/intrinsics/probes/mma_m16n8k32_f32_e2m1_e4m3.ll +++ b/intrinsics/probes/mma_m16n8k32_f32_e2m1_e4m3.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_m16n8k32_f32_e2m1_e5m2.ll b/intrinsics/probes/mma_m16n8k32_f32_e2m1_e5m2.ll index 06909b366d..9bcd01e3d9 100644 --- a/intrinsics/probes/mma_m16n8k32_f32_e2m1_e5m2.ll +++ b/intrinsics/probes/mma_m16n8k32_f32_e2m1_e5m2.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_m16n8k32_f32_e2m3_e2m1.ll b/intrinsics/probes/mma_m16n8k32_f32_e2m3_e2m1.ll index e6132a62a3..2b6cf6a49d 100644 --- a/intrinsics/probes/mma_m16n8k32_f32_e2m3_e2m1.ll +++ b/intrinsics/probes/mma_m16n8k32_f32_e2m3_e2m1.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_m16n8k32_f32_e2m3_e2m3.ll b/intrinsics/probes/mma_m16n8k32_f32_e2m3_e2m3.ll index aaff36bc8c..9984919269 100644 --- a/intrinsics/probes/mma_m16n8k32_f32_e2m3_e2m3.ll +++ b/intrinsics/probes/mma_m16n8k32_f32_e2m3_e2m3.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_m16n8k32_f32_e2m3_e3m2.ll b/intrinsics/probes/mma_m16n8k32_f32_e2m3_e3m2.ll index 72691a9470..870859bb80 100644 --- a/intrinsics/probes/mma_m16n8k32_f32_e2m3_e3m2.ll +++ b/intrinsics/probes/mma_m16n8k32_f32_e2m3_e3m2.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_m16n8k32_f32_e2m3_e4m3.ll b/intrinsics/probes/mma_m16n8k32_f32_e2m3_e4m3.ll index cfc30081b0..4bc97562b2 100644 --- a/intrinsics/probes/mma_m16n8k32_f32_e2m3_e4m3.ll +++ b/intrinsics/probes/mma_m16n8k32_f32_e2m3_e4m3.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_m16n8k32_f32_e2m3_e5m2.ll b/intrinsics/probes/mma_m16n8k32_f32_e2m3_e5m2.ll index dea510a97d..3adaa0ab19 100644 --- a/intrinsics/probes/mma_m16n8k32_f32_e2m3_e5m2.ll +++ b/intrinsics/probes/mma_m16n8k32_f32_e2m3_e5m2.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_m16n8k32_f32_e3m2_e2m1.ll b/intrinsics/probes/mma_m16n8k32_f32_e3m2_e2m1.ll index f3646e0525..bfb4db5480 100644 --- a/intrinsics/probes/mma_m16n8k32_f32_e3m2_e2m1.ll +++ b/intrinsics/probes/mma_m16n8k32_f32_e3m2_e2m1.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_m16n8k32_f32_e3m2_e2m3.ll b/intrinsics/probes/mma_m16n8k32_f32_e3m2_e2m3.ll index dc4a0a0788..fd957d8344 100644 --- a/intrinsics/probes/mma_m16n8k32_f32_e3m2_e2m3.ll +++ b/intrinsics/probes/mma_m16n8k32_f32_e3m2_e2m3.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_m16n8k32_f32_e3m2_e3m2.ll b/intrinsics/probes/mma_m16n8k32_f32_e3m2_e3m2.ll index 1a443642e5..016682d835 100644 --- a/intrinsics/probes/mma_m16n8k32_f32_e3m2_e3m2.ll +++ b/intrinsics/probes/mma_m16n8k32_f32_e3m2_e3m2.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_m16n8k32_f32_e3m2_e4m3.ll b/intrinsics/probes/mma_m16n8k32_f32_e3m2_e4m3.ll index 39e7d1e454..56312d7bd9 100644 --- a/intrinsics/probes/mma_m16n8k32_f32_e3m2_e4m3.ll +++ b/intrinsics/probes/mma_m16n8k32_f32_e3m2_e4m3.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_m16n8k32_f32_e3m2_e5m2.ll b/intrinsics/probes/mma_m16n8k32_f32_e3m2_e5m2.ll index b16fbb03b7..89777ec37a 100644 --- a/intrinsics/probes/mma_m16n8k32_f32_e3m2_e5m2.ll +++ b/intrinsics/probes/mma_m16n8k32_f32_e3m2_e5m2.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_m16n8k32_f32_e4m3_e2m1.ll b/intrinsics/probes/mma_m16n8k32_f32_e4m3_e2m1.ll index 11506fa759..0511a6ea3b 100644 --- a/intrinsics/probes/mma_m16n8k32_f32_e4m3_e2m1.ll +++ b/intrinsics/probes/mma_m16n8k32_f32_e4m3_e2m1.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_m16n8k32_f32_e4m3_e2m3.ll b/intrinsics/probes/mma_m16n8k32_f32_e4m3_e2m3.ll index c77ba085ba..3c419b8b68 100644 --- a/intrinsics/probes/mma_m16n8k32_f32_e4m3_e2m3.ll +++ b/intrinsics/probes/mma_m16n8k32_f32_e4m3_e2m3.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_m16n8k32_f32_e4m3_e3m2.ll b/intrinsics/probes/mma_m16n8k32_f32_e4m3_e3m2.ll index 079793106d..f18813cf6d 100644 --- a/intrinsics/probes/mma_m16n8k32_f32_e4m3_e3m2.ll +++ b/intrinsics/probes/mma_m16n8k32_f32_e4m3_e3m2.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_m16n8k32_f32_e4m3_e4m3.ll b/intrinsics/probes/mma_m16n8k32_f32_e4m3_e4m3.ll index 05cac96a48..5a3ca1e558 100644 --- a/intrinsics/probes/mma_m16n8k32_f32_e4m3_e4m3.ll +++ b/intrinsics/probes/mma_m16n8k32_f32_e4m3_e4m3.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_m16n8k32_f32_e4m3_e5m2.ll b/intrinsics/probes/mma_m16n8k32_f32_e4m3_e5m2.ll index 4a4a3e0f26..3c03edf13b 100644 --- a/intrinsics/probes/mma_m16n8k32_f32_e4m3_e5m2.ll +++ b/intrinsics/probes/mma_m16n8k32_f32_e4m3_e5m2.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_m16n8k32_f32_e5m2_e2m1.ll b/intrinsics/probes/mma_m16n8k32_f32_e5m2_e2m1.ll index 3f1d753959..d28e94d5ff 100644 --- a/intrinsics/probes/mma_m16n8k32_f32_e5m2_e2m1.ll +++ b/intrinsics/probes/mma_m16n8k32_f32_e5m2_e2m1.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_m16n8k32_f32_e5m2_e2m3.ll b/intrinsics/probes/mma_m16n8k32_f32_e5m2_e2m3.ll index 7e00129bf4..53cc69702a 100644 --- a/intrinsics/probes/mma_m16n8k32_f32_e5m2_e2m3.ll +++ b/intrinsics/probes/mma_m16n8k32_f32_e5m2_e2m3.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_m16n8k32_f32_e5m2_e3m2.ll b/intrinsics/probes/mma_m16n8k32_f32_e5m2_e3m2.ll index eafcbde3f7..ca770d0f9f 100644 --- a/intrinsics/probes/mma_m16n8k32_f32_e5m2_e3m2.ll +++ b/intrinsics/probes/mma_m16n8k32_f32_e5m2_e3m2.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_m16n8k32_f32_e5m2_e4m3.ll b/intrinsics/probes/mma_m16n8k32_f32_e5m2_e4m3.ll index 10a36f0d7d..272cff9cd1 100644 --- a/intrinsics/probes/mma_m16n8k32_f32_e5m2_e4m3.ll +++ b/intrinsics/probes/mma_m16n8k32_f32_e5m2_e4m3.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_m16n8k32_f32_e5m2_e5m2.ll b/intrinsics/probes/mma_m16n8k32_f32_e5m2_e5m2.ll index ad431e59d4..bd4c12dc74 100644 --- a/intrinsics/probes/mma_m16n8k32_f32_e5m2_e5m2.ll +++ b/intrinsics/probes/mma_m16n8k32_f32_e5m2_e5m2.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_m16n8k32_fp8_f16_e4m3_e4m3.ll b/intrinsics/probes/mma_m16n8k32_fp8_f16_e4m3_e4m3.ll index 87e11ab7f2..1bcf42153f 100644 --- a/intrinsics/probes/mma_m16n8k32_fp8_f16_e4m3_e4m3.ll +++ b/intrinsics/probes/mma_m16n8k32_fp8_f16_e4m3_e4m3.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_m16n8k32_fp8_f16_e4m3_e5m2.ll b/intrinsics/probes/mma_m16n8k32_fp8_f16_e4m3_e5m2.ll index b2a237aac6..4b1dc68868 100644 --- a/intrinsics/probes/mma_m16n8k32_fp8_f16_e4m3_e5m2.ll +++ b/intrinsics/probes/mma_m16n8k32_fp8_f16_e4m3_e5m2.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_m16n8k32_fp8_f16_e5m2_e4m3.ll b/intrinsics/probes/mma_m16n8k32_fp8_f16_e5m2_e4m3.ll index 167afddb15..3f1989b2e1 100644 --- a/intrinsics/probes/mma_m16n8k32_fp8_f16_e5m2_e4m3.ll +++ b/intrinsics/probes/mma_m16n8k32_fp8_f16_e5m2_e4m3.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_m16n8k32_fp8_f16_e5m2_e5m2.ll b/intrinsics/probes/mma_m16n8k32_fp8_f16_e5m2_e5m2.ll index 76549b099c..9d4a45ffaa 100644 --- a/intrinsics/probes/mma_m16n8k32_fp8_f16_e5m2_e5m2.ll +++ b/intrinsics/probes/mma_m16n8k32_fp8_f16_e5m2_e5m2.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_m16n8k32_fp8_f32_e4m3_e4m3.ll b/intrinsics/probes/mma_m16n8k32_fp8_f32_e4m3_e4m3.ll index f26e4baab7..778f690528 100644 --- a/intrinsics/probes/mma_m16n8k32_fp8_f32_e4m3_e4m3.ll +++ b/intrinsics/probes/mma_m16n8k32_fp8_f32_e4m3_e4m3.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_m16n8k32_fp8_f32_e4m3_e5m2.ll b/intrinsics/probes/mma_m16n8k32_fp8_f32_e4m3_e5m2.ll index 55d0d36893..e53f7519be 100644 --- a/intrinsics/probes/mma_m16n8k32_fp8_f32_e4m3_e5m2.ll +++ b/intrinsics/probes/mma_m16n8k32_fp8_f32_e4m3_e5m2.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_m16n8k32_fp8_f32_e5m2_e4m3.ll b/intrinsics/probes/mma_m16n8k32_fp8_f32_e5m2_e4m3.ll index 83d9e80705..7531bd493a 100644 --- a/intrinsics/probes/mma_m16n8k32_fp8_f32_e5m2_e4m3.ll +++ b/intrinsics/probes/mma_m16n8k32_fp8_f32_e5m2_e4m3.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_m16n8k32_fp8_f32_e5m2_e5m2.ll b/intrinsics/probes/mma_m16n8k32_fp8_f32_e5m2_e5m2.ll index ef1a1e1166..d059c9eef1 100644 --- a/intrinsics/probes/mma_m16n8k32_fp8_f32_e5m2_e5m2.ll +++ b/intrinsics/probes/mma_m16n8k32_fp8_f32_e5m2_e5m2.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_m16n8k32_mxf8f6f4_f32_e2m1_e2m1.ll b/intrinsics/probes/mma_m16n8k32_mxf8f6f4_f32_e2m1_e2m1.ll index 6a38c7e1ea..27ef31a6af 100644 --- a/intrinsics/probes/mma_m16n8k32_mxf8f6f4_f32_e2m1_e2m1.ll +++ b/intrinsics/probes/mma_m16n8k32_mxf8f6f4_f32_e2m1_e2m1.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_m16n8k32_mxf8f6f4_f32_e2m1_e2m3.ll b/intrinsics/probes/mma_m16n8k32_mxf8f6f4_f32_e2m1_e2m3.ll index fcf70f1013..db4cff946f 100644 --- a/intrinsics/probes/mma_m16n8k32_mxf8f6f4_f32_e2m1_e2m3.ll +++ b/intrinsics/probes/mma_m16n8k32_mxf8f6f4_f32_e2m1_e2m3.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_m16n8k32_mxf8f6f4_f32_e2m1_e3m2.ll b/intrinsics/probes/mma_m16n8k32_mxf8f6f4_f32_e2m1_e3m2.ll index b48644c317..df7538d6f7 100644 --- a/intrinsics/probes/mma_m16n8k32_mxf8f6f4_f32_e2m1_e3m2.ll +++ b/intrinsics/probes/mma_m16n8k32_mxf8f6f4_f32_e2m1_e3m2.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_m16n8k32_mxf8f6f4_f32_e2m1_e4m3.ll b/intrinsics/probes/mma_m16n8k32_mxf8f6f4_f32_e2m1_e4m3.ll index 6b8a2f55db..65fd02208c 100644 --- a/intrinsics/probes/mma_m16n8k32_mxf8f6f4_f32_e2m1_e4m3.ll +++ b/intrinsics/probes/mma_m16n8k32_mxf8f6f4_f32_e2m1_e4m3.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_m16n8k32_mxf8f6f4_f32_e2m1_e5m2.ll b/intrinsics/probes/mma_m16n8k32_mxf8f6f4_f32_e2m1_e5m2.ll index 55d85802e1..c6d2152e53 100644 --- a/intrinsics/probes/mma_m16n8k32_mxf8f6f4_f32_e2m1_e5m2.ll +++ b/intrinsics/probes/mma_m16n8k32_mxf8f6f4_f32_e2m1_e5m2.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_m16n8k32_mxf8f6f4_f32_e2m3_e2m1.ll b/intrinsics/probes/mma_m16n8k32_mxf8f6f4_f32_e2m3_e2m1.ll index 2eb31c5aff..9ff2de13e3 100644 --- a/intrinsics/probes/mma_m16n8k32_mxf8f6f4_f32_e2m3_e2m1.ll +++ b/intrinsics/probes/mma_m16n8k32_mxf8f6f4_f32_e2m3_e2m1.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_m16n8k32_mxf8f6f4_f32_e2m3_e2m3.ll b/intrinsics/probes/mma_m16n8k32_mxf8f6f4_f32_e2m3_e2m3.ll index 855888b23a..6824c11ef2 100644 --- a/intrinsics/probes/mma_m16n8k32_mxf8f6f4_f32_e2m3_e2m3.ll +++ b/intrinsics/probes/mma_m16n8k32_mxf8f6f4_f32_e2m3_e2m3.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_m16n8k32_mxf8f6f4_f32_e2m3_e3m2.ll b/intrinsics/probes/mma_m16n8k32_mxf8f6f4_f32_e2m3_e3m2.ll index 8956209c3e..922e28de3d 100644 --- a/intrinsics/probes/mma_m16n8k32_mxf8f6f4_f32_e2m3_e3m2.ll +++ b/intrinsics/probes/mma_m16n8k32_mxf8f6f4_f32_e2m3_e3m2.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_m16n8k32_mxf8f6f4_f32_e2m3_e4m3.ll b/intrinsics/probes/mma_m16n8k32_mxf8f6f4_f32_e2m3_e4m3.ll index d2fa467771..4ddcb1e914 100644 --- a/intrinsics/probes/mma_m16n8k32_mxf8f6f4_f32_e2m3_e4m3.ll +++ b/intrinsics/probes/mma_m16n8k32_mxf8f6f4_f32_e2m3_e4m3.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_m16n8k32_mxf8f6f4_f32_e2m3_e5m2.ll b/intrinsics/probes/mma_m16n8k32_mxf8f6f4_f32_e2m3_e5m2.ll index 6ce9b21d0e..1caff4d4b1 100644 --- a/intrinsics/probes/mma_m16n8k32_mxf8f6f4_f32_e2m3_e5m2.ll +++ b/intrinsics/probes/mma_m16n8k32_mxf8f6f4_f32_e2m3_e5m2.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_m16n8k32_mxf8f6f4_f32_e3m2_e2m1.ll b/intrinsics/probes/mma_m16n8k32_mxf8f6f4_f32_e3m2_e2m1.ll index 6b427d4868..b37c76679c 100644 --- a/intrinsics/probes/mma_m16n8k32_mxf8f6f4_f32_e3m2_e2m1.ll +++ b/intrinsics/probes/mma_m16n8k32_mxf8f6f4_f32_e3m2_e2m1.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_m16n8k32_mxf8f6f4_f32_e3m2_e2m3.ll b/intrinsics/probes/mma_m16n8k32_mxf8f6f4_f32_e3m2_e2m3.ll index 643f8bd0b2..0f9fa3e408 100644 --- a/intrinsics/probes/mma_m16n8k32_mxf8f6f4_f32_e3m2_e2m3.ll +++ b/intrinsics/probes/mma_m16n8k32_mxf8f6f4_f32_e3m2_e2m3.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_m16n8k32_mxf8f6f4_f32_e3m2_e3m2.ll b/intrinsics/probes/mma_m16n8k32_mxf8f6f4_f32_e3m2_e3m2.ll index 9911bcd6d3..8da80e4011 100644 --- a/intrinsics/probes/mma_m16n8k32_mxf8f6f4_f32_e3m2_e3m2.ll +++ b/intrinsics/probes/mma_m16n8k32_mxf8f6f4_f32_e3m2_e3m2.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_m16n8k32_mxf8f6f4_f32_e3m2_e4m3.ll b/intrinsics/probes/mma_m16n8k32_mxf8f6f4_f32_e3m2_e4m3.ll index 6d27d67b05..83dd78ed78 100644 --- a/intrinsics/probes/mma_m16n8k32_mxf8f6f4_f32_e3m2_e4m3.ll +++ b/intrinsics/probes/mma_m16n8k32_mxf8f6f4_f32_e3m2_e4m3.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_m16n8k32_mxf8f6f4_f32_e3m2_e5m2.ll b/intrinsics/probes/mma_m16n8k32_mxf8f6f4_f32_e3m2_e5m2.ll index e90a91cef0..7723a60ecd 100644 --- a/intrinsics/probes/mma_m16n8k32_mxf8f6f4_f32_e3m2_e5m2.ll +++ b/intrinsics/probes/mma_m16n8k32_mxf8f6f4_f32_e3m2_e5m2.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_m16n8k32_mxf8f6f4_f32_e4m3_e2m1.ll b/intrinsics/probes/mma_m16n8k32_mxf8f6f4_f32_e4m3_e2m1.ll index 9246bc5d91..7389ae087f 100644 --- a/intrinsics/probes/mma_m16n8k32_mxf8f6f4_f32_e4m3_e2m1.ll +++ b/intrinsics/probes/mma_m16n8k32_mxf8f6f4_f32_e4m3_e2m1.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_m16n8k32_mxf8f6f4_f32_e4m3_e2m3.ll b/intrinsics/probes/mma_m16n8k32_mxf8f6f4_f32_e4m3_e2m3.ll index 4cea7330e3..b83f8ce937 100644 --- a/intrinsics/probes/mma_m16n8k32_mxf8f6f4_f32_e4m3_e2m3.ll +++ b/intrinsics/probes/mma_m16n8k32_mxf8f6f4_f32_e4m3_e2m3.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_m16n8k32_mxf8f6f4_f32_e4m3_e3m2.ll b/intrinsics/probes/mma_m16n8k32_mxf8f6f4_f32_e4m3_e3m2.ll index 805ee1c88f..7e362b1eaa 100644 --- a/intrinsics/probes/mma_m16n8k32_mxf8f6f4_f32_e4m3_e3m2.ll +++ b/intrinsics/probes/mma_m16n8k32_mxf8f6f4_f32_e4m3_e3m2.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_m16n8k32_mxf8f6f4_f32_e4m3_e4m3.ll b/intrinsics/probes/mma_m16n8k32_mxf8f6f4_f32_e4m3_e4m3.ll index 092c3d1d4c..a57c2029a4 100644 --- a/intrinsics/probes/mma_m16n8k32_mxf8f6f4_f32_e4m3_e4m3.ll +++ b/intrinsics/probes/mma_m16n8k32_mxf8f6f4_f32_e4m3_e4m3.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_m16n8k32_mxf8f6f4_f32_e4m3_e5m2.ll b/intrinsics/probes/mma_m16n8k32_mxf8f6f4_f32_e4m3_e5m2.ll index d9ddd07632..d440c203a8 100644 --- a/intrinsics/probes/mma_m16n8k32_mxf8f6f4_f32_e4m3_e5m2.ll +++ b/intrinsics/probes/mma_m16n8k32_mxf8f6f4_f32_e4m3_e5m2.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_m16n8k32_mxf8f6f4_f32_e5m2_e2m1.ll b/intrinsics/probes/mma_m16n8k32_mxf8f6f4_f32_e5m2_e2m1.ll index dc32d48fb0..1e429af53e 100644 --- a/intrinsics/probes/mma_m16n8k32_mxf8f6f4_f32_e5m2_e2m1.ll +++ b/intrinsics/probes/mma_m16n8k32_mxf8f6f4_f32_e5m2_e2m1.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_m16n8k32_mxf8f6f4_f32_e5m2_e2m3.ll b/intrinsics/probes/mma_m16n8k32_mxf8f6f4_f32_e5m2_e2m3.ll index 60327ac107..8fa9f97579 100644 --- a/intrinsics/probes/mma_m16n8k32_mxf8f6f4_f32_e5m2_e2m3.ll +++ b/intrinsics/probes/mma_m16n8k32_mxf8f6f4_f32_e5m2_e2m3.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_m16n8k32_mxf8f6f4_f32_e5m2_e3m2.ll b/intrinsics/probes/mma_m16n8k32_mxf8f6f4_f32_e5m2_e3m2.ll index b17233052b..4bb7954c93 100644 --- a/intrinsics/probes/mma_m16n8k32_mxf8f6f4_f32_e5m2_e3m2.ll +++ b/intrinsics/probes/mma_m16n8k32_mxf8f6f4_f32_e5m2_e3m2.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_m16n8k32_mxf8f6f4_f32_e5m2_e4m3.ll b/intrinsics/probes/mma_m16n8k32_mxf8f6f4_f32_e5m2_e4m3.ll index 8b921ac965..f2a5f522b4 100644 --- a/intrinsics/probes/mma_m16n8k32_mxf8f6f4_f32_e5m2_e4m3.ll +++ b/intrinsics/probes/mma_m16n8k32_mxf8f6f4_f32_e5m2_e4m3.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_m16n8k32_mxf8f6f4_f32_e5m2_e5m2.ll b/intrinsics/probes/mma_m16n8k32_mxf8f6f4_f32_e5m2_e5m2.ll index f0dac7fccf..c826d723ba 100644 --- a/intrinsics/probes/mma_m16n8k32_mxf8f6f4_f32_e5m2_e5m2.ll +++ b/intrinsics/probes/mma_m16n8k32_mxf8f6f4_f32_e5m2_e5m2.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_m16n8k32_s32_s4.ll b/intrinsics/probes/mma_m16n8k32_s32_s4.ll index 4461f8535d..e708371523 100644 --- a/intrinsics/probes/mma_m16n8k32_s32_s4.ll +++ b/intrinsics/probes/mma_m16n8k32_s32_s4.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_m16n8k32_s32_s4_satfinite.ll b/intrinsics/probes/mma_m16n8k32_s32_s4_satfinite.ll index a522a62276..fa49ea3bd7 100644 --- a/intrinsics/probes/mma_m16n8k32_s32_s4_satfinite.ll +++ b/intrinsics/probes/mma_m16n8k32_s32_s4_satfinite.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_m16n8k32_s32_s4_u4.ll b/intrinsics/probes/mma_m16n8k32_s32_s4_u4.ll index a7de09e038..f3820a8ad0 100644 --- a/intrinsics/probes/mma_m16n8k32_s32_s4_u4.ll +++ b/intrinsics/probes/mma_m16n8k32_s32_s4_u4.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_m16n8k32_s32_s4_u4_satfinite.ll b/intrinsics/probes/mma_m16n8k32_s32_s4_u4_satfinite.ll index e3035ce972..823f2b3ba4 100644 --- a/intrinsics/probes/mma_m16n8k32_s32_s4_u4_satfinite.ll +++ b/intrinsics/probes/mma_m16n8k32_s32_s4_u4_satfinite.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_m16n8k32_s32_s8.ll b/intrinsics/probes/mma_m16n8k32_s32_s8.ll index f7fbaa8415..56a772a4f0 100644 --- a/intrinsics/probes/mma_m16n8k32_s32_s8.ll +++ b/intrinsics/probes/mma_m16n8k32_s32_s8.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_m16n8k32_s32_s8_satfinite.ll b/intrinsics/probes/mma_m16n8k32_s32_s8_satfinite.ll index 17f0a67562..c3c24b0f43 100644 --- a/intrinsics/probes/mma_m16n8k32_s32_s8_satfinite.ll +++ b/intrinsics/probes/mma_m16n8k32_s32_s8_satfinite.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_m16n8k32_s32_s8_u8.ll b/intrinsics/probes/mma_m16n8k32_s32_s8_u8.ll index 5c18de03fd..f4978deaec 100644 --- a/intrinsics/probes/mma_m16n8k32_s32_s8_u8.ll +++ b/intrinsics/probes/mma_m16n8k32_s32_s8_u8.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_m16n8k32_s32_s8_u8_satfinite.ll b/intrinsics/probes/mma_m16n8k32_s32_s8_u8_satfinite.ll index 202e3b9674..3005103459 100644 --- a/intrinsics/probes/mma_m16n8k32_s32_s8_u8_satfinite.ll +++ b/intrinsics/probes/mma_m16n8k32_s32_s8_u8_satfinite.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_m16n8k32_s32_u4.ll b/intrinsics/probes/mma_m16n8k32_s32_u4.ll index 5c7f1f9c4c..65ea1d039d 100644 --- a/intrinsics/probes/mma_m16n8k32_s32_u4.ll +++ b/intrinsics/probes/mma_m16n8k32_s32_u4.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_m16n8k32_s32_u4_s4.ll b/intrinsics/probes/mma_m16n8k32_s32_u4_s4.ll index d7979aa7fe..215eb638d0 100644 --- a/intrinsics/probes/mma_m16n8k32_s32_u4_s4.ll +++ b/intrinsics/probes/mma_m16n8k32_s32_u4_s4.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_m16n8k32_s32_u4_s4_satfinite.ll b/intrinsics/probes/mma_m16n8k32_s32_u4_s4_satfinite.ll index fb395d2d8b..9aa14feb5c 100644 --- a/intrinsics/probes/mma_m16n8k32_s32_u4_s4_satfinite.ll +++ b/intrinsics/probes/mma_m16n8k32_s32_u4_s4_satfinite.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_m16n8k32_s32_u4_satfinite.ll b/intrinsics/probes/mma_m16n8k32_s32_u4_satfinite.ll index a7f492722e..386b36628a 100644 --- a/intrinsics/probes/mma_m16n8k32_s32_u4_satfinite.ll +++ b/intrinsics/probes/mma_m16n8k32_s32_u4_satfinite.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_m16n8k32_s32_u8.ll b/intrinsics/probes/mma_m16n8k32_s32_u8.ll index a5452e1a59..bd92bd458d 100644 --- a/intrinsics/probes/mma_m16n8k32_s32_u8.ll +++ b/intrinsics/probes/mma_m16n8k32_s32_u8.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_m16n8k32_s32_u8_s8.ll b/intrinsics/probes/mma_m16n8k32_s32_u8_s8.ll index 50ed676893..418a4f2e52 100644 --- a/intrinsics/probes/mma_m16n8k32_s32_u8_s8.ll +++ b/intrinsics/probes/mma_m16n8k32_s32_u8_s8.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_m16n8k32_s32_u8_s8_satfinite.ll b/intrinsics/probes/mma_m16n8k32_s32_u8_s8_satfinite.ll index 8a3196776e..4fb1e97438 100644 --- a/intrinsics/probes/mma_m16n8k32_s32_u8_s8_satfinite.ll +++ b/intrinsics/probes/mma_m16n8k32_s32_u8_s8_satfinite.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_m16n8k32_s32_u8_satfinite.ll b/intrinsics/probes/mma_m16n8k32_s32_u8_satfinite.ll index 2bffe86b18..e0c08fadce 100644 --- a/intrinsics/probes/mma_m16n8k32_s32_u8_satfinite.ll +++ b/intrinsics/probes/mma_m16n8k32_s32_u8_satfinite.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_m16n8k4_f32_tf32.ll b/intrinsics/probes/mma_m16n8k4_f32_tf32.ll index f185beaa91..87fb14e0b5 100644 --- a/intrinsics/probes/mma_m16n8k4_f32_tf32.ll +++ b/intrinsics/probes/mma_m16n8k4_f32_tf32.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_m16n8k64_s32_s4.ll b/intrinsics/probes/mma_m16n8k64_s32_s4.ll index 3b4c0366e5..a08a34f20f 100644 --- a/intrinsics/probes/mma_m16n8k64_s32_s4.ll +++ b/intrinsics/probes/mma_m16n8k64_s32_s4.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_m16n8k64_s32_s4_satfinite.ll b/intrinsics/probes/mma_m16n8k64_s32_s4_satfinite.ll index 3d89ffebd2..7ad68fd73d 100644 --- a/intrinsics/probes/mma_m16n8k64_s32_s4_satfinite.ll +++ b/intrinsics/probes/mma_m16n8k64_s32_s4_satfinite.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_m16n8k64_s32_s4_u4.ll b/intrinsics/probes/mma_m16n8k64_s32_s4_u4.ll index 10117b2e8d..52144f2082 100644 --- a/intrinsics/probes/mma_m16n8k64_s32_s4_u4.ll +++ b/intrinsics/probes/mma_m16n8k64_s32_s4_u4.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_m16n8k64_s32_s4_u4_satfinite.ll b/intrinsics/probes/mma_m16n8k64_s32_s4_u4_satfinite.ll index 8409cb8fa8..94f6452592 100644 --- a/intrinsics/probes/mma_m16n8k64_s32_s4_u4_satfinite.ll +++ b/intrinsics/probes/mma_m16n8k64_s32_s4_u4_satfinite.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_m16n8k64_s32_u4.ll b/intrinsics/probes/mma_m16n8k64_s32_u4.ll index e1ffbfeb18..28c5c4f60a 100644 --- a/intrinsics/probes/mma_m16n8k64_s32_u4.ll +++ b/intrinsics/probes/mma_m16n8k64_s32_u4.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_m16n8k64_s32_u4_s4.ll b/intrinsics/probes/mma_m16n8k64_s32_u4_s4.ll index 8e267d0e0b..35f6aaa050 100644 --- a/intrinsics/probes/mma_m16n8k64_s32_u4_s4.ll +++ b/intrinsics/probes/mma_m16n8k64_s32_u4_s4.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_m16n8k64_s32_u4_s4_satfinite.ll b/intrinsics/probes/mma_m16n8k64_s32_u4_s4_satfinite.ll index 95499005a4..26dc06ba3d 100644 --- a/intrinsics/probes/mma_m16n8k64_s32_u4_s4_satfinite.ll +++ b/intrinsics/probes/mma_m16n8k64_s32_u4_s4_satfinite.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_m16n8k64_s32_u4_satfinite.ll b/intrinsics/probes/mma_m16n8k64_s32_u4_satfinite.ll index bdb385c3b5..3b73642f75 100644 --- a/intrinsics/probes/mma_m16n8k64_s32_u4_satfinite.ll +++ b/intrinsics/probes/mma_m16n8k64_s32_u4_satfinite.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_m16n8k8_f16_f16.ll b/intrinsics/probes/mma_m16n8k8_f16_f16.ll index bd26ecd369..1da3463784 100644 --- a/intrinsics/probes/mma_m16n8k8_f16_f16.ll +++ b/intrinsics/probes/mma_m16n8k8_f16_f16.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_m16n8k8_f32_bf16.ll b/intrinsics/probes/mma_m16n8k8_f32_bf16.ll index b5cb50c9e8..b1ae22f765 100644 --- a/intrinsics/probes/mma_m16n8k8_f32_bf16.ll +++ b/intrinsics/probes/mma_m16n8k8_f32_bf16.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_m16n8k8_f32_f16.ll b/intrinsics/probes/mma_m16n8k8_f32_f16.ll index d5e30dc668..b6b24c9783 100644 --- a/intrinsics/probes/mma_m16n8k8_f32_f16.ll +++ b/intrinsics/probes/mma_m16n8k8_f32_f16.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_m16n8k8_f32_tf32.ll b/intrinsics/probes/mma_m16n8k8_f32_tf32.ll index ecfd73905a..0749d1eea6 100644 --- a/intrinsics/probes/mma_m16n8k8_f32_tf32.ll +++ b/intrinsics/probes/mma_m16n8k8_f32_tf32.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_m8n8k128_s32_b1_and_popc.ll b/intrinsics/probes/mma_m8n8k128_s32_b1_and_popc.ll index 3cea5711d4..e6bddccbe4 100644 --- a/intrinsics/probes/mma_m8n8k128_s32_b1_and_popc.ll +++ b/intrinsics/probes/mma_m8n8k128_s32_b1_and_popc.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_m8n8k128_s32_b1_xor_popc.ll b/intrinsics/probes/mma_m8n8k128_s32_b1_xor_popc.ll index 44d635c964..c6c4498dda 100644 --- a/intrinsics/probes/mma_m8n8k128_s32_b1_xor_popc.ll +++ b/intrinsics/probes/mma_m8n8k128_s32_b1_xor_popc.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_m8n8k16_s32_s8.ll b/intrinsics/probes/mma_m8n8k16_s32_s8.ll index 20239e99da..a7032831f6 100644 --- a/intrinsics/probes/mma_m8n8k16_s32_s8.ll +++ b/intrinsics/probes/mma_m8n8k16_s32_s8.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_m8n8k16_s32_s8_satfinite.ll b/intrinsics/probes/mma_m8n8k16_s32_s8_satfinite.ll index cd75db8127..64a16982ca 100644 --- a/intrinsics/probes/mma_m8n8k16_s32_s8_satfinite.ll +++ b/intrinsics/probes/mma_m8n8k16_s32_s8_satfinite.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_m8n8k16_s32_s8_u8.ll b/intrinsics/probes/mma_m8n8k16_s32_s8_u8.ll index 35ecf306ed..ff6b08f506 100644 --- a/intrinsics/probes/mma_m8n8k16_s32_s8_u8.ll +++ b/intrinsics/probes/mma_m8n8k16_s32_s8_u8.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_m8n8k16_s32_s8_u8_satfinite.ll b/intrinsics/probes/mma_m8n8k16_s32_s8_u8_satfinite.ll index 3aae20cb18..02b4aea693 100644 --- a/intrinsics/probes/mma_m8n8k16_s32_s8_u8_satfinite.ll +++ b/intrinsics/probes/mma_m8n8k16_s32_s8_u8_satfinite.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_m8n8k16_s32_u8.ll b/intrinsics/probes/mma_m8n8k16_s32_u8.ll index d60e82c4b7..ae3902a68a 100644 --- a/intrinsics/probes/mma_m8n8k16_s32_u8.ll +++ b/intrinsics/probes/mma_m8n8k16_s32_u8.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_m8n8k16_s32_u8_s8.ll b/intrinsics/probes/mma_m8n8k16_s32_u8_s8.ll index e7cf9e0b40..5037d7a9ac 100644 --- a/intrinsics/probes/mma_m8n8k16_s32_u8_s8.ll +++ b/intrinsics/probes/mma_m8n8k16_s32_u8_s8.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_m8n8k16_s32_u8_s8_satfinite.ll b/intrinsics/probes/mma_m8n8k16_s32_u8_s8_satfinite.ll index 1ccf9ea9c5..45f88547a0 100644 --- a/intrinsics/probes/mma_m8n8k16_s32_u8_s8_satfinite.ll +++ b/intrinsics/probes/mma_m8n8k16_s32_u8_s8_satfinite.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_m8n8k16_s32_u8_satfinite.ll b/intrinsics/probes/mma_m8n8k16_s32_u8_satfinite.ll index 285313c689..4c0c79a095 100644 --- a/intrinsics/probes/mma_m8n8k16_s32_u8_satfinite.ll +++ b/intrinsics/probes/mma_m8n8k16_s32_u8_satfinite.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_m8n8k32_s32_s4.ll b/intrinsics/probes/mma_m8n8k32_s32_s4.ll index 236e1083c4..db8f6c6e83 100644 --- a/intrinsics/probes/mma_m8n8k32_s32_s4.ll +++ b/intrinsics/probes/mma_m8n8k32_s32_s4.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_m8n8k32_s32_s4_satfinite.ll b/intrinsics/probes/mma_m8n8k32_s32_s4_satfinite.ll index 6cec38ff8e..6fca0e5472 100644 --- a/intrinsics/probes/mma_m8n8k32_s32_s4_satfinite.ll +++ b/intrinsics/probes/mma_m8n8k32_s32_s4_satfinite.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_m8n8k32_s32_s4_u4.ll b/intrinsics/probes/mma_m8n8k32_s32_s4_u4.ll index 41ef593cde..cf3a8b0e28 100644 --- a/intrinsics/probes/mma_m8n8k32_s32_s4_u4.ll +++ b/intrinsics/probes/mma_m8n8k32_s32_s4_u4.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_m8n8k32_s32_s4_u4_satfinite.ll b/intrinsics/probes/mma_m8n8k32_s32_s4_u4_satfinite.ll index 6d02318443..f5fbafa211 100644 --- a/intrinsics/probes/mma_m8n8k32_s32_s4_u4_satfinite.ll +++ b/intrinsics/probes/mma_m8n8k32_s32_s4_u4_satfinite.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_m8n8k32_s32_u4.ll b/intrinsics/probes/mma_m8n8k32_s32_u4.ll index a1958c795a..cfddd24fd7 100644 --- a/intrinsics/probes/mma_m8n8k32_s32_u4.ll +++ b/intrinsics/probes/mma_m8n8k32_s32_u4.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_m8n8k32_s32_u4_s4.ll b/intrinsics/probes/mma_m8n8k32_s32_u4_s4.ll index 9352da8290..b83510c877 100644 --- a/intrinsics/probes/mma_m8n8k32_s32_u4_s4.ll +++ b/intrinsics/probes/mma_m8n8k32_s32_u4_s4.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_m8n8k32_s32_u4_s4_satfinite.ll b/intrinsics/probes/mma_m8n8k32_s32_u4_s4_satfinite.ll index 26e735b651..4d4c7bbffa 100644 --- a/intrinsics/probes/mma_m8n8k32_s32_u4_s4_satfinite.ll +++ b/intrinsics/probes/mma_m8n8k32_s32_u4_s4_satfinite.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_m8n8k32_s32_u4_satfinite.ll b/intrinsics/probes/mma_m8n8k32_s32_u4_satfinite.ll index bab895c687..9c0bd4e837 100644 --- a/intrinsics/probes/mma_m8n8k32_s32_u4_satfinite.ll +++ b/intrinsics/probes/mma_m8n8k32_s32_u4_satfinite.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_m8n8k4_f64.ll b/intrinsics/probes/mma_m8n8k4_f64.ll index ba4a74a915..5e5b33da61 100644 --- a/intrinsics/probes/mma_m8n8k4_f64.ll +++ b/intrinsics/probes/mma_m8n8k4_f64.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_sp_m16n8k128_s32_s4.ll b/intrinsics/probes/mma_sp_m16n8k128_s32_s4.ll index d621429823..e817a88812 100644 --- a/intrinsics/probes/mma_sp_m16n8k128_s32_s4.ll +++ b/intrinsics/probes/mma_sp_m16n8k128_s32_s4.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_sp_m16n8k128_s32_s4_satfinite.ll b/intrinsics/probes/mma_sp_m16n8k128_s32_s4_satfinite.ll index af6dce3ce6..00a2a37f16 100644 --- a/intrinsics/probes/mma_sp_m16n8k128_s32_s4_satfinite.ll +++ b/intrinsics/probes/mma_sp_m16n8k128_s32_s4_satfinite.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_sp_m16n8k128_s32_s4_u4.ll b/intrinsics/probes/mma_sp_m16n8k128_s32_s4_u4.ll index af88810759..834727d21e 100644 --- a/intrinsics/probes/mma_sp_m16n8k128_s32_s4_u4.ll +++ b/intrinsics/probes/mma_sp_m16n8k128_s32_s4_u4.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_sp_m16n8k128_s32_s4_u4_satfinite.ll b/intrinsics/probes/mma_sp_m16n8k128_s32_s4_u4_satfinite.ll index c23575c915..4e9b7dfb19 100644 --- a/intrinsics/probes/mma_sp_m16n8k128_s32_s4_u4_satfinite.ll +++ b/intrinsics/probes/mma_sp_m16n8k128_s32_s4_u4_satfinite.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_sp_m16n8k128_s32_u4.ll b/intrinsics/probes/mma_sp_m16n8k128_s32_u4.ll index 4e3ddc4957..b6345a6b3e 100644 --- a/intrinsics/probes/mma_sp_m16n8k128_s32_u4.ll +++ b/intrinsics/probes/mma_sp_m16n8k128_s32_u4.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_sp_m16n8k128_s32_u4_s4.ll b/intrinsics/probes/mma_sp_m16n8k128_s32_u4_s4.ll index 70eb458830..f7e22aad4e 100644 --- a/intrinsics/probes/mma_sp_m16n8k128_s32_u4_s4.ll +++ b/intrinsics/probes/mma_sp_m16n8k128_s32_u4_s4.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_sp_m16n8k128_s32_u4_s4_satfinite.ll b/intrinsics/probes/mma_sp_m16n8k128_s32_u4_s4_satfinite.ll index 3678ffe9e1..fc20a7ac54 100644 --- a/intrinsics/probes/mma_sp_m16n8k128_s32_u4_s4_satfinite.ll +++ b/intrinsics/probes/mma_sp_m16n8k128_s32_u4_s4_satfinite.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_sp_m16n8k128_s32_u4_satfinite.ll b/intrinsics/probes/mma_sp_m16n8k128_s32_u4_satfinite.ll index db4606ec50..7c3afc2015 100644 --- a/intrinsics/probes/mma_sp_m16n8k128_s32_u4_satfinite.ll +++ b/intrinsics/probes/mma_sp_m16n8k128_s32_u4_satfinite.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_sp_m16n8k32_s32_s8.ll b/intrinsics/probes/mma_sp_m16n8k32_s32_s8.ll index 7547637a79..60fb5a2f8e 100644 --- a/intrinsics/probes/mma_sp_m16n8k32_s32_s8.ll +++ b/intrinsics/probes/mma_sp_m16n8k32_s32_s8.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_sp_m16n8k32_s32_s8_satfinite.ll b/intrinsics/probes/mma_sp_m16n8k32_s32_s8_satfinite.ll index aa01a83dc7..0aa7f9cb91 100644 --- a/intrinsics/probes/mma_sp_m16n8k32_s32_s8_satfinite.ll +++ b/intrinsics/probes/mma_sp_m16n8k32_s32_s8_satfinite.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_sp_m16n8k32_s32_s8_u8.ll b/intrinsics/probes/mma_sp_m16n8k32_s32_s8_u8.ll index 54a1d737ac..d729e41f77 100644 --- a/intrinsics/probes/mma_sp_m16n8k32_s32_s8_u8.ll +++ b/intrinsics/probes/mma_sp_m16n8k32_s32_s8_u8.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_sp_m16n8k32_s32_s8_u8_satfinite.ll b/intrinsics/probes/mma_sp_m16n8k32_s32_s8_u8_satfinite.ll index de055e040a..0b62eb78a7 100644 --- a/intrinsics/probes/mma_sp_m16n8k32_s32_s8_u8_satfinite.ll +++ b/intrinsics/probes/mma_sp_m16n8k32_s32_s8_u8_satfinite.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_sp_m16n8k32_s32_u8.ll b/intrinsics/probes/mma_sp_m16n8k32_s32_u8.ll index c95f5f197e..aabb55882d 100644 --- a/intrinsics/probes/mma_sp_m16n8k32_s32_u8.ll +++ b/intrinsics/probes/mma_sp_m16n8k32_s32_u8.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_sp_m16n8k32_s32_u8_s8.ll b/intrinsics/probes/mma_sp_m16n8k32_s32_u8_s8.ll index ec5a5c9d90..bfc5ccd527 100644 --- a/intrinsics/probes/mma_sp_m16n8k32_s32_u8_s8.ll +++ b/intrinsics/probes/mma_sp_m16n8k32_s32_u8_s8.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_sp_m16n8k32_s32_u8_s8_satfinite.ll b/intrinsics/probes/mma_sp_m16n8k32_s32_u8_s8_satfinite.ll index 03962e57e1..f0504531cb 100644 --- a/intrinsics/probes/mma_sp_m16n8k32_s32_u8_s8_satfinite.ll +++ b/intrinsics/probes/mma_sp_m16n8k32_s32_u8_s8_satfinite.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_sp_m16n8k32_s32_u8_satfinite.ll b/intrinsics/probes/mma_sp_m16n8k32_s32_u8_satfinite.ll index 7e0b052dda..c8f231b9f7 100644 --- a/intrinsics/probes/mma_sp_m16n8k32_s32_u8_satfinite.ll +++ b/intrinsics/probes/mma_sp_m16n8k32_s32_u8_satfinite.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_sp_m16n8k64_s32_s4.ll b/intrinsics/probes/mma_sp_m16n8k64_s32_s4.ll index bb39a8a068..83c90778bc 100644 --- a/intrinsics/probes/mma_sp_m16n8k64_s32_s4.ll +++ b/intrinsics/probes/mma_sp_m16n8k64_s32_s4.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_sp_m16n8k64_s32_s4_satfinite.ll b/intrinsics/probes/mma_sp_m16n8k64_s32_s4_satfinite.ll index d9e9f6db19..c15257725e 100644 --- a/intrinsics/probes/mma_sp_m16n8k64_s32_s4_satfinite.ll +++ b/intrinsics/probes/mma_sp_m16n8k64_s32_s4_satfinite.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_sp_m16n8k64_s32_s4_u4.ll b/intrinsics/probes/mma_sp_m16n8k64_s32_s4_u4.ll index f3dd2a9a76..20ced0633b 100644 --- a/intrinsics/probes/mma_sp_m16n8k64_s32_s4_u4.ll +++ b/intrinsics/probes/mma_sp_m16n8k64_s32_s4_u4.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_sp_m16n8k64_s32_s4_u4_satfinite.ll b/intrinsics/probes/mma_sp_m16n8k64_s32_s4_u4_satfinite.ll index 03eb525216..85181f75c3 100644 --- a/intrinsics/probes/mma_sp_m16n8k64_s32_s4_u4_satfinite.ll +++ b/intrinsics/probes/mma_sp_m16n8k64_s32_s4_u4_satfinite.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_sp_m16n8k64_s32_s8.ll b/intrinsics/probes/mma_sp_m16n8k64_s32_s8.ll index 39f09f9d3d..c3c754bbb9 100644 --- a/intrinsics/probes/mma_sp_m16n8k64_s32_s8.ll +++ b/intrinsics/probes/mma_sp_m16n8k64_s32_s8.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_sp_m16n8k64_s32_s8_satfinite.ll b/intrinsics/probes/mma_sp_m16n8k64_s32_s8_satfinite.ll index 0fd797dedf..65ea55bcb3 100644 --- a/intrinsics/probes/mma_sp_m16n8k64_s32_s8_satfinite.ll +++ b/intrinsics/probes/mma_sp_m16n8k64_s32_s8_satfinite.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_sp_m16n8k64_s32_s8_u8.ll b/intrinsics/probes/mma_sp_m16n8k64_s32_s8_u8.ll index 32ee6e77f5..afc243df16 100644 --- a/intrinsics/probes/mma_sp_m16n8k64_s32_s8_u8.ll +++ b/intrinsics/probes/mma_sp_m16n8k64_s32_s8_u8.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_sp_m16n8k64_s32_s8_u8_satfinite.ll b/intrinsics/probes/mma_sp_m16n8k64_s32_s8_u8_satfinite.ll index b795d52762..39d2403afb 100644 --- a/intrinsics/probes/mma_sp_m16n8k64_s32_s8_u8_satfinite.ll +++ b/intrinsics/probes/mma_sp_m16n8k64_s32_s8_u8_satfinite.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_sp_m16n8k64_s32_u4.ll b/intrinsics/probes/mma_sp_m16n8k64_s32_u4.ll index 86b30965c7..df1e632310 100644 --- a/intrinsics/probes/mma_sp_m16n8k64_s32_u4.ll +++ b/intrinsics/probes/mma_sp_m16n8k64_s32_u4.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_sp_m16n8k64_s32_u4_s4.ll b/intrinsics/probes/mma_sp_m16n8k64_s32_u4_s4.ll index e48df9b3c5..a3319d7c41 100644 --- a/intrinsics/probes/mma_sp_m16n8k64_s32_u4_s4.ll +++ b/intrinsics/probes/mma_sp_m16n8k64_s32_u4_s4.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_sp_m16n8k64_s32_u4_s4_satfinite.ll b/intrinsics/probes/mma_sp_m16n8k64_s32_u4_s4_satfinite.ll index 1fc2b51cfe..73173ef474 100644 --- a/intrinsics/probes/mma_sp_m16n8k64_s32_u4_s4_satfinite.ll +++ b/intrinsics/probes/mma_sp_m16n8k64_s32_u4_s4_satfinite.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_sp_m16n8k64_s32_u4_satfinite.ll b/intrinsics/probes/mma_sp_m16n8k64_s32_u4_satfinite.ll index b407370a07..4f990af050 100644 --- a/intrinsics/probes/mma_sp_m16n8k64_s32_u4_satfinite.ll +++ b/intrinsics/probes/mma_sp_m16n8k64_s32_u4_satfinite.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_sp_m16n8k64_s32_u8.ll b/intrinsics/probes/mma_sp_m16n8k64_s32_u8.ll index 466800b6cf..86e7eac0e3 100644 --- a/intrinsics/probes/mma_sp_m16n8k64_s32_u8.ll +++ b/intrinsics/probes/mma_sp_m16n8k64_s32_u8.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_sp_m16n8k64_s32_u8_s8.ll b/intrinsics/probes/mma_sp_m16n8k64_s32_u8_s8.ll index eb2e33b15d..427e6b9da1 100644 --- a/intrinsics/probes/mma_sp_m16n8k64_s32_u8_s8.ll +++ b/intrinsics/probes/mma_sp_m16n8k64_s32_u8_s8.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_sp_m16n8k64_s32_u8_s8_satfinite.ll b/intrinsics/probes/mma_sp_m16n8k64_s32_u8_s8_satfinite.ll index 001f56a865..4ab4ba1ab2 100644 --- a/intrinsics/probes/mma_sp_m16n8k64_s32_u8_s8_satfinite.ll +++ b/intrinsics/probes/mma_sp_m16n8k64_s32_u8_s8_satfinite.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_sp_m16n8k64_s32_u8_satfinite.ll b/intrinsics/probes/mma_sp_m16n8k64_s32_u8_satfinite.ll index a5736ae7ba..4376016fa9 100644 --- a/intrinsics/probes/mma_sp_m16n8k64_s32_u8_satfinite.ll +++ b/intrinsics/probes/mma_sp_m16n8k64_s32_u8_satfinite.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_sp_ordered_metadata_m16n8k128_s32_s4.ll b/intrinsics/probes/mma_sp_ordered_metadata_m16n8k128_s32_s4.ll index 825f98edab..a43ef1fbe0 100644 --- a/intrinsics/probes/mma_sp_ordered_metadata_m16n8k128_s32_s4.ll +++ b/intrinsics/probes/mma_sp_ordered_metadata_m16n8k128_s32_s4.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_sp_ordered_metadata_m16n8k128_s32_s4_satfinite.ll b/intrinsics/probes/mma_sp_ordered_metadata_m16n8k128_s32_s4_satfinite.ll index ab84c8daad..8c3f3e6753 100644 --- a/intrinsics/probes/mma_sp_ordered_metadata_m16n8k128_s32_s4_satfinite.ll +++ b/intrinsics/probes/mma_sp_ordered_metadata_m16n8k128_s32_s4_satfinite.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_sp_ordered_metadata_m16n8k128_s32_s4_u4.ll b/intrinsics/probes/mma_sp_ordered_metadata_m16n8k128_s32_s4_u4.ll index 98e125c26c..f9951b4f50 100644 --- a/intrinsics/probes/mma_sp_ordered_metadata_m16n8k128_s32_s4_u4.ll +++ b/intrinsics/probes/mma_sp_ordered_metadata_m16n8k128_s32_s4_u4.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_sp_ordered_metadata_m16n8k128_s32_s4_u4_satfinite.ll b/intrinsics/probes/mma_sp_ordered_metadata_m16n8k128_s32_s4_u4_satfinite.ll index 21ac72add4..a00e002460 100644 --- a/intrinsics/probes/mma_sp_ordered_metadata_m16n8k128_s32_s4_u4_satfinite.ll +++ b/intrinsics/probes/mma_sp_ordered_metadata_m16n8k128_s32_s4_u4_satfinite.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_sp_ordered_metadata_m16n8k128_s32_u4.ll b/intrinsics/probes/mma_sp_ordered_metadata_m16n8k128_s32_u4.ll index 4526e56215..78c0a3f0c9 100644 --- a/intrinsics/probes/mma_sp_ordered_metadata_m16n8k128_s32_u4.ll +++ b/intrinsics/probes/mma_sp_ordered_metadata_m16n8k128_s32_u4.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_sp_ordered_metadata_m16n8k128_s32_u4_s4.ll b/intrinsics/probes/mma_sp_ordered_metadata_m16n8k128_s32_u4_s4.ll index 4eeeb3b6fc..8e5dc997c6 100644 --- a/intrinsics/probes/mma_sp_ordered_metadata_m16n8k128_s32_u4_s4.ll +++ b/intrinsics/probes/mma_sp_ordered_metadata_m16n8k128_s32_u4_s4.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_sp_ordered_metadata_m16n8k128_s32_u4_s4_satfinite.ll b/intrinsics/probes/mma_sp_ordered_metadata_m16n8k128_s32_u4_s4_satfinite.ll index 8555ef5ff2..c95079768b 100644 --- a/intrinsics/probes/mma_sp_ordered_metadata_m16n8k128_s32_u4_s4_satfinite.ll +++ b/intrinsics/probes/mma_sp_ordered_metadata_m16n8k128_s32_u4_s4_satfinite.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_sp_ordered_metadata_m16n8k128_s32_u4_satfinite.ll b/intrinsics/probes/mma_sp_ordered_metadata_m16n8k128_s32_u4_satfinite.ll index 55fcaf569d..4896a3c182 100644 --- a/intrinsics/probes/mma_sp_ordered_metadata_m16n8k128_s32_u4_satfinite.ll +++ b/intrinsics/probes/mma_sp_ordered_metadata_m16n8k128_s32_u4_satfinite.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_sp_ordered_metadata_m16n8k16_f16_f16.ll b/intrinsics/probes/mma_sp_ordered_metadata_m16n8k16_f16_f16.ll new file mode 100644 index 0000000000..a4ca33ec0a --- /dev/null +++ b/intrinsics/probes/mma_sp_ordered_metadata_m16n8k16_f16_f16.ll @@ -0,0 +1,26 @@ +; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. +; SPDX-License-Identifier: Apache-2.0 +; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. +; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. + +target triple = "nvptx64-nvidia-cuda" + +define { i32, i32 } @probe_mma_sp_ordered_metadata_m16n8k16_f16_f16_selector_0(i32 %c0, i32 %c1, i32 %a0, i32 %a1, i32 %b0, i32 %b1, i32 %metadata) #0 { + %result = call { i32, i32 } asm sideeffect "mma.sp::ordered_metadata.sync.aligned.m16n8k16.row.col.f16.f16.f16.f16 {$0, $1}, {$4, $5}, {$6, $7}, {$2, $3}, $8, $9;", "=r,=r,r,r,r,r,r,r,r,n"(i32 %c0, i32 %c1, i32 %a0, i32 %a1, i32 %b0, i32 %b1, i32 %metadata, i32 0) #0 + ret { i32, i32 } %result +} +define { i32, i32 } @probe_mma_sp_ordered_metadata_m16n8k16_f16_f16_selector_1(i32 %c0, i32 %c1, i32 %a0, i32 %a1, i32 %b0, i32 %b1, i32 %metadata) #0 { + %result = call { i32, i32 } asm sideeffect "mma.sp::ordered_metadata.sync.aligned.m16n8k16.row.col.f16.f16.f16.f16 {$0, $1}, {$4, $5}, {$6, $7}, {$2, $3}, $8, $9;", "=r,=r,r,r,r,r,r,r,r,n"(i32 %c0, i32 %c1, i32 %a0, i32 %a1, i32 %b0, i32 %b1, i32 %metadata, i32 1) #0 + ret { i32, i32 } %result +} +define { i32, i32 } @probe_mma_sp_ordered_metadata_m16n8k16_f16_f16_selector_2(i32 %c0, i32 %c1, i32 %a0, i32 %a1, i32 %b0, i32 %b1, i32 %metadata) #0 { + %result = call { i32, i32 } asm sideeffect "mma.sp::ordered_metadata.sync.aligned.m16n8k16.row.col.f16.f16.f16.f16 {$0, $1}, {$4, $5}, {$6, $7}, {$2, $3}, $8, $9;", "=r,=r,r,r,r,r,r,r,r,n"(i32 %c0, i32 %c1, i32 %a0, i32 %a1, i32 %b0, i32 %b1, i32 %metadata, i32 2) #0 + ret { i32, i32 } %result +} +define { i32, i32 } @probe_mma_sp_ordered_metadata_m16n8k16_f16_f16_selector_3(i32 %c0, i32 %c1, i32 %a0, i32 %a1, i32 %b0, i32 %b1, i32 %metadata) #0 { + %result = call { i32, i32 } asm sideeffect "mma.sp::ordered_metadata.sync.aligned.m16n8k16.row.col.f16.f16.f16.f16 {$0, $1}, {$4, $5}, {$6, $7}, {$2, $3}, $8, $9;", "=r,=r,r,r,r,r,r,r,r,n"(i32 %c0, i32 %c1, i32 %a0, i32 %a1, i32 %b0, i32 %b1, i32 %metadata, i32 3) #0 + ret { i32, i32 } %result +} + +attributes #0 = { convergent } diff --git a/intrinsics/probes/mma_sp_ordered_metadata_m16n8k16_f32_bf16.ll b/intrinsics/probes/mma_sp_ordered_metadata_m16n8k16_f32_bf16.ll new file mode 100644 index 0000000000..e6d4457df8 --- /dev/null +++ b/intrinsics/probes/mma_sp_ordered_metadata_m16n8k16_f32_bf16.ll @@ -0,0 +1,26 @@ +; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. +; SPDX-License-Identifier: Apache-2.0 +; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. +; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. + +target triple = "nvptx64-nvidia-cuda" + +define { float, float, float, float } @probe_mma_sp_ordered_metadata_m16n8k16_f32_bf16_selector_0(float %c0, float %c1, float %c2, float %c3, i32 %a0, i32 %a1, i32 %b0, i32 %b1, i32 %metadata) #0 { + %result = call { float, float, float, float } asm sideeffect "mma.sp::ordered_metadata.sync.aligned.m16n8k16.row.col.f32.bf16.bf16.f32 {$0, $1, $2, $3}, {$8, $9}, {$10, $11}, {$4, $5, $6, $7}, $12, $13;", "=f,=f,=f,=f,f,f,f,f,r,r,r,r,r,n"(float %c0, float %c1, float %c2, float %c3, i32 %a0, i32 %a1, i32 %b0, i32 %b1, i32 %metadata, i32 0) #0 + ret { float, float, float, float } %result +} +define { float, float, float, float } @probe_mma_sp_ordered_metadata_m16n8k16_f32_bf16_selector_1(float %c0, float %c1, float %c2, float %c3, i32 %a0, i32 %a1, i32 %b0, i32 %b1, i32 %metadata) #0 { + %result = call { float, float, float, float } asm sideeffect "mma.sp::ordered_metadata.sync.aligned.m16n8k16.row.col.f32.bf16.bf16.f32 {$0, $1, $2, $3}, {$8, $9}, {$10, $11}, {$4, $5, $6, $7}, $12, $13;", "=f,=f,=f,=f,f,f,f,f,r,r,r,r,r,n"(float %c0, float %c1, float %c2, float %c3, i32 %a0, i32 %a1, i32 %b0, i32 %b1, i32 %metadata, i32 1) #0 + ret { float, float, float, float } %result +} +define { float, float, float, float } @probe_mma_sp_ordered_metadata_m16n8k16_f32_bf16_selector_2(float %c0, float %c1, float %c2, float %c3, i32 %a0, i32 %a1, i32 %b0, i32 %b1, i32 %metadata) #0 { + %result = call { float, float, float, float } asm sideeffect "mma.sp::ordered_metadata.sync.aligned.m16n8k16.row.col.f32.bf16.bf16.f32 {$0, $1, $2, $3}, {$8, $9}, {$10, $11}, {$4, $5, $6, $7}, $12, $13;", "=f,=f,=f,=f,f,f,f,f,r,r,r,r,r,n"(float %c0, float %c1, float %c2, float %c3, i32 %a0, i32 %a1, i32 %b0, i32 %b1, i32 %metadata, i32 2) #0 + ret { float, float, float, float } %result +} +define { float, float, float, float } @probe_mma_sp_ordered_metadata_m16n8k16_f32_bf16_selector_3(float %c0, float %c1, float %c2, float %c3, i32 %a0, i32 %a1, i32 %b0, i32 %b1, i32 %metadata) #0 { + %result = call { float, float, float, float } asm sideeffect "mma.sp::ordered_metadata.sync.aligned.m16n8k16.row.col.f32.bf16.bf16.f32 {$0, $1, $2, $3}, {$8, $9}, {$10, $11}, {$4, $5, $6, $7}, $12, $13;", "=f,=f,=f,=f,f,f,f,f,r,r,r,r,r,n"(float %c0, float %c1, float %c2, float %c3, i32 %a0, i32 %a1, i32 %b0, i32 %b1, i32 %metadata, i32 3) #0 + ret { float, float, float, float } %result +} + +attributes #0 = { convergent } diff --git a/intrinsics/probes/mma_sp_ordered_metadata_m16n8k16_f32_f16.ll b/intrinsics/probes/mma_sp_ordered_metadata_m16n8k16_f32_f16.ll new file mode 100644 index 0000000000..50fce10da2 --- /dev/null +++ b/intrinsics/probes/mma_sp_ordered_metadata_m16n8k16_f32_f16.ll @@ -0,0 +1,26 @@ +; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. +; SPDX-License-Identifier: Apache-2.0 +; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. +; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. + +target triple = "nvptx64-nvidia-cuda" + +define { float, float, float, float } @probe_mma_sp_ordered_metadata_m16n8k16_f32_f16_selector_0(float %c0, float %c1, float %c2, float %c3, i32 %a0, i32 %a1, i32 %b0, i32 %b1, i32 %metadata) #0 { + %result = call { float, float, float, float } asm sideeffect "mma.sp::ordered_metadata.sync.aligned.m16n8k16.row.col.f32.f16.f16.f32 {$0, $1, $2, $3}, {$8, $9}, {$10, $11}, {$4, $5, $6, $7}, $12, $13;", "=f,=f,=f,=f,f,f,f,f,r,r,r,r,r,n"(float %c0, float %c1, float %c2, float %c3, i32 %a0, i32 %a1, i32 %b0, i32 %b1, i32 %metadata, i32 0) #0 + ret { float, float, float, float } %result +} +define { float, float, float, float } @probe_mma_sp_ordered_metadata_m16n8k16_f32_f16_selector_1(float %c0, float %c1, float %c2, float %c3, i32 %a0, i32 %a1, i32 %b0, i32 %b1, i32 %metadata) #0 { + %result = call { float, float, float, float } asm sideeffect "mma.sp::ordered_metadata.sync.aligned.m16n8k16.row.col.f32.f16.f16.f32 {$0, $1, $2, $3}, {$8, $9}, {$10, $11}, {$4, $5, $6, $7}, $12, $13;", "=f,=f,=f,=f,f,f,f,f,r,r,r,r,r,n"(float %c0, float %c1, float %c2, float %c3, i32 %a0, i32 %a1, i32 %b0, i32 %b1, i32 %metadata, i32 1) #0 + ret { float, float, float, float } %result +} +define { float, float, float, float } @probe_mma_sp_ordered_metadata_m16n8k16_f32_f16_selector_2(float %c0, float %c1, float %c2, float %c3, i32 %a0, i32 %a1, i32 %b0, i32 %b1, i32 %metadata) #0 { + %result = call { float, float, float, float } asm sideeffect "mma.sp::ordered_metadata.sync.aligned.m16n8k16.row.col.f32.f16.f16.f32 {$0, $1, $2, $3}, {$8, $9}, {$10, $11}, {$4, $5, $6, $7}, $12, $13;", "=f,=f,=f,=f,f,f,f,f,r,r,r,r,r,n"(float %c0, float %c1, float %c2, float %c3, i32 %a0, i32 %a1, i32 %b0, i32 %b1, i32 %metadata, i32 2) #0 + ret { float, float, float, float } %result +} +define { float, float, float, float } @probe_mma_sp_ordered_metadata_m16n8k16_f32_f16_selector_3(float %c0, float %c1, float %c2, float %c3, i32 %a0, i32 %a1, i32 %b0, i32 %b1, i32 %metadata) #0 { + %result = call { float, float, float, float } asm sideeffect "mma.sp::ordered_metadata.sync.aligned.m16n8k16.row.col.f32.f16.f16.f32 {$0, $1, $2, $3}, {$8, $9}, {$10, $11}, {$4, $5, $6, $7}, $12, $13;", "=f,=f,=f,=f,f,f,f,f,r,r,r,r,r,n"(float %c0, float %c1, float %c2, float %c3, i32 %a0, i32 %a1, i32 %b0, i32 %b1, i32 %metadata, i32 3) #0 + ret { float, float, float, float } %result +} + +attributes #0 = { convergent } diff --git a/intrinsics/probes/mma_sp_ordered_metadata_m16n8k16_f32_tf32.ll b/intrinsics/probes/mma_sp_ordered_metadata_m16n8k16_f32_tf32.ll new file mode 100644 index 0000000000..1b5726b8e5 --- /dev/null +++ b/intrinsics/probes/mma_sp_ordered_metadata_m16n8k16_f32_tf32.ll @@ -0,0 +1,18 @@ +; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. +; SPDX-License-Identifier: Apache-2.0 +; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. +; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. + +target triple = "nvptx64-nvidia-cuda" + +define { float, float, float, float } @probe_mma_sp_ordered_metadata_m16n8k16_f32_tf32_selector_0(float %c0, float %c1, float %c2, float %c3, i32 %a0, i32 %a1, i32 %a2, i32 %a3, i32 %b0, i32 %b1, i32 %b2, i32 %b3, i32 %metadata) #0 { + %result = call { float, float, float, float } asm sideeffect "mma.sp::ordered_metadata.sync.aligned.m16n8k16.row.col.f32.tf32.tf32.f32 {$0, $1, $2, $3}, {$8, $9, $10, $11}, {$12, $13, $14, $15}, {$4, $5, $6, $7}, $16, $17;", "=f,=f,=f,=f,f,f,f,f,r,r,r,r,r,r,r,r,r,n"(float %c0, float %c1, float %c2, float %c3, i32 %a0, i32 %a1, i32 %a2, i32 %a3, i32 %b0, i32 %b1, i32 %b2, i32 %b3, i32 %metadata, i32 0) #0 + ret { float, float, float, float } %result +} +define { float, float, float, float } @probe_mma_sp_ordered_metadata_m16n8k16_f32_tf32_selector_1(float %c0, float %c1, float %c2, float %c3, i32 %a0, i32 %a1, i32 %a2, i32 %a3, i32 %b0, i32 %b1, i32 %b2, i32 %b3, i32 %metadata) #0 { + %result = call { float, float, float, float } asm sideeffect "mma.sp::ordered_metadata.sync.aligned.m16n8k16.row.col.f32.tf32.tf32.f32 {$0, $1, $2, $3}, {$8, $9, $10, $11}, {$12, $13, $14, $15}, {$4, $5, $6, $7}, $16, $17;", "=f,=f,=f,=f,f,f,f,f,r,r,r,r,r,r,r,r,r,n"(float %c0, float %c1, float %c2, float %c3, i32 %a0, i32 %a1, i32 %a2, i32 %a3, i32 %b0, i32 %b1, i32 %b2, i32 %b3, i32 %metadata, i32 1) #0 + ret { float, float, float, float } %result +} + +attributes #0 = { convergent } diff --git a/intrinsics/probes/mma_sp_ordered_metadata_m16n8k32_f16_f16.ll b/intrinsics/probes/mma_sp_ordered_metadata_m16n8k32_f16_f16.ll new file mode 100644 index 0000000000..7ebaefee05 --- /dev/null +++ b/intrinsics/probes/mma_sp_ordered_metadata_m16n8k32_f16_f16.ll @@ -0,0 +1,18 @@ +; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. +; SPDX-License-Identifier: Apache-2.0 +; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. +; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. + +target triple = "nvptx64-nvidia-cuda" + +define { i32, i32 } @probe_mma_sp_ordered_metadata_m16n8k32_f16_f16_selector_0(i32 %c0, i32 %c1, i32 %a0, i32 %a1, i32 %a2, i32 %a3, i32 %b0, i32 %b1, i32 %b2, i32 %b3, i32 %metadata) #0 { + %result = call { i32, i32 } asm sideeffect "mma.sp::ordered_metadata.sync.aligned.m16n8k32.row.col.f16.f16.f16.f16 {$0, $1}, {$4, $5, $6, $7}, {$8, $9, $10, $11}, {$2, $3}, $12, $13;", "=r,=r,r,r,r,r,r,r,r,r,r,r,r,n"(i32 %c0, i32 %c1, i32 %a0, i32 %a1, i32 %a2, i32 %a3, i32 %b0, i32 %b1, i32 %b2, i32 %b3, i32 %metadata, i32 0) #0 + ret { i32, i32 } %result +} +define { i32, i32 } @probe_mma_sp_ordered_metadata_m16n8k32_f16_f16_selector_1(i32 %c0, i32 %c1, i32 %a0, i32 %a1, i32 %a2, i32 %a3, i32 %b0, i32 %b1, i32 %b2, i32 %b3, i32 %metadata) #0 { + %result = call { i32, i32 } asm sideeffect "mma.sp::ordered_metadata.sync.aligned.m16n8k32.row.col.f16.f16.f16.f16 {$0, $1}, {$4, $5, $6, $7}, {$8, $9, $10, $11}, {$2, $3}, $12, $13;", "=r,=r,r,r,r,r,r,r,r,r,r,r,r,n"(i32 %c0, i32 %c1, i32 %a0, i32 %a1, i32 %a2, i32 %a3, i32 %b0, i32 %b1, i32 %b2, i32 %b3, i32 %metadata, i32 1) #0 + ret { i32, i32 } %result +} + +attributes #0 = { convergent } diff --git a/intrinsics/probes/mma_sp_ordered_metadata_m16n8k32_f32_bf16.ll b/intrinsics/probes/mma_sp_ordered_metadata_m16n8k32_f32_bf16.ll new file mode 100644 index 0000000000..6f10c542d4 --- /dev/null +++ b/intrinsics/probes/mma_sp_ordered_metadata_m16n8k32_f32_bf16.ll @@ -0,0 +1,18 @@ +; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. +; SPDX-License-Identifier: Apache-2.0 +; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. +; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. + +target triple = "nvptx64-nvidia-cuda" + +define { float, float, float, float } @probe_mma_sp_ordered_metadata_m16n8k32_f32_bf16_selector_0(float %c0, float %c1, float %c2, float %c3, i32 %a0, i32 %a1, i32 %a2, i32 %a3, i32 %b0, i32 %b1, i32 %b2, i32 %b3, i32 %metadata) #0 { + %result = call { float, float, float, float } asm sideeffect "mma.sp::ordered_metadata.sync.aligned.m16n8k32.row.col.f32.bf16.bf16.f32 {$0, $1, $2, $3}, {$8, $9, $10, $11}, {$12, $13, $14, $15}, {$4, $5, $6, $7}, $16, $17;", "=f,=f,=f,=f,f,f,f,f,r,r,r,r,r,r,r,r,r,n"(float %c0, float %c1, float %c2, float %c3, i32 %a0, i32 %a1, i32 %a2, i32 %a3, i32 %b0, i32 %b1, i32 %b2, i32 %b3, i32 %metadata, i32 0) #0 + ret { float, float, float, float } %result +} +define { float, float, float, float } @probe_mma_sp_ordered_metadata_m16n8k32_f32_bf16_selector_1(float %c0, float %c1, float %c2, float %c3, i32 %a0, i32 %a1, i32 %a2, i32 %a3, i32 %b0, i32 %b1, i32 %b2, i32 %b3, i32 %metadata) #0 { + %result = call { float, float, float, float } asm sideeffect "mma.sp::ordered_metadata.sync.aligned.m16n8k32.row.col.f32.bf16.bf16.f32 {$0, $1, $2, $3}, {$8, $9, $10, $11}, {$12, $13, $14, $15}, {$4, $5, $6, $7}, $16, $17;", "=f,=f,=f,=f,f,f,f,f,r,r,r,r,r,r,r,r,r,n"(float %c0, float %c1, float %c2, float %c3, i32 %a0, i32 %a1, i32 %a2, i32 %a3, i32 %b0, i32 %b1, i32 %b2, i32 %b3, i32 %metadata, i32 1) #0 + ret { float, float, float, float } %result +} + +attributes #0 = { convergent } diff --git a/intrinsics/probes/mma_sp_ordered_metadata_m16n8k32_f32_f16.ll b/intrinsics/probes/mma_sp_ordered_metadata_m16n8k32_f32_f16.ll new file mode 100644 index 0000000000..770bed1f1a --- /dev/null +++ b/intrinsics/probes/mma_sp_ordered_metadata_m16n8k32_f32_f16.ll @@ -0,0 +1,18 @@ +; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. +; SPDX-License-Identifier: Apache-2.0 +; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. +; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. + +target triple = "nvptx64-nvidia-cuda" + +define { float, float, float, float } @probe_mma_sp_ordered_metadata_m16n8k32_f32_f16_selector_0(float %c0, float %c1, float %c2, float %c3, i32 %a0, i32 %a1, i32 %a2, i32 %a3, i32 %b0, i32 %b1, i32 %b2, i32 %b3, i32 %metadata) #0 { + %result = call { float, float, float, float } asm sideeffect "mma.sp::ordered_metadata.sync.aligned.m16n8k32.row.col.f32.f16.f16.f32 {$0, $1, $2, $3}, {$8, $9, $10, $11}, {$12, $13, $14, $15}, {$4, $5, $6, $7}, $16, $17;", "=f,=f,=f,=f,f,f,f,f,r,r,r,r,r,r,r,r,r,n"(float %c0, float %c1, float %c2, float %c3, i32 %a0, i32 %a1, i32 %a2, i32 %a3, i32 %b0, i32 %b1, i32 %b2, i32 %b3, i32 %metadata, i32 0) #0 + ret { float, float, float, float } %result +} +define { float, float, float, float } @probe_mma_sp_ordered_metadata_m16n8k32_f32_f16_selector_1(float %c0, float %c1, float %c2, float %c3, i32 %a0, i32 %a1, i32 %a2, i32 %a3, i32 %b0, i32 %b1, i32 %b2, i32 %b3, i32 %metadata) #0 { + %result = call { float, float, float, float } asm sideeffect "mma.sp::ordered_metadata.sync.aligned.m16n8k32.row.col.f32.f16.f16.f32 {$0, $1, $2, $3}, {$8, $9, $10, $11}, {$12, $13, $14, $15}, {$4, $5, $6, $7}, $16, $17;", "=f,=f,=f,=f,f,f,f,f,r,r,r,r,r,r,r,r,r,n"(float %c0, float %c1, float %c2, float %c3, i32 %a0, i32 %a1, i32 %a2, i32 %a3, i32 %b0, i32 %b1, i32 %b2, i32 %b3, i32 %metadata, i32 1) #0 + ret { float, float, float, float } %result +} + +attributes #0 = { convergent } diff --git a/intrinsics/probes/mma_sp_ordered_metadata_m16n8k32_s32_s8.ll b/intrinsics/probes/mma_sp_ordered_metadata_m16n8k32_s32_s8.ll index b619a55529..fa58cdbff6 100644 --- a/intrinsics/probes/mma_sp_ordered_metadata_m16n8k32_s32_s8.ll +++ b/intrinsics/probes/mma_sp_ordered_metadata_m16n8k32_s32_s8.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_sp_ordered_metadata_m16n8k32_s32_s8_satfinite.ll b/intrinsics/probes/mma_sp_ordered_metadata_m16n8k32_s32_s8_satfinite.ll index 11d501e644..dcc289756d 100644 --- a/intrinsics/probes/mma_sp_ordered_metadata_m16n8k32_s32_s8_satfinite.ll +++ b/intrinsics/probes/mma_sp_ordered_metadata_m16n8k32_s32_s8_satfinite.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_sp_ordered_metadata_m16n8k32_s32_s8_u8.ll b/intrinsics/probes/mma_sp_ordered_metadata_m16n8k32_s32_s8_u8.ll index 957f1c4911..0b18c7236c 100644 --- a/intrinsics/probes/mma_sp_ordered_metadata_m16n8k32_s32_s8_u8.ll +++ b/intrinsics/probes/mma_sp_ordered_metadata_m16n8k32_s32_s8_u8.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_sp_ordered_metadata_m16n8k32_s32_s8_u8_satfinite.ll b/intrinsics/probes/mma_sp_ordered_metadata_m16n8k32_s32_s8_u8_satfinite.ll index 71c24ca017..596aceb445 100644 --- a/intrinsics/probes/mma_sp_ordered_metadata_m16n8k32_s32_s8_u8_satfinite.ll +++ b/intrinsics/probes/mma_sp_ordered_metadata_m16n8k32_s32_s8_u8_satfinite.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_sp_ordered_metadata_m16n8k32_s32_u8.ll b/intrinsics/probes/mma_sp_ordered_metadata_m16n8k32_s32_u8.ll index 9d21299bfb..26dab5df37 100644 --- a/intrinsics/probes/mma_sp_ordered_metadata_m16n8k32_s32_u8.ll +++ b/intrinsics/probes/mma_sp_ordered_metadata_m16n8k32_s32_u8.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_sp_ordered_metadata_m16n8k32_s32_u8_s8.ll b/intrinsics/probes/mma_sp_ordered_metadata_m16n8k32_s32_u8_s8.ll index 507932dcaa..348301bd74 100644 --- a/intrinsics/probes/mma_sp_ordered_metadata_m16n8k32_s32_u8_s8.ll +++ b/intrinsics/probes/mma_sp_ordered_metadata_m16n8k32_s32_u8_s8.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_sp_ordered_metadata_m16n8k32_s32_u8_s8_satfinite.ll b/intrinsics/probes/mma_sp_ordered_metadata_m16n8k32_s32_u8_s8_satfinite.ll index 0868339bc9..47d6fa962f 100644 --- a/intrinsics/probes/mma_sp_ordered_metadata_m16n8k32_s32_u8_s8_satfinite.ll +++ b/intrinsics/probes/mma_sp_ordered_metadata_m16n8k32_s32_u8_s8_satfinite.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_sp_ordered_metadata_m16n8k32_s32_u8_satfinite.ll b/intrinsics/probes/mma_sp_ordered_metadata_m16n8k32_s32_u8_satfinite.ll index e67e348119..327ee8b4b7 100644 --- a/intrinsics/probes/mma_sp_ordered_metadata_m16n8k32_s32_u8_satfinite.ll +++ b/intrinsics/probes/mma_sp_ordered_metadata_m16n8k32_s32_u8_satfinite.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e2m1_e2m1_f16.ll b/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e2m1_e2m1_f16.ll index 6870997f99..c74396cf78 100644 --- a/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e2m1_e2m1_f16.ll +++ b/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e2m1_e2m1_f16.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e2m1_e2m3_f16.ll b/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e2m1_e2m3_f16.ll index 079baff417..eb8b3053f5 100644 --- a/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e2m1_e2m3_f16.ll +++ b/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e2m1_e2m3_f16.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e2m1_e3m2_f16.ll b/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e2m1_e3m2_f16.ll index 3a1486a0b9..4e351f270b 100644 --- a/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e2m1_e3m2_f16.ll +++ b/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e2m1_e3m2_f16.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e2m1_e4m3_f16.ll b/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e2m1_e4m3_f16.ll index a5f209ea48..232ba4febb 100644 --- a/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e2m1_e4m3_f16.ll +++ b/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e2m1_e4m3_f16.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e2m1_e5m2_f16.ll b/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e2m1_e5m2_f16.ll index bab6a2827a..ed009fd2a2 100644 --- a/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e2m1_e5m2_f16.ll +++ b/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e2m1_e5m2_f16.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e2m3_e2m1_f16.ll b/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e2m3_e2m1_f16.ll index e887da76a9..6f3fd5ba4a 100644 --- a/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e2m3_e2m1_f16.ll +++ b/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e2m3_e2m1_f16.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e2m3_e2m3_f16.ll b/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e2m3_e2m3_f16.ll index df47680037..c7c303b358 100644 --- a/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e2m3_e2m3_f16.ll +++ b/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e2m3_e2m3_f16.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e2m3_e3m2_f16.ll b/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e2m3_e3m2_f16.ll index 58bebfd4c7..69369e9889 100644 --- a/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e2m3_e3m2_f16.ll +++ b/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e2m3_e3m2_f16.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e2m3_e4m3_f16.ll b/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e2m3_e4m3_f16.ll index 54554f3f13..6b01b9e2f3 100644 --- a/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e2m3_e4m3_f16.ll +++ b/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e2m3_e4m3_f16.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e2m3_e5m2_f16.ll b/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e2m3_e5m2_f16.ll index e1bba040b0..bd173567f9 100644 --- a/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e2m3_e5m2_f16.ll +++ b/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e2m3_e5m2_f16.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e3m2_e2m1_f16.ll b/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e3m2_e2m1_f16.ll index 5850031ec7..3698519534 100644 --- a/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e3m2_e2m1_f16.ll +++ b/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e3m2_e2m1_f16.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e3m2_e2m3_f16.ll b/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e3m2_e2m3_f16.ll index ecb51809bc..af215d45ef 100644 --- a/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e3m2_e2m3_f16.ll +++ b/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e3m2_e2m3_f16.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e3m2_e3m2_f16.ll b/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e3m2_e3m2_f16.ll index ae52420a76..efdc478255 100644 --- a/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e3m2_e3m2_f16.ll +++ b/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e3m2_e3m2_f16.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e3m2_e4m3_f16.ll b/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e3m2_e4m3_f16.ll index d738838d4b..b4156b05a3 100644 --- a/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e3m2_e4m3_f16.ll +++ b/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e3m2_e4m3_f16.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e3m2_e5m2_f16.ll b/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e3m2_e5m2_f16.ll index 13be0c90a5..a79fb5764f 100644 --- a/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e3m2_e5m2_f16.ll +++ b/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e3m2_e5m2_f16.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e4m3_e2m1_f16.ll b/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e4m3_e2m1_f16.ll index 39f6fd0fe3..c1508a1110 100644 --- a/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e4m3_e2m1_f16.ll +++ b/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e4m3_e2m1_f16.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e4m3_e2m3_f16.ll b/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e4m3_e2m3_f16.ll index 1cbb9fe850..4c97d8067e 100644 --- a/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e4m3_e2m3_f16.ll +++ b/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e4m3_e2m3_f16.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e4m3_e3m2_f16.ll b/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e4m3_e3m2_f16.ll index 6c69770512..b77e8b95ae 100644 --- a/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e4m3_e3m2_f16.ll +++ b/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e4m3_e3m2_f16.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e4m3_e4m3_f16.ll b/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e4m3_e4m3_f16.ll index 6d6b9dcbc0..1131759139 100644 --- a/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e4m3_e4m3_f16.ll +++ b/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e4m3_e4m3_f16.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e4m3_e5m2_f16.ll b/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e4m3_e5m2_f16.ll index ccf6c195e1..286a9987d9 100644 --- a/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e4m3_e5m2_f16.ll +++ b/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e4m3_e5m2_f16.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e5m2_e2m1_f16.ll b/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e5m2_e2m1_f16.ll index 6d981f61d9..6dafb6268e 100644 --- a/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e5m2_e2m1_f16.ll +++ b/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e5m2_e2m1_f16.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e5m2_e2m3_f16.ll b/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e5m2_e2m3_f16.ll index d199b9f61e..a663f7f58d 100644 --- a/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e5m2_e2m3_f16.ll +++ b/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e5m2_e2m3_f16.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e5m2_e3m2_f16.ll b/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e5m2_e3m2_f16.ll index b4cfd50d6e..00e0c95b5e 100644 --- a/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e5m2_e3m2_f16.ll +++ b/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e5m2_e3m2_f16.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e5m2_e4m3_f16.ll b/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e5m2_e4m3_f16.ll index 07c1b88fd1..6ae1da4f88 100644 --- a/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e5m2_e4m3_f16.ll +++ b/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e5m2_e4m3_f16.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e5m2_e5m2_f16.ll b/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e5m2_e5m2_f16.ll index cab969dd61..a86299a3ae 100644 --- a/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e5m2_e5m2_f16.ll +++ b/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e5m2_e5m2_f16.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e2m1_e2m1_f32.ll b/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e2m1_e2m1_f32.ll index a59ae95d43..72efb5833e 100644 --- a/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e2m1_e2m1_f32.ll +++ b/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e2m1_e2m1_f32.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e2m1_e2m3_f32.ll b/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e2m1_e2m3_f32.ll index 690f1a72c4..760f2e7bb2 100644 --- a/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e2m1_e2m3_f32.ll +++ b/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e2m1_e2m3_f32.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e2m1_e3m2_f32.ll b/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e2m1_e3m2_f32.ll index bee9fd10e2..d49b14074b 100644 --- a/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e2m1_e3m2_f32.ll +++ b/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e2m1_e3m2_f32.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e2m1_e4m3_f32.ll b/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e2m1_e4m3_f32.ll index 1dd2ec9466..b980765082 100644 --- a/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e2m1_e4m3_f32.ll +++ b/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e2m1_e4m3_f32.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e2m1_e5m2_f32.ll b/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e2m1_e5m2_f32.ll index a5e0319bac..387a39e2ff 100644 --- a/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e2m1_e5m2_f32.ll +++ b/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e2m1_e5m2_f32.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e2m3_e2m1_f32.ll b/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e2m3_e2m1_f32.ll index c075c28915..21f07a17b2 100644 --- a/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e2m3_e2m1_f32.ll +++ b/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e2m3_e2m1_f32.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e2m3_e2m3_f32.ll b/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e2m3_e2m3_f32.ll index 5db28e139e..39d40f62fe 100644 --- a/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e2m3_e2m3_f32.ll +++ b/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e2m3_e2m3_f32.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e2m3_e3m2_f32.ll b/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e2m3_e3m2_f32.ll index 0b7bb5bb62..b122961d41 100644 --- a/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e2m3_e3m2_f32.ll +++ b/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e2m3_e3m2_f32.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e2m3_e4m3_f32.ll b/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e2m3_e4m3_f32.ll index 4a53e07dec..c30342ddc5 100644 --- a/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e2m3_e4m3_f32.ll +++ b/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e2m3_e4m3_f32.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e2m3_e5m2_f32.ll b/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e2m3_e5m2_f32.ll index 71648f6316..57a860697e 100644 --- a/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e2m3_e5m2_f32.ll +++ b/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e2m3_e5m2_f32.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e3m2_e2m1_f32.ll b/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e3m2_e2m1_f32.ll index 25878af74a..e59ec6a1ef 100644 --- a/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e3m2_e2m1_f32.ll +++ b/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e3m2_e2m1_f32.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e3m2_e2m3_f32.ll b/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e3m2_e2m3_f32.ll index 2034907650..26d0e9a9d3 100644 --- a/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e3m2_e2m3_f32.ll +++ b/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e3m2_e2m3_f32.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e3m2_e3m2_f32.ll b/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e3m2_e3m2_f32.ll index 4a4ca52550..7f0e9677c7 100644 --- a/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e3m2_e3m2_f32.ll +++ b/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e3m2_e3m2_f32.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e3m2_e4m3_f32.ll b/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e3m2_e4m3_f32.ll index a7edf0b0e6..ecba3f057c 100644 --- a/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e3m2_e4m3_f32.ll +++ b/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e3m2_e4m3_f32.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e3m2_e5m2_f32.ll b/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e3m2_e5m2_f32.ll index 7760b299de..c141cac592 100644 --- a/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e3m2_e5m2_f32.ll +++ b/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e3m2_e5m2_f32.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e4m3_e2m1_f32.ll b/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e4m3_e2m1_f32.ll index eca69e2d75..e1388dab7b 100644 --- a/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e4m3_e2m1_f32.ll +++ b/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e4m3_e2m1_f32.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e4m3_e2m3_f32.ll b/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e4m3_e2m3_f32.ll index 6c48136937..039c058613 100644 --- a/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e4m3_e2m3_f32.ll +++ b/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e4m3_e2m3_f32.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e4m3_e3m2_f32.ll b/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e4m3_e3m2_f32.ll index c23874baf4..30f699c1a6 100644 --- a/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e4m3_e3m2_f32.ll +++ b/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e4m3_e3m2_f32.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e4m3_e4m3_f32.ll b/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e4m3_e4m3_f32.ll index 561adb54f4..4288b737e1 100644 --- a/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e4m3_e4m3_f32.ll +++ b/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e4m3_e4m3_f32.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e4m3_e5m2_f32.ll b/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e4m3_e5m2_f32.ll index 670d319857..49ec37bd29 100644 --- a/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e4m3_e5m2_f32.ll +++ b/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e4m3_e5m2_f32.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e5m2_e2m1_f32.ll b/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e5m2_e2m1_f32.ll index e81557561f..0943f3dc3c 100644 --- a/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e5m2_e2m1_f32.ll +++ b/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e5m2_e2m1_f32.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e5m2_e2m3_f32.ll b/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e5m2_e2m3_f32.ll index ad9e3bf394..cf50621384 100644 --- a/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e5m2_e2m3_f32.ll +++ b/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e5m2_e2m3_f32.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e5m2_e3m2_f32.ll b/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e5m2_e3m2_f32.ll index 85c647b914..fb5d7678be 100644 --- a/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e5m2_e3m2_f32.ll +++ b/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e5m2_e3m2_f32.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e5m2_e4m3_f32.ll b/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e5m2_e4m3_f32.ll index 6fda594758..9e8f837bb5 100644 --- a/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e5m2_e4m3_f32.ll +++ b/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e5m2_e4m3_f32.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e5m2_e5m2_f32.ll b/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e5m2_e5m2_f32.ll index e405fe8f88..844687cafe 100644 --- a/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e5m2_e5m2_f32.ll +++ b/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e5m2_e5m2_f32.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_s32_s4.ll b/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_s32_s4.ll index b5e854d2f5..60f53577e8 100644 --- a/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_s32_s4.ll +++ b/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_s32_s4.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_s32_s4_satfinite.ll b/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_s32_s4_satfinite.ll index d4a20db95e..1c697f9f0a 100644 --- a/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_s32_s4_satfinite.ll +++ b/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_s32_s4_satfinite.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_s32_s4_u4.ll b/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_s32_s4_u4.ll index a35a57e12f..5e5f12055e 100644 --- a/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_s32_s4_u4.ll +++ b/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_s32_s4_u4.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_s32_s4_u4_satfinite.ll b/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_s32_s4_u4_satfinite.ll index 024987eecc..50bcd748a8 100644 --- a/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_s32_s4_u4_satfinite.ll +++ b/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_s32_s4_u4_satfinite.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_s32_s8.ll b/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_s32_s8.ll index ce996ea1dc..e1bdfa2bb7 100644 --- a/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_s32_s8.ll +++ b/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_s32_s8.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_s32_s8_satfinite.ll b/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_s32_s8_satfinite.ll index cce7683006..4b5042b666 100644 --- a/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_s32_s8_satfinite.ll +++ b/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_s32_s8_satfinite.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_s32_s8_u8.ll b/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_s32_s8_u8.ll index faac6bf587..e09157982b 100644 --- a/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_s32_s8_u8.ll +++ b/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_s32_s8_u8.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_s32_s8_u8_satfinite.ll b/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_s32_s8_u8_satfinite.ll index d6168ce256..708f672846 100644 --- a/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_s32_s8_u8_satfinite.ll +++ b/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_s32_s8_u8_satfinite.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_s32_u4.ll b/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_s32_u4.ll index 84e52865b8..2e48fa4df2 100644 --- a/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_s32_u4.ll +++ b/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_s32_u4.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_s32_u4_s4.ll b/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_s32_u4_s4.ll index fa83b43e1a..883bb01abc 100644 --- a/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_s32_u4_s4.ll +++ b/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_s32_u4_s4.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_s32_u4_s4_satfinite.ll b/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_s32_u4_s4_satfinite.ll index 0de9ab28af..0bf3b2c81c 100644 --- a/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_s32_u4_s4_satfinite.ll +++ b/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_s32_u4_s4_satfinite.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_s32_u4_satfinite.ll b/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_s32_u4_satfinite.ll index 53115acccf..fa996482c9 100644 --- a/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_s32_u4_satfinite.ll +++ b/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_s32_u4_satfinite.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_s32_u8.ll b/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_s32_u8.ll index 4985b68f73..a9136e0079 100644 --- a/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_s32_u8.ll +++ b/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_s32_u8.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_s32_u8_s8.ll b/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_s32_u8_s8.ll index 9eee865423..dc6271cff7 100644 --- a/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_s32_u8_s8.ll +++ b/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_s32_u8_s8.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_s32_u8_s8_satfinite.ll b/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_s32_u8_s8_satfinite.ll index a0bc988004..1b40519c7e 100644 --- a/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_s32_u8_s8_satfinite.ll +++ b/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_s32_u8_s8_satfinite.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_s32_u8_satfinite.ll b/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_s32_u8_satfinite.ll index e44732f855..7415587910 100644 --- a/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_s32_u8_satfinite.ll +++ b/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_s32_u8_satfinite.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_sp_ordered_metadata_m16n8k8_f32_tf32.ll b/intrinsics/probes/mma_sp_ordered_metadata_m16n8k8_f32_tf32.ll new file mode 100644 index 0000000000..d2da021b6c --- /dev/null +++ b/intrinsics/probes/mma_sp_ordered_metadata_m16n8k8_f32_tf32.ll @@ -0,0 +1,26 @@ +; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. +; SPDX-License-Identifier: Apache-2.0 +; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. +; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. + +target triple = "nvptx64-nvidia-cuda" + +define { float, float, float, float } @probe_mma_sp_ordered_metadata_m16n8k8_f32_tf32_selector_0(float %c0, float %c1, float %c2, float %c3, i32 %a0, i32 %a1, i32 %b0, i32 %b1, i32 %metadata) #0 { + %result = call { float, float, float, float } asm sideeffect "mma.sp::ordered_metadata.sync.aligned.m16n8k8.row.col.f32.tf32.tf32.f32 {$0, $1, $2, $3}, {$8, $9}, {$10, $11}, {$4, $5, $6, $7}, $12, $13;", "=f,=f,=f,=f,f,f,f,f,r,r,r,r,r,n"(float %c0, float %c1, float %c2, float %c3, i32 %a0, i32 %a1, i32 %b0, i32 %b1, i32 %metadata, i32 0) #0 + ret { float, float, float, float } %result +} +define { float, float, float, float } @probe_mma_sp_ordered_metadata_m16n8k8_f32_tf32_selector_1(float %c0, float %c1, float %c2, float %c3, i32 %a0, i32 %a1, i32 %b0, i32 %b1, i32 %metadata) #0 { + %result = call { float, float, float, float } asm sideeffect "mma.sp::ordered_metadata.sync.aligned.m16n8k8.row.col.f32.tf32.tf32.f32 {$0, $1, $2, $3}, {$8, $9}, {$10, $11}, {$4, $5, $6, $7}, $12, $13;", "=f,=f,=f,=f,f,f,f,f,r,r,r,r,r,n"(float %c0, float %c1, float %c2, float %c3, i32 %a0, i32 %a1, i32 %b0, i32 %b1, i32 %metadata, i32 1) #0 + ret { float, float, float, float } %result +} +define { float, float, float, float } @probe_mma_sp_ordered_metadata_m16n8k8_f32_tf32_selector_2(float %c0, float %c1, float %c2, float %c3, i32 %a0, i32 %a1, i32 %b0, i32 %b1, i32 %metadata) #0 { + %result = call { float, float, float, float } asm sideeffect "mma.sp::ordered_metadata.sync.aligned.m16n8k8.row.col.f32.tf32.tf32.f32 {$0, $1, $2, $3}, {$8, $9}, {$10, $11}, {$4, $5, $6, $7}, $12, $13;", "=f,=f,=f,=f,f,f,f,f,r,r,r,r,r,n"(float %c0, float %c1, float %c2, float %c3, i32 %a0, i32 %a1, i32 %b0, i32 %b1, i32 %metadata, i32 2) #0 + ret { float, float, float, float } %result +} +define { float, float, float, float } @probe_mma_sp_ordered_metadata_m16n8k8_f32_tf32_selector_3(float %c0, float %c1, float %c2, float %c3, i32 %a0, i32 %a1, i32 %b0, i32 %b1, i32 %metadata) #0 { + %result = call { float, float, float, float } asm sideeffect "mma.sp::ordered_metadata.sync.aligned.m16n8k8.row.col.f32.tf32.tf32.f32 {$0, $1, $2, $3}, {$8, $9}, {$10, $11}, {$4, $5, $6, $7}, $12, $13;", "=f,=f,=f,=f,f,f,f,f,r,r,r,r,r,n"(float %c0, float %c1, float %c2, float %c3, i32 %a0, i32 %a1, i32 %b0, i32 %b1, i32 %metadata, i32 3) #0 + ret { float, float, float, float } %result +} + +attributes #0 = { convergent } diff --git a/intrinsics/probes/movmatrix_trans_b16.ll b/intrinsics/probes/movmatrix_trans_b16.ll index 6fe10e1f8b..cc3b8a8669 100644 --- a/intrinsics/probes/movmatrix_trans_b16.ll +++ b/intrinsics/probes/movmatrix_trans_b16.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mul_bf16x2.ll b/intrinsics/probes/mul_bf16x2.ll index 2cdce707ac..9ca17c0256 100644 --- a/intrinsics/probes/mul_bf16x2.ll +++ b/intrinsics/probes/mul_bf16x2.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mul_f16x2.ll b/intrinsics/probes/mul_f16x2.ll index b19dca1c4b..28b3c822bb 100644 --- a/intrinsics/probes/mul_f16x2.ll +++ b/intrinsics/probes/mul_f16x2.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mul_f32x2.ll b/intrinsics/probes/mul_f32x2.ll index 6db60d0f4a..f6eed01ef2 100644 --- a/intrinsics/probes/mul_f32x2.ll +++ b/intrinsics/probes/mul_f32x2.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mul_ftz_f32x2.ll b/intrinsics/probes/mul_ftz_f32x2.ll index 8e90fce65a..a34465703d 100644 --- a/intrinsics/probes/mul_ftz_f32x2.ll +++ b/intrinsics/probes/mul_ftz_f32x2.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mul_rm_f32.ll b/intrinsics/probes/mul_rm_f32.ll index bee2fc329a..c3898f246c 100644 --- a/intrinsics/probes/mul_rm_f32.ll +++ b/intrinsics/probes/mul_rm_f32.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mul_rm_f64.ll b/intrinsics/probes/mul_rm_f64.ll index 2c94945af0..09ae60941e 100644 --- a/intrinsics/probes/mul_rm_f64.ll +++ b/intrinsics/probes/mul_rm_f64.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mul_rm_ftz_f32.ll b/intrinsics/probes/mul_rm_ftz_f32.ll index 63d560b15c..d44914d507 100644 --- a/intrinsics/probes/mul_rm_ftz_f32.ll +++ b/intrinsics/probes/mul_rm_ftz_f32.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mul_rn_f32.ll b/intrinsics/probes/mul_rn_f32.ll index 6ba5d4e386..6ebe2e232b 100644 --- a/intrinsics/probes/mul_rn_f32.ll +++ b/intrinsics/probes/mul_rn_f32.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mul_rn_f64.ll b/intrinsics/probes/mul_rn_f64.ll index aac7f70bc3..634e665de5 100644 --- a/intrinsics/probes/mul_rn_f64.ll +++ b/intrinsics/probes/mul_rn_f64.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mul_rn_ftz_f32.ll b/intrinsics/probes/mul_rn_ftz_f32.ll index d3a13eaa04..e19e020d13 100644 --- a/intrinsics/probes/mul_rn_ftz_f32.ll +++ b/intrinsics/probes/mul_rn_ftz_f32.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mul_rp_f32.ll b/intrinsics/probes/mul_rp_f32.ll index 0def362de0..a6abf967ad 100644 --- a/intrinsics/probes/mul_rp_f32.ll +++ b/intrinsics/probes/mul_rp_f32.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mul_rp_f64.ll b/intrinsics/probes/mul_rp_f64.ll index 4bd55c875b..13afe13232 100644 --- a/intrinsics/probes/mul_rp_f64.ll +++ b/intrinsics/probes/mul_rp_f64.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mul_rp_ftz_f32.ll b/intrinsics/probes/mul_rp_ftz_f32.ll index a6262366fb..4c95a2ee2a 100644 --- a/intrinsics/probes/mul_rp_ftz_f32.ll +++ b/intrinsics/probes/mul_rp_ftz_f32.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mul_rz_f32.ll b/intrinsics/probes/mul_rz_f32.ll index 8a3cbcee4e..f274ef5d0b 100644 --- a/intrinsics/probes/mul_rz_f32.ll +++ b/intrinsics/probes/mul_rz_f32.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mul_rz_f64.ll b/intrinsics/probes/mul_rz_f64.ll index dc0540b2b3..271cb74853 100644 --- a/intrinsics/probes/mul_rz_f64.ll +++ b/intrinsics/probes/mul_rz_f64.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mul_rz_ftz_f32.ll b/intrinsics/probes/mul_rz_ftz_f32.ll index fa1f0524ba..e906a6d3f8 100644 --- a/intrinsics/probes/mul_rz_ftz_f32.ll +++ b/intrinsics/probes/mul_rz_ftz_f32.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/nanosleep.ll b/intrinsics/probes/nanosleep.ll index 04849ebe8c..baf5ac02be 100644 --- a/intrinsics/probes/nanosleep.ll +++ b/intrinsics/probes/nanosleep.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/neg_bf16x2.ll b/intrinsics/probes/neg_bf16x2.ll index 4f69426fa8..39c56fcf66 100644 --- a/intrinsics/probes/neg_bf16x2.ll +++ b/intrinsics/probes/neg_bf16x2.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/neg_f16x2.ll b/intrinsics/probes/neg_f16x2.ll index 8b49dc7ead..3bf58b1df9 100644 --- a/intrinsics/probes/neg_f16x2.ll +++ b/intrinsics/probes/neg_f16x2.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/nsmid.lib_nvvm.ll b/intrinsics/probes/nsmid.lib_nvvm.ll index 7bdca003c7..d73e1e352a 100644 --- a/intrinsics/probes/nsmid.lib_nvvm.ll +++ b/intrinsics/probes/nsmid.lib_nvvm.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/nsmid.llvm_nvptx.ll b/intrinsics/probes/nsmid.llvm_nvptx.ll index a0bcd61ccc..4f3f35c223 100644 --- a/intrinsics/probes/nsmid.llvm_nvptx.ll +++ b/intrinsics/probes/nsmid.llvm_nvptx.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/nwarpid.lib_nvvm.ll b/intrinsics/probes/nwarpid.lib_nvvm.ll index 2a5722dd3e..99af03f4ed 100644 --- a/intrinsics/probes/nwarpid.lib_nvvm.ll +++ b/intrinsics/probes/nwarpid.lib_nvvm.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/nwarpid.llvm_nvptx.ll b/intrinsics/probes/nwarpid.llvm_nvptx.ll index f928961fb5..76b3f93851 100644 --- a/intrinsics/probes/nwarpid.llvm_nvptx.ll +++ b/intrinsics/probes/nwarpid.llvm_nvptx.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/packed_atomic_add_bf16x2.ll b/intrinsics/probes/packed_atomic_add_bf16x2.ll index 04336fa5ec..3ef4310ad8 100644 --- a/intrinsics/probes/packed_atomic_add_bf16x2.ll +++ b/intrinsics/probes/packed_atomic_add_bf16x2.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/packed_atomic_add_f16x2.ll b/intrinsics/probes/packed_atomic_add_f16x2.ll index 0c08871b7e..16109dbefe 100644 --- a/intrinsics/probes/packed_atomic_add_f16x2.ll +++ b/intrinsics/probes/packed_atomic_add_f16x2.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/pmevent.ll b/intrinsics/probes/pmevent.ll index 8affded19f..ec83c9bf5e 100644 --- a/intrinsics/probes/pmevent.ll +++ b/intrinsics/probes/pmevent.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/prefetch_tma_descriptor.ll b/intrinsics/probes/prefetch_tma_descriptor.ll index 1394d4d253..b45f762321 100644 --- a/intrinsics/probes/prefetch_tma_descriptor.ll +++ b/intrinsics/probes/prefetch_tma_descriptor.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/prmt.ll b/intrinsics/probes/prmt.ll index f49e52ddd3..4703cab29d 100644 --- a/intrinsics/probes/prmt.ll +++ b/intrinsics/probes/prmt.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/prmt_b4e.ll b/intrinsics/probes/prmt_b4e.ll index ecc3820e5e..1d876108b0 100644 --- a/intrinsics/probes/prmt_b4e.ll +++ b/intrinsics/probes/prmt_b4e.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/prmt_ecl.ll b/intrinsics/probes/prmt_ecl.ll index d1efc4f31a..ad49f5da11 100644 --- a/intrinsics/probes/prmt_ecl.ll +++ b/intrinsics/probes/prmt_ecl.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/prmt_ecr.ll b/intrinsics/probes/prmt_ecr.ll index 5d8cce8f0d..2beb04f801 100644 --- a/intrinsics/probes/prmt_ecr.ll +++ b/intrinsics/probes/prmt_ecr.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/prmt_f4e.ll b/intrinsics/probes/prmt_f4e.ll index 0c9f733be1..afb02fd9a6 100644 --- a/intrinsics/probes/prmt_f4e.ll +++ b/intrinsics/probes/prmt_f4e.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/prmt_rc16.ll b/intrinsics/probes/prmt_rc16.ll index 6edc62459e..d954d88393 100644 --- a/intrinsics/probes/prmt_rc16.ll +++ b/intrinsics/probes/prmt_rc16.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/prmt_rc8.ll b/intrinsics/probes/prmt_rc8.ll index 4113a950ed..24a1bc8989 100644 --- a/intrinsics/probes/prmt_rc8.ll +++ b/intrinsics/probes/prmt_rc8.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/rcp_approx_ftz_f32.ll b/intrinsics/probes/rcp_approx_ftz_f32.ll index 7c4febf9d3..4daa525d28 100644 --- a/intrinsics/probes/rcp_approx_ftz_f32.ll +++ b/intrinsics/probes/rcp_approx_ftz_f32.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/rcp_approx_ftz_f64.ll b/intrinsics/probes/rcp_approx_ftz_f64.ll index bc70c0e11b..5556060578 100644 --- a/intrinsics/probes/rcp_approx_ftz_f64.ll +++ b/intrinsics/probes/rcp_approx_ftz_f64.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/rcp_rm_f32.ll b/intrinsics/probes/rcp_rm_f32.ll index 194f1afc95..bb78ded0b1 100644 --- a/intrinsics/probes/rcp_rm_f32.ll +++ b/intrinsics/probes/rcp_rm_f32.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/rcp_rm_f64.ll b/intrinsics/probes/rcp_rm_f64.ll index d71603c16d..532d1281e7 100644 --- a/intrinsics/probes/rcp_rm_f64.ll +++ b/intrinsics/probes/rcp_rm_f64.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/rcp_rm_ftz_f32.ll b/intrinsics/probes/rcp_rm_ftz_f32.ll index 05816ac204..d1f5405ab6 100644 --- a/intrinsics/probes/rcp_rm_ftz_f32.ll +++ b/intrinsics/probes/rcp_rm_ftz_f32.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/rcp_rn_f32.ll b/intrinsics/probes/rcp_rn_f32.ll index 1b92f0d6f3..bd561c714f 100644 --- a/intrinsics/probes/rcp_rn_f32.ll +++ b/intrinsics/probes/rcp_rn_f32.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/rcp_rn_f64.ll b/intrinsics/probes/rcp_rn_f64.ll index 8d91a7700a..1800b9adae 100644 --- a/intrinsics/probes/rcp_rn_f64.ll +++ b/intrinsics/probes/rcp_rn_f64.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/rcp_rn_ftz_f32.ll b/intrinsics/probes/rcp_rn_ftz_f32.ll index b2d5fc136d..cb045b8219 100644 --- a/intrinsics/probes/rcp_rn_ftz_f32.ll +++ b/intrinsics/probes/rcp_rn_ftz_f32.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/rcp_rp_f32.ll b/intrinsics/probes/rcp_rp_f32.ll index 48eafc0436..ac5c703f07 100644 --- a/intrinsics/probes/rcp_rp_f32.ll +++ b/intrinsics/probes/rcp_rp_f32.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/rcp_rp_f64.ll b/intrinsics/probes/rcp_rp_f64.ll index 830c245248..4e0eb86646 100644 --- a/intrinsics/probes/rcp_rp_f64.ll +++ b/intrinsics/probes/rcp_rp_f64.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/rcp_rp_ftz_f32.ll b/intrinsics/probes/rcp_rp_ftz_f32.ll index c5868abf8e..21f7f1fb46 100644 --- a/intrinsics/probes/rcp_rp_ftz_f32.ll +++ b/intrinsics/probes/rcp_rp_ftz_f32.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/rcp_rz_f32.ll b/intrinsics/probes/rcp_rz_f32.ll index 7310891ede..ec2565c322 100644 --- a/intrinsics/probes/rcp_rz_f32.ll +++ b/intrinsics/probes/rcp_rz_f32.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/rcp_rz_f64.ll b/intrinsics/probes/rcp_rz_f64.ll index 8e26992a99..6dd9121c25 100644 --- a/intrinsics/probes/rcp_rz_f64.ll +++ b/intrinsics/probes/rcp_rz_f64.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/rcp_rz_ftz_f32.ll b/intrinsics/probes/rcp_rz_ftz_f32.ll index fbf753530f..ed02b0b1e8 100644 --- a/intrinsics/probes/rcp_rz_ftz_f32.ll +++ b/intrinsics/probes/rcp_rz_ftz_f32.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/redux_sync_add.ll b/intrinsics/probes/redux_sync_add.ll index 9597fe2cad..2f77010ed8 100644 --- a/intrinsics/probes/redux_sync_add.ll +++ b/intrinsics/probes/redux_sync_add.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/redux_sync_and.ll b/intrinsics/probes/redux_sync_and.ll index 479887a61f..72613f856f 100644 --- a/intrinsics/probes/redux_sync_and.ll +++ b/intrinsics/probes/redux_sync_and.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/redux_sync_max_abs_f32.ll b/intrinsics/probes/redux_sync_max_abs_f32.ll index 4c3f7d13bf..476516c309 100644 --- a/intrinsics/probes/redux_sync_max_abs_f32.ll +++ b/intrinsics/probes/redux_sync_max_abs_f32.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/redux_sync_max_abs_nan_f32.ll b/intrinsics/probes/redux_sync_max_abs_nan_f32.ll index f70197f17f..9225469445 100644 --- a/intrinsics/probes/redux_sync_max_abs_nan_f32.ll +++ b/intrinsics/probes/redux_sync_max_abs_nan_f32.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/redux_sync_max_f32.ll b/intrinsics/probes/redux_sync_max_f32.ll index d47773007e..2cd061df1b 100644 --- a/intrinsics/probes/redux_sync_max_f32.ll +++ b/intrinsics/probes/redux_sync_max_f32.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/redux_sync_max_i32.ll b/intrinsics/probes/redux_sync_max_i32.ll index 5992708ccd..0c6b0cfaf2 100644 --- a/intrinsics/probes/redux_sync_max_i32.ll +++ b/intrinsics/probes/redux_sync_max_i32.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/redux_sync_max_nan_f32.ll b/intrinsics/probes/redux_sync_max_nan_f32.ll index 94f5c67f5d..17959249f1 100644 --- a/intrinsics/probes/redux_sync_max_nan_f32.ll +++ b/intrinsics/probes/redux_sync_max_nan_f32.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/redux_sync_max_u32.ll b/intrinsics/probes/redux_sync_max_u32.ll index 8c59886e5a..26ad91eb88 100644 --- a/intrinsics/probes/redux_sync_max_u32.ll +++ b/intrinsics/probes/redux_sync_max_u32.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/redux_sync_min_abs_f32.ll b/intrinsics/probes/redux_sync_min_abs_f32.ll index ea41269cb0..68b062d9ba 100644 --- a/intrinsics/probes/redux_sync_min_abs_f32.ll +++ b/intrinsics/probes/redux_sync_min_abs_f32.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/redux_sync_min_abs_nan_f32.ll b/intrinsics/probes/redux_sync_min_abs_nan_f32.ll index 4f322937b5..b3c59afa5d 100644 --- a/intrinsics/probes/redux_sync_min_abs_nan_f32.ll +++ b/intrinsics/probes/redux_sync_min_abs_nan_f32.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/redux_sync_min_f32.ll b/intrinsics/probes/redux_sync_min_f32.ll index d305bf2e67..ce2a1377dc 100644 --- a/intrinsics/probes/redux_sync_min_f32.ll +++ b/intrinsics/probes/redux_sync_min_f32.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/redux_sync_min_i32.ll b/intrinsics/probes/redux_sync_min_i32.ll index 0a573b0d47..a31a7b63f6 100644 --- a/intrinsics/probes/redux_sync_min_i32.ll +++ b/intrinsics/probes/redux_sync_min_i32.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/redux_sync_min_nan_f32.ll b/intrinsics/probes/redux_sync_min_nan_f32.ll index 912d05acca..cca7ca7d4b 100644 --- a/intrinsics/probes/redux_sync_min_nan_f32.ll +++ b/intrinsics/probes/redux_sync_min_nan_f32.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/redux_sync_min_u32.ll b/intrinsics/probes/redux_sync_min_u32.ll index 07645387a7..0a0985082d 100644 --- a/intrinsics/probes/redux_sync_min_u32.ll +++ b/intrinsics/probes/redux_sync_min_u32.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/redux_sync_or.ll b/intrinsics/probes/redux_sync_or.ll index 1910676bf7..93022112ac 100644 --- a/intrinsics/probes/redux_sync_or.ll +++ b/intrinsics/probes/redux_sync_or.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/redux_sync_xor.ll b/intrinsics/probes/redux_sync_xor.ll index c25b009b68..1e4f141654 100644 --- a/intrinsics/probes/redux_sync_xor.ll +++ b/intrinsics/probes/redux_sync_xor.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/rsqrt_approx_f32.ll b/intrinsics/probes/rsqrt_approx_f32.ll index 018c34e6e7..2baef40c26 100644 --- a/intrinsics/probes/rsqrt_approx_f32.ll +++ b/intrinsics/probes/rsqrt_approx_f32.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/rsqrt_approx_f64.ll b/intrinsics/probes/rsqrt_approx_f64.ll index 074094fbfb..190568d2d2 100644 --- a/intrinsics/probes/rsqrt_approx_f64.ll +++ b/intrinsics/probes/rsqrt_approx_f64.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/rsqrt_approx_ftz_f32.ll b/intrinsics/probes/rsqrt_approx_ftz_f32.ll index b8a6014d75..3ff4d286c8 100644 --- a/intrinsics/probes/rsqrt_approx_ftz_f32.ll +++ b/intrinsics/probes/rsqrt_approx_ftz_f32.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/setmaxnreg_dec.ll b/intrinsics/probes/setmaxnreg_dec.ll index 7995e4459b..3818f4848b 100644 --- a/intrinsics/probes/setmaxnreg_dec.ll +++ b/intrinsics/probes/setmaxnreg_dec.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/setmaxnreg_inc.ll b/intrinsics/probes/setmaxnreg_inc.ll index bc7f903173..47153dfa27 100644 --- a/intrinsics/probes/setmaxnreg_inc.ll +++ b/intrinsics/probes/setmaxnreg_inc.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/shuffle_down_f32_sync.ll b/intrinsics/probes/shuffle_down_f32_sync.ll index 7cd1c23d35..7ea2a92ce4 100644 --- a/intrinsics/probes/shuffle_down_f32_sync.ll +++ b/intrinsics/probes/shuffle_down_f32_sync.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/shuffle_down_sync.ll b/intrinsics/probes/shuffle_down_sync.ll index 0bc2871374..1bfc07aa7e 100644 --- a/intrinsics/probes/shuffle_down_sync.ll +++ b/intrinsics/probes/shuffle_down_sync.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/shuffle_down_u64_sync.ll b/intrinsics/probes/shuffle_down_u64_sync.ll index 84fa7d803a..0118734a4d 100644 --- a/intrinsics/probes/shuffle_down_u64_sync.ll +++ b/intrinsics/probes/shuffle_down_u64_sync.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/shuffle_f32_sync.ll b/intrinsics/probes/shuffle_f32_sync.ll index 520033be1e..fb49372788 100644 --- a/intrinsics/probes/shuffle_f32_sync.ll +++ b/intrinsics/probes/shuffle_f32_sync.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/shuffle_sync.ll b/intrinsics/probes/shuffle_sync.ll index ac79b668d9..058c27dbe3 100644 --- a/intrinsics/probes/shuffle_sync.ll +++ b/intrinsics/probes/shuffle_sync.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/shuffle_u64_sync.ll b/intrinsics/probes/shuffle_u64_sync.ll index 0b337162b3..92b8bd1faf 100644 --- a/intrinsics/probes/shuffle_u64_sync.ll +++ b/intrinsics/probes/shuffle_u64_sync.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/shuffle_up_f32_sync.ll b/intrinsics/probes/shuffle_up_f32_sync.ll index 4009d9e36c..e4976056af 100644 --- a/intrinsics/probes/shuffle_up_f32_sync.ll +++ b/intrinsics/probes/shuffle_up_f32_sync.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/shuffle_up_sync.ll b/intrinsics/probes/shuffle_up_sync.ll index 39c58ed319..4ed3f034c5 100644 --- a/intrinsics/probes/shuffle_up_sync.ll +++ b/intrinsics/probes/shuffle_up_sync.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/shuffle_up_u64_sync.ll b/intrinsics/probes/shuffle_up_u64_sync.ll index 2cc6c009c8..dbd13a5269 100644 --- a/intrinsics/probes/shuffle_up_u64_sync.ll +++ b/intrinsics/probes/shuffle_up_u64_sync.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/shuffle_xor_f32_sync.ll b/intrinsics/probes/shuffle_xor_f32_sync.ll index 501e7c11a7..3214c102e1 100644 --- a/intrinsics/probes/shuffle_xor_f32_sync.ll +++ b/intrinsics/probes/shuffle_xor_f32_sync.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/shuffle_xor_sync.ll b/intrinsics/probes/shuffle_xor_sync.ll index f3b0c4413d..45e107cf70 100644 --- a/intrinsics/probes/shuffle_xor_sync.ll +++ b/intrinsics/probes/shuffle_xor_sync.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/shuffle_xor_u64_sync.ll b/intrinsics/probes/shuffle_xor_u64_sync.ll index d9eb71da62..3ce1fac28a 100644 --- a/intrinsics/probes/shuffle_xor_u64_sync.ll +++ b/intrinsics/probes/shuffle_xor_u64_sync.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/sin_approx_f32.ll b/intrinsics/probes/sin_approx_f32.ll index 1c80c8586d..bd3f77ad68 100644 --- a/intrinsics/probes/sin_approx_f32.ll +++ b/intrinsics/probes/sin_approx_f32.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/sin_approx_ftz_f32.ll b/intrinsics/probes/sin_approx_ftz_f32.ll index 40d3b11018..3542da776b 100644 --- a/intrinsics/probes/sin_approx_ftz_f32.ll +++ b/intrinsics/probes/sin_approx_ftz_f32.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/smid.lib_nvvm.ll b/intrinsics/probes/smid.lib_nvvm.ll index 9f8e76dd7f..b699e7a5f2 100644 --- a/intrinsics/probes/smid.lib_nvvm.ll +++ b/intrinsics/probes/smid.lib_nvvm.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/smid.llvm_nvptx.ll b/intrinsics/probes/smid.llvm_nvptx.ll index 16c7e50773..29162e2c9d 100644 --- a/intrinsics/probes/smid.llvm_nvptx.ll +++ b/intrinsics/probes/smid.llvm_nvptx.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/sqrt_approx_f32.ll b/intrinsics/probes/sqrt_approx_f32.ll index 27dd8488c2..add8a7051c 100644 --- a/intrinsics/probes/sqrt_approx_f32.ll +++ b/intrinsics/probes/sqrt_approx_f32.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/sqrt_approx_ftz_f32.ll b/intrinsics/probes/sqrt_approx_ftz_f32.ll index 819a68a4cf..f5e716b440 100644 --- a/intrinsics/probes/sqrt_approx_ftz_f32.ll +++ b/intrinsics/probes/sqrt_approx_ftz_f32.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/sqrt_rm_f32.ll b/intrinsics/probes/sqrt_rm_f32.ll index cc8102c1e1..6c9c8653ad 100644 --- a/intrinsics/probes/sqrt_rm_f32.ll +++ b/intrinsics/probes/sqrt_rm_f32.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/sqrt_rm_f64.ll b/intrinsics/probes/sqrt_rm_f64.ll index e7dd046d4f..6a21977478 100644 --- a/intrinsics/probes/sqrt_rm_f64.ll +++ b/intrinsics/probes/sqrt_rm_f64.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/sqrt_rm_ftz_f32.ll b/intrinsics/probes/sqrt_rm_ftz_f32.ll index 0a17576025..9cce63ab91 100644 --- a/intrinsics/probes/sqrt_rm_ftz_f32.ll +++ b/intrinsics/probes/sqrt_rm_ftz_f32.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/sqrt_rn_f32.ll b/intrinsics/probes/sqrt_rn_f32.ll index 67c858ff91..600444a360 100644 --- a/intrinsics/probes/sqrt_rn_f32.ll +++ b/intrinsics/probes/sqrt_rn_f32.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/sqrt_rn_f64.ll b/intrinsics/probes/sqrt_rn_f64.ll index c070b11aff..174ddcc068 100644 --- a/intrinsics/probes/sqrt_rn_f64.ll +++ b/intrinsics/probes/sqrt_rn_f64.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/sqrt_rn_ftz_f32.ll b/intrinsics/probes/sqrt_rn_ftz_f32.ll index 38adecdc87..300563707a 100644 --- a/intrinsics/probes/sqrt_rn_ftz_f32.ll +++ b/intrinsics/probes/sqrt_rn_ftz_f32.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/sqrt_rp_f32.ll b/intrinsics/probes/sqrt_rp_f32.ll index 8331e91e01..1d013c8f0a 100644 --- a/intrinsics/probes/sqrt_rp_f32.ll +++ b/intrinsics/probes/sqrt_rp_f32.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/sqrt_rp_f64.ll b/intrinsics/probes/sqrt_rp_f64.ll index 45cf74bc18..2095108e41 100644 --- a/intrinsics/probes/sqrt_rp_f64.ll +++ b/intrinsics/probes/sqrt_rp_f64.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/sqrt_rp_ftz_f32.ll b/intrinsics/probes/sqrt_rp_ftz_f32.ll index f541fba825..7b81360219 100644 --- a/intrinsics/probes/sqrt_rp_ftz_f32.ll +++ b/intrinsics/probes/sqrt_rp_ftz_f32.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/sqrt_rz_f32.ll b/intrinsics/probes/sqrt_rz_f32.ll index 05e1d2515a..5d0ee554dd 100644 --- a/intrinsics/probes/sqrt_rz_f32.ll +++ b/intrinsics/probes/sqrt_rz_f32.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/sqrt_rz_f64.ll b/intrinsics/probes/sqrt_rz_f64.ll index 9c773afc28..4385505f6b 100644 --- a/intrinsics/probes/sqrt_rz_f64.ll +++ b/intrinsics/probes/sqrt_rz_f64.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/sqrt_rz_ftz_f32.ll b/intrinsics/probes/sqrt_rz_ftz_f32.ll index f354280ba2..eabe559309 100644 --- a/intrinsics/probes/sqrt_rz_ftz_f32.ll +++ b/intrinsics/probes/sqrt_rz_ftz_f32.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/stmatrix_m8n8_x2_b16.ll b/intrinsics/probes/stmatrix_m8n8_x2_b16.ll index cc669dc06b..4546663ca7 100644 --- a/intrinsics/probes/stmatrix_m8n8_x2_b16.ll +++ b/intrinsics/probes/stmatrix_m8n8_x2_b16.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/stmatrix_m8n8_x2_trans_b16.ll b/intrinsics/probes/stmatrix_m8n8_x2_trans_b16.ll index 18c85187f5..ee84ae682f 100644 --- a/intrinsics/probes/stmatrix_m8n8_x2_trans_b16.ll +++ b/intrinsics/probes/stmatrix_m8n8_x2_trans_b16.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/stmatrix_m8n8_x4_b16.ll b/intrinsics/probes/stmatrix_m8n8_x4_b16.ll index 6f79fc7cc2..866df842c7 100644 --- a/intrinsics/probes/stmatrix_m8n8_x4_b16.ll +++ b/intrinsics/probes/stmatrix_m8n8_x4_b16.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/stmatrix_m8n8_x4_trans_b16.ll b/intrinsics/probes/stmatrix_m8n8_x4_trans_b16.ll index 4db9081501..6ab1f9efb5 100644 --- a/intrinsics/probes/stmatrix_m8n8_x4_trans_b16.ll +++ b/intrinsics/probes/stmatrix_m8n8_x4_trans_b16.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/sub_bf16x2.ll b/intrinsics/probes/sub_bf16x2.ll index 7a8dfd16f6..fb354b8b65 100644 --- a/intrinsics/probes/sub_bf16x2.ll +++ b/intrinsics/probes/sub_bf16x2.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/sub_f16x2.ll b/intrinsics/probes/sub_f16x2.ll index 9eeeb1d72b..4aaf5e94c0 100644 --- a/intrinsics/probes/sub_f16x2.ll +++ b/intrinsics/probes/sub_f16x2.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/sub_f32x2.ll b/intrinsics/probes/sub_f32x2.ll index cd508228e0..f4016e470b 100644 --- a/intrinsics/probes/sub_f32x2.ll +++ b/intrinsics/probes/sub_f32x2.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/sub_ftz_f32x2.ll b/intrinsics/probes/sub_ftz_f32x2.ll index ae83442a8a..1c6ef39f1c 100644 --- a/intrinsics/probes/sub_ftz_f32x2.ll +++ b/intrinsics/probes/sub_ftz_f32x2.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/sync_mask.ll b/intrinsics/probes/sync_mask.ll index c0401556d7..1c1dcd31bc 100644 --- a/intrinsics/probes/sync_mask.ll +++ b/intrinsics/probes/sync_mask.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/sync_threads.ll b/intrinsics/probes/sync_threads.ll index 8e37116d9c..01d44307fe 100644 --- a/intrinsics/probes/sync_threads.ll +++ b/intrinsics/probes/sync_threads.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tanh_approx_f32.ll b/intrinsics/probes/tanh_approx_f32.ll index 6ab0b78af0..c9112731fa 100644 --- a/intrinsics/probes/tanh_approx_f32.ll +++ b/intrinsics/probes/tanh_approx_f32.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_alloc.ll b/intrinsics/probes/tcgen05_alloc.ll index 104602923d..395476b12f 100644 --- a/intrinsics/probes/tcgen05_alloc.ll +++ b/intrinsics/probes/tcgen05_alloc.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_alloc_cg2.ll b/intrinsics/probes/tcgen05_alloc_cg2.ll index 6ed68fe060..bb3c0776aa 100644 --- a/intrinsics/probes/tcgen05_alloc_cg2.ll +++ b/intrinsics/probes/tcgen05_alloc_cg2.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_commit.ll b/intrinsics/probes/tcgen05_commit.ll index f74f105aab..df4063574e 100644 --- a/intrinsics/probes/tcgen05_commit.ll +++ b/intrinsics/probes/tcgen05_commit.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_commit_cg2.ll b/intrinsics/probes/tcgen05_commit_cg2.ll index 78a7334d14..6e17bebdba 100644 --- a/intrinsics/probes/tcgen05_commit_cg2.ll +++ b/intrinsics/probes/tcgen05_commit_cg2.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_commit_multicast.ll b/intrinsics/probes/tcgen05_commit_multicast.ll index 5775aa71c2..9a8dadf0f1 100644 --- a/intrinsics/probes/tcgen05_commit_multicast.ll +++ b/intrinsics/probes/tcgen05_commit_multicast.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_commit_multicast_cg2.ll b/intrinsics/probes/tcgen05_commit_multicast_cg2.ll index 9b8321e1c2..359372976d 100644 --- a/intrinsics/probes/tcgen05_commit_multicast_cg2.ll +++ b/intrinsics/probes/tcgen05_commit_multicast_cg2.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_commit_shared_cluster.ll b/intrinsics/probes/tcgen05_commit_shared_cluster.ll index 8428679824..921954cba3 100644 --- a/intrinsics/probes/tcgen05_commit_shared_cluster.ll +++ b/intrinsics/probes/tcgen05_commit_shared_cluster.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_commit_shared_cluster_cg2.ll b/intrinsics/probes/tcgen05_commit_shared_cluster_cg2.ll index 35112504db..b3760c375a 100644 --- a/intrinsics/probes/tcgen05_commit_shared_cluster_cg2.ll +++ b/intrinsics/probes/tcgen05_commit_shared_cluster_cg2.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_cp_128x128b.ll b/intrinsics/probes/tcgen05_cp_128x128b.ll index 7972dc19f7..9d2b3d8e96 100644 --- a/intrinsics/probes/tcgen05_cp_128x128b.ll +++ b/intrinsics/probes/tcgen05_cp_128x128b.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_cp_128x128b_b4x16_p64.ll b/intrinsics/probes/tcgen05_cp_128x128b_b4x16_p64.ll index f348df680c..855611ea4b 100644 --- a/intrinsics/probes/tcgen05_cp_128x128b_b4x16_p64.ll +++ b/intrinsics/probes/tcgen05_cp_128x128b_b4x16_p64.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_cp_128x128b_b4x16_p64_cg2.ll b/intrinsics/probes/tcgen05_cp_128x128b_b4x16_p64_cg2.ll index b56416d001..aea2266f2d 100644 --- a/intrinsics/probes/tcgen05_cp_128x128b_b4x16_p64_cg2.ll +++ b/intrinsics/probes/tcgen05_cp_128x128b_b4x16_p64_cg2.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_cp_128x128b_b6x16_p32.ll b/intrinsics/probes/tcgen05_cp_128x128b_b6x16_p32.ll index c7082b1401..671404ba16 100644 --- a/intrinsics/probes/tcgen05_cp_128x128b_b6x16_p32.ll +++ b/intrinsics/probes/tcgen05_cp_128x128b_b6x16_p32.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_cp_128x128b_b6x16_p32_cg2.ll b/intrinsics/probes/tcgen05_cp_128x128b_b6x16_p32_cg2.ll index b26e5d912b..8efb430c41 100644 --- a/intrinsics/probes/tcgen05_cp_128x128b_b6x16_p32_cg2.ll +++ b/intrinsics/probes/tcgen05_cp_128x128b_b6x16_p32_cg2.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_cp_128x128b_cg2.ll b/intrinsics/probes/tcgen05_cp_128x128b_cg2.ll index 2c99c2b441..512e3b8868 100644 --- a/intrinsics/probes/tcgen05_cp_128x128b_cg2.ll +++ b/intrinsics/probes/tcgen05_cp_128x128b_cg2.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_cp_128x256b_b4x16_p64.ll b/intrinsics/probes/tcgen05_cp_128x256b_b4x16_p64.ll index 87fed09fb6..80a7cdecd4 100644 --- a/intrinsics/probes/tcgen05_cp_128x256b_b4x16_p64.ll +++ b/intrinsics/probes/tcgen05_cp_128x256b_b4x16_p64.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_cp_128x256b_b4x16_p64_cg2.ll b/intrinsics/probes/tcgen05_cp_128x256b_b4x16_p64_cg2.ll index 6ecb8dddba..2ff2f750b7 100644 --- a/intrinsics/probes/tcgen05_cp_128x256b_b4x16_p64_cg2.ll +++ b/intrinsics/probes/tcgen05_cp_128x256b_b4x16_p64_cg2.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_cp_128x256b_b6x16_p32.ll b/intrinsics/probes/tcgen05_cp_128x256b_b6x16_p32.ll index 39b5e8c274..0aa5c3b84e 100644 --- a/intrinsics/probes/tcgen05_cp_128x256b_b6x16_p32.ll +++ b/intrinsics/probes/tcgen05_cp_128x256b_b6x16_p32.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_cp_128x256b_b6x16_p32_cg2.ll b/intrinsics/probes/tcgen05_cp_128x256b_b6x16_p32_cg2.ll index 4c2f35cf3e..362e8251a4 100644 --- a/intrinsics/probes/tcgen05_cp_128x256b_b6x16_p32_cg2.ll +++ b/intrinsics/probes/tcgen05_cp_128x256b_b6x16_p32_cg2.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_cp_32x128b_warpx4.ll b/intrinsics/probes/tcgen05_cp_32x128b_warpx4.ll index 7391d0edab..4990a76d59 100644 --- a/intrinsics/probes/tcgen05_cp_32x128b_warpx4.ll +++ b/intrinsics/probes/tcgen05_cp_32x128b_warpx4.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_cp_32x128b_warpx4_b4x16_p64.ll b/intrinsics/probes/tcgen05_cp_32x128b_warpx4_b4x16_p64.ll index c6f8686143..adc1a18eee 100644 --- a/intrinsics/probes/tcgen05_cp_32x128b_warpx4_b4x16_p64.ll +++ b/intrinsics/probes/tcgen05_cp_32x128b_warpx4_b4x16_p64.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_cp_32x128b_warpx4_b4x16_p64_cg2.ll b/intrinsics/probes/tcgen05_cp_32x128b_warpx4_b4x16_p64_cg2.ll index fc2013ec92..f41307246b 100644 --- a/intrinsics/probes/tcgen05_cp_32x128b_warpx4_b4x16_p64_cg2.ll +++ b/intrinsics/probes/tcgen05_cp_32x128b_warpx4_b4x16_p64_cg2.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_cp_32x128b_warpx4_b6x16_p32.ll b/intrinsics/probes/tcgen05_cp_32x128b_warpx4_b6x16_p32.ll index 1f1b7f26ce..6c45202b05 100644 --- a/intrinsics/probes/tcgen05_cp_32x128b_warpx4_b6x16_p32.ll +++ b/intrinsics/probes/tcgen05_cp_32x128b_warpx4_b6x16_p32.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_cp_32x128b_warpx4_b6x16_p32_cg2.ll b/intrinsics/probes/tcgen05_cp_32x128b_warpx4_b6x16_p32_cg2.ll index b86d3b8280..eef7760c90 100644 --- a/intrinsics/probes/tcgen05_cp_32x128b_warpx4_b6x16_p32_cg2.ll +++ b/intrinsics/probes/tcgen05_cp_32x128b_warpx4_b6x16_p32_cg2.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_cp_32x128b_warpx4_cg2.ll b/intrinsics/probes/tcgen05_cp_32x128b_warpx4_cg2.ll index 6d88b0f391..4b1d9f39de 100644 --- a/intrinsics/probes/tcgen05_cp_32x128b_warpx4_cg2.ll +++ b/intrinsics/probes/tcgen05_cp_32x128b_warpx4_cg2.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_cp_4x256b.ll b/intrinsics/probes/tcgen05_cp_4x256b.ll index a3ab43628b..d41c987477 100644 --- a/intrinsics/probes/tcgen05_cp_4x256b.ll +++ b/intrinsics/probes/tcgen05_cp_4x256b.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_cp_4x256b_b4x16_p64.ll b/intrinsics/probes/tcgen05_cp_4x256b_b4x16_p64.ll index e19c9cbe81..bc9e35f6c8 100644 --- a/intrinsics/probes/tcgen05_cp_4x256b_b4x16_p64.ll +++ b/intrinsics/probes/tcgen05_cp_4x256b_b4x16_p64.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_cp_4x256b_b4x16_p64_cg2.ll b/intrinsics/probes/tcgen05_cp_4x256b_b4x16_p64_cg2.ll index 1715b86bae..40cf888f9c 100644 --- a/intrinsics/probes/tcgen05_cp_4x256b_b4x16_p64_cg2.ll +++ b/intrinsics/probes/tcgen05_cp_4x256b_b4x16_p64_cg2.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_cp_4x256b_b6x16_p32.ll b/intrinsics/probes/tcgen05_cp_4x256b_b6x16_p32.ll index 3357c0df12..d21740c19a 100644 --- a/intrinsics/probes/tcgen05_cp_4x256b_b6x16_p32.ll +++ b/intrinsics/probes/tcgen05_cp_4x256b_b6x16_p32.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_cp_4x256b_b6x16_p32_cg2.ll b/intrinsics/probes/tcgen05_cp_4x256b_b6x16_p32_cg2.ll index ced973e617..e6acb77810 100644 --- a/intrinsics/probes/tcgen05_cp_4x256b_b6x16_p32_cg2.ll +++ b/intrinsics/probes/tcgen05_cp_4x256b_b6x16_p32_cg2.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_cp_4x256b_cg2.ll b/intrinsics/probes/tcgen05_cp_4x256b_cg2.ll index 8ae43f0bda..333d391640 100644 --- a/intrinsics/probes/tcgen05_cp_4x256b_cg2.ll +++ b/intrinsics/probes/tcgen05_cp_4x256b_cg2.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_cp_64x128b_warpx2_01_23.ll b/intrinsics/probes/tcgen05_cp_64x128b_warpx2_01_23.ll index b52466e219..7a5ff5c246 100644 --- a/intrinsics/probes/tcgen05_cp_64x128b_warpx2_01_23.ll +++ b/intrinsics/probes/tcgen05_cp_64x128b_warpx2_01_23.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_cp_64x128b_warpx2_01_23_b4x16_p64.ll b/intrinsics/probes/tcgen05_cp_64x128b_warpx2_01_23_b4x16_p64.ll index 2279b86b97..d872374c74 100644 --- a/intrinsics/probes/tcgen05_cp_64x128b_warpx2_01_23_b4x16_p64.ll +++ b/intrinsics/probes/tcgen05_cp_64x128b_warpx2_01_23_b4x16_p64.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_cp_64x128b_warpx2_01_23_b4x16_p64_cg2.ll b/intrinsics/probes/tcgen05_cp_64x128b_warpx2_01_23_b4x16_p64_cg2.ll index 686c31aeef..c2b940f10b 100644 --- a/intrinsics/probes/tcgen05_cp_64x128b_warpx2_01_23_b4x16_p64_cg2.ll +++ b/intrinsics/probes/tcgen05_cp_64x128b_warpx2_01_23_b4x16_p64_cg2.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_cp_64x128b_warpx2_01_23_b6x16_p32.ll b/intrinsics/probes/tcgen05_cp_64x128b_warpx2_01_23_b6x16_p32.ll index eaeb532ebd..2b204fc118 100644 --- a/intrinsics/probes/tcgen05_cp_64x128b_warpx2_01_23_b6x16_p32.ll +++ b/intrinsics/probes/tcgen05_cp_64x128b_warpx2_01_23_b6x16_p32.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_cp_64x128b_warpx2_01_23_b6x16_p32_cg2.ll b/intrinsics/probes/tcgen05_cp_64x128b_warpx2_01_23_b6x16_p32_cg2.ll index 2509cf5a5c..a7d55f8adb 100644 --- a/intrinsics/probes/tcgen05_cp_64x128b_warpx2_01_23_b6x16_p32_cg2.ll +++ b/intrinsics/probes/tcgen05_cp_64x128b_warpx2_01_23_b6x16_p32_cg2.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_cp_64x128b_warpx2_01_23_cg2.ll b/intrinsics/probes/tcgen05_cp_64x128b_warpx2_01_23_cg2.ll index 7b2be3e6c0..02750ee9c2 100644 --- a/intrinsics/probes/tcgen05_cp_64x128b_warpx2_01_23_cg2.ll +++ b/intrinsics/probes/tcgen05_cp_64x128b_warpx2_01_23_cg2.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_cp_64x128b_warpx2_02_13.ll b/intrinsics/probes/tcgen05_cp_64x128b_warpx2_02_13.ll index a610257d19..f7c6f3e67d 100644 --- a/intrinsics/probes/tcgen05_cp_64x128b_warpx2_02_13.ll +++ b/intrinsics/probes/tcgen05_cp_64x128b_warpx2_02_13.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_cp_64x128b_warpx2_02_13_b4x16_p64.ll b/intrinsics/probes/tcgen05_cp_64x128b_warpx2_02_13_b4x16_p64.ll index 54bf901fde..1e31db543e 100644 --- a/intrinsics/probes/tcgen05_cp_64x128b_warpx2_02_13_b4x16_p64.ll +++ b/intrinsics/probes/tcgen05_cp_64x128b_warpx2_02_13_b4x16_p64.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_cp_64x128b_warpx2_02_13_b4x16_p64_cg2.ll b/intrinsics/probes/tcgen05_cp_64x128b_warpx2_02_13_b4x16_p64_cg2.ll index 6acd2f8f4c..93b8b586c4 100644 --- a/intrinsics/probes/tcgen05_cp_64x128b_warpx2_02_13_b4x16_p64_cg2.ll +++ b/intrinsics/probes/tcgen05_cp_64x128b_warpx2_02_13_b4x16_p64_cg2.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_cp_64x128b_warpx2_02_13_b6x16_p32.ll b/intrinsics/probes/tcgen05_cp_64x128b_warpx2_02_13_b6x16_p32.ll index 608e948ee6..7817a24d91 100644 --- a/intrinsics/probes/tcgen05_cp_64x128b_warpx2_02_13_b6x16_p32.ll +++ b/intrinsics/probes/tcgen05_cp_64x128b_warpx2_02_13_b6x16_p32.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_cp_64x128b_warpx2_02_13_b6x16_p32_cg2.ll b/intrinsics/probes/tcgen05_cp_64x128b_warpx2_02_13_b6x16_p32_cg2.ll index eb1e45e101..1f3e8386d4 100644 --- a/intrinsics/probes/tcgen05_cp_64x128b_warpx2_02_13_b6x16_p32_cg2.ll +++ b/intrinsics/probes/tcgen05_cp_64x128b_warpx2_02_13_b6x16_p32_cg2.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_cp_64x128b_warpx2_02_13_cg2.ll b/intrinsics/probes/tcgen05_cp_64x128b_warpx2_02_13_cg2.ll index 03318fc156..9655da1c30 100644 --- a/intrinsics/probes/tcgen05_cp_64x128b_warpx2_02_13_cg2.ll +++ b/intrinsics/probes/tcgen05_cp_64x128b_warpx2_02_13_cg2.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_cp_smem_to_tmem.ll b/intrinsics/probes/tcgen05_cp_smem_to_tmem.ll index 6b63caf67f..49737787b9 100644 --- a/intrinsics/probes/tcgen05_cp_smem_to_tmem.ll +++ b/intrinsics/probes/tcgen05_cp_smem_to_tmem.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_cp_smem_to_tmem_cg2.ll b/intrinsics/probes/tcgen05_cp_smem_to_tmem_cg2.ll index 2e67e04302..dc48063f79 100644 --- a/intrinsics/probes/tcgen05_cp_smem_to_tmem_cg2.ll +++ b/intrinsics/probes/tcgen05_cp_smem_to_tmem_cg2.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_dealloc.ll b/intrinsics/probes/tcgen05_dealloc.ll index e848993cdb..e873437f4a 100644 --- a/intrinsics/probes/tcgen05_dealloc.ll +++ b/intrinsics/probes/tcgen05_dealloc.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_dealloc_cg2.ll b/intrinsics/probes/tcgen05_dealloc_cg2.ll index 922c0ba8d0..3103d29e66 100644 --- a/intrinsics/probes/tcgen05_dealloc_cg2.ll +++ b/intrinsics/probes/tcgen05_dealloc_cg2.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_fence_after_thread_sync.ll b/intrinsics/probes/tcgen05_fence_after_thread_sync.ll index 477350f318..2745ef99cb 100644 --- a/intrinsics/probes/tcgen05_fence_after_thread_sync.ll +++ b/intrinsics/probes/tcgen05_fence_after_thread_sync.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_fence_before_thread_sync.ll b/intrinsics/probes/tcgen05_fence_before_thread_sync.ll index 5b0f910be9..2e9601396f 100644 --- a/intrinsics/probes/tcgen05_fence_before_thread_sync.ll +++ b/intrinsics/probes/tcgen05_fence_before_thread_sync.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_ld_16x128b_x16_pack16.ll b/intrinsics/probes/tcgen05_ld_16x128b_x16_pack16.ll index 354cee137a..c3ffca22f2 100644 --- a/intrinsics/probes/tcgen05_ld_16x128b_x16_pack16.ll +++ b/intrinsics/probes/tcgen05_ld_16x128b_x16_pack16.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_ld_16x128b_x16_raw.ll b/intrinsics/probes/tcgen05_ld_16x128b_x16_raw.ll index bd6c10d4de..49d21c8945 100644 --- a/intrinsics/probes/tcgen05_ld_16x128b_x16_raw.ll +++ b/intrinsics/probes/tcgen05_ld_16x128b_x16_raw.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_ld_16x128b_x1_pack16.ll b/intrinsics/probes/tcgen05_ld_16x128b_x1_pack16.ll index beff8963b5..8037147818 100644 --- a/intrinsics/probes/tcgen05_ld_16x128b_x1_pack16.ll +++ b/intrinsics/probes/tcgen05_ld_16x128b_x1_pack16.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_ld_16x128b_x1_raw.ll b/intrinsics/probes/tcgen05_ld_16x128b_x1_raw.ll index 6873dc2c62..9ca908fc4c 100644 --- a/intrinsics/probes/tcgen05_ld_16x128b_x1_raw.ll +++ b/intrinsics/probes/tcgen05_ld_16x128b_x1_raw.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_ld_16x128b_x2_pack16.ll b/intrinsics/probes/tcgen05_ld_16x128b_x2_pack16.ll index 344a2563ae..a3faebaa3a 100644 --- a/intrinsics/probes/tcgen05_ld_16x128b_x2_pack16.ll +++ b/intrinsics/probes/tcgen05_ld_16x128b_x2_pack16.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_ld_16x128b_x2_raw.ll b/intrinsics/probes/tcgen05_ld_16x128b_x2_raw.ll index cc4bfd7471..2dda6e7cf5 100644 --- a/intrinsics/probes/tcgen05_ld_16x128b_x2_raw.ll +++ b/intrinsics/probes/tcgen05_ld_16x128b_x2_raw.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_ld_16x128b_x32_pack16.ll b/intrinsics/probes/tcgen05_ld_16x128b_x32_pack16.ll index a0ef451831..e70850c329 100644 --- a/intrinsics/probes/tcgen05_ld_16x128b_x32_pack16.ll +++ b/intrinsics/probes/tcgen05_ld_16x128b_x32_pack16.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_ld_16x128b_x32_raw.ll b/intrinsics/probes/tcgen05_ld_16x128b_x32_raw.ll index 1ecaff0de6..62cdd90bf2 100644 --- a/intrinsics/probes/tcgen05_ld_16x128b_x32_raw.ll +++ b/intrinsics/probes/tcgen05_ld_16x128b_x32_raw.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_ld_16x128b_x4_pack16.ll b/intrinsics/probes/tcgen05_ld_16x128b_x4_pack16.ll index 0ce0fc6f99..e4cec7c6a0 100644 --- a/intrinsics/probes/tcgen05_ld_16x128b_x4_pack16.ll +++ b/intrinsics/probes/tcgen05_ld_16x128b_x4_pack16.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_ld_16x128b_x4_raw.ll b/intrinsics/probes/tcgen05_ld_16x128b_x4_raw.ll index 4c7efc8ab0..9de52f6c24 100644 --- a/intrinsics/probes/tcgen05_ld_16x128b_x4_raw.ll +++ b/intrinsics/probes/tcgen05_ld_16x128b_x4_raw.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_ld_16x128b_x64_pack16.ll b/intrinsics/probes/tcgen05_ld_16x128b_x64_pack16.ll index 344f1ae20f..c267c1f75f 100644 --- a/intrinsics/probes/tcgen05_ld_16x128b_x64_pack16.ll +++ b/intrinsics/probes/tcgen05_ld_16x128b_x64_pack16.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_ld_16x128b_x64_raw.ll b/intrinsics/probes/tcgen05_ld_16x128b_x64_raw.ll index cf7887d8e4..5f819b3ffc 100644 --- a/intrinsics/probes/tcgen05_ld_16x128b_x64_raw.ll +++ b/intrinsics/probes/tcgen05_ld_16x128b_x64_raw.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_ld_16x128b_x8_pack16.ll b/intrinsics/probes/tcgen05_ld_16x128b_x8_pack16.ll index c8424496c2..e3288a032b 100644 --- a/intrinsics/probes/tcgen05_ld_16x128b_x8_pack16.ll +++ b/intrinsics/probes/tcgen05_ld_16x128b_x8_pack16.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_ld_16x128b_x8_raw.ll b/intrinsics/probes/tcgen05_ld_16x128b_x8_raw.ll index 53558f2947..5f098b5250 100644 --- a/intrinsics/probes/tcgen05_ld_16x128b_x8_raw.ll +++ b/intrinsics/probes/tcgen05_ld_16x128b_x8_raw.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_ld_16x256b_pure.ll b/intrinsics/probes/tcgen05_ld_16x256b_pure.ll index cd5d7d7e4c..c38ea27ed7 100644 --- a/intrinsics/probes/tcgen05_ld_16x256b_pure.ll +++ b/intrinsics/probes/tcgen05_ld_16x256b_pure.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_ld_16x256b_x16_pack16.ll b/intrinsics/probes/tcgen05_ld_16x256b_x16_pack16.ll index a78aee2dc4..6764676055 100644 --- a/intrinsics/probes/tcgen05_ld_16x256b_x16_pack16.ll +++ b/intrinsics/probes/tcgen05_ld_16x256b_x16_pack16.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_ld_16x256b_x16_raw.ll b/intrinsics/probes/tcgen05_ld_16x256b_x16_raw.ll index a4c42e81ba..c0f32240c4 100644 --- a/intrinsics/probes/tcgen05_ld_16x256b_x16_raw.ll +++ b/intrinsics/probes/tcgen05_ld_16x256b_x16_raw.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_ld_16x256b_x1_pack16.ll b/intrinsics/probes/tcgen05_ld_16x256b_x1_pack16.ll index 25eaf0e149..163f5d5359 100644 --- a/intrinsics/probes/tcgen05_ld_16x256b_x1_pack16.ll +++ b/intrinsics/probes/tcgen05_ld_16x256b_x1_pack16.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_ld_16x256b_x1_raw.ll b/intrinsics/probes/tcgen05_ld_16x256b_x1_raw.ll index 95a8dc24db..23f1fb0ebd 100644 --- a/intrinsics/probes/tcgen05_ld_16x256b_x1_raw.ll +++ b/intrinsics/probes/tcgen05_ld_16x256b_x1_raw.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_ld_16x256b_x2_pack16.ll b/intrinsics/probes/tcgen05_ld_16x256b_x2_pack16.ll index 25999a627c..42901f8862 100644 --- a/intrinsics/probes/tcgen05_ld_16x256b_x2_pack16.ll +++ b/intrinsics/probes/tcgen05_ld_16x256b_x2_pack16.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_ld_16x256b_x2_raw.ll b/intrinsics/probes/tcgen05_ld_16x256b_x2_raw.ll index eb1e0c3ab1..1136977a04 100644 --- a/intrinsics/probes/tcgen05_ld_16x256b_x2_raw.ll +++ b/intrinsics/probes/tcgen05_ld_16x256b_x2_raw.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_ld_16x256b_x32_pack16.ll b/intrinsics/probes/tcgen05_ld_16x256b_x32_pack16.ll index c17de02424..ea25345e24 100644 --- a/intrinsics/probes/tcgen05_ld_16x256b_x32_pack16.ll +++ b/intrinsics/probes/tcgen05_ld_16x256b_x32_pack16.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_ld_16x256b_x32_raw.ll b/intrinsics/probes/tcgen05_ld_16x256b_x32_raw.ll index 16594c1d75..34394d5cf7 100644 --- a/intrinsics/probes/tcgen05_ld_16x256b_x32_raw.ll +++ b/intrinsics/probes/tcgen05_ld_16x256b_x32_raw.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_ld_16x256b_x4_pack16.ll b/intrinsics/probes/tcgen05_ld_16x256b_x4_pack16.ll index fad23a0e8a..5d3257d327 100644 --- a/intrinsics/probes/tcgen05_ld_16x256b_x4_pack16.ll +++ b/intrinsics/probes/tcgen05_ld_16x256b_x4_pack16.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_ld_16x256b_x4_raw.ll b/intrinsics/probes/tcgen05_ld_16x256b_x4_raw.ll index afe7106659..096a9efbd3 100644 --- a/intrinsics/probes/tcgen05_ld_16x256b_x4_raw.ll +++ b/intrinsics/probes/tcgen05_ld_16x256b_x4_raw.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_ld_16x256b_x8_pack16.ll b/intrinsics/probes/tcgen05_ld_16x256b_x8_pack16.ll index 88ca59b16b..4005eb0ce4 100644 --- a/intrinsics/probes/tcgen05_ld_16x256b_x8_pack16.ll +++ b/intrinsics/probes/tcgen05_ld_16x256b_x8_pack16.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_ld_16x256b_x8_pure.ll b/intrinsics/probes/tcgen05_ld_16x256b_x8_pure.ll index 65d2ea9545..22a86465a3 100644 --- a/intrinsics/probes/tcgen05_ld_16x256b_x8_pure.ll +++ b/intrinsics/probes/tcgen05_ld_16x256b_x8_pure.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_ld_16x256b_x8_raw.ll b/intrinsics/probes/tcgen05_ld_16x256b_x8_raw.ll index 020444c8bb..7519fe305d 100644 --- a/intrinsics/probes/tcgen05_ld_16x256b_x8_raw.ll +++ b/intrinsics/probes/tcgen05_ld_16x256b_x8_raw.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_ld_16x32bx2_x128_pack16.ll b/intrinsics/probes/tcgen05_ld_16x32bx2_x128_pack16.ll index 8dd5286627..41569e59cc 100644 --- a/intrinsics/probes/tcgen05_ld_16x32bx2_x128_pack16.ll +++ b/intrinsics/probes/tcgen05_ld_16x32bx2_x128_pack16.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_ld_16x32bx2_x128_raw.ll b/intrinsics/probes/tcgen05_ld_16x32bx2_x128_raw.ll index 7bfdad6e7d..cdf2fcdfb0 100644 --- a/intrinsics/probes/tcgen05_ld_16x32bx2_x128_raw.ll +++ b/intrinsics/probes/tcgen05_ld_16x32bx2_x128_raw.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_ld_16x32bx2_x16_pack16.ll b/intrinsics/probes/tcgen05_ld_16x32bx2_x16_pack16.ll index f12cc8f191..751c7633fe 100644 --- a/intrinsics/probes/tcgen05_ld_16x32bx2_x16_pack16.ll +++ b/intrinsics/probes/tcgen05_ld_16x32bx2_x16_pack16.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_ld_16x32bx2_x16_raw.ll b/intrinsics/probes/tcgen05_ld_16x32bx2_x16_raw.ll index 83322aa019..a7b8fbbaf1 100644 --- a/intrinsics/probes/tcgen05_ld_16x32bx2_x16_raw.ll +++ b/intrinsics/probes/tcgen05_ld_16x32bx2_x16_raw.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_ld_16x32bx2_x1_pack16.ll b/intrinsics/probes/tcgen05_ld_16x32bx2_x1_pack16.ll index 25ad7d0b01..b37f91ed9b 100644 --- a/intrinsics/probes/tcgen05_ld_16x32bx2_x1_pack16.ll +++ b/intrinsics/probes/tcgen05_ld_16x32bx2_x1_pack16.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_ld_16x32bx2_x1_raw.ll b/intrinsics/probes/tcgen05_ld_16x32bx2_x1_raw.ll index ab2c058edb..cf59f5d9e9 100644 --- a/intrinsics/probes/tcgen05_ld_16x32bx2_x1_raw.ll +++ b/intrinsics/probes/tcgen05_ld_16x32bx2_x1_raw.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_ld_16x32bx2_x2_pack16.ll b/intrinsics/probes/tcgen05_ld_16x32bx2_x2_pack16.ll index cc55d59ac3..26bd0f0d74 100644 --- a/intrinsics/probes/tcgen05_ld_16x32bx2_x2_pack16.ll +++ b/intrinsics/probes/tcgen05_ld_16x32bx2_x2_pack16.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_ld_16x32bx2_x2_raw.ll b/intrinsics/probes/tcgen05_ld_16x32bx2_x2_raw.ll index 5911dde587..ff61960622 100644 --- a/intrinsics/probes/tcgen05_ld_16x32bx2_x2_raw.ll +++ b/intrinsics/probes/tcgen05_ld_16x32bx2_x2_raw.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_ld_16x32bx2_x32_pack16.ll b/intrinsics/probes/tcgen05_ld_16x32bx2_x32_pack16.ll index 18824fb0a3..13ce5fc05c 100644 --- a/intrinsics/probes/tcgen05_ld_16x32bx2_x32_pack16.ll +++ b/intrinsics/probes/tcgen05_ld_16x32bx2_x32_pack16.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_ld_16x32bx2_x32_raw.ll b/intrinsics/probes/tcgen05_ld_16x32bx2_x32_raw.ll index 99c9622ad2..4e58125768 100644 --- a/intrinsics/probes/tcgen05_ld_16x32bx2_x32_raw.ll +++ b/intrinsics/probes/tcgen05_ld_16x32bx2_x32_raw.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_ld_16x32bx2_x4_pack16.ll b/intrinsics/probes/tcgen05_ld_16x32bx2_x4_pack16.ll index e66e29fa50..4702a4ef65 100644 --- a/intrinsics/probes/tcgen05_ld_16x32bx2_x4_pack16.ll +++ b/intrinsics/probes/tcgen05_ld_16x32bx2_x4_pack16.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_ld_16x32bx2_x4_raw.ll b/intrinsics/probes/tcgen05_ld_16x32bx2_x4_raw.ll index e07a4ac692..1d1259b1bb 100644 --- a/intrinsics/probes/tcgen05_ld_16x32bx2_x4_raw.ll +++ b/intrinsics/probes/tcgen05_ld_16x32bx2_x4_raw.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_ld_16x32bx2_x64_pack16.ll b/intrinsics/probes/tcgen05_ld_16x32bx2_x64_pack16.ll index 076fcd099b..6cea24fac1 100644 --- a/intrinsics/probes/tcgen05_ld_16x32bx2_x64_pack16.ll +++ b/intrinsics/probes/tcgen05_ld_16x32bx2_x64_pack16.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_ld_16x32bx2_x64_raw.ll b/intrinsics/probes/tcgen05_ld_16x32bx2_x64_raw.ll index 592d3552a7..c788838d06 100644 --- a/intrinsics/probes/tcgen05_ld_16x32bx2_x64_raw.ll +++ b/intrinsics/probes/tcgen05_ld_16x32bx2_x64_raw.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_ld_16x32bx2_x8_pack16.ll b/intrinsics/probes/tcgen05_ld_16x32bx2_x8_pack16.ll index d7d76cead3..ba2529a5f2 100644 --- a/intrinsics/probes/tcgen05_ld_16x32bx2_x8_pack16.ll +++ b/intrinsics/probes/tcgen05_ld_16x32bx2_x8_pack16.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_ld_16x32bx2_x8_raw.ll b/intrinsics/probes/tcgen05_ld_16x32bx2_x8_raw.ll index 9f5ed8e4f7..783252cc32 100644 --- a/intrinsics/probes/tcgen05_ld_16x32bx2_x8_raw.ll +++ b/intrinsics/probes/tcgen05_ld_16x32bx2_x8_raw.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_ld_16x64b_x128_pack16.ll b/intrinsics/probes/tcgen05_ld_16x64b_x128_pack16.ll index b3f8d45cc1..11e76f5ff8 100644 --- a/intrinsics/probes/tcgen05_ld_16x64b_x128_pack16.ll +++ b/intrinsics/probes/tcgen05_ld_16x64b_x128_pack16.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_ld_16x64b_x128_raw.ll b/intrinsics/probes/tcgen05_ld_16x64b_x128_raw.ll index e52f680484..caa958555d 100644 --- a/intrinsics/probes/tcgen05_ld_16x64b_x128_raw.ll +++ b/intrinsics/probes/tcgen05_ld_16x64b_x128_raw.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_ld_16x64b_x16_pack16.ll b/intrinsics/probes/tcgen05_ld_16x64b_x16_pack16.ll index a0675b9ba7..32b5de094a 100644 --- a/intrinsics/probes/tcgen05_ld_16x64b_x16_pack16.ll +++ b/intrinsics/probes/tcgen05_ld_16x64b_x16_pack16.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_ld_16x64b_x16_raw.ll b/intrinsics/probes/tcgen05_ld_16x64b_x16_raw.ll index 102458721d..031947283e 100644 --- a/intrinsics/probes/tcgen05_ld_16x64b_x16_raw.ll +++ b/intrinsics/probes/tcgen05_ld_16x64b_x16_raw.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_ld_16x64b_x1_pack16.ll b/intrinsics/probes/tcgen05_ld_16x64b_x1_pack16.ll index 5d7b27c83f..6fddb3691f 100644 --- a/intrinsics/probes/tcgen05_ld_16x64b_x1_pack16.ll +++ b/intrinsics/probes/tcgen05_ld_16x64b_x1_pack16.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_ld_16x64b_x1_raw.ll b/intrinsics/probes/tcgen05_ld_16x64b_x1_raw.ll index 9fe3271164..4009b29111 100644 --- a/intrinsics/probes/tcgen05_ld_16x64b_x1_raw.ll +++ b/intrinsics/probes/tcgen05_ld_16x64b_x1_raw.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_ld_16x64b_x2_pack16.ll b/intrinsics/probes/tcgen05_ld_16x64b_x2_pack16.ll index 7e49edf764..c23d3e6cca 100644 --- a/intrinsics/probes/tcgen05_ld_16x64b_x2_pack16.ll +++ b/intrinsics/probes/tcgen05_ld_16x64b_x2_pack16.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_ld_16x64b_x2_raw.ll b/intrinsics/probes/tcgen05_ld_16x64b_x2_raw.ll index 8713d03534..8183bb390b 100644 --- a/intrinsics/probes/tcgen05_ld_16x64b_x2_raw.ll +++ b/intrinsics/probes/tcgen05_ld_16x64b_x2_raw.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_ld_16x64b_x32_pack16.ll b/intrinsics/probes/tcgen05_ld_16x64b_x32_pack16.ll index 8327283224..3e3f95af9a 100644 --- a/intrinsics/probes/tcgen05_ld_16x64b_x32_pack16.ll +++ b/intrinsics/probes/tcgen05_ld_16x64b_x32_pack16.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_ld_16x64b_x32_raw.ll b/intrinsics/probes/tcgen05_ld_16x64b_x32_raw.ll index 818c2ded3e..4f06d4a0e8 100644 --- a/intrinsics/probes/tcgen05_ld_16x64b_x32_raw.ll +++ b/intrinsics/probes/tcgen05_ld_16x64b_x32_raw.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_ld_16x64b_x4_pack16.ll b/intrinsics/probes/tcgen05_ld_16x64b_x4_pack16.ll index 4c5387bb02..40bf139366 100644 --- a/intrinsics/probes/tcgen05_ld_16x64b_x4_pack16.ll +++ b/intrinsics/probes/tcgen05_ld_16x64b_x4_pack16.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_ld_16x64b_x4_raw.ll b/intrinsics/probes/tcgen05_ld_16x64b_x4_raw.ll index fda568db2e..8eac7fa585 100644 --- a/intrinsics/probes/tcgen05_ld_16x64b_x4_raw.ll +++ b/intrinsics/probes/tcgen05_ld_16x64b_x4_raw.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_ld_16x64b_x64_pack16.ll b/intrinsics/probes/tcgen05_ld_16x64b_x64_pack16.ll index 9ab5b89436..f588434ded 100644 --- a/intrinsics/probes/tcgen05_ld_16x64b_x64_pack16.ll +++ b/intrinsics/probes/tcgen05_ld_16x64b_x64_pack16.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_ld_16x64b_x64_raw.ll b/intrinsics/probes/tcgen05_ld_16x64b_x64_raw.ll index 183a8942ae..20442155b9 100644 --- a/intrinsics/probes/tcgen05_ld_16x64b_x64_raw.ll +++ b/intrinsics/probes/tcgen05_ld_16x64b_x64_raw.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_ld_16x64b_x8_pack16.ll b/intrinsics/probes/tcgen05_ld_16x64b_x8_pack16.ll index 3306a5f1b8..8a78a97786 100644 --- a/intrinsics/probes/tcgen05_ld_16x64b_x8_pack16.ll +++ b/intrinsics/probes/tcgen05_ld_16x64b_x8_pack16.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_ld_16x64b_x8_raw.ll b/intrinsics/probes/tcgen05_ld_16x64b_x8_raw.ll index e780f561f4..0ed7f88de8 100644 --- a/intrinsics/probes/tcgen05_ld_16x64b_x8_raw.ll +++ b/intrinsics/probes/tcgen05_ld_16x64b_x8_raw.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_ld_32x32b_x128_pack16.ll b/intrinsics/probes/tcgen05_ld_32x32b_x128_pack16.ll index c0e6da6119..2fec4c6cdf 100644 --- a/intrinsics/probes/tcgen05_ld_32x32b_x128_pack16.ll +++ b/intrinsics/probes/tcgen05_ld_32x32b_x128_pack16.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_ld_32x32b_x128_raw.ll b/intrinsics/probes/tcgen05_ld_32x32b_x128_raw.ll index 8dbb031e9d..9c514c056e 100644 --- a/intrinsics/probes/tcgen05_ld_32x32b_x128_raw.ll +++ b/intrinsics/probes/tcgen05_ld_32x32b_x128_raw.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_ld_32x32b_x16_pack16.ll b/intrinsics/probes/tcgen05_ld_32x32b_x16_pack16.ll index a5adc918dd..0423e70beb 100644 --- a/intrinsics/probes/tcgen05_ld_32x32b_x16_pack16.ll +++ b/intrinsics/probes/tcgen05_ld_32x32b_x16_pack16.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_ld_32x32b_x16_raw.ll b/intrinsics/probes/tcgen05_ld_32x32b_x16_raw.ll index 7ac52ccf87..7e69b7c78e 100644 --- a/intrinsics/probes/tcgen05_ld_32x32b_x16_raw.ll +++ b/intrinsics/probes/tcgen05_ld_32x32b_x16_raw.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_ld_32x32b_x1_pack16.ll b/intrinsics/probes/tcgen05_ld_32x32b_x1_pack16.ll index a25fa63027..7e82ef8a0a 100644 --- a/intrinsics/probes/tcgen05_ld_32x32b_x1_pack16.ll +++ b/intrinsics/probes/tcgen05_ld_32x32b_x1_pack16.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_ld_32x32b_x1_raw.ll b/intrinsics/probes/tcgen05_ld_32x32b_x1_raw.ll index d98b8eb722..416c7157af 100644 --- a/intrinsics/probes/tcgen05_ld_32x32b_x1_raw.ll +++ b/intrinsics/probes/tcgen05_ld_32x32b_x1_raw.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_ld_32x32b_x2_pack16.ll b/intrinsics/probes/tcgen05_ld_32x32b_x2_pack16.ll index bc9503b615..dbc6e91597 100644 --- a/intrinsics/probes/tcgen05_ld_32x32b_x2_pack16.ll +++ b/intrinsics/probes/tcgen05_ld_32x32b_x2_pack16.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_ld_32x32b_x2_raw.ll b/intrinsics/probes/tcgen05_ld_32x32b_x2_raw.ll index d8d7af513a..52f0110599 100644 --- a/intrinsics/probes/tcgen05_ld_32x32b_x2_raw.ll +++ b/intrinsics/probes/tcgen05_ld_32x32b_x2_raw.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_ld_32x32b_x32_pack16.ll b/intrinsics/probes/tcgen05_ld_32x32b_x32_pack16.ll index e7e60e3aa8..6aa3212834 100644 --- a/intrinsics/probes/tcgen05_ld_32x32b_x32_pack16.ll +++ b/intrinsics/probes/tcgen05_ld_32x32b_x32_pack16.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_ld_32x32b_x32_raw.ll b/intrinsics/probes/tcgen05_ld_32x32b_x32_raw.ll index fe20bea78b..3e278f4962 100644 --- a/intrinsics/probes/tcgen05_ld_32x32b_x32_raw.ll +++ b/intrinsics/probes/tcgen05_ld_32x32b_x32_raw.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_ld_32x32b_x4_pack16.ll b/intrinsics/probes/tcgen05_ld_32x32b_x4_pack16.ll index 6d31b0fcdc..800bba6dbc 100644 --- a/intrinsics/probes/tcgen05_ld_32x32b_x4_pack16.ll +++ b/intrinsics/probes/tcgen05_ld_32x32b_x4_pack16.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_ld_32x32b_x4_raw.ll b/intrinsics/probes/tcgen05_ld_32x32b_x4_raw.ll index d8ed3ef203..bf8978b41c 100644 --- a/intrinsics/probes/tcgen05_ld_32x32b_x4_raw.ll +++ b/intrinsics/probes/tcgen05_ld_32x32b_x4_raw.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_ld_32x32b_x64_pack16.ll b/intrinsics/probes/tcgen05_ld_32x32b_x64_pack16.ll index 734552addf..f61adbc9d5 100644 --- a/intrinsics/probes/tcgen05_ld_32x32b_x64_pack16.ll +++ b/intrinsics/probes/tcgen05_ld_32x32b_x64_pack16.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_ld_32x32b_x64_raw.ll b/intrinsics/probes/tcgen05_ld_32x32b_x64_raw.ll index a58a1de46e..648be5e95d 100644 --- a/intrinsics/probes/tcgen05_ld_32x32b_x64_raw.ll +++ b/intrinsics/probes/tcgen05_ld_32x32b_x64_raw.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_ld_32x32b_x8_pack16.ll b/intrinsics/probes/tcgen05_ld_32x32b_x8_pack16.ll index 421f5f8329..614abe4c68 100644 --- a/intrinsics/probes/tcgen05_ld_32x32b_x8_pack16.ll +++ b/intrinsics/probes/tcgen05_ld_32x32b_x8_pack16.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_ld_32x32b_x8_raw.ll b/intrinsics/probes/tcgen05_ld_32x32b_x8_raw.ll index 4dc1c28bda..4cb7264037 100644 --- a/intrinsics/probes/tcgen05_ld_32x32b_x8_raw.ll +++ b/intrinsics/probes/tcgen05_ld_32x32b_x8_raw.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_load_wait.ll b/intrinsics/probes/tcgen05_load_wait.ll index a10c20c1e9..f41012224a 100644 --- a/intrinsics/probes/tcgen05_load_wait.ll +++ b/intrinsics/probes/tcgen05_load_wait.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_mma_e2m1.ll b/intrinsics/probes/tcgen05_mma_e2m1.ll index 1eaea5df47..0e392ed2ba 100644 --- a/intrinsics/probes/tcgen05_mma_e2m1.ll +++ b/intrinsics/probes/tcgen05_mma_e2m1.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_mma_e2m3.ll b/intrinsics/probes/tcgen05_mma_e2m3.ll index df54689237..3945d93f42 100644 --- a/intrinsics/probes/tcgen05_mma_e2m3.ll +++ b/intrinsics/probes/tcgen05_mma_e2m3.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_mma_e3m2.ll b/intrinsics/probes/tcgen05_mma_e3m2.ll index acfe5dae31..fa29cf7e4a 100644 --- a/intrinsics/probes/tcgen05_mma_e3m2.ll +++ b/intrinsics/probes/tcgen05_mma_e3m2.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_mma_e4m3.ll b/intrinsics/probes/tcgen05_mma_e4m3.ll index fffb2c37e1..5ab762738f 100644 --- a/intrinsics/probes/tcgen05_mma_e4m3.ll +++ b/intrinsics/probes/tcgen05_mma_e4m3.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_mma_e5m2.ll b/intrinsics/probes/tcgen05_mma_e5m2.ll index c3401e1b95..9c003b6df1 100644 --- a/intrinsics/probes/tcgen05_mma_e5m2.ll +++ b/intrinsics/probes/tcgen05_mma_e5m2.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_mma_f16.ll b/intrinsics/probes/tcgen05_mma_f16.ll index df17154531..3538ae9df7 100644 --- a/intrinsics/probes/tcgen05_mma_f16.ll +++ b/intrinsics/probes/tcgen05_mma_f16.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_mma_f16_cg2.ll b/intrinsics/probes/tcgen05_mma_f16_cg2.ll index ecc00ea4f4..ce0cf87a68 100644 --- a/intrinsics/probes/tcgen05_mma_f16_cg2.ll +++ b/intrinsics/probes/tcgen05_mma_f16_cg2.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_mma_shared.ll b/intrinsics/probes/tcgen05_mma_shared.ll index 580ece1109..a475a9bc3e 100644 --- a/intrinsics/probes/tcgen05_mma_shared.ll +++ b/intrinsics/probes/tcgen05_mma_shared.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_mma_sp_shared.ll b/intrinsics/probes/tcgen05_mma_sp_shared.ll index 8dd45e10c7..119573ec85 100644 --- a/intrinsics/probes/tcgen05_mma_sp_shared.ll +++ b/intrinsics/probes/tcgen05_mma_sp_shared.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_mma_sp_tensor.ll b/intrinsics/probes/tcgen05_mma_sp_tensor.ll index 69581d5c58..1e12ee88af 100644 --- a/intrinsics/probes/tcgen05_mma_sp_tensor.ll +++ b/intrinsics/probes/tcgen05_mma_sp_tensor.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_mma_sp_tensor_ashift.ll b/intrinsics/probes/tcgen05_mma_sp_tensor_ashift.ll index b0f70e611b..40d88557d1 100644 --- a/intrinsics/probes/tcgen05_mma_sp_tensor_ashift.ll +++ b/intrinsics/probes/tcgen05_mma_sp_tensor_ashift.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_mma_tensor.ll b/intrinsics/probes/tcgen05_mma_tensor.ll index 98d39bddcc..eba2322e23 100644 --- a/intrinsics/probes/tcgen05_mma_tensor.ll +++ b/intrinsics/probes/tcgen05_mma_tensor.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_mma_tensor_ashift.ll b/intrinsics/probes/tcgen05_mma_tensor_ashift.ll index 0f1a2d149f..b38ee094c7 100644 --- a/intrinsics/probes/tcgen05_mma_tensor_ashift.ll +++ b/intrinsics/probes/tcgen05_mma_tensor_ashift.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_mma_ws_bf16.ll b/intrinsics/probes/tcgen05_mma_ws_bf16.ll index 9054761ff7..75f3125099 100644 --- a/intrinsics/probes/tcgen05_mma_ws_bf16.ll +++ b/intrinsics/probes/tcgen05_mma_ws_bf16.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_mma_ws_e2m1.ll b/intrinsics/probes/tcgen05_mma_ws_e2m1.ll index b93ce0a7bc..f38606f74f 100644 --- a/intrinsics/probes/tcgen05_mma_ws_e2m1.ll +++ b/intrinsics/probes/tcgen05_mma_ws_e2m1.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_mma_ws_e2m3.ll b/intrinsics/probes/tcgen05_mma_ws_e2m3.ll index be1e31db2c..8b51383110 100644 --- a/intrinsics/probes/tcgen05_mma_ws_e2m3.ll +++ b/intrinsics/probes/tcgen05_mma_ws_e2m3.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_mma_ws_e3m2.ll b/intrinsics/probes/tcgen05_mma_ws_e3m2.ll index 7943164d16..9881fc100d 100644 --- a/intrinsics/probes/tcgen05_mma_ws_e3m2.ll +++ b/intrinsics/probes/tcgen05_mma_ws_e3m2.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_mma_ws_e4m3.ll b/intrinsics/probes/tcgen05_mma_ws_e4m3.ll index 1e736c274c..58ed36f1b2 100644 --- a/intrinsics/probes/tcgen05_mma_ws_e4m3.ll +++ b/intrinsics/probes/tcgen05_mma_ws_e4m3.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_mma_ws_e5m2.ll b/intrinsics/probes/tcgen05_mma_ws_e5m2.ll index f6e2400b22..f8194296cc 100644 --- a/intrinsics/probes/tcgen05_mma_ws_e5m2.ll +++ b/intrinsics/probes/tcgen05_mma_ws_e5m2.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_mma_ws_f16.ll b/intrinsics/probes/tcgen05_mma_ws_f16.ll index 9cc35ebb88..f812166573 100644 --- a/intrinsics/probes/tcgen05_mma_ws_f16.ll +++ b/intrinsics/probes/tcgen05_mma_ws_f16.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_mma_ws_shared.ll b/intrinsics/probes/tcgen05_mma_ws_shared.ll index 258ed384e6..e893ce30c6 100644 --- a/intrinsics/probes/tcgen05_mma_ws_shared.ll +++ b/intrinsics/probes/tcgen05_mma_ws_shared.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_mma_ws_shared_zero_col_mask.ll b/intrinsics/probes/tcgen05_mma_ws_shared_zero_col_mask.ll index 2086352334..03c1d2d092 100644 --- a/intrinsics/probes/tcgen05_mma_ws_shared_zero_col_mask.ll +++ b/intrinsics/probes/tcgen05_mma_ws_shared_zero_col_mask.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_mma_ws_sp_shared.ll b/intrinsics/probes/tcgen05_mma_ws_sp_shared.ll index 7d1a831543..60a36cc2c0 100644 --- a/intrinsics/probes/tcgen05_mma_ws_sp_shared.ll +++ b/intrinsics/probes/tcgen05_mma_ws_sp_shared.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_mma_ws_sp_shared_zero_col_mask.ll b/intrinsics/probes/tcgen05_mma_ws_sp_shared_zero_col_mask.ll index 91c8ba36ac..edda2fbc71 100644 --- a/intrinsics/probes/tcgen05_mma_ws_sp_shared_zero_col_mask.ll +++ b/intrinsics/probes/tcgen05_mma_ws_sp_shared_zero_col_mask.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_mma_ws_sp_tensor.ll b/intrinsics/probes/tcgen05_mma_ws_sp_tensor.ll index 62649307ba..6d2c3f5ea3 100644 --- a/intrinsics/probes/tcgen05_mma_ws_sp_tensor.ll +++ b/intrinsics/probes/tcgen05_mma_ws_sp_tensor.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_mma_ws_sp_tensor_zero_col_mask.ll b/intrinsics/probes/tcgen05_mma_ws_sp_tensor_zero_col_mask.ll index 43b784ccdc..5505621478 100644 --- a/intrinsics/probes/tcgen05_mma_ws_sp_tensor_zero_col_mask.ll +++ b/intrinsics/probes/tcgen05_mma_ws_sp_tensor_zero_col_mask.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_mma_ws_tensor.ll b/intrinsics/probes/tcgen05_mma_ws_tensor.ll index 6cbdabafff..f5d7fb1fbd 100644 --- a/intrinsics/probes/tcgen05_mma_ws_tensor.ll +++ b/intrinsics/probes/tcgen05_mma_ws_tensor.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_mma_ws_tensor_zero_col_mask.ll b/intrinsics/probes/tcgen05_mma_ws_tensor_zero_col_mask.ll index 1bccfc294c..2e1dbfea5a 100644 --- a/intrinsics/probes/tcgen05_mma_ws_tensor_zero_col_mask.ll +++ b/intrinsics/probes/tcgen05_mma_ws_tensor_zero_col_mask.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_mma_ws_tf32.ll b/intrinsics/probes/tcgen05_mma_ws_tf32.ll index 7a2f05e2da..e1a19058c5 100644 --- a/intrinsics/probes/tcgen05_mma_ws_tf32.ll +++ b/intrinsics/probes/tcgen05_mma_ws_tf32.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_relinquish_alloc_permit.ll b/intrinsics/probes/tcgen05_relinquish_alloc_permit.ll index ca5e583fd4..a848a0ab7c 100644 --- a/intrinsics/probes/tcgen05_relinquish_alloc_permit.ll +++ b/intrinsics/probes/tcgen05_relinquish_alloc_permit.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_relinquish_alloc_permit_cg2.ll b/intrinsics/probes/tcgen05_relinquish_alloc_permit_cg2.ll index 6fc592898d..a5ff47253b 100644 --- a/intrinsics/probes/tcgen05_relinquish_alloc_permit_cg2.ll +++ b/intrinsics/probes/tcgen05_relinquish_alloc_permit_cg2.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_shift_down.ll b/intrinsics/probes/tcgen05_shift_down.ll index 31a3dd9a2b..10530bce10 100644 --- a/intrinsics/probes/tcgen05_shift_down.ll +++ b/intrinsics/probes/tcgen05_shift_down.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_shift_down_cg2.ll b/intrinsics/probes/tcgen05_shift_down_cg2.ll index 29dbe7ade7..2a7f85ad59 100644 --- a/intrinsics/probes/tcgen05_shift_down_cg2.ll +++ b/intrinsics/probes/tcgen05_shift_down_cg2.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_st_16x128b_x16_raw.ll b/intrinsics/probes/tcgen05_st_16x128b_x16_raw.ll index 1dea4e2828..2bf86a0c86 100644 --- a/intrinsics/probes/tcgen05_st_16x128b_x16_raw.ll +++ b/intrinsics/probes/tcgen05_st_16x128b_x16_raw.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_st_16x128b_x16_unpack16.ll b/intrinsics/probes/tcgen05_st_16x128b_x16_unpack16.ll index dee5320752..53826ee3b7 100644 --- a/intrinsics/probes/tcgen05_st_16x128b_x16_unpack16.ll +++ b/intrinsics/probes/tcgen05_st_16x128b_x16_unpack16.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_st_16x128b_x1_raw.ll b/intrinsics/probes/tcgen05_st_16x128b_x1_raw.ll index 03d1eed754..00f52efa30 100644 --- a/intrinsics/probes/tcgen05_st_16x128b_x1_raw.ll +++ b/intrinsics/probes/tcgen05_st_16x128b_x1_raw.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_st_16x128b_x1_unpack16.ll b/intrinsics/probes/tcgen05_st_16x128b_x1_unpack16.ll index 2ee308f8fd..4b7e15298a 100644 --- a/intrinsics/probes/tcgen05_st_16x128b_x1_unpack16.ll +++ b/intrinsics/probes/tcgen05_st_16x128b_x1_unpack16.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_st_16x128b_x2_raw.ll b/intrinsics/probes/tcgen05_st_16x128b_x2_raw.ll index a3737da91c..6f30c3f3c8 100644 --- a/intrinsics/probes/tcgen05_st_16x128b_x2_raw.ll +++ b/intrinsics/probes/tcgen05_st_16x128b_x2_raw.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_st_16x128b_x2_unpack16.ll b/intrinsics/probes/tcgen05_st_16x128b_x2_unpack16.ll index 2bc467f1c8..aeb0c49e0a 100644 --- a/intrinsics/probes/tcgen05_st_16x128b_x2_unpack16.ll +++ b/intrinsics/probes/tcgen05_st_16x128b_x2_unpack16.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_st_16x128b_x32_raw.ll b/intrinsics/probes/tcgen05_st_16x128b_x32_raw.ll index 423087f571..36c42972df 100644 --- a/intrinsics/probes/tcgen05_st_16x128b_x32_raw.ll +++ b/intrinsics/probes/tcgen05_st_16x128b_x32_raw.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_st_16x128b_x32_unpack16.ll b/intrinsics/probes/tcgen05_st_16x128b_x32_unpack16.ll index dc1c21ec19..858d797609 100644 --- a/intrinsics/probes/tcgen05_st_16x128b_x32_unpack16.ll +++ b/intrinsics/probes/tcgen05_st_16x128b_x32_unpack16.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_st_16x128b_x4_raw.ll b/intrinsics/probes/tcgen05_st_16x128b_x4_raw.ll index 679ed87fc3..de55b5a5c9 100644 --- a/intrinsics/probes/tcgen05_st_16x128b_x4_raw.ll +++ b/intrinsics/probes/tcgen05_st_16x128b_x4_raw.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_st_16x128b_x4_unpack16.ll b/intrinsics/probes/tcgen05_st_16x128b_x4_unpack16.ll index ca8cd6e547..f9d7bd6043 100644 --- a/intrinsics/probes/tcgen05_st_16x128b_x4_unpack16.ll +++ b/intrinsics/probes/tcgen05_st_16x128b_x4_unpack16.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_st_16x128b_x64_raw.ll b/intrinsics/probes/tcgen05_st_16x128b_x64_raw.ll index 833c5f3ac0..b980befadc 100644 --- a/intrinsics/probes/tcgen05_st_16x128b_x64_raw.ll +++ b/intrinsics/probes/tcgen05_st_16x128b_x64_raw.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_st_16x128b_x64_unpack16.ll b/intrinsics/probes/tcgen05_st_16x128b_x64_unpack16.ll index e6eb612d01..c5bed924f2 100644 --- a/intrinsics/probes/tcgen05_st_16x128b_x64_unpack16.ll +++ b/intrinsics/probes/tcgen05_st_16x128b_x64_unpack16.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_st_16x128b_x8_raw.ll b/intrinsics/probes/tcgen05_st_16x128b_x8_raw.ll index ec98bd81a2..47a1a9f69b 100644 --- a/intrinsics/probes/tcgen05_st_16x128b_x8_raw.ll +++ b/intrinsics/probes/tcgen05_st_16x128b_x8_raw.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_st_16x128b_x8_unpack16.ll b/intrinsics/probes/tcgen05_st_16x128b_x8_unpack16.ll index e474971815..c77f37ccfd 100644 --- a/intrinsics/probes/tcgen05_st_16x128b_x8_unpack16.ll +++ b/intrinsics/probes/tcgen05_st_16x128b_x8_unpack16.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_st_16x256b_x16_raw.ll b/intrinsics/probes/tcgen05_st_16x256b_x16_raw.ll index 68b2657306..07493acd22 100644 --- a/intrinsics/probes/tcgen05_st_16x256b_x16_raw.ll +++ b/intrinsics/probes/tcgen05_st_16x256b_x16_raw.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_st_16x256b_x16_unpack16.ll b/intrinsics/probes/tcgen05_st_16x256b_x16_unpack16.ll index 036c2cea90..fb978a4dcc 100644 --- a/intrinsics/probes/tcgen05_st_16x256b_x16_unpack16.ll +++ b/intrinsics/probes/tcgen05_st_16x256b_x16_unpack16.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_st_16x256b_x1_raw.ll b/intrinsics/probes/tcgen05_st_16x256b_x1_raw.ll index 7c6ce5ec1b..758e8b51cd 100644 --- a/intrinsics/probes/tcgen05_st_16x256b_x1_raw.ll +++ b/intrinsics/probes/tcgen05_st_16x256b_x1_raw.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_st_16x256b_x1_unpack16.ll b/intrinsics/probes/tcgen05_st_16x256b_x1_unpack16.ll index 2b48538494..888a2e8510 100644 --- a/intrinsics/probes/tcgen05_st_16x256b_x1_unpack16.ll +++ b/intrinsics/probes/tcgen05_st_16x256b_x1_unpack16.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_st_16x256b_x2_raw.ll b/intrinsics/probes/tcgen05_st_16x256b_x2_raw.ll index 576cb1f892..594540c9c7 100644 --- a/intrinsics/probes/tcgen05_st_16x256b_x2_raw.ll +++ b/intrinsics/probes/tcgen05_st_16x256b_x2_raw.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_st_16x256b_x2_unpack16.ll b/intrinsics/probes/tcgen05_st_16x256b_x2_unpack16.ll index 7ac85c2bdb..4499c05916 100644 --- a/intrinsics/probes/tcgen05_st_16x256b_x2_unpack16.ll +++ b/intrinsics/probes/tcgen05_st_16x256b_x2_unpack16.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_st_16x256b_x32_raw.ll b/intrinsics/probes/tcgen05_st_16x256b_x32_raw.ll index be1725d05a..c57ced1114 100644 --- a/intrinsics/probes/tcgen05_st_16x256b_x32_raw.ll +++ b/intrinsics/probes/tcgen05_st_16x256b_x32_raw.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_st_16x256b_x32_unpack16.ll b/intrinsics/probes/tcgen05_st_16x256b_x32_unpack16.ll index 72c1db7df1..d352fd53f0 100644 --- a/intrinsics/probes/tcgen05_st_16x256b_x32_unpack16.ll +++ b/intrinsics/probes/tcgen05_st_16x256b_x32_unpack16.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_st_16x256b_x4_raw.ll b/intrinsics/probes/tcgen05_st_16x256b_x4_raw.ll index 290456e17f..884b9dddea 100644 --- a/intrinsics/probes/tcgen05_st_16x256b_x4_raw.ll +++ b/intrinsics/probes/tcgen05_st_16x256b_x4_raw.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_st_16x256b_x4_unpack16.ll b/intrinsics/probes/tcgen05_st_16x256b_x4_unpack16.ll index 2f661acba7..9d73e662ed 100644 --- a/intrinsics/probes/tcgen05_st_16x256b_x4_unpack16.ll +++ b/intrinsics/probes/tcgen05_st_16x256b_x4_unpack16.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_st_16x256b_x8_raw.ll b/intrinsics/probes/tcgen05_st_16x256b_x8_raw.ll index 00ec2be3d6..0b7d6ca53c 100644 --- a/intrinsics/probes/tcgen05_st_16x256b_x8_raw.ll +++ b/intrinsics/probes/tcgen05_st_16x256b_x8_raw.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_st_16x256b_x8_unpack16.ll b/intrinsics/probes/tcgen05_st_16x256b_x8_unpack16.ll index 48044881fe..17b317336f 100644 --- a/intrinsics/probes/tcgen05_st_16x256b_x8_unpack16.ll +++ b/intrinsics/probes/tcgen05_st_16x256b_x8_unpack16.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_st_16x32bx2_x128_raw.ll b/intrinsics/probes/tcgen05_st_16x32bx2_x128_raw.ll index d175339198..f220020ca5 100644 --- a/intrinsics/probes/tcgen05_st_16x32bx2_x128_raw.ll +++ b/intrinsics/probes/tcgen05_st_16x32bx2_x128_raw.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_st_16x32bx2_x128_unpack16.ll b/intrinsics/probes/tcgen05_st_16x32bx2_x128_unpack16.ll index a5647599ea..c8a2668c9f 100644 --- a/intrinsics/probes/tcgen05_st_16x32bx2_x128_unpack16.ll +++ b/intrinsics/probes/tcgen05_st_16x32bx2_x128_unpack16.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_st_16x32bx2_x16_raw.ll b/intrinsics/probes/tcgen05_st_16x32bx2_x16_raw.ll index 9b80675be8..2efb313c73 100644 --- a/intrinsics/probes/tcgen05_st_16x32bx2_x16_raw.ll +++ b/intrinsics/probes/tcgen05_st_16x32bx2_x16_raw.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_st_16x32bx2_x16_unpack16.ll b/intrinsics/probes/tcgen05_st_16x32bx2_x16_unpack16.ll index 6dcd8b6ab3..74607bf3cb 100644 --- a/intrinsics/probes/tcgen05_st_16x32bx2_x16_unpack16.ll +++ b/intrinsics/probes/tcgen05_st_16x32bx2_x16_unpack16.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_st_16x32bx2_x1_raw.ll b/intrinsics/probes/tcgen05_st_16x32bx2_x1_raw.ll index 6f1863005a..367fe518f5 100644 --- a/intrinsics/probes/tcgen05_st_16x32bx2_x1_raw.ll +++ b/intrinsics/probes/tcgen05_st_16x32bx2_x1_raw.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_st_16x32bx2_x1_unpack16.ll b/intrinsics/probes/tcgen05_st_16x32bx2_x1_unpack16.ll index dd4f5fddd1..64c9bb1080 100644 --- a/intrinsics/probes/tcgen05_st_16x32bx2_x1_unpack16.ll +++ b/intrinsics/probes/tcgen05_st_16x32bx2_x1_unpack16.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_st_16x32bx2_x2_raw.ll b/intrinsics/probes/tcgen05_st_16x32bx2_x2_raw.ll index f86baae8e6..1c5a22528e 100644 --- a/intrinsics/probes/tcgen05_st_16x32bx2_x2_raw.ll +++ b/intrinsics/probes/tcgen05_st_16x32bx2_x2_raw.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_st_16x32bx2_x2_unpack16.ll b/intrinsics/probes/tcgen05_st_16x32bx2_x2_unpack16.ll index f4027cf870..6f141023d3 100644 --- a/intrinsics/probes/tcgen05_st_16x32bx2_x2_unpack16.ll +++ b/intrinsics/probes/tcgen05_st_16x32bx2_x2_unpack16.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_st_16x32bx2_x32_raw.ll b/intrinsics/probes/tcgen05_st_16x32bx2_x32_raw.ll index 8720a1e257..83a792af82 100644 --- a/intrinsics/probes/tcgen05_st_16x32bx2_x32_raw.ll +++ b/intrinsics/probes/tcgen05_st_16x32bx2_x32_raw.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_st_16x32bx2_x32_unpack16.ll b/intrinsics/probes/tcgen05_st_16x32bx2_x32_unpack16.ll index 79b4ca721b..bdecd86b64 100644 --- a/intrinsics/probes/tcgen05_st_16x32bx2_x32_unpack16.ll +++ b/intrinsics/probes/tcgen05_st_16x32bx2_x32_unpack16.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_st_16x32bx2_x4_raw.ll b/intrinsics/probes/tcgen05_st_16x32bx2_x4_raw.ll index 96aa8781a0..f22a7eec51 100644 --- a/intrinsics/probes/tcgen05_st_16x32bx2_x4_raw.ll +++ b/intrinsics/probes/tcgen05_st_16x32bx2_x4_raw.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_st_16x32bx2_x4_unpack16.ll b/intrinsics/probes/tcgen05_st_16x32bx2_x4_unpack16.ll index fcfe875fc4..523ef01ded 100644 --- a/intrinsics/probes/tcgen05_st_16x32bx2_x4_unpack16.ll +++ b/intrinsics/probes/tcgen05_st_16x32bx2_x4_unpack16.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_st_16x32bx2_x64_raw.ll b/intrinsics/probes/tcgen05_st_16x32bx2_x64_raw.ll index 7cb12d1c19..399d60db07 100644 --- a/intrinsics/probes/tcgen05_st_16x32bx2_x64_raw.ll +++ b/intrinsics/probes/tcgen05_st_16x32bx2_x64_raw.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_st_16x32bx2_x64_unpack16.ll b/intrinsics/probes/tcgen05_st_16x32bx2_x64_unpack16.ll index d806d07192..ebbf3ba29c 100644 --- a/intrinsics/probes/tcgen05_st_16x32bx2_x64_unpack16.ll +++ b/intrinsics/probes/tcgen05_st_16x32bx2_x64_unpack16.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_st_16x32bx2_x8_raw.ll b/intrinsics/probes/tcgen05_st_16x32bx2_x8_raw.ll index ca40495102..860c825fd7 100644 --- a/intrinsics/probes/tcgen05_st_16x32bx2_x8_raw.ll +++ b/intrinsics/probes/tcgen05_st_16x32bx2_x8_raw.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_st_16x32bx2_x8_unpack16.ll b/intrinsics/probes/tcgen05_st_16x32bx2_x8_unpack16.ll index 173b2b9352..1ff3e8fdb7 100644 --- a/intrinsics/probes/tcgen05_st_16x32bx2_x8_unpack16.ll +++ b/intrinsics/probes/tcgen05_st_16x32bx2_x8_unpack16.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_st_16x64b_x128_raw.ll b/intrinsics/probes/tcgen05_st_16x64b_x128_raw.ll index 6827349033..79de57288c 100644 --- a/intrinsics/probes/tcgen05_st_16x64b_x128_raw.ll +++ b/intrinsics/probes/tcgen05_st_16x64b_x128_raw.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_st_16x64b_x128_unpack16.ll b/intrinsics/probes/tcgen05_st_16x64b_x128_unpack16.ll index ad919f97b0..0cdf3394b4 100644 --- a/intrinsics/probes/tcgen05_st_16x64b_x128_unpack16.ll +++ b/intrinsics/probes/tcgen05_st_16x64b_x128_unpack16.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_st_16x64b_x16_raw.ll b/intrinsics/probes/tcgen05_st_16x64b_x16_raw.ll index 3c521b73c1..7c50da734f 100644 --- a/intrinsics/probes/tcgen05_st_16x64b_x16_raw.ll +++ b/intrinsics/probes/tcgen05_st_16x64b_x16_raw.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_st_16x64b_x16_unpack16.ll b/intrinsics/probes/tcgen05_st_16x64b_x16_unpack16.ll index 30555297a2..e0853f8b8f 100644 --- a/intrinsics/probes/tcgen05_st_16x64b_x16_unpack16.ll +++ b/intrinsics/probes/tcgen05_st_16x64b_x16_unpack16.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_st_16x64b_x1_raw.ll b/intrinsics/probes/tcgen05_st_16x64b_x1_raw.ll index 4e4fa64d41..b840ca698f 100644 --- a/intrinsics/probes/tcgen05_st_16x64b_x1_raw.ll +++ b/intrinsics/probes/tcgen05_st_16x64b_x1_raw.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_st_16x64b_x1_unpack16.ll b/intrinsics/probes/tcgen05_st_16x64b_x1_unpack16.ll index 9d5b484406..e0799b8193 100644 --- a/intrinsics/probes/tcgen05_st_16x64b_x1_unpack16.ll +++ b/intrinsics/probes/tcgen05_st_16x64b_x1_unpack16.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_st_16x64b_x2_raw.ll b/intrinsics/probes/tcgen05_st_16x64b_x2_raw.ll index be45d45ed8..70b94c630d 100644 --- a/intrinsics/probes/tcgen05_st_16x64b_x2_raw.ll +++ b/intrinsics/probes/tcgen05_st_16x64b_x2_raw.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_st_16x64b_x2_unpack16.ll b/intrinsics/probes/tcgen05_st_16x64b_x2_unpack16.ll index edeb87db0e..de0ae8c4cb 100644 --- a/intrinsics/probes/tcgen05_st_16x64b_x2_unpack16.ll +++ b/intrinsics/probes/tcgen05_st_16x64b_x2_unpack16.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_st_16x64b_x32_raw.ll b/intrinsics/probes/tcgen05_st_16x64b_x32_raw.ll index 9b0888367d..734325a724 100644 --- a/intrinsics/probes/tcgen05_st_16x64b_x32_raw.ll +++ b/intrinsics/probes/tcgen05_st_16x64b_x32_raw.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_st_16x64b_x32_unpack16.ll b/intrinsics/probes/tcgen05_st_16x64b_x32_unpack16.ll index 8376059f18..55525f1a4f 100644 --- a/intrinsics/probes/tcgen05_st_16x64b_x32_unpack16.ll +++ b/intrinsics/probes/tcgen05_st_16x64b_x32_unpack16.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_st_16x64b_x4_raw.ll b/intrinsics/probes/tcgen05_st_16x64b_x4_raw.ll index ce1e535303..5d437a4ae1 100644 --- a/intrinsics/probes/tcgen05_st_16x64b_x4_raw.ll +++ b/intrinsics/probes/tcgen05_st_16x64b_x4_raw.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_st_16x64b_x4_unpack16.ll b/intrinsics/probes/tcgen05_st_16x64b_x4_unpack16.ll index d11f3dac43..870e66fe43 100644 --- a/intrinsics/probes/tcgen05_st_16x64b_x4_unpack16.ll +++ b/intrinsics/probes/tcgen05_st_16x64b_x4_unpack16.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_st_16x64b_x64_raw.ll b/intrinsics/probes/tcgen05_st_16x64b_x64_raw.ll index 2880e82a9b..d27c713e9a 100644 --- a/intrinsics/probes/tcgen05_st_16x64b_x64_raw.ll +++ b/intrinsics/probes/tcgen05_st_16x64b_x64_raw.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_st_16x64b_x64_unpack16.ll b/intrinsics/probes/tcgen05_st_16x64b_x64_unpack16.ll index d995c21393..a1ff35a666 100644 --- a/intrinsics/probes/tcgen05_st_16x64b_x64_unpack16.ll +++ b/intrinsics/probes/tcgen05_st_16x64b_x64_unpack16.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_st_16x64b_x8_raw.ll b/intrinsics/probes/tcgen05_st_16x64b_x8_raw.ll index d6e2d4f57a..21d122e9ad 100644 --- a/intrinsics/probes/tcgen05_st_16x64b_x8_raw.ll +++ b/intrinsics/probes/tcgen05_st_16x64b_x8_raw.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_st_16x64b_x8_unpack16.ll b/intrinsics/probes/tcgen05_st_16x64b_x8_unpack16.ll index 79799630c7..52d5c71dc6 100644 --- a/intrinsics/probes/tcgen05_st_16x64b_x8_unpack16.ll +++ b/intrinsics/probes/tcgen05_st_16x64b_x8_unpack16.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_st_32x32b_x128_raw.ll b/intrinsics/probes/tcgen05_st_32x32b_x128_raw.ll index f51e646153..baf545e3ac 100644 --- a/intrinsics/probes/tcgen05_st_32x32b_x128_raw.ll +++ b/intrinsics/probes/tcgen05_st_32x32b_x128_raw.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_st_32x32b_x128_unpack16.ll b/intrinsics/probes/tcgen05_st_32x32b_x128_unpack16.ll index 80f421a66f..e19e601cef 100644 --- a/intrinsics/probes/tcgen05_st_32x32b_x128_unpack16.ll +++ b/intrinsics/probes/tcgen05_st_32x32b_x128_unpack16.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_st_32x32b_x16_raw.ll b/intrinsics/probes/tcgen05_st_32x32b_x16_raw.ll index e2828ab2ce..e7e542e860 100644 --- a/intrinsics/probes/tcgen05_st_32x32b_x16_raw.ll +++ b/intrinsics/probes/tcgen05_st_32x32b_x16_raw.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_st_32x32b_x16_unpack16.ll b/intrinsics/probes/tcgen05_st_32x32b_x16_unpack16.ll index 74198d8eb0..35e474bc3e 100644 --- a/intrinsics/probes/tcgen05_st_32x32b_x16_unpack16.ll +++ b/intrinsics/probes/tcgen05_st_32x32b_x16_unpack16.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_st_32x32b_x1_raw.ll b/intrinsics/probes/tcgen05_st_32x32b_x1_raw.ll index 4590dd7b1a..15125e1904 100644 --- a/intrinsics/probes/tcgen05_st_32x32b_x1_raw.ll +++ b/intrinsics/probes/tcgen05_st_32x32b_x1_raw.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_st_32x32b_x1_unpack16.ll b/intrinsics/probes/tcgen05_st_32x32b_x1_unpack16.ll index 8f0fcdb2ac..e4bf5d9b1f 100644 --- a/intrinsics/probes/tcgen05_st_32x32b_x1_unpack16.ll +++ b/intrinsics/probes/tcgen05_st_32x32b_x1_unpack16.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_st_32x32b_x2_raw.ll b/intrinsics/probes/tcgen05_st_32x32b_x2_raw.ll index eac341a416..e334d4a363 100644 --- a/intrinsics/probes/tcgen05_st_32x32b_x2_raw.ll +++ b/intrinsics/probes/tcgen05_st_32x32b_x2_raw.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_st_32x32b_x2_unpack16.ll b/intrinsics/probes/tcgen05_st_32x32b_x2_unpack16.ll index a68352dc3c..f1c0ca603a 100644 --- a/intrinsics/probes/tcgen05_st_32x32b_x2_unpack16.ll +++ b/intrinsics/probes/tcgen05_st_32x32b_x2_unpack16.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_st_32x32b_x32_raw.ll b/intrinsics/probes/tcgen05_st_32x32b_x32_raw.ll index 020c9e3d6a..0185455ee3 100644 --- a/intrinsics/probes/tcgen05_st_32x32b_x32_raw.ll +++ b/intrinsics/probes/tcgen05_st_32x32b_x32_raw.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_st_32x32b_x32_unpack16.ll b/intrinsics/probes/tcgen05_st_32x32b_x32_unpack16.ll index a1cb9e3969..554c65e028 100644 --- a/intrinsics/probes/tcgen05_st_32x32b_x32_unpack16.ll +++ b/intrinsics/probes/tcgen05_st_32x32b_x32_unpack16.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_st_32x32b_x4_raw.ll b/intrinsics/probes/tcgen05_st_32x32b_x4_raw.ll index 7923e2231f..faf191d511 100644 --- a/intrinsics/probes/tcgen05_st_32x32b_x4_raw.ll +++ b/intrinsics/probes/tcgen05_st_32x32b_x4_raw.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_st_32x32b_x4_unpack16.ll b/intrinsics/probes/tcgen05_st_32x32b_x4_unpack16.ll index 5eac0152d0..c7194b4c5e 100644 --- a/intrinsics/probes/tcgen05_st_32x32b_x4_unpack16.ll +++ b/intrinsics/probes/tcgen05_st_32x32b_x4_unpack16.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_st_32x32b_x64_raw.ll b/intrinsics/probes/tcgen05_st_32x32b_x64_raw.ll index 28242d9f4a..60ceacfc5e 100644 --- a/intrinsics/probes/tcgen05_st_32x32b_x64_raw.ll +++ b/intrinsics/probes/tcgen05_st_32x32b_x64_raw.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_st_32x32b_x64_unpack16.ll b/intrinsics/probes/tcgen05_st_32x32b_x64_unpack16.ll index b836bcdf8e..a5fbe7cf83 100644 --- a/intrinsics/probes/tcgen05_st_32x32b_x64_unpack16.ll +++ b/intrinsics/probes/tcgen05_st_32x32b_x64_unpack16.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_st_32x32b_x8_raw.ll b/intrinsics/probes/tcgen05_st_32x32b_x8_raw.ll index 4d7b9f45f3..9ca1fa0790 100644 --- a/intrinsics/probes/tcgen05_st_32x32b_x8_raw.ll +++ b/intrinsics/probes/tcgen05_st_32x32b_x8_raw.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_st_32x32b_x8_unpack16.ll b/intrinsics/probes/tcgen05_st_32x32b_x8_unpack16.ll index b7233c3a06..a26c97609e 100644 --- a/intrinsics/probes/tcgen05_st_32x32b_x8_unpack16.ll +++ b/intrinsics/probes/tcgen05_st_32x32b_x8_unpack16.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_store_wait.ll b/intrinsics/probes/tcgen05_store_wait.ll index 835e16e519..e4f6e41160 100644 --- a/intrinsics/probes/tcgen05_store_wait.ll +++ b/intrinsics/probes/tcgen05_store_wait.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tensormap_replace_box_dim.ll b/intrinsics/probes/tensormap_replace_box_dim.ll index 8c57de35d9..f158f2f0dc 100644 --- a/intrinsics/probes/tensormap_replace_box_dim.ll +++ b/intrinsics/probes/tensormap_replace_box_dim.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tensormap_replace_element_stride.ll b/intrinsics/probes/tensormap_replace_element_stride.ll index 85f70a09d8..c23269a103 100644 --- a/intrinsics/probes/tensormap_replace_element_stride.ll +++ b/intrinsics/probes/tensormap_replace_element_stride.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tensormap_replace_element_type.ll b/intrinsics/probes/tensormap_replace_element_type.ll index c8c33636c6..8688bfce09 100644 --- a/intrinsics/probes/tensormap_replace_element_type.ll +++ b/intrinsics/probes/tensormap_replace_element_type.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tensormap_replace_fill_mode.ll b/intrinsics/probes/tensormap_replace_fill_mode.ll index e33585c4a7..8a897ccef0 100644 --- a/intrinsics/probes/tensormap_replace_fill_mode.ll +++ b/intrinsics/probes/tensormap_replace_fill_mode.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tensormap_replace_global_address.ll b/intrinsics/probes/tensormap_replace_global_address.ll index 999fa6c959..0a0e3f1235 100644 --- a/intrinsics/probes/tensormap_replace_global_address.ll +++ b/intrinsics/probes/tensormap_replace_global_address.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tensormap_replace_global_dim.ll b/intrinsics/probes/tensormap_replace_global_dim.ll index b13d3f1a89..6f6644854b 100644 --- a/intrinsics/probes/tensormap_replace_global_dim.ll +++ b/intrinsics/probes/tensormap_replace_global_dim.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tensormap_replace_global_stride.ll b/intrinsics/probes/tensormap_replace_global_stride.ll index 7b8c2225ae..3474d9f7bd 100644 --- a/intrinsics/probes/tensormap_replace_global_stride.ll +++ b/intrinsics/probes/tensormap_replace_global_stride.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tensormap_replace_interleave_layout.ll b/intrinsics/probes/tensormap_replace_interleave_layout.ll index 199d3ca55b..a6dd5deb39 100644 --- a/intrinsics/probes/tensormap_replace_interleave_layout.ll +++ b/intrinsics/probes/tensormap_replace_interleave_layout.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tensormap_replace_rank.ll b/intrinsics/probes/tensormap_replace_rank.ll index c1f54b8585..736ee9408c 100644 --- a/intrinsics/probes/tensormap_replace_rank.ll +++ b/intrinsics/probes/tensormap_replace_rank.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tensormap_replace_swizzle_atomicity.ll b/intrinsics/probes/tensormap_replace_swizzle_atomicity.ll index b93f90d76a..cd7602266b 100644 --- a/intrinsics/probes/tensormap_replace_swizzle_atomicity.ll +++ b/intrinsics/probes/tensormap_replace_swizzle_atomicity.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tensormap_replace_swizzle_mode.ll b/intrinsics/probes/tensormap_replace_swizzle_mode.ll index fc1a6678ec..8ad823cfc9 100644 --- a/intrinsics/probes/tensormap_replace_swizzle_mode.ll +++ b/intrinsics/probes/tensormap_replace_swizzle_mode.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/thread_idx_x.ll b/intrinsics/probes/thread_idx_x.ll index 2d79f19671..9d1fb23a13 100644 --- a/intrinsics/probes/thread_idx_x.ll +++ b/intrinsics/probes/thread_idx_x.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/thread_idx_y.ll b/intrinsics/probes/thread_idx_y.ll index 3d2cbd2e6c..7ef1181d6d 100644 --- a/intrinsics/probes/thread_idx_y.ll +++ b/intrinsics/probes/thread_idx_y.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/thread_idx_z.ll b/intrinsics/probes/thread_idx_z.ll index e617e3900e..e99cfe1b50 100644 --- a/intrinsics/probes/thread_idx_z.ll +++ b/intrinsics/probes/thread_idx_z.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/threadfence.ll b/intrinsics/probes/threadfence.ll index 6abe80a335..3c3013e01c 100644 --- a/intrinsics/probes/threadfence.ll +++ b/intrinsics/probes/threadfence.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/threadfence_block.ll b/intrinsics/probes/threadfence_block.ll index 14e9e1225c..fa3b74ba12 100644 --- a/intrinsics/probes/threadfence_block.ll +++ b/intrinsics/probes/threadfence_block.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/threadfence_system.ll b/intrinsics/probes/threadfence_system.ll index 17e5970536..b5ad50576a 100644 --- a/intrinsics/probes/threadfence_system.ll +++ b/intrinsics/probes/threadfence_system.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/total_smem_size.lib_nvvm.ll b/intrinsics/probes/total_smem_size.lib_nvvm.ll index 32820a2aab..64b9ae4fe3 100644 --- a/intrinsics/probes/total_smem_size.lib_nvvm.ll +++ b/intrinsics/probes/total_smem_size.lib_nvvm.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/total_smem_size.llvm_nvptx.ll b/intrinsics/probes/total_smem_size.llvm_nvptx.ll index 05cf326e1e..4fab0040a5 100644 --- a/intrinsics/probes/total_smem_size.llvm_nvptx.ll +++ b/intrinsics/probes/total_smem_size.llvm_nvptx.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/trap.ll b/intrinsics/probes/trap.ll index f55df22f02..7bdf46cab1 100644 --- a/intrinsics/probes/trap.ll +++ b/intrinsics/probes/trap.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/uni_sync.ll b/intrinsics/probes/uni_sync.ll index 342b057ab4..bf9dc187ca 100644 --- a/intrinsics/probes/uni_sync.ll +++ b/intrinsics/probes/uni_sync.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/warpid.lib_nvvm.ll b/intrinsics/probes/warpid.lib_nvvm.ll index d640a6c7df..a27e213b33 100644 --- a/intrinsics/probes/warpid.lib_nvvm.ll +++ b/intrinsics/probes/warpid.lib_nvvm.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/warpid.llvm_nvptx.ll b/intrinsics/probes/warpid.llvm_nvptx.ll index f11b20f9d1..1f4a68de2e 100644 --- a/intrinsics/probes/warpid.llvm_nvptx.ll +++ b/intrinsics/probes/warpid.llvm_nvptx.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/wgmma_commit_group.ll b/intrinsics/probes/wgmma_commit_group.ll index bc8994c180..fcfb524f34 100644 --- a/intrinsics/probes/wgmma_commit_group.ll +++ b/intrinsics/probes/wgmma_commit_group.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/wgmma_fence.ll b/intrinsics/probes/wgmma_fence.ll index 941254c595..8b4d9ae36b 100644 --- a/intrinsics/probes/wgmma_fence.ll +++ b/intrinsics/probes/wgmma_fence.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/wgmma_wait_group.ll b/intrinsics/probes/wgmma_wait_group.ll index 9e3ca05480..9245042ff8 100644 --- a/intrinsics/probes/wgmma_wait_group.ll +++ b/intrinsics/probes/wgmma_wait_group.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 02a6a6b3415ab7468c40db4cf5becc52a6c53da5ef7d944933e9cfa5858b4397. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 20bc41c2ab93828b7f97b6ee90efccfc118317a590803216a3a045b1c2879889. ; LLVM source: 16696adcd119e6ba9cc175207d984d7021211acb. target triple = "nvptx64-nvidia-cuda"