From 5465e198bd8f9cebb44c5f77a99d4fbea41f6b79 Mon Sep 17 00:00:00 2001 From: "Sam, Joochul Chang" Date: Sat, 22 Aug 2026 18:42:49 +0900 Subject: [PATCH 1/3] feat(intrinsics): add CTA barrier reductions Signed-off-by: Sam, Joochul Chang --- crates/cuda-device/src/barrier.rs | 1 + .../cuda-device/src/generated/async_copy.rs | 2 +- crates/cuda-device/src/generated/atomic.rs | 2 +- .../src/generated/barrier_reduction.rs | 160 + crates/cuda-device/src/generated/bf16.rs | 2 +- crates/cuda-device/src/generated/bf16x2.rs | 2 +- crates/cuda-device/src/generated/clc.rs | 2 +- .../src/generated/cluster_barrier.rs | 2 +- .../src/generated/cluster_memory.rs | 2 +- .../cuda-device/src/generated/cluster_sreg.rs | 2 +- crates/cuda-device/src/generated/convert.rs | 2 +- .../src/generated/counted_barrier.rs | 20 +- .../src/generated/debug_control.rs | 2 +- .../cuda-device/src/generated/debug_sreg.rs | 2 +- crates/cuda-device/src/generated/dotprod.rs | 2 +- crates/cuda-device/src/generated/f16.rs | 2 +- crates/cuda-device/src/generated/f16x2.rs | 2 +- crates/cuda-device/src/generated/f32x2.rs | 2 +- crates/cuda-device/src/generated/fence.rs | 2 +- crates/cuda-device/src/generated/float.rs | 2 +- .../src/generated/grid_dependency.rs | 2 +- crates/cuda-device/src/generated/grid_sreg.rs | 2 +- crates/cuda-device/src/generated/i16x2.rs | 2 +- crates/cuda-device/src/generated/int.rs | 2 +- crates/cuda-device/src/generated/ldmatrix.rs | 2 +- .../src/generated/mbarrier_basic.rs | 2 +- .../src/generated/mbarrier_extended.rs | 2 +- crates/cuda-device/src/generated/movmatrix.rs | 2 +- crates/cuda-device/src/generated/prmt.rs | 2 +- .../src/generated/register_control.rs | 2 +- .../cuda-device/src/generated/register_mma.rs | 2 +- .../cuda-device/src/generated/shared_sreg.rs | 2 +- .../cuda-device/src/generated/sparse_mma.rs | 2 +- crates/cuda-device/src/generated/sreg.rs | 2 +- crates/cuda-device/src/generated/stmatrix.rs | 2 +- crates/cuda-device/src/generated/tcgen05.rs | 2 +- crates/cuda-device/src/generated/tma.rs | 2 +- crates/cuda-device/src/generated/warp_sreg.rs | 2 +- .../src/generated/wgmma_control.rs | 2 +- crates/cuda-intrinsics-gen/src/model.rs | 4 + crates/cuda-intrinsics-gen/src/probe.rs | 13 +- crates/cuda-intrinsics-gen/src/render.rs | 288 +- crates/cuda-intrinsics-gen/src/resolve.rs | 172 +- .../cuda-intrinsics/src/generated/abi_v1.rs | 220 +- crates/cuda-intrinsics/src/generated/mod.rs | 102 +- .../src/generated_intrinsic_targets.rs | 1766 ++++++++++- .../src/ops/generated/active_mask.rs | 2 +- .../src/ops/generated/barrier_reduction.rs | 213 ++ crates/dialect-nvvm/src/ops/generated/clc.rs | 2 +- .../src/ops/generated/cluster_barrier.rs | 2 +- .../src/ops/generated/cluster_memory.rs | 2 +- .../src/ops/generated/cp_async.rs | 2 +- .../src/ops/generated/debug_control.rs | 2 +- .../dialect-nvvm/src/ops/generated/dotprod.rs | 2 +- .../dialect-nvvm/src/ops/generated/elect.rs | 2 +- .../src/ops/generated/execution_control.rs | 18 +- .../src/ops/generated/extended_minmax.rs | 2 +- .../src/ops/generated/integer_minmax.rs | 2 +- .../src/ops/generated/ldmatrix.rs | 2 +- .../src/ops/generated/mbarrier_basic.rs | 2 +- .../src/ops/generated/mbarrier_extended.rs | 2 +- crates/dialect-nvvm/src/ops/generated/mod.rs | 5 +- .../src/ops/generated/movmatrix.rs | 2 +- .../src/ops/generated/packed_alu.rs | 2 +- .../src/ops/generated/packed_atomic.rs | 2 +- .../src/ops/generated/packed_conversion.rs | 2 +- crates/dialect-nvvm/src/ops/generated/prmt.rs | 2 +- .../dialect-nvvm/src/ops/generated/redux.rs | 2 +- .../src/ops/generated/register_mma.rs | 2 +- .../src/ops/generated/scalar_arithmetic.rs | 2 +- .../src/ops/generated/scalar_conversion.rs | 2 +- .../src/ops/generated/scalar_math.rs | 2 +- .../src/ops/generated/sparse_mma.rs | 2 +- crates/dialect-nvvm/src/ops/generated/sreg.rs | 2 +- .../src/ops/generated/stmatrix.rs | 2 +- crates/dialect-nvvm/src/ops/generated/sync.rs | 2 +- .../dialect-nvvm/src/ops/generated/tcgen05.rs | 2 +- crates/dialect-nvvm/src/ops/generated/tma.rs | 2 +- crates/dialect-nvvm/src/ops/generated/vote.rs | 2 +- .../src/ops/generated/warp_barrier.rs | 2 +- .../src/ops/generated/warp_match.rs | 2 +- .../src/ops/generated/warp_shuffle.rs | 2 +- .../src/ops/generated/wgmma_control.rs | 2 +- .../terminator/intrinsics/generated.rs | 1171 ++++++- .../src/convert/generated_intrinsics.rs | 285 +- .../convert/intrinsics/barrier_reduction.rs | 124 + .../convert/intrinsics/execution_control.rs | 6 +- .../mir-lower/src/convert/intrinsics/mod.rs | 2 + crates/mir-lower/tests/lowering_test.rs | 295 ++ .../src/generated_intrinsics.rs | 54 +- intrinsics/abi-v1.toml | 91 + intrinsics/catalog.json | 2707 ++++++++++++++++- ...2.9-libnvvm-12.9.86-barrier-reduction.json | 649 ++++ ...2.9-libnvvm-12.9.86-execution-control.json | 51 + ...lvm-22.1.2-1cb4e383-barrier-reduction.json | 724 +++++ ...lvm-22.1.2-1cb4e383-execution-control.json | 30 + intrinsics/generated-reference.md | 145 +- intrinsics/overlay.toml | 3 +- intrinsics/overlay/barrier_reduction.toml | 478 +++ intrinsics/overlay/counted_barrier.toml | 42 +- intrinsics/probes/abs_bf16x2.ll | 2 +- intrinsics/probes/abs_f16x2.ll | 2 +- intrinsics/probes/active_mask.ll | 2 +- intrinsics/probes/add_bf16x2.ll | 2 +- intrinsics/probes/add_f16x2.ll | 2 +- intrinsics/probes/add_f32x2.ll | 2 +- intrinsics/probes/add_ftz_f32x2.ll | 2 +- intrinsics/probes/add_rm_f32.ll | 2 +- intrinsics/probes/add_rm_f64.ll | 2 +- intrinsics/probes/add_rm_ftz_f32.ll | 2 +- intrinsics/probes/add_rm_ftz_sat_f32.ll | 2 +- intrinsics/probes/add_rm_sat_f32.ll | 2 +- intrinsics/probes/add_rn_f32.ll | 2 +- intrinsics/probes/add_rn_f64.ll | 2 +- intrinsics/probes/add_rn_ftz_f32.ll | 2 +- intrinsics/probes/add_rn_ftz_sat_f32.ll | 2 +- intrinsics/probes/add_rn_sat_f32.ll | 2 +- intrinsics/probes/add_rp_f32.ll | 2 +- intrinsics/probes/add_rp_f64.ll | 2 +- intrinsics/probes/add_rp_ftz_f32.ll | 2 +- intrinsics/probes/add_rp_ftz_sat_f32.ll | 2 +- intrinsics/probes/add_rp_sat_f32.ll | 2 +- intrinsics/probes/add_rz_f32.ll | 2 +- intrinsics/probes/add_rz_f64.ll | 2 +- intrinsics/probes/add_rz_ftz_f32.ll | 2 +- intrinsics/probes/add_rz_ftz_sat_f32.ll | 2 +- intrinsics/probes/add_rz_sat_f32.ll | 2 +- intrinsics/probes/all_sync.ll | 2 +- intrinsics/probes/any_sync.ll | 2 +- intrinsics/probes/ballot_sync.ll | 2 +- intrinsics/probes/barrier_cluster_arrive.ll | 2 +- .../probes/barrier_cluster_arrive_aligned.ll | 2 +- .../probes/barrier_cluster_arrive_relaxed.ll | 2 +- .../barrier_cluster_arrive_relaxed_aligned.ll | 2 +- intrinsics/probes/barrier_cluster_wait.ll | 2 +- .../probes/barrier_cluster_wait_aligned.ll | 2 +- intrinsics/probes/barrier_cta_arrive.ll | 2 +- .../probes/barrier_cta_arrive_aligned.ll | 2 +- .../probes/barrier_cta_red_and_aligned_all.ll | 21 + .../barrier_cta_red_and_aligned_count.ll | 31 + intrinsics/probes/barrier_cta_red_and_all.ll | 21 + .../probes/barrier_cta_red_and_count.ll | 31 + .../probes/barrier_cta_red_or_aligned_all.ll | 21 + .../barrier_cta_red_or_aligned_count.ll | 31 + intrinsics/probes/barrier_cta_red_or_all.ll | 21 + intrinsics/probes/barrier_cta_red_or_count.ll | 31 + .../barrier_cta_red_popc_aligned_all.ll | 21 + .../barrier_cta_red_popc_aligned_count.ll | 31 + intrinsics/probes/barrier_cta_red_popc_all.ll | 21 + .../probes/barrier_cta_red_popc_count.ll | 31 + intrinsics/probes/barrier_cta_sync.ll | 2 +- intrinsics/probes/barrier_cta_sync_aligned.ll | 2 +- intrinsics/probes/barrier_cta_sync_all.ll | 21 + intrinsics/probes/block_dim_x.ll | 2 +- intrinsics/probes/block_dim_y.ll | 2 +- intrinsics/probes/block_dim_z.ll | 2 +- intrinsics/probes/block_idx_x.ll | 2 +- intrinsics/probes/block_idx_y.ll | 2 +- intrinsics/probes/block_idx_z.ll | 2 +- intrinsics/probes/breakpoint.ll | 2 +- .../probes/clc_query_get_first_ctaid_x.ll | 2 +- .../probes/clc_query_get_first_ctaid_y.ll | 2 +- .../probes/clc_query_get_first_ctaid_z.ll | 2 +- intrinsics/probes/clc_query_is_canceled.ll | 2 +- intrinsics/probes/clc_try_cancel.ll | 2 +- intrinsics/probes/clc_try_cancel_multicast.ll | 2 +- intrinsics/probes/clock.lib_nvvm.ll | 2 +- intrinsics/probes/clock.llvm_nvptx.ll | 2 +- intrinsics/probes/clock64.lib_nvvm.ll | 2 +- intrinsics/probes/clock64.llvm_nvptx.ll | 2 +- intrinsics/probes/cluster_block_count.ll | 2 +- intrinsics/probes/cluster_block_idx_x.ll | 2 +- intrinsics/probes/cluster_block_idx_y.ll | 2 +- intrinsics/probes/cluster_block_idx_z.ll | 2 +- intrinsics/probes/cluster_block_rank.ll | 2 +- intrinsics/probes/cluster_dim_x.ll | 2 +- intrinsics/probes/cluster_dim_y.ll | 2 +- intrinsics/probes/cluster_dim_z.ll | 2 +- intrinsics/probes/cluster_grid_dim_x.ll | 2 +- intrinsics/probes/cluster_grid_dim_y.ll | 2 +- intrinsics/probes/cluster_grid_dim_z.ll | 2 +- intrinsics/probes/cluster_idx_x.ll | 2 +- intrinsics/probes/cluster_idx_y.ll | 2 +- intrinsics/probes/cluster_idx_z.ll | 2 +- intrinsics/probes/cos_approx_f32.ll | 2 +- intrinsics/probes/cos_approx_ftz_f32.ll | 2 +- .../probes/cp_async_bulk_commit_group.ll | 2 +- .../cp_async_bulk_prefetch_tensor_1d_l2.ll | 2 +- ...c_bulk_prefetch_tensor_1d_l2_cache_hint.ll | 2 +- .../cp_async_bulk_prefetch_tensor_2d_l2.ll | 2 +- ...c_bulk_prefetch_tensor_2d_l2_cache_hint.ll | 2 +- .../cp_async_bulk_prefetch_tensor_3d_l2.ll | 2 +- ...c_bulk_prefetch_tensor_3d_l2_cache_hint.ll | 2 +- .../cp_async_bulk_prefetch_tensor_4d_l2.ll | 2 +- ...c_bulk_prefetch_tensor_4d_l2_cache_hint.ll | 2 +- .../cp_async_bulk_prefetch_tensor_5d_l2.ll | 2 +- ...c_bulk_prefetch_tensor_5d_l2_cache_hint.ll | 2 +- ...sync_bulk_prefetch_tensor_gather4_2d_l2.ll | 2 +- ...refetch_tensor_gather4_2d_l2_cache_hint.ll | 2 +- .../probes/cp_async_bulk_tensor_1d_g2s.ll | 2 +- .../probes/cp_async_bulk_tensor_1d_s2g.ll | 2 +- .../probes/cp_async_bulk_tensor_2d_g2s.ll | 2 +- .../cp_async_bulk_tensor_2d_g2s_multicast.ll | 2 +- ..._async_bulk_tensor_2d_g2s_multicast_cg2.ll | 2 +- .../probes/cp_async_bulk_tensor_2d_s2g.ll | 2 +- .../probes/cp_async_bulk_tensor_3d_g2s.ll | 2 +- .../probes/cp_async_bulk_tensor_3d_s2g.ll | 2 +- .../probes/cp_async_bulk_tensor_4d_g2s.ll | 2 +- .../probes/cp_async_bulk_tensor_4d_s2g.ll | 2 +- .../probes/cp_async_bulk_tensor_5d_g2s.ll | 2 +- .../probes/cp_async_bulk_tensor_5d_s2g.ll | 2 +- ..._async_bulk_tensor_reduce_add_im2col_3d.ll | 2 +- ..._async_bulk_tensor_reduce_add_im2col_4d.ll | 2 +- ..._async_bulk_tensor_reduce_add_im2col_5d.ll | 2 +- ...cp_async_bulk_tensor_reduce_add_tile_1d.ll | 2 +- ...cp_async_bulk_tensor_reduce_add_tile_2d.ll | 2 +- ...cp_async_bulk_tensor_reduce_add_tile_3d.ll | 2 +- ...cp_async_bulk_tensor_reduce_add_tile_4d.ll | 2 +- ...cp_async_bulk_tensor_reduce_add_tile_5d.ll | 2 +- ..._async_bulk_tensor_reduce_and_im2col_3d.ll | 2 +- ..._async_bulk_tensor_reduce_and_im2col_4d.ll | 2 +- ..._async_bulk_tensor_reduce_and_im2col_5d.ll | 2 +- ...cp_async_bulk_tensor_reduce_and_tile_1d.ll | 2 +- ...cp_async_bulk_tensor_reduce_and_tile_2d.ll | 2 +- ...cp_async_bulk_tensor_reduce_and_tile_3d.ll | 2 +- ...cp_async_bulk_tensor_reduce_and_tile_4d.ll | 2 +- ...cp_async_bulk_tensor_reduce_and_tile_5d.ll | 2 +- ..._async_bulk_tensor_reduce_dec_im2col_3d.ll | 2 +- ..._async_bulk_tensor_reduce_dec_im2col_4d.ll | 2 +- ..._async_bulk_tensor_reduce_dec_im2col_5d.ll | 2 +- ...cp_async_bulk_tensor_reduce_dec_tile_1d.ll | 2 +- ...cp_async_bulk_tensor_reduce_dec_tile_2d.ll | 2 +- ...cp_async_bulk_tensor_reduce_dec_tile_3d.ll | 2 +- ...cp_async_bulk_tensor_reduce_dec_tile_4d.ll | 2 +- ...cp_async_bulk_tensor_reduce_dec_tile_5d.ll | 2 +- ..._async_bulk_tensor_reduce_inc_im2col_3d.ll | 2 +- ..._async_bulk_tensor_reduce_inc_im2col_4d.ll | 2 +- ..._async_bulk_tensor_reduce_inc_im2col_5d.ll | 2 +- ...cp_async_bulk_tensor_reduce_inc_tile_1d.ll | 2 +- ...cp_async_bulk_tensor_reduce_inc_tile_2d.ll | 2 +- ...cp_async_bulk_tensor_reduce_inc_tile_3d.ll | 2 +- ...cp_async_bulk_tensor_reduce_inc_tile_4d.ll | 2 +- ...cp_async_bulk_tensor_reduce_inc_tile_5d.ll | 2 +- ..._async_bulk_tensor_reduce_max_im2col_3d.ll | 2 +- ..._async_bulk_tensor_reduce_max_im2col_4d.ll | 2 +- ..._async_bulk_tensor_reduce_max_im2col_5d.ll | 2 +- ...cp_async_bulk_tensor_reduce_max_tile_1d.ll | 2 +- ...cp_async_bulk_tensor_reduce_max_tile_2d.ll | 2 +- ...cp_async_bulk_tensor_reduce_max_tile_3d.ll | 2 +- ...cp_async_bulk_tensor_reduce_max_tile_4d.ll | 2 +- ...cp_async_bulk_tensor_reduce_max_tile_5d.ll | 2 +- ..._async_bulk_tensor_reduce_min_im2col_3d.ll | 2 +- ..._async_bulk_tensor_reduce_min_im2col_4d.ll | 2 +- ..._async_bulk_tensor_reduce_min_im2col_5d.ll | 2 +- ...cp_async_bulk_tensor_reduce_min_tile_1d.ll | 2 +- ...cp_async_bulk_tensor_reduce_min_tile_2d.ll | 2 +- ...cp_async_bulk_tensor_reduce_min_tile_3d.ll | 2 +- ...cp_async_bulk_tensor_reduce_min_tile_4d.ll | 2 +- ...cp_async_bulk_tensor_reduce_min_tile_5d.ll | 2 +- ...p_async_bulk_tensor_reduce_or_im2col_3d.ll | 2 +- ...p_async_bulk_tensor_reduce_or_im2col_4d.ll | 2 +- ...p_async_bulk_tensor_reduce_or_im2col_5d.ll | 2 +- .../cp_async_bulk_tensor_reduce_or_tile_1d.ll | 2 +- .../cp_async_bulk_tensor_reduce_or_tile_2d.ll | 2 +- .../cp_async_bulk_tensor_reduce_or_tile_3d.ll | 2 +- .../cp_async_bulk_tensor_reduce_or_tile_4d.ll | 2 +- .../cp_async_bulk_tensor_reduce_or_tile_5d.ll | 2 +- ..._async_bulk_tensor_reduce_xor_im2col_3d.ll | 2 +- ..._async_bulk_tensor_reduce_xor_im2col_4d.ll | 2 +- ..._async_bulk_tensor_reduce_xor_im2col_5d.ll | 2 +- ...cp_async_bulk_tensor_reduce_xor_tile_1d.ll | 2 +- ...cp_async_bulk_tensor_reduce_xor_tile_2d.ll | 2 +- ...cp_async_bulk_tensor_reduce_xor_tile_3d.ll | 2 +- ...cp_async_bulk_tensor_reduce_xor_tile_4d.ll | 2 +- ...cp_async_bulk_tensor_reduce_xor_tile_5d.ll | 2 +- intrinsics/probes/cp_async_bulk_wait_group.ll | 2 +- .../probes/cp_async_bulk_wait_group_read.ll | 2 +- intrinsics/probes/cp_async_ca_16.ll | 2 +- intrinsics/probes/cp_async_ca_4.ll | 2 +- intrinsics/probes/cp_async_ca_8.ll | 2 +- intrinsics/probes/cp_async_ca_zfill_16.ll | 2 +- intrinsics/probes/cp_async_ca_zfill_4.ll | 2 +- intrinsics/probes/cp_async_ca_zfill_8.ll | 2 +- intrinsics/probes/cp_async_cg_16.ll | 2 +- intrinsics/probes/cp_async_cg_zfill_16.ll | 2 +- intrinsics/probes/cp_async_commit_group.ll | 2 +- intrinsics/probes/cp_async_mbarrier_arrive.ll | 2 +- .../probes/cp_async_mbarrier_arrive_noinc.ll | 2 +- .../cp_async_mbarrier_arrive_noinc_shared.ll | 2 +- .../probes/cp_async_mbarrier_arrive_shared.ll | 2 +- intrinsics/probes/cp_async_wait_all.ll | 2 +- intrinsics/probes/cp_async_wait_group.ll | 2 +- intrinsics/probes/cvt_f16x2_f32.ll | 2 +- intrinsics/probes/cvt_f32x2_bf16x2.ll | 2 +- intrinsics/probes/cvt_rn_f16x2_e4m3x2.ll | 2 +- intrinsics/probes/cvt_rn_f16x2_e5m2x2.ll | 2 +- intrinsics/probes/cvt_rn_relu_bf16x2_f32.ll | 2 +- intrinsics/probes/cvt_rn_relu_f16x2_e4m3x2.ll | 2 +- intrinsics/probes/cvt_rn_relu_f16x2_e5m2x2.ll | 2 +- intrinsics/probes/cvt_rn_relu_f16x2_f32.ll | 2 +- .../probes/cvt_rn_relu_satfinite_tf32_f32.ll | 2 +- intrinsics/probes/cvt_rn_relu_tf32_f32.ll | 2 +- .../probes/cvt_rn_satfinite_e4m3x2_f16x2.ll | 2 +- .../probes/cvt_rn_satfinite_e4m3x2_f32.ll | 2 +- .../probes/cvt_rn_satfinite_e5m2x2_f16x2.ll | 2 +- .../probes/cvt_rn_satfinite_e5m2x2_f32.ll | 2 +- .../cvt_rn_satfinite_relu_e4m3x2_f16x2.ll | 2 +- .../cvt_rn_satfinite_relu_e4m3x2_f32.ll | 2 +- .../cvt_rn_satfinite_relu_e5m2x2_f16x2.ll | 2 +- .../cvt_rn_satfinite_relu_e5m2x2_f32.ll | 2 +- .../probes/cvt_rn_satfinite_tf32_f32.ll | 2 +- intrinsics/probes/cvt_rn_tf32_f32.ll | 2 +- .../probes/cvt_rna_satfinite_tf32_f32.ll | 2 +- intrinsics/probes/cvt_rna_tf32_f32.ll | 2 +- intrinsics/probes/cvt_rz_bf16x2_f32.ll | 2 +- intrinsics/probes/cvt_rz_f16x2_f32.ll | 2 +- .../probes/cvt_rz_relu_satfinite_tf32_f32.ll | 2 +- intrinsics/probes/cvt_rz_relu_tf32_f32.ll | 2 +- .../probes/cvt_rz_satfinite_tf32_f32.ll | 2 +- intrinsics/probes/cvt_rz_tf32_f32.ll | 2 +- intrinsics/probes/div_rm_f32.ll | 2 +- intrinsics/probes/div_rm_f64.ll | 2 +- intrinsics/probes/div_rm_ftz_f32.ll | 2 +- intrinsics/probes/div_rn_f32.ll | 2 +- intrinsics/probes/div_rn_f64.ll | 2 +- intrinsics/probes/div_rn_ftz_f32.ll | 2 +- intrinsics/probes/div_rp_f32.ll | 2 +- intrinsics/probes/div_rp_f64.ll | 2 +- intrinsics/probes/div_rp_ftz_f32.ll | 2 +- intrinsics/probes/div_rz_f32.ll | 2 +- intrinsics/probes/div_rz_f64.ll | 2 +- intrinsics/probes/div_rz_ftz_f32.ll | 2 +- intrinsics/probes/dp2a_s32.ll | 2 +- intrinsics/probes/dp2a_u32.ll | 2 +- intrinsics/probes/dp4a_s32.ll | 2 +- intrinsics/probes/dp4a_u32.ll | 2 +- intrinsics/probes/dsmem_read_u32.ll | 2 +- .../probes/dynamic_smem_size.lib_nvvm.ll | 2 +- .../probes/dynamic_smem_size.llvm_nvptx.ll | 2 +- intrinsics/probes/elect_sync.lib_nvvm.ll | 2 +- intrinsics/probes/elect_sync.llvm_nvptx.ll | 2 +- intrinsics/probes/envreg1.lib_nvvm.ll | 2 +- intrinsics/probes/envreg1.llvm_nvptx.ll | 2 +- intrinsics/probes/envreg2.lib_nvvm.ll | 2 +- intrinsics/probes/envreg2.llvm_nvptx.ll | 2 +- intrinsics/probes/ex2_approx_f32.ll | 2 +- intrinsics/probes/ex2_approx_ftz_f32.ll | 2 +- .../fence_mbarrier_init_release_cluster.ll | 2 +- ..._generic_acquire_shared_cluster_cluster.ll | 2 +- ...sync_generic_release_shared_cta_cluster.ll | 2 +- .../probes/fence_proxy_async_shared_cta.ll | 2 +- ...proxy_tensormap_generic_acquire_cluster.ll | 2 +- ...nce_proxy_tensormap_generic_acquire_cta.ll | 2 +- ...nce_proxy_tensormap_generic_acquire_gpu.ll | 2 +- ..._proxy_tensormap_generic_acquire_system.ll | 2 +- ...proxy_tensormap_generic_release_cluster.ll | 2 +- ...nce_proxy_tensormap_generic_release_cta.ll | 2 +- ...nce_proxy_tensormap_generic_release_gpu.ll | 2 +- ..._proxy_tensormap_generic_release_system.ll | 2 +- intrinsics/probes/fma_bf16x2.ll | 2 +- intrinsics/probes/fma_f16x2.ll | 2 +- intrinsics/probes/fma_f32x2.ll | 2 +- intrinsics/probes/fma_ftz_f16x2.ll | 2 +- intrinsics/probes/fma_ftz_f32x2.ll | 2 +- intrinsics/probes/fma_ftz_relu_f16x2.ll | 2 +- intrinsics/probes/fma_ftz_sat_f16x2.ll | 2 +- intrinsics/probes/fma_relu_bf16x2.ll | 2 +- intrinsics/probes/fma_relu_f16x2.ll | 2 +- intrinsics/probes/fma_rm_f32.ll | 2 +- intrinsics/probes/fma_rm_f64.ll | 2 +- intrinsics/probes/fma_rm_ftz_f32.ll | 2 +- intrinsics/probes/fma_rm_ftz_sat_f32.ll | 2 +- intrinsics/probes/fma_rm_sat_f32.ll | 2 +- intrinsics/probes/fma_rn_f32.ll | 2 +- intrinsics/probes/fma_rn_f64.ll | 2 +- intrinsics/probes/fma_rn_ftz_f32.ll | 2 +- intrinsics/probes/fma_rn_ftz_sat_f32.ll | 2 +- intrinsics/probes/fma_rn_sat_f32.ll | 2 +- intrinsics/probes/fma_rp_f32.ll | 2 +- intrinsics/probes/fma_rp_f64.ll | 2 +- intrinsics/probes/fma_rp_ftz_f32.ll | 2 +- intrinsics/probes/fma_rp_ftz_sat_f32.ll | 2 +- intrinsics/probes/fma_rp_sat_f32.ll | 2 +- intrinsics/probes/fma_rz_f32.ll | 2 +- intrinsics/probes/fma_rz_f64.ll | 2 +- intrinsics/probes/fma_rz_ftz_f32.ll | 2 +- intrinsics/probes/fma_rz_ftz_sat_f32.ll | 2 +- intrinsics/probes/fma_rz_sat_f32.ll | 2 +- intrinsics/probes/fma_sat_f16x2.ll | 2 +- intrinsics/probes/globaltimer.lib_nvvm.ll | 2 +- intrinsics/probes/globaltimer.llvm_nvptx.ll | 2 +- .../grid_dependency_launch_dependents.ll | 2 +- intrinsics/probes/grid_dependency_wait.ll | 2 +- intrinsics/probes/grid_dim_x.ll | 2 +- intrinsics/probes/grid_dim_y.ll | 2 +- intrinsics/probes/grid_dim_z.ll | 2 +- intrinsics/probes/gridid.lib_nvvm.ll | 2 +- intrinsics/probes/gridid.llvm_nvptx.ll | 2 +- intrinsics/probes/lane_id.ll | 2 +- intrinsics/probes/lanemask_eq.ll | 2 +- intrinsics/probes/lanemask_ge.ll | 2 +- intrinsics/probes/lanemask_gt.ll | 2 +- intrinsics/probes/lanemask_le.ll | 2 +- intrinsics/probes/lanemask_lt.ll | 2 +- .../probes/ldmatrix_m16n16_x1_trans_b8.ll | 2 +- ...dmatrix_m16n16_x1_trans_b8x16_b4x16_p64.ll | 2 +- ...dmatrix_m16n16_x1_trans_b8x16_b6x16_p32.ll | 2 +- .../probes/ldmatrix_m16n16_x2_trans_b8.ll | 2 +- ...dmatrix_m16n16_x2_trans_b8x16_b4x16_p64.ll | 2 +- ...dmatrix_m16n16_x2_trans_b8x16_b6x16_p32.ll | 2 +- .../ldmatrix_m8n16_x1_b8x16_b4x16_p64.ll | 2 +- .../ldmatrix_m8n16_x1_b8x16_b6x16_p32.ll | 2 +- .../ldmatrix_m8n16_x2_b8x16_b4x16_p64.ll | 2 +- .../ldmatrix_m8n16_x2_b8x16_b6x16_p32.ll | 2 +- .../ldmatrix_m8n16_x4_b8x16_b4x16_p64.ll | 2 +- .../ldmatrix_m8n16_x4_b8x16_b6x16_p32.ll | 2 +- intrinsics/probes/ldmatrix_m8n8_x1_b16.ll | 2 +- .../probes/ldmatrix_m8n8_x1_trans_b16.ll | 2 +- intrinsics/probes/ldmatrix_m8n8_x2_b16.ll | 2 +- .../probes/ldmatrix_m8n8_x2_trans_b16.ll | 2 +- intrinsics/probes/ldmatrix_m8n8_x4_b16.ll | 2 +- .../probes/ldmatrix_m8n8_x4_trans_b16.ll | 2 +- intrinsics/probes/lg2_approx_f32.ll | 2 +- intrinsics/probes/lg2_approx_ftz_f32.ll | 2 +- intrinsics/probes/map_shared_rank.ll | 2 +- intrinsics/probes/match_all_i64_sync.ll | 2 +- intrinsics/probes/match_all_sync.ll | 2 +- intrinsics/probes/match_any_i64_sync.ll | 2 +- intrinsics/probes/match_any_sync.ll | 2 +- intrinsics/probes/max_bf16.ll | 2 +- intrinsics/probes/max_bf16x2.ll | 2 +- intrinsics/probes/max_f16.ll | 2 +- intrinsics/probes/max_f16x2.ll | 2 +- intrinsics/probes/max_ftz_f16.ll | 2 +- intrinsics/probes/max_ftz_f16x2.ll | 2 +- intrinsics/probes/max_ftz_nan_f16.ll | 2 +- intrinsics/probes/max_ftz_nan_f16x2.ll | 2 +- .../probes/max_ftz_nan_xorsign_abs_f16.ll | 2 +- .../probes/max_ftz_nan_xorsign_abs_f16x2.ll | 2 +- .../probes/max_ftz_nan_xorsign_abs_f32.ll | 2 +- intrinsics/probes/max_ftz_xorsign_abs_f16.ll | 2 +- .../probes/max_ftz_xorsign_abs_f16x2.ll | 2 +- intrinsics/probes/max_ftz_xorsign_abs_f32.ll | 2 +- intrinsics/probes/max_nan_bf16.ll | 2 +- intrinsics/probes/max_nan_bf16x2.ll | 2 +- intrinsics/probes/max_nan_f16.ll | 2 +- intrinsics/probes/max_nan_f16x2.ll | 2 +- intrinsics/probes/max_nan_xorsign_abs_bf16.ll | 2 +- .../probes/max_nan_xorsign_abs_bf16x2.ll | 2 +- intrinsics/probes/max_nan_xorsign_abs_f16.ll | 2 +- .../probes/max_nan_xorsign_abs_f16x2.ll | 2 +- intrinsics/probes/max_nan_xorsign_abs_f32.ll | 2 +- intrinsics/probes/max_relu_s16x2.ll | 2 +- intrinsics/probes/max_relu_s32.ll | 2 +- intrinsics/probes/max_s16x2.ll | 2 +- intrinsics/probes/max_u16x2.ll | 2 +- intrinsics/probes/max_xorsign_abs_bf16.ll | 2 +- intrinsics/probes/max_xorsign_abs_bf16x2.ll | 2 +- intrinsics/probes/max_xorsign_abs_f16.ll | 2 +- intrinsics/probes/max_xorsign_abs_f16x2.ll | 2 +- intrinsics/probes/max_xorsign_abs_f32.ll | 2 +- intrinsics/probes/mbarrier_arrive.ll | 2 +- intrinsics/probes/mbarrier_arrive_cluster.ll | 2 +- .../probes/mbarrier_arrive_expect_tx.ll | 2 +- .../mbarrier_arrive_expect_tx_cluster.ll | 2 +- intrinsics/probes/mbarrier_init.ll | 2 +- intrinsics/probes/mbarrier_inval.ll | 2 +- intrinsics/probes/mbarrier_test_wait.ll | 2 +- intrinsics/probes/mbarrier_try_wait.ll | 2 +- intrinsics/probes/mbarrier_try_wait_parity.ll | 2 +- .../mbarrier_try_wait_parity_cluster.ll | 2 +- intrinsics/probes/min_bf16.ll | 2 +- intrinsics/probes/min_bf16x2.ll | 2 +- intrinsics/probes/min_f16.ll | 2 +- intrinsics/probes/min_f16x2.ll | 2 +- intrinsics/probes/min_ftz_f16.ll | 2 +- intrinsics/probes/min_ftz_f16x2.ll | 2 +- intrinsics/probes/min_ftz_nan_f16.ll | 2 +- intrinsics/probes/min_ftz_nan_f16x2.ll | 2 +- .../probes/min_ftz_nan_xorsign_abs_f16.ll | 2 +- .../probes/min_ftz_nan_xorsign_abs_f16x2.ll | 2 +- .../probes/min_ftz_nan_xorsign_abs_f32.ll | 2 +- intrinsics/probes/min_ftz_xorsign_abs_f16.ll | 2 +- .../probes/min_ftz_xorsign_abs_f16x2.ll | 2 +- intrinsics/probes/min_ftz_xorsign_abs_f32.ll | 2 +- intrinsics/probes/min_nan_bf16.ll | 2 +- intrinsics/probes/min_nan_bf16x2.ll | 2 +- intrinsics/probes/min_nan_f16.ll | 2 +- intrinsics/probes/min_nan_f16x2.ll | 2 +- intrinsics/probes/min_nan_xorsign_abs_bf16.ll | 2 +- .../probes/min_nan_xorsign_abs_bf16x2.ll | 2 +- intrinsics/probes/min_nan_xorsign_abs_f16.ll | 2 +- .../probes/min_nan_xorsign_abs_f16x2.ll | 2 +- intrinsics/probes/min_nan_xorsign_abs_f32.ll | 2 +- intrinsics/probes/min_relu_s16x2.ll | 2 +- intrinsics/probes/min_relu_s32.ll | 2 +- intrinsics/probes/min_s16x2.ll | 2 +- intrinsics/probes/min_u16x2.ll | 2 +- intrinsics/probes/min_xorsign_abs_bf16.ll | 2 +- intrinsics/probes/min_xorsign_abs_bf16x2.ll | 2 +- intrinsics/probes/min_xorsign_abs_f16.ll | 2 +- intrinsics/probes/min_xorsign_abs_f16x2.ll | 2 +- intrinsics/probes/min_xorsign_abs_f32.ll | 2 +- .../probes/mma_m16n8k128_s32_b1_and_popc.ll | 2 +- .../probes/mma_m16n8k128_s32_b1_xor_popc.ll | 2 +- intrinsics/probes/mma_m16n8k16_f16_f16.ll | 2 +- intrinsics/probes/mma_m16n8k16_f32_bf16.ll | 2 +- intrinsics/probes/mma_m16n8k16_f32_f16.ll | 2 +- .../probes/mma_m16n8k16_fp8_f16_e4m3_e4m3.ll | 2 +- .../probes/mma_m16n8k16_fp8_f16_e4m3_e5m2.ll | 2 +- .../probes/mma_m16n8k16_fp8_f16_e5m2_e4m3.ll | 2 +- .../probes/mma_m16n8k16_fp8_f16_e5m2_e5m2.ll | 2 +- .../probes/mma_m16n8k16_fp8_f32_e4m3_e4m3.ll | 2 +- .../probes/mma_m16n8k16_fp8_f32_e4m3_e5m2.ll | 2 +- .../probes/mma_m16n8k16_fp8_f32_e5m2_e4m3.ll | 2 +- .../probes/mma_m16n8k16_fp8_f32_e5m2_e5m2.ll | 2 +- intrinsics/probes/mma_m16n8k16_s32_s8.ll | 2 +- .../probes/mma_m16n8k16_s32_s8_satfinite.ll | 2 +- intrinsics/probes/mma_m16n8k16_s32_s8_u8.ll | 2 +- .../mma_m16n8k16_s32_s8_u8_satfinite.ll | 2 +- intrinsics/probes/mma_m16n8k16_s32_u8.ll | 2 +- intrinsics/probes/mma_m16n8k16_s32_u8_s8.ll | 2 +- .../mma_m16n8k16_s32_u8_s8_satfinite.ll | 2 +- .../probes/mma_m16n8k16_s32_u8_satfinite.ll | 2 +- .../probes/mma_m16n8k256_s32_b1_and_popc.ll | 2 +- .../probes/mma_m16n8k256_s32_b1_xor_popc.ll | 2 +- .../probes/mma_m16n8k32_f16_e2m1_e2m1.ll | 2 +- .../probes/mma_m16n8k32_f16_e2m1_e2m3.ll | 2 +- .../probes/mma_m16n8k32_f16_e2m1_e3m2.ll | 2 +- .../probes/mma_m16n8k32_f16_e2m1_e4m3.ll | 2 +- .../probes/mma_m16n8k32_f16_e2m1_e5m2.ll | 2 +- .../probes/mma_m16n8k32_f16_e2m3_e2m1.ll | 2 +- .../probes/mma_m16n8k32_f16_e2m3_e2m3.ll | 2 +- .../probes/mma_m16n8k32_f16_e2m3_e3m2.ll | 2 +- .../probes/mma_m16n8k32_f16_e2m3_e4m3.ll | 2 +- .../probes/mma_m16n8k32_f16_e2m3_e5m2.ll | 2 +- .../probes/mma_m16n8k32_f16_e3m2_e2m1.ll | 2 +- .../probes/mma_m16n8k32_f16_e3m2_e2m3.ll | 2 +- .../probes/mma_m16n8k32_f16_e3m2_e3m2.ll | 2 +- .../probes/mma_m16n8k32_f16_e3m2_e4m3.ll | 2 +- .../probes/mma_m16n8k32_f16_e3m2_e5m2.ll | 2 +- .../probes/mma_m16n8k32_f16_e4m3_e2m1.ll | 2 +- .../probes/mma_m16n8k32_f16_e4m3_e2m3.ll | 2 +- .../probes/mma_m16n8k32_f16_e4m3_e3m2.ll | 2 +- .../probes/mma_m16n8k32_f16_e4m3_e4m3.ll | 2 +- .../probes/mma_m16n8k32_f16_e4m3_e5m2.ll | 2 +- .../probes/mma_m16n8k32_f16_e5m2_e2m1.ll | 2 +- .../probes/mma_m16n8k32_f16_e5m2_e2m3.ll | 2 +- .../probes/mma_m16n8k32_f16_e5m2_e3m2.ll | 2 +- .../probes/mma_m16n8k32_f16_e5m2_e4m3.ll | 2 +- .../probes/mma_m16n8k32_f16_e5m2_e5m2.ll | 2 +- .../probes/mma_m16n8k32_f32_e2m1_e2m1.ll | 2 +- .../probes/mma_m16n8k32_f32_e2m1_e2m3.ll | 2 +- .../probes/mma_m16n8k32_f32_e2m1_e3m2.ll | 2 +- .../probes/mma_m16n8k32_f32_e2m1_e4m3.ll | 2 +- .../probes/mma_m16n8k32_f32_e2m1_e5m2.ll | 2 +- .../probes/mma_m16n8k32_f32_e2m3_e2m1.ll | 2 +- .../probes/mma_m16n8k32_f32_e2m3_e2m3.ll | 2 +- .../probes/mma_m16n8k32_f32_e2m3_e3m2.ll | 2 +- .../probes/mma_m16n8k32_f32_e2m3_e4m3.ll | 2 +- .../probes/mma_m16n8k32_f32_e2m3_e5m2.ll | 2 +- .../probes/mma_m16n8k32_f32_e3m2_e2m1.ll | 2 +- .../probes/mma_m16n8k32_f32_e3m2_e2m3.ll | 2 +- .../probes/mma_m16n8k32_f32_e3m2_e3m2.ll | 2 +- .../probes/mma_m16n8k32_f32_e3m2_e4m3.ll | 2 +- .../probes/mma_m16n8k32_f32_e3m2_e5m2.ll | 2 +- .../probes/mma_m16n8k32_f32_e4m3_e2m1.ll | 2 +- .../probes/mma_m16n8k32_f32_e4m3_e2m3.ll | 2 +- .../probes/mma_m16n8k32_f32_e4m3_e3m2.ll | 2 +- .../probes/mma_m16n8k32_f32_e4m3_e4m3.ll | 2 +- .../probes/mma_m16n8k32_f32_e4m3_e5m2.ll | 2 +- .../probes/mma_m16n8k32_f32_e5m2_e2m1.ll | 2 +- .../probes/mma_m16n8k32_f32_e5m2_e2m3.ll | 2 +- .../probes/mma_m16n8k32_f32_e5m2_e3m2.ll | 2 +- .../probes/mma_m16n8k32_f32_e5m2_e4m3.ll | 2 +- .../probes/mma_m16n8k32_f32_e5m2_e5m2.ll | 2 +- .../probes/mma_m16n8k32_fp8_f16_e4m3_e4m3.ll | 2 +- .../probes/mma_m16n8k32_fp8_f16_e4m3_e5m2.ll | 2 +- .../probes/mma_m16n8k32_fp8_f16_e5m2_e4m3.ll | 2 +- .../probes/mma_m16n8k32_fp8_f16_e5m2_e5m2.ll | 2 +- .../probes/mma_m16n8k32_fp8_f32_e4m3_e4m3.ll | 2 +- .../probes/mma_m16n8k32_fp8_f32_e4m3_e5m2.ll | 2 +- .../probes/mma_m16n8k32_fp8_f32_e5m2_e4m3.ll | 2 +- .../probes/mma_m16n8k32_fp8_f32_e5m2_e5m2.ll | 2 +- .../mma_m16n8k32_mxf8f6f4_f32_e2m1_e2m1.ll | 2 +- .../mma_m16n8k32_mxf8f6f4_f32_e2m1_e2m3.ll | 2 +- .../mma_m16n8k32_mxf8f6f4_f32_e2m1_e3m2.ll | 2 +- .../mma_m16n8k32_mxf8f6f4_f32_e2m1_e4m3.ll | 2 +- .../mma_m16n8k32_mxf8f6f4_f32_e2m1_e5m2.ll | 2 +- .../mma_m16n8k32_mxf8f6f4_f32_e2m3_e2m1.ll | 2 +- .../mma_m16n8k32_mxf8f6f4_f32_e2m3_e2m3.ll | 2 +- .../mma_m16n8k32_mxf8f6f4_f32_e2m3_e3m2.ll | 2 +- .../mma_m16n8k32_mxf8f6f4_f32_e2m3_e4m3.ll | 2 +- .../mma_m16n8k32_mxf8f6f4_f32_e2m3_e5m2.ll | 2 +- .../mma_m16n8k32_mxf8f6f4_f32_e3m2_e2m1.ll | 2 +- .../mma_m16n8k32_mxf8f6f4_f32_e3m2_e2m3.ll | 2 +- .../mma_m16n8k32_mxf8f6f4_f32_e3m2_e3m2.ll | 2 +- .../mma_m16n8k32_mxf8f6f4_f32_e3m2_e4m3.ll | 2 +- .../mma_m16n8k32_mxf8f6f4_f32_e3m2_e5m2.ll | 2 +- .../mma_m16n8k32_mxf8f6f4_f32_e4m3_e2m1.ll | 2 +- .../mma_m16n8k32_mxf8f6f4_f32_e4m3_e2m3.ll | 2 +- .../mma_m16n8k32_mxf8f6f4_f32_e4m3_e3m2.ll | 2 +- .../mma_m16n8k32_mxf8f6f4_f32_e4m3_e4m3.ll | 2 +- .../mma_m16n8k32_mxf8f6f4_f32_e4m3_e5m2.ll | 2 +- .../mma_m16n8k32_mxf8f6f4_f32_e5m2_e2m1.ll | 2 +- .../mma_m16n8k32_mxf8f6f4_f32_e5m2_e2m3.ll | 2 +- .../mma_m16n8k32_mxf8f6f4_f32_e5m2_e3m2.ll | 2 +- .../mma_m16n8k32_mxf8f6f4_f32_e5m2_e4m3.ll | 2 +- .../mma_m16n8k32_mxf8f6f4_f32_e5m2_e5m2.ll | 2 +- intrinsics/probes/mma_m16n8k32_s32_s4.ll | 2 +- .../probes/mma_m16n8k32_s32_s4_satfinite.ll | 2 +- intrinsics/probes/mma_m16n8k32_s32_s4_u4.ll | 2 +- .../mma_m16n8k32_s32_s4_u4_satfinite.ll | 2 +- intrinsics/probes/mma_m16n8k32_s32_s8.ll | 2 +- .../probes/mma_m16n8k32_s32_s8_satfinite.ll | 2 +- intrinsics/probes/mma_m16n8k32_s32_s8_u8.ll | 2 +- .../mma_m16n8k32_s32_s8_u8_satfinite.ll | 2 +- intrinsics/probes/mma_m16n8k32_s32_u4.ll | 2 +- intrinsics/probes/mma_m16n8k32_s32_u4_s4.ll | 2 +- .../mma_m16n8k32_s32_u4_s4_satfinite.ll | 2 +- .../probes/mma_m16n8k32_s32_u4_satfinite.ll | 2 +- intrinsics/probes/mma_m16n8k32_s32_u8.ll | 2 +- intrinsics/probes/mma_m16n8k32_s32_u8_s8.ll | 2 +- .../mma_m16n8k32_s32_u8_s8_satfinite.ll | 2 +- .../probes/mma_m16n8k32_s32_u8_satfinite.ll | 2 +- intrinsics/probes/mma_m16n8k4_f32_tf32.ll | 2 +- intrinsics/probes/mma_m16n8k64_s32_s4.ll | 2 +- .../probes/mma_m16n8k64_s32_s4_satfinite.ll | 2 +- intrinsics/probes/mma_m16n8k64_s32_s4_u4.ll | 2 +- .../mma_m16n8k64_s32_s4_u4_satfinite.ll | 2 +- intrinsics/probes/mma_m16n8k64_s32_u4.ll | 2 +- intrinsics/probes/mma_m16n8k64_s32_u4_s4.ll | 2 +- .../mma_m16n8k64_s32_u4_s4_satfinite.ll | 2 +- .../probes/mma_m16n8k64_s32_u4_satfinite.ll | 2 +- intrinsics/probes/mma_m16n8k8_f16_f16.ll | 2 +- intrinsics/probes/mma_m16n8k8_f32_bf16.ll | 2 +- intrinsics/probes/mma_m16n8k8_f32_f16.ll | 2 +- intrinsics/probes/mma_m16n8k8_f32_tf32.ll | 2 +- .../probes/mma_m8n8k128_s32_b1_and_popc.ll | 2 +- .../probes/mma_m8n8k128_s32_b1_xor_popc.ll | 2 +- intrinsics/probes/mma_m8n8k16_s32_s8.ll | 2 +- .../probes/mma_m8n8k16_s32_s8_satfinite.ll | 2 +- intrinsics/probes/mma_m8n8k16_s32_s8_u8.ll | 2 +- .../probes/mma_m8n8k16_s32_s8_u8_satfinite.ll | 2 +- intrinsics/probes/mma_m8n8k16_s32_u8.ll | 2 +- intrinsics/probes/mma_m8n8k16_s32_u8_s8.ll | 2 +- .../probes/mma_m8n8k16_s32_u8_s8_satfinite.ll | 2 +- .../probes/mma_m8n8k16_s32_u8_satfinite.ll | 2 +- intrinsics/probes/mma_m8n8k32_s32_s4.ll | 2 +- .../probes/mma_m8n8k32_s32_s4_satfinite.ll | 2 +- intrinsics/probes/mma_m8n8k32_s32_s4_u4.ll | 2 +- .../probes/mma_m8n8k32_s32_s4_u4_satfinite.ll | 2 +- intrinsics/probes/mma_m8n8k32_s32_u4.ll | 2 +- intrinsics/probes/mma_m8n8k32_s32_u4_s4.ll | 2 +- .../probes/mma_m8n8k32_s32_u4_s4_satfinite.ll | 2 +- .../probes/mma_m8n8k32_s32_u4_satfinite.ll | 2 +- intrinsics/probes/mma_m8n8k4_f64.ll | 2 +- intrinsics/probes/mma_sp_m16n8k128_s32_s4.ll | 2 +- .../mma_sp_m16n8k128_s32_s4_satfinite.ll | 2 +- .../probes/mma_sp_m16n8k128_s32_s4_u4.ll | 2 +- .../mma_sp_m16n8k128_s32_s4_u4_satfinite.ll | 2 +- intrinsics/probes/mma_sp_m16n8k128_s32_u4.ll | 2 +- .../probes/mma_sp_m16n8k128_s32_u4_s4.ll | 2 +- .../mma_sp_m16n8k128_s32_u4_s4_satfinite.ll | 2 +- .../mma_sp_m16n8k128_s32_u4_satfinite.ll | 2 +- intrinsics/probes/mma_sp_m16n8k32_s32_s8.ll | 2 +- .../mma_sp_m16n8k32_s32_s8_satfinite.ll | 2 +- .../probes/mma_sp_m16n8k32_s32_s8_u8.ll | 2 +- .../mma_sp_m16n8k32_s32_s8_u8_satfinite.ll | 2 +- intrinsics/probes/mma_sp_m16n8k32_s32_u8.ll | 2 +- .../probes/mma_sp_m16n8k32_s32_u8_s8.ll | 2 +- .../mma_sp_m16n8k32_s32_u8_s8_satfinite.ll | 2 +- .../mma_sp_m16n8k32_s32_u8_satfinite.ll | 2 +- intrinsics/probes/mma_sp_m16n8k64_s32_s4.ll | 2 +- .../mma_sp_m16n8k64_s32_s4_satfinite.ll | 2 +- .../probes/mma_sp_m16n8k64_s32_s4_u4.ll | 2 +- .../mma_sp_m16n8k64_s32_s4_u4_satfinite.ll | 2 +- intrinsics/probes/mma_sp_m16n8k64_s32_s8.ll | 2 +- .../mma_sp_m16n8k64_s32_s8_satfinite.ll | 2 +- .../probes/mma_sp_m16n8k64_s32_s8_u8.ll | 2 +- .../mma_sp_m16n8k64_s32_s8_u8_satfinite.ll | 2 +- intrinsics/probes/mma_sp_m16n8k64_s32_u4.ll | 2 +- .../probes/mma_sp_m16n8k64_s32_u4_s4.ll | 2 +- .../mma_sp_m16n8k64_s32_u4_s4_satfinite.ll | 2 +- .../mma_sp_m16n8k64_s32_u4_satfinite.ll | 2 +- intrinsics/probes/mma_sp_m16n8k64_s32_u8.ll | 2 +- .../probes/mma_sp_m16n8k64_s32_u8_s8.ll | 2 +- .../mma_sp_m16n8k64_s32_u8_s8_satfinite.ll | 2 +- .../mma_sp_m16n8k64_s32_u8_satfinite.ll | 2 +- ...ma_sp_ordered_metadata_m16n8k128_s32_s4.ll | 2 +- ...red_metadata_m16n8k128_s32_s4_satfinite.ll | 2 +- ...sp_ordered_metadata_m16n8k128_s32_s4_u4.ll | 2 +- ..._metadata_m16n8k128_s32_s4_u4_satfinite.ll | 2 +- ...ma_sp_ordered_metadata_m16n8k128_s32_u4.ll | 2 +- ...sp_ordered_metadata_m16n8k128_s32_u4_s4.ll | 2 +- ..._metadata_m16n8k128_s32_u4_s4_satfinite.ll | 2 +- ...red_metadata_m16n8k128_s32_u4_satfinite.ll | 2 +- ...mma_sp_ordered_metadata_m16n8k32_s32_s8.ll | 2 +- ...ered_metadata_m16n8k32_s32_s8_satfinite.ll | 2 +- ..._sp_ordered_metadata_m16n8k32_s32_s8_u8.ll | 2 +- ...d_metadata_m16n8k32_s32_s8_u8_satfinite.ll | 2 +- ...mma_sp_ordered_metadata_m16n8k32_s32_u8.ll | 2 +- ..._sp_ordered_metadata_m16n8k32_s32_u8_s8.ll | 2 +- ...d_metadata_m16n8k32_s32_u8_s8_satfinite.ll | 2 +- ...ered_metadata_m16n8k32_s32_u8_satfinite.ll | 2 +- ..._m16n8k64_kind_f8f6f4_f16_e2m1_e2m1_f16.ll | 2 +- ..._m16n8k64_kind_f8f6f4_f16_e2m1_e2m3_f16.ll | 2 +- ..._m16n8k64_kind_f8f6f4_f16_e2m1_e3m2_f16.ll | 2 +- ..._m16n8k64_kind_f8f6f4_f16_e2m1_e4m3_f16.ll | 2 +- ..._m16n8k64_kind_f8f6f4_f16_e2m1_e5m2_f16.ll | 2 +- ..._m16n8k64_kind_f8f6f4_f16_e2m3_e2m1_f16.ll | 2 +- ..._m16n8k64_kind_f8f6f4_f16_e2m3_e2m3_f16.ll | 2 +- ..._m16n8k64_kind_f8f6f4_f16_e2m3_e3m2_f16.ll | 2 +- ..._m16n8k64_kind_f8f6f4_f16_e2m3_e4m3_f16.ll | 2 +- ..._m16n8k64_kind_f8f6f4_f16_e2m3_e5m2_f16.ll | 2 +- ..._m16n8k64_kind_f8f6f4_f16_e3m2_e2m1_f16.ll | 2 +- ..._m16n8k64_kind_f8f6f4_f16_e3m2_e2m3_f16.ll | 2 +- ..._m16n8k64_kind_f8f6f4_f16_e3m2_e3m2_f16.ll | 2 +- ..._m16n8k64_kind_f8f6f4_f16_e3m2_e4m3_f16.ll | 2 +- ..._m16n8k64_kind_f8f6f4_f16_e3m2_e5m2_f16.ll | 2 +- ..._m16n8k64_kind_f8f6f4_f16_e4m3_e2m1_f16.ll | 2 +- ..._m16n8k64_kind_f8f6f4_f16_e4m3_e2m3_f16.ll | 2 +- ..._m16n8k64_kind_f8f6f4_f16_e4m3_e3m2_f16.ll | 2 +- ..._m16n8k64_kind_f8f6f4_f16_e4m3_e4m3_f16.ll | 2 +- ..._m16n8k64_kind_f8f6f4_f16_e4m3_e5m2_f16.ll | 2 +- ..._m16n8k64_kind_f8f6f4_f16_e5m2_e2m1_f16.ll | 2 +- ..._m16n8k64_kind_f8f6f4_f16_e5m2_e2m3_f16.ll | 2 +- ..._m16n8k64_kind_f8f6f4_f16_e5m2_e3m2_f16.ll | 2 +- ..._m16n8k64_kind_f8f6f4_f16_e5m2_e4m3_f16.ll | 2 +- ..._m16n8k64_kind_f8f6f4_f16_e5m2_e5m2_f16.ll | 2 +- ..._m16n8k64_kind_f8f6f4_f32_e2m1_e2m1_f32.ll | 2 +- ..._m16n8k64_kind_f8f6f4_f32_e2m1_e2m3_f32.ll | 2 +- ..._m16n8k64_kind_f8f6f4_f32_e2m1_e3m2_f32.ll | 2 +- ..._m16n8k64_kind_f8f6f4_f32_e2m1_e4m3_f32.ll | 2 +- ..._m16n8k64_kind_f8f6f4_f32_e2m1_e5m2_f32.ll | 2 +- ..._m16n8k64_kind_f8f6f4_f32_e2m3_e2m1_f32.ll | 2 +- ..._m16n8k64_kind_f8f6f4_f32_e2m3_e2m3_f32.ll | 2 +- ..._m16n8k64_kind_f8f6f4_f32_e2m3_e3m2_f32.ll | 2 +- ..._m16n8k64_kind_f8f6f4_f32_e2m3_e4m3_f32.ll | 2 +- ..._m16n8k64_kind_f8f6f4_f32_e2m3_e5m2_f32.ll | 2 +- ..._m16n8k64_kind_f8f6f4_f32_e3m2_e2m1_f32.ll | 2 +- ..._m16n8k64_kind_f8f6f4_f32_e3m2_e2m3_f32.ll | 2 +- ..._m16n8k64_kind_f8f6f4_f32_e3m2_e3m2_f32.ll | 2 +- ..._m16n8k64_kind_f8f6f4_f32_e3m2_e4m3_f32.ll | 2 +- ..._m16n8k64_kind_f8f6f4_f32_e3m2_e5m2_f32.ll | 2 +- ..._m16n8k64_kind_f8f6f4_f32_e4m3_e2m1_f32.ll | 2 +- ..._m16n8k64_kind_f8f6f4_f32_e4m3_e2m3_f32.ll | 2 +- ..._m16n8k64_kind_f8f6f4_f32_e4m3_e3m2_f32.ll | 2 +- ..._m16n8k64_kind_f8f6f4_f32_e4m3_e4m3_f32.ll | 2 +- ..._m16n8k64_kind_f8f6f4_f32_e4m3_e5m2_f32.ll | 2 +- ..._m16n8k64_kind_f8f6f4_f32_e5m2_e2m1_f32.ll | 2 +- ..._m16n8k64_kind_f8f6f4_f32_e5m2_e2m3_f32.ll | 2 +- ..._m16n8k64_kind_f8f6f4_f32_e5m2_e3m2_f32.ll | 2 +- ..._m16n8k64_kind_f8f6f4_f32_e5m2_e4m3_f32.ll | 2 +- ..._m16n8k64_kind_f8f6f4_f32_e5m2_e5m2_f32.ll | 2 +- ...mma_sp_ordered_metadata_m16n8k64_s32_s4.ll | 2 +- ...ered_metadata_m16n8k64_s32_s4_satfinite.ll | 2 +- ..._sp_ordered_metadata_m16n8k64_s32_s4_u4.ll | 2 +- ...d_metadata_m16n8k64_s32_s4_u4_satfinite.ll | 2 +- ...mma_sp_ordered_metadata_m16n8k64_s32_s8.ll | 2 +- ...ered_metadata_m16n8k64_s32_s8_satfinite.ll | 2 +- ..._sp_ordered_metadata_m16n8k64_s32_s8_u8.ll | 2 +- ...d_metadata_m16n8k64_s32_s8_u8_satfinite.ll | 2 +- ...mma_sp_ordered_metadata_m16n8k64_s32_u4.ll | 2 +- ..._sp_ordered_metadata_m16n8k64_s32_u4_s4.ll | 2 +- ...d_metadata_m16n8k64_s32_u4_s4_satfinite.ll | 2 +- ...ered_metadata_m16n8k64_s32_u4_satfinite.ll | 2 +- ...mma_sp_ordered_metadata_m16n8k64_s32_u8.ll | 2 +- ..._sp_ordered_metadata_m16n8k64_s32_u8_s8.ll | 2 +- ...d_metadata_m16n8k64_s32_u8_s8_satfinite.ll | 2 +- ...ered_metadata_m16n8k64_s32_u8_satfinite.ll | 2 +- intrinsics/probes/movmatrix_trans_b16.ll | 2 +- intrinsics/probes/mul_bf16x2.ll | 2 +- intrinsics/probes/mul_f16x2.ll | 2 +- intrinsics/probes/mul_f32x2.ll | 2 +- intrinsics/probes/mul_ftz_f32x2.ll | 2 +- intrinsics/probes/mul_rm_f32.ll | 2 +- intrinsics/probes/mul_rm_f64.ll | 2 +- intrinsics/probes/mul_rm_ftz_f32.ll | 2 +- intrinsics/probes/mul_rn_f32.ll | 2 +- intrinsics/probes/mul_rn_f64.ll | 2 +- intrinsics/probes/mul_rn_ftz_f32.ll | 2 +- intrinsics/probes/mul_rp_f32.ll | 2 +- intrinsics/probes/mul_rp_f64.ll | 2 +- intrinsics/probes/mul_rp_ftz_f32.ll | 2 +- intrinsics/probes/mul_rz_f32.ll | 2 +- intrinsics/probes/mul_rz_f64.ll | 2 +- intrinsics/probes/mul_rz_ftz_f32.ll | 2 +- intrinsics/probes/nanosleep.ll | 2 +- intrinsics/probes/neg_bf16x2.ll | 2 +- intrinsics/probes/neg_f16x2.ll | 2 +- intrinsics/probes/nsmid.lib_nvvm.ll | 2 +- intrinsics/probes/nsmid.llvm_nvptx.ll | 2 +- intrinsics/probes/nwarpid.lib_nvvm.ll | 2 +- intrinsics/probes/nwarpid.llvm_nvptx.ll | 2 +- intrinsics/probes/packed_atomic_add_bf16x2.ll | 2 +- intrinsics/probes/packed_atomic_add_f16x2.ll | 2 +- intrinsics/probes/pmevent.ll | 2 +- intrinsics/probes/prefetch_tma_descriptor.ll | 2 +- intrinsics/probes/prmt.ll | 2 +- intrinsics/probes/prmt_b4e.ll | 2 +- intrinsics/probes/prmt_ecl.ll | 2 +- intrinsics/probes/prmt_ecr.ll | 2 +- intrinsics/probes/prmt_f4e.ll | 2 +- intrinsics/probes/prmt_rc16.ll | 2 +- intrinsics/probes/prmt_rc8.ll | 2 +- intrinsics/probes/rcp_approx_ftz_f32.ll | 2 +- intrinsics/probes/rcp_approx_ftz_f64.ll | 2 +- intrinsics/probes/rcp_rm_f32.ll | 2 +- intrinsics/probes/rcp_rm_f64.ll | 2 +- intrinsics/probes/rcp_rm_ftz_f32.ll | 2 +- intrinsics/probes/rcp_rn_f32.ll | 2 +- intrinsics/probes/rcp_rn_f64.ll | 2 +- intrinsics/probes/rcp_rn_ftz_f32.ll | 2 +- intrinsics/probes/rcp_rp_f32.ll | 2 +- intrinsics/probes/rcp_rp_f64.ll | 2 +- intrinsics/probes/rcp_rp_ftz_f32.ll | 2 +- intrinsics/probes/rcp_rz_f32.ll | 2 +- intrinsics/probes/rcp_rz_f64.ll | 2 +- intrinsics/probes/rcp_rz_ftz_f32.ll | 2 +- intrinsics/probes/redux_sync_add.ll | 2 +- intrinsics/probes/redux_sync_and.ll | 2 +- intrinsics/probes/redux_sync_max_abs_f32.ll | 2 +- .../probes/redux_sync_max_abs_nan_f32.ll | 2 +- intrinsics/probes/redux_sync_max_f32.ll | 2 +- intrinsics/probes/redux_sync_max_i32.ll | 2 +- intrinsics/probes/redux_sync_max_nan_f32.ll | 2 +- intrinsics/probes/redux_sync_max_u32.ll | 2 +- intrinsics/probes/redux_sync_min_abs_f32.ll | 2 +- .../probes/redux_sync_min_abs_nan_f32.ll | 2 +- intrinsics/probes/redux_sync_min_f32.ll | 2 +- intrinsics/probes/redux_sync_min_i32.ll | 2 +- intrinsics/probes/redux_sync_min_nan_f32.ll | 2 +- intrinsics/probes/redux_sync_min_u32.ll | 2 +- intrinsics/probes/redux_sync_or.ll | 2 +- intrinsics/probes/redux_sync_xor.ll | 2 +- intrinsics/probes/rsqrt_approx_f32.ll | 2 +- intrinsics/probes/rsqrt_approx_f64.ll | 2 +- intrinsics/probes/rsqrt_approx_ftz_f32.ll | 2 +- intrinsics/probes/setmaxnreg_dec.ll | 2 +- intrinsics/probes/setmaxnreg_inc.ll | 2 +- intrinsics/probes/shuffle_down_f32_sync.ll | 2 +- intrinsics/probes/shuffle_down_sync.ll | 2 +- intrinsics/probes/shuffle_down_u64_sync.ll | 2 +- intrinsics/probes/shuffle_f32_sync.ll | 2 +- intrinsics/probes/shuffle_sync.ll | 2 +- intrinsics/probes/shuffle_u64_sync.ll | 2 +- intrinsics/probes/shuffle_up_f32_sync.ll | 2 +- intrinsics/probes/shuffle_up_sync.ll | 2 +- intrinsics/probes/shuffle_up_u64_sync.ll | 2 +- intrinsics/probes/shuffle_xor_f32_sync.ll | 2 +- intrinsics/probes/shuffle_xor_sync.ll | 2 +- intrinsics/probes/shuffle_xor_u64_sync.ll | 2 +- intrinsics/probes/sin_approx_f32.ll | 2 +- intrinsics/probes/sin_approx_ftz_f32.ll | 2 +- intrinsics/probes/smid.lib_nvvm.ll | 2 +- intrinsics/probes/smid.llvm_nvptx.ll | 2 +- intrinsics/probes/sqrt_approx_f32.ll | 2 +- intrinsics/probes/sqrt_approx_ftz_f32.ll | 2 +- intrinsics/probes/sqrt_rm_f32.ll | 2 +- intrinsics/probes/sqrt_rm_f64.ll | 2 +- intrinsics/probes/sqrt_rm_ftz_f32.ll | 2 +- intrinsics/probes/sqrt_rn_f32.ll | 2 +- intrinsics/probes/sqrt_rn_f64.ll | 2 +- intrinsics/probes/sqrt_rn_ftz_f32.ll | 2 +- intrinsics/probes/sqrt_rp_f32.ll | 2 +- intrinsics/probes/sqrt_rp_f64.ll | 2 +- intrinsics/probes/sqrt_rp_ftz_f32.ll | 2 +- intrinsics/probes/sqrt_rz_f32.ll | 2 +- intrinsics/probes/sqrt_rz_f64.ll | 2 +- intrinsics/probes/sqrt_rz_ftz_f32.ll | 2 +- intrinsics/probes/stmatrix_m8n8_x2_b16.ll | 2 +- .../probes/stmatrix_m8n8_x2_trans_b16.ll | 2 +- intrinsics/probes/stmatrix_m8n8_x4_b16.ll | 2 +- .../probes/stmatrix_m8n8_x4_trans_b16.ll | 2 +- intrinsics/probes/sub_bf16x2.ll | 2 +- intrinsics/probes/sub_f16x2.ll | 2 +- intrinsics/probes/sub_f32x2.ll | 2 +- intrinsics/probes/sub_ftz_f32x2.ll | 2 +- intrinsics/probes/sync_mask.ll | 2 +- intrinsics/probes/sync_threads.ll | 2 +- intrinsics/probes/tanh_approx_f32.ll | 2 +- intrinsics/probes/tcgen05_alloc.ll | 2 +- intrinsics/probes/tcgen05_alloc_cg2.ll | 2 +- intrinsics/probes/tcgen05_commit.ll | 2 +- intrinsics/probes/tcgen05_commit_cg2.ll | 2 +- intrinsics/probes/tcgen05_commit_multicast.ll | 2 +- .../probes/tcgen05_commit_multicast_cg2.ll | 2 +- .../probes/tcgen05_commit_shared_cluster.ll | 2 +- .../tcgen05_commit_shared_cluster_cg2.ll | 2 +- intrinsics/probes/tcgen05_cp_128x128b.ll | 2 +- .../probes/tcgen05_cp_128x128b_b4x16_p64.ll | 2 +- .../tcgen05_cp_128x128b_b4x16_p64_cg2.ll | 2 +- .../probes/tcgen05_cp_128x128b_b6x16_p32.ll | 2 +- .../tcgen05_cp_128x128b_b6x16_p32_cg2.ll | 2 +- intrinsics/probes/tcgen05_cp_128x128b_cg2.ll | 2 +- .../probes/tcgen05_cp_128x256b_b4x16_p64.ll | 2 +- .../tcgen05_cp_128x256b_b4x16_p64_cg2.ll | 2 +- .../probes/tcgen05_cp_128x256b_b6x16_p32.ll | 2 +- .../tcgen05_cp_128x256b_b6x16_p32_cg2.ll | 2 +- .../probes/tcgen05_cp_32x128b_warpx4.ll | 2 +- .../tcgen05_cp_32x128b_warpx4_b4x16_p64.ll | 2 +- ...tcgen05_cp_32x128b_warpx4_b4x16_p64_cg2.ll | 2 +- .../tcgen05_cp_32x128b_warpx4_b6x16_p32.ll | 2 +- ...tcgen05_cp_32x128b_warpx4_b6x16_p32_cg2.ll | 2 +- .../probes/tcgen05_cp_32x128b_warpx4_cg2.ll | 2 +- intrinsics/probes/tcgen05_cp_4x256b.ll | 2 +- .../probes/tcgen05_cp_4x256b_b4x16_p64.ll | 2 +- .../probes/tcgen05_cp_4x256b_b4x16_p64_cg2.ll | 2 +- .../probes/tcgen05_cp_4x256b_b6x16_p32.ll | 2 +- .../probes/tcgen05_cp_4x256b_b6x16_p32_cg2.ll | 2 +- intrinsics/probes/tcgen05_cp_4x256b_cg2.ll | 2 +- .../probes/tcgen05_cp_64x128b_warpx2_01_23.ll | 2 +- ...gen05_cp_64x128b_warpx2_01_23_b4x16_p64.ll | 2 +- ...5_cp_64x128b_warpx2_01_23_b4x16_p64_cg2.ll | 2 +- ...gen05_cp_64x128b_warpx2_01_23_b6x16_p32.ll | 2 +- ...5_cp_64x128b_warpx2_01_23_b6x16_p32_cg2.ll | 2 +- .../tcgen05_cp_64x128b_warpx2_01_23_cg2.ll | 2 +- .../probes/tcgen05_cp_64x128b_warpx2_02_13.ll | 2 +- ...gen05_cp_64x128b_warpx2_02_13_b4x16_p64.ll | 2 +- ...5_cp_64x128b_warpx2_02_13_b4x16_p64_cg2.ll | 2 +- ...gen05_cp_64x128b_warpx2_02_13_b6x16_p32.ll | 2 +- ...5_cp_64x128b_warpx2_02_13_b6x16_p32_cg2.ll | 2 +- .../tcgen05_cp_64x128b_warpx2_02_13_cg2.ll | 2 +- intrinsics/probes/tcgen05_cp_smem_to_tmem.ll | 2 +- .../probes/tcgen05_cp_smem_to_tmem_cg2.ll | 2 +- intrinsics/probes/tcgen05_dealloc.ll | 2 +- intrinsics/probes/tcgen05_dealloc_cg2.ll | 2 +- .../probes/tcgen05_fence_after_thread_sync.ll | 2 +- .../tcgen05_fence_before_thread_sync.ll | 2 +- .../probes/tcgen05_ld_16x128b_x16_pack16.ll | 2 +- .../probes/tcgen05_ld_16x128b_x16_raw.ll | 2 +- .../probes/tcgen05_ld_16x128b_x1_pack16.ll | 2 +- .../probes/tcgen05_ld_16x128b_x1_raw.ll | 2 +- .../probes/tcgen05_ld_16x128b_x2_pack16.ll | 2 +- .../probes/tcgen05_ld_16x128b_x2_raw.ll | 2 +- .../probes/tcgen05_ld_16x128b_x32_pack16.ll | 2 +- .../probes/tcgen05_ld_16x128b_x32_raw.ll | 2 +- .../probes/tcgen05_ld_16x128b_x4_pack16.ll | 2 +- .../probes/tcgen05_ld_16x128b_x4_raw.ll | 2 +- .../probes/tcgen05_ld_16x128b_x64_pack16.ll | 2 +- .../probes/tcgen05_ld_16x128b_x64_raw.ll | 2 +- .../probes/tcgen05_ld_16x128b_x8_pack16.ll | 2 +- .../probes/tcgen05_ld_16x128b_x8_raw.ll | 2 +- intrinsics/probes/tcgen05_ld_16x256b_pure.ll | 2 +- .../probes/tcgen05_ld_16x256b_x16_pack16.ll | 2 +- .../probes/tcgen05_ld_16x256b_x16_raw.ll | 2 +- .../probes/tcgen05_ld_16x256b_x1_pack16.ll | 2 +- .../probes/tcgen05_ld_16x256b_x1_raw.ll | 2 +- .../probes/tcgen05_ld_16x256b_x2_pack16.ll | 2 +- .../probes/tcgen05_ld_16x256b_x2_raw.ll | 2 +- .../probes/tcgen05_ld_16x256b_x32_pack16.ll | 2 +- .../probes/tcgen05_ld_16x256b_x32_raw.ll | 2 +- .../probes/tcgen05_ld_16x256b_x4_pack16.ll | 2 +- .../probes/tcgen05_ld_16x256b_x4_raw.ll | 2 +- .../probes/tcgen05_ld_16x256b_x8_pack16.ll | 2 +- .../probes/tcgen05_ld_16x256b_x8_pure.ll | 2 +- .../probes/tcgen05_ld_16x256b_x8_raw.ll | 2 +- .../probes/tcgen05_ld_16x32bx2_x128_pack16.ll | 2 +- .../probes/tcgen05_ld_16x32bx2_x128_raw.ll | 2 +- .../probes/tcgen05_ld_16x32bx2_x16_pack16.ll | 2 +- .../probes/tcgen05_ld_16x32bx2_x16_raw.ll | 2 +- .../probes/tcgen05_ld_16x32bx2_x1_pack16.ll | 2 +- .../probes/tcgen05_ld_16x32bx2_x1_raw.ll | 2 +- .../probes/tcgen05_ld_16x32bx2_x2_pack16.ll | 2 +- .../probes/tcgen05_ld_16x32bx2_x2_raw.ll | 2 +- .../probes/tcgen05_ld_16x32bx2_x32_pack16.ll | 2 +- .../probes/tcgen05_ld_16x32bx2_x32_raw.ll | 2 +- .../probes/tcgen05_ld_16x32bx2_x4_pack16.ll | 2 +- .../probes/tcgen05_ld_16x32bx2_x4_raw.ll | 2 +- .../probes/tcgen05_ld_16x32bx2_x64_pack16.ll | 2 +- .../probes/tcgen05_ld_16x32bx2_x64_raw.ll | 2 +- .../probes/tcgen05_ld_16x32bx2_x8_pack16.ll | 2 +- .../probes/tcgen05_ld_16x32bx2_x8_raw.ll | 2 +- .../probes/tcgen05_ld_16x64b_x128_pack16.ll | 2 +- .../probes/tcgen05_ld_16x64b_x128_raw.ll | 2 +- .../probes/tcgen05_ld_16x64b_x16_pack16.ll | 2 +- .../probes/tcgen05_ld_16x64b_x16_raw.ll | 2 +- .../probes/tcgen05_ld_16x64b_x1_pack16.ll | 2 +- intrinsics/probes/tcgen05_ld_16x64b_x1_raw.ll | 2 +- .../probes/tcgen05_ld_16x64b_x2_pack16.ll | 2 +- intrinsics/probes/tcgen05_ld_16x64b_x2_raw.ll | 2 +- .../probes/tcgen05_ld_16x64b_x32_pack16.ll | 2 +- .../probes/tcgen05_ld_16x64b_x32_raw.ll | 2 +- .../probes/tcgen05_ld_16x64b_x4_pack16.ll | 2 +- intrinsics/probes/tcgen05_ld_16x64b_x4_raw.ll | 2 +- .../probes/tcgen05_ld_16x64b_x64_pack16.ll | 2 +- .../probes/tcgen05_ld_16x64b_x64_raw.ll | 2 +- .../probes/tcgen05_ld_16x64b_x8_pack16.ll | 2 +- intrinsics/probes/tcgen05_ld_16x64b_x8_raw.ll | 2 +- .../probes/tcgen05_ld_32x32b_x128_pack16.ll | 2 +- .../probes/tcgen05_ld_32x32b_x128_raw.ll | 2 +- .../probes/tcgen05_ld_32x32b_x16_pack16.ll | 2 +- .../probes/tcgen05_ld_32x32b_x16_raw.ll | 2 +- .../probes/tcgen05_ld_32x32b_x1_pack16.ll | 2 +- intrinsics/probes/tcgen05_ld_32x32b_x1_raw.ll | 2 +- .../probes/tcgen05_ld_32x32b_x2_pack16.ll | 2 +- intrinsics/probes/tcgen05_ld_32x32b_x2_raw.ll | 2 +- .../probes/tcgen05_ld_32x32b_x32_pack16.ll | 2 +- .../probes/tcgen05_ld_32x32b_x32_raw.ll | 2 +- .../probes/tcgen05_ld_32x32b_x4_pack16.ll | 2 +- intrinsics/probes/tcgen05_ld_32x32b_x4_raw.ll | 2 +- .../probes/tcgen05_ld_32x32b_x64_pack16.ll | 2 +- .../probes/tcgen05_ld_32x32b_x64_raw.ll | 2 +- .../probes/tcgen05_ld_32x32b_x8_pack16.ll | 2 +- intrinsics/probes/tcgen05_ld_32x32b_x8_raw.ll | 2 +- intrinsics/probes/tcgen05_load_wait.ll | 2 +- intrinsics/probes/tcgen05_mma_e2m1.ll | 2 +- intrinsics/probes/tcgen05_mma_e2m3.ll | 2 +- intrinsics/probes/tcgen05_mma_e3m2.ll | 2 +- intrinsics/probes/tcgen05_mma_e4m3.ll | 2 +- intrinsics/probes/tcgen05_mma_e5m2.ll | 2 +- intrinsics/probes/tcgen05_mma_f16.ll | 2 +- intrinsics/probes/tcgen05_mma_f16_cg2.ll | 2 +- intrinsics/probes/tcgen05_mma_shared.ll | 2 +- intrinsics/probes/tcgen05_mma_sp_shared.ll | 2 +- intrinsics/probes/tcgen05_mma_sp_tensor.ll | 2 +- .../probes/tcgen05_mma_sp_tensor_ashift.ll | 2 +- intrinsics/probes/tcgen05_mma_tensor.ll | 2 +- .../probes/tcgen05_mma_tensor_ashift.ll | 2 +- intrinsics/probes/tcgen05_mma_ws_bf16.ll | 2 +- intrinsics/probes/tcgen05_mma_ws_e2m1.ll | 2 +- intrinsics/probes/tcgen05_mma_ws_e2m3.ll | 2 +- intrinsics/probes/tcgen05_mma_ws_e3m2.ll | 2 +- intrinsics/probes/tcgen05_mma_ws_e4m3.ll | 2 +- intrinsics/probes/tcgen05_mma_ws_e5m2.ll | 2 +- intrinsics/probes/tcgen05_mma_ws_f16.ll | 2 +- intrinsics/probes/tcgen05_mma_ws_shared.ll | 2 +- .../tcgen05_mma_ws_shared_zero_col_mask.ll | 2 +- intrinsics/probes/tcgen05_mma_ws_sp_shared.ll | 2 +- .../tcgen05_mma_ws_sp_shared_zero_col_mask.ll | 2 +- intrinsics/probes/tcgen05_mma_ws_sp_tensor.ll | 2 +- .../tcgen05_mma_ws_sp_tensor_zero_col_mask.ll | 2 +- intrinsics/probes/tcgen05_mma_ws_tensor.ll | 2 +- .../tcgen05_mma_ws_tensor_zero_col_mask.ll | 2 +- intrinsics/probes/tcgen05_mma_ws_tf32.ll | 2 +- .../probes/tcgen05_relinquish_alloc_permit.ll | 2 +- .../tcgen05_relinquish_alloc_permit_cg2.ll | 2 +- intrinsics/probes/tcgen05_shift_down.ll | 2 +- intrinsics/probes/tcgen05_shift_down_cg2.ll | 2 +- .../probes/tcgen05_st_16x128b_x16_raw.ll | 2 +- .../probes/tcgen05_st_16x128b_x16_unpack16.ll | 2 +- .../probes/tcgen05_st_16x128b_x1_raw.ll | 2 +- .../probes/tcgen05_st_16x128b_x1_unpack16.ll | 2 +- .../probes/tcgen05_st_16x128b_x2_raw.ll | 2 +- .../probes/tcgen05_st_16x128b_x2_unpack16.ll | 2 +- .../probes/tcgen05_st_16x128b_x32_raw.ll | 2 +- .../probes/tcgen05_st_16x128b_x32_unpack16.ll | 2 +- .../probes/tcgen05_st_16x128b_x4_raw.ll | 2 +- .../probes/tcgen05_st_16x128b_x4_unpack16.ll | 2 +- .../probes/tcgen05_st_16x128b_x64_raw.ll | 2 +- .../probes/tcgen05_st_16x128b_x64_unpack16.ll | 2 +- .../probes/tcgen05_st_16x128b_x8_raw.ll | 2 +- .../probes/tcgen05_st_16x128b_x8_unpack16.ll | 2 +- .../probes/tcgen05_st_16x256b_x16_raw.ll | 2 +- .../probes/tcgen05_st_16x256b_x16_unpack16.ll | 2 +- .../probes/tcgen05_st_16x256b_x1_raw.ll | 2 +- .../probes/tcgen05_st_16x256b_x1_unpack16.ll | 2 +- .../probes/tcgen05_st_16x256b_x2_raw.ll | 2 +- .../probes/tcgen05_st_16x256b_x2_unpack16.ll | 2 +- .../probes/tcgen05_st_16x256b_x32_raw.ll | 2 +- .../probes/tcgen05_st_16x256b_x32_unpack16.ll | 2 +- .../probes/tcgen05_st_16x256b_x4_raw.ll | 2 +- .../probes/tcgen05_st_16x256b_x4_unpack16.ll | 2 +- .../probes/tcgen05_st_16x256b_x8_raw.ll | 2 +- .../probes/tcgen05_st_16x256b_x8_unpack16.ll | 2 +- .../probes/tcgen05_st_16x32bx2_x128_raw.ll | 2 +- .../tcgen05_st_16x32bx2_x128_unpack16.ll | 2 +- .../probes/tcgen05_st_16x32bx2_x16_raw.ll | 2 +- .../tcgen05_st_16x32bx2_x16_unpack16.ll | 2 +- .../probes/tcgen05_st_16x32bx2_x1_raw.ll | 2 +- .../probes/tcgen05_st_16x32bx2_x1_unpack16.ll | 2 +- .../probes/tcgen05_st_16x32bx2_x2_raw.ll | 2 +- .../probes/tcgen05_st_16x32bx2_x2_unpack16.ll | 2 +- .../probes/tcgen05_st_16x32bx2_x32_raw.ll | 2 +- .../tcgen05_st_16x32bx2_x32_unpack16.ll | 2 +- .../probes/tcgen05_st_16x32bx2_x4_raw.ll | 2 +- .../probes/tcgen05_st_16x32bx2_x4_unpack16.ll | 2 +- .../probes/tcgen05_st_16x32bx2_x64_raw.ll | 2 +- .../tcgen05_st_16x32bx2_x64_unpack16.ll | 2 +- .../probes/tcgen05_st_16x32bx2_x8_raw.ll | 2 +- .../probes/tcgen05_st_16x32bx2_x8_unpack16.ll | 2 +- .../probes/tcgen05_st_16x64b_x128_raw.ll | 2 +- .../probes/tcgen05_st_16x64b_x128_unpack16.ll | 2 +- .../probes/tcgen05_st_16x64b_x16_raw.ll | 2 +- .../probes/tcgen05_st_16x64b_x16_unpack16.ll | 2 +- intrinsics/probes/tcgen05_st_16x64b_x1_raw.ll | 2 +- .../probes/tcgen05_st_16x64b_x1_unpack16.ll | 2 +- intrinsics/probes/tcgen05_st_16x64b_x2_raw.ll | 2 +- .../probes/tcgen05_st_16x64b_x2_unpack16.ll | 2 +- .../probes/tcgen05_st_16x64b_x32_raw.ll | 2 +- .../probes/tcgen05_st_16x64b_x32_unpack16.ll | 2 +- intrinsics/probes/tcgen05_st_16x64b_x4_raw.ll | 2 +- .../probes/tcgen05_st_16x64b_x4_unpack16.ll | 2 +- .../probes/tcgen05_st_16x64b_x64_raw.ll | 2 +- .../probes/tcgen05_st_16x64b_x64_unpack16.ll | 2 +- intrinsics/probes/tcgen05_st_16x64b_x8_raw.ll | 2 +- .../probes/tcgen05_st_16x64b_x8_unpack16.ll | 2 +- .../probes/tcgen05_st_32x32b_x128_raw.ll | 2 +- .../probes/tcgen05_st_32x32b_x128_unpack16.ll | 2 +- .../probes/tcgen05_st_32x32b_x16_raw.ll | 2 +- .../probes/tcgen05_st_32x32b_x16_unpack16.ll | 2 +- intrinsics/probes/tcgen05_st_32x32b_x1_raw.ll | 2 +- .../probes/tcgen05_st_32x32b_x1_unpack16.ll | 2 +- intrinsics/probes/tcgen05_st_32x32b_x2_raw.ll | 2 +- .../probes/tcgen05_st_32x32b_x2_unpack16.ll | 2 +- .../probes/tcgen05_st_32x32b_x32_raw.ll | 2 +- .../probes/tcgen05_st_32x32b_x32_unpack16.ll | 2 +- intrinsics/probes/tcgen05_st_32x32b_x4_raw.ll | 2 +- .../probes/tcgen05_st_32x32b_x4_unpack16.ll | 2 +- .../probes/tcgen05_st_32x32b_x64_raw.ll | 2 +- .../probes/tcgen05_st_32x32b_x64_unpack16.ll | 2 +- intrinsics/probes/tcgen05_st_32x32b_x8_raw.ll | 2 +- .../probes/tcgen05_st_32x32b_x8_unpack16.ll | 2 +- intrinsics/probes/tcgen05_store_wait.ll | 2 +- .../probes/tensormap_replace_box_dim.ll | 2 +- .../tensormap_replace_element_stride.ll | 2 +- .../probes/tensormap_replace_element_type.ll | 2 +- .../probes/tensormap_replace_fill_mode.ll | 2 +- .../tensormap_replace_global_address.ll | 2 +- .../probes/tensormap_replace_global_dim.ll | 2 +- .../probes/tensormap_replace_global_stride.ll | 2 +- .../tensormap_replace_interleave_layout.ll | 2 +- intrinsics/probes/tensormap_replace_rank.ll | 2 +- .../tensormap_replace_swizzle_atomicity.ll | 2 +- .../probes/tensormap_replace_swizzle_mode.ll | 2 +- intrinsics/probes/thread_idx_x.ll | 2 +- intrinsics/probes/thread_idx_y.ll | 2 +- intrinsics/probes/thread_idx_z.ll | 2 +- intrinsics/probes/threadfence.ll | 2 +- intrinsics/probes/threadfence_block.ll | 2 +- intrinsics/probes/threadfence_system.ll | 2 +- intrinsics/probes/total_smem_size.lib_nvvm.ll | 2 +- .../probes/total_smem_size.llvm_nvptx.ll | 2 +- intrinsics/probes/trap.ll | 2 +- intrinsics/probes/uni_sync.ll | 2 +- intrinsics/probes/warpid.lib_nvvm.ll | 2 +- intrinsics/probes/warpid.llvm_nvptx.ll | 2 +- intrinsics/probes/wgmma_commit_group.ll | 2 +- intrinsics/probes/wgmma_fence.ll | 2 +- intrinsics/probes/wgmma_wait_group.ll | 2 +- 1141 files changed, 11211 insertions(+), 1157 deletions(-) create mode 100644 crates/cuda-device/src/generated/barrier_reduction.rs create mode 100644 crates/dialect-nvvm/src/ops/generated/barrier_reduction.rs create mode 100644 crates/mir-lower/src/convert/intrinsics/barrier_reduction.rs create mode 100644 intrinsics/evidence/cuda-12.9-libnvvm-12.9.86-barrier-reduction.json create mode 100644 intrinsics/evidence/cuda-12.9-libnvvm-12.9.86-execution-control.json create mode 100644 intrinsics/evidence/rust-llvm-22.1.2-1cb4e383-barrier-reduction.json create mode 100644 intrinsics/overlay/barrier_reduction.toml create mode 100644 intrinsics/probes/barrier_cta_red_and_aligned_all.ll create mode 100644 intrinsics/probes/barrier_cta_red_and_aligned_count.ll create mode 100644 intrinsics/probes/barrier_cta_red_and_all.ll create mode 100644 intrinsics/probes/barrier_cta_red_and_count.ll create mode 100644 intrinsics/probes/barrier_cta_red_or_aligned_all.ll create mode 100644 intrinsics/probes/barrier_cta_red_or_aligned_count.ll create mode 100644 intrinsics/probes/barrier_cta_red_or_all.ll create mode 100644 intrinsics/probes/barrier_cta_red_or_count.ll create mode 100644 intrinsics/probes/barrier_cta_red_popc_aligned_all.ll create mode 100644 intrinsics/probes/barrier_cta_red_popc_aligned_count.ll create mode 100644 intrinsics/probes/barrier_cta_red_popc_all.ll create mode 100644 intrinsics/probes/barrier_cta_red_popc_count.ll create mode 100644 intrinsics/probes/barrier_cta_sync_all.ll diff --git a/crates/cuda-device/src/barrier.rs b/crates/cuda-device/src/barrier.rs index 4fda977a61..8a4d39dc00 100644 --- a/crates/cuda-device/src/barrier.rs +++ b/crates/cuda-device/src/barrier.rs @@ -105,6 +105,7 @@ impl Barrier { include!("generated/mbarrier_basic.rs"); include!("generated/mbarrier_extended.rs"); include!("generated/counted_barrier.rs"); +include!("generated/barrier_reduction.rs"); // ============================================================================= // Barrier Arrive Operations diff --git a/crates/cuda-device/src/generated/async_copy.rs b/crates/cuda-device/src/generated/async_copy.rs index 0e1579499b..e7278d1440 100644 --- a/crates/cuda-device/src/generated/async_copy.rs +++ b/crates/cuda-device/src/generated/async_copy.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. // LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. // Included inside `cuda_device::async_copy` to keep existing paths stable. diff --git a/crates/cuda-device/src/generated/atomic.rs b/crates/cuda-device/src/generated/atomic.rs index c5d2af23c3..fe9d5ab595 100644 --- a/crates/cuda-device/src/generated/atomic.rs +++ b/crates/cuda-device/src/generated/atomic.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. // LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. // Included inside `cuda_device::atomic` to keep existing paths stable. diff --git a/crates/cuda-device/src/generated/barrier_reduction.rs b/crates/cuda-device/src/generated/barrier_reduction.rs new file mode 100644 index 0000000000..810f257c1b --- /dev/null +++ b/crates/cuda-device/src/generated/barrier_reduction.rs @@ -0,0 +1,160 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: Apache-2.0 + */ + +// @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. +// LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. + +// Included inside `cuda_device::barrier`. + +/// Reduces predicates with AND while synchronizing all arriving CTA threads at an aligned numbered barrier. +/// +/// # Safety +/// All participating threads must use a compatible barrier protocol. +#[inline(never)] +pub unsafe fn barrier_cta_red_and_aligned_all(barrier_id: u32, predicate: bool) -> bool { + let _ = (barrier_id, predicate); + unreachable!("barrier_cta_red_and_aligned_all called outside CUDA kernel context") +} + +/// Reduces predicates with AND while synchronizing the requested number of CTA threads at an aligned numbered barrier. +/// +/// # Safety +/// All participating threads must use a compatible barrier protocol. +#[inline(never)] +pub unsafe fn barrier_cta_red_and_aligned_count( + barrier_id: u32, + thread_count: u32, + predicate: bool, +) -> bool { + let _ = (barrier_id, predicate); + let _ = thread_count; + unreachable!("barrier_cta_red_and_aligned_count called outside CUDA kernel context") +} + +/// Reduces predicates with AND while synchronizing all arriving CTA threads at a numbered barrier. +/// +/// # Safety +/// All participating threads must use a compatible barrier protocol. +#[inline(never)] +pub unsafe fn barrier_cta_red_and_all(barrier_id: u32, predicate: bool) -> bool { + let _ = (barrier_id, predicate); + unreachable!("barrier_cta_red_and_all called outside CUDA kernel context") +} + +/// Reduces predicates with AND while synchronizing the requested number of CTA threads at a numbered barrier. +/// +/// # Safety +/// All participating threads must use a compatible barrier protocol. +#[inline(never)] +pub unsafe fn barrier_cta_red_and_count( + barrier_id: u32, + thread_count: u32, + predicate: bool, +) -> bool { + let _ = (barrier_id, predicate); + let _ = thread_count; + unreachable!("barrier_cta_red_and_count called outside CUDA kernel context") +} + +/// Reduces predicates with OR while synchronizing all arriving CTA threads at an aligned numbered barrier. +/// +/// # Safety +/// All participating threads must use a compatible barrier protocol. +#[inline(never)] +pub unsafe fn barrier_cta_red_or_aligned_all(barrier_id: u32, predicate: bool) -> bool { + let _ = (barrier_id, predicate); + unreachable!("barrier_cta_red_or_aligned_all called outside CUDA kernel context") +} + +/// Reduces predicates with OR while synchronizing the requested number of CTA threads at an aligned numbered barrier. +/// +/// # Safety +/// All participating threads must use a compatible barrier protocol. +#[inline(never)] +pub unsafe fn barrier_cta_red_or_aligned_count( + barrier_id: u32, + thread_count: u32, + predicate: bool, +) -> bool { + let _ = (barrier_id, predicate); + let _ = thread_count; + unreachable!("barrier_cta_red_or_aligned_count called outside CUDA kernel context") +} + +/// Reduces predicates with OR while synchronizing all arriving CTA threads at a numbered barrier. +/// +/// # Safety +/// All participating threads must use a compatible barrier protocol. +#[inline(never)] +pub unsafe fn barrier_cta_red_or_all(barrier_id: u32, predicate: bool) -> bool { + let _ = (barrier_id, predicate); + unreachable!("barrier_cta_red_or_all called outside CUDA kernel context") +} + +/// Reduces predicates with OR while synchronizing the requested number of CTA threads at a numbered barrier. +/// +/// # Safety +/// All participating threads must use a compatible barrier protocol. +#[inline(never)] +pub unsafe fn barrier_cta_red_or_count( + barrier_id: u32, + thread_count: u32, + predicate: bool, +) -> bool { + let _ = (barrier_id, predicate); + let _ = thread_count; + unreachable!("barrier_cta_red_or_count called outside CUDA kernel context") +} + +/// Counts true predicates while synchronizing all arriving CTA threads at an aligned numbered barrier. +/// +/// # Safety +/// All participating threads must use a compatible barrier protocol. +#[inline(never)] +pub unsafe fn barrier_cta_red_popc_aligned_all(barrier_id: u32, predicate: bool) -> u32 { + let _ = (barrier_id, predicate); + unreachable!("barrier_cta_red_popc_aligned_all called outside CUDA kernel context") +} + +/// Counts true predicates while synchronizing the requested number of CTA threads at an aligned numbered barrier. +/// +/// # Safety +/// All participating threads must use a compatible barrier protocol. +#[inline(never)] +pub unsafe fn barrier_cta_red_popc_aligned_count( + barrier_id: u32, + thread_count: u32, + predicate: bool, +) -> u32 { + let _ = (barrier_id, predicate); + let _ = thread_count; + unreachable!("barrier_cta_red_popc_aligned_count called outside CUDA kernel context") +} + +/// Counts true predicates while synchronizing all arriving CTA threads at a numbered barrier. +/// +/// # Safety +/// All participating threads must use a compatible barrier protocol. +#[inline(never)] +pub unsafe fn barrier_cta_red_popc_all(barrier_id: u32, predicate: bool) -> u32 { + let _ = (barrier_id, predicate); + unreachable!("barrier_cta_red_popc_all called outside CUDA kernel context") +} + +/// Counts true predicates while synchronizing the requested number of CTA threads at a numbered barrier. +/// +/// # Safety +/// All participating threads must use a compatible barrier protocol. +#[inline(never)] +pub unsafe fn barrier_cta_red_popc_count( + barrier_id: u32, + thread_count: u32, + predicate: bool, +) -> u32 { + let _ = (barrier_id, predicate); + let _ = thread_count; + unreachable!("barrier_cta_red_popc_count called outside CUDA kernel context") +} diff --git a/crates/cuda-device/src/generated/bf16.rs b/crates/cuda-device/src/generated/bf16.rs index a1e65cb521..baad8b7921 100644 --- a/crates/cuda-device/src/generated/bf16.rs +++ b/crates/cuda-device/src/generated/bf16.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. // LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. // Included inside `cuda_device::bf16` to keep existing paths stable. diff --git a/crates/cuda-device/src/generated/bf16x2.rs b/crates/cuda-device/src/generated/bf16x2.rs index 6af9552315..8fff361708 100644 --- a/crates/cuda-device/src/generated/bf16x2.rs +++ b/crates/cuda-device/src/generated/bf16x2.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. // LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. // Included inside `cuda_device::bf16x2` to keep existing paths stable. diff --git a/crates/cuda-device/src/generated/clc.rs b/crates/cuda-device/src/generated/clc.rs index 32a5f4704c..80c81164be 100644 --- a/crates/cuda-device/src/generated/clc.rs +++ b/crates/cuda-device/src/generated/clc.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. // LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. // Included inside `cuda_device::clc` to keep its public API stable. diff --git a/crates/cuda-device/src/generated/cluster_barrier.rs b/crates/cuda-device/src/generated/cluster_barrier.rs index a8345299bf..2bec9e0a72 100644 --- a/crates/cuda-device/src/generated/cluster_barrier.rs +++ b/crates/cuda-device/src/generated/cluster_barrier.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. // LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. // Included inside `cuda_device::cluster` to keep public paths stable. diff --git a/crates/cuda-device/src/generated/cluster_memory.rs b/crates/cuda-device/src/generated/cluster_memory.rs index 8c98654e72..6247809ec0 100644 --- a/crates/cuda-device/src/generated/cluster_memory.rs +++ b/crates/cuda-device/src/generated/cluster_memory.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. // LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. // Included inside `cuda_device::cluster` to keep its public API stable. diff --git a/crates/cuda-device/src/generated/cluster_sreg.rs b/crates/cuda-device/src/generated/cluster_sreg.rs index c772a1baaa..3dee50ebf0 100644 --- a/crates/cuda-device/src/generated/cluster_sreg.rs +++ b/crates/cuda-device/src/generated/cluster_sreg.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. // LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. // This file is included inside `cuda_device::cluster`. diff --git a/crates/cuda-device/src/generated/convert.rs b/crates/cuda-device/src/generated/convert.rs index e83dfbceb8..b53fa39e11 100644 --- a/crates/cuda-device/src/generated/convert.rs +++ b/crates/cuda-device/src/generated/convert.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. // LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. // Included inside `cuda_device::convert`. diff --git a/crates/cuda-device/src/generated/counted_barrier.rs b/crates/cuda-device/src/generated/counted_barrier.rs index c615692d92..f7dc45ad2a 100644 --- a/crates/cuda-device/src/generated/counted_barrier.rs +++ b/crates/cuda-device/src/generated/counted_barrier.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. // LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. // Included inside `cuda_device::barrier` to keep its public API stable. @@ -12,7 +12,7 @@ /// Signals arrival of the requested number of CTA threads at a numbered barrier without waiting. /// /// # Safety -/// Every participating thread must use a compatible barrier ID and expected thread count. +/// Every participating thread must use a compatible barrier protocol. #[inline(never)] pub unsafe fn barrier_cta_arrive(barrier_id: u32, thread_count: u32) { let _ = (barrier_id, thread_count); @@ -22,7 +22,7 @@ pub unsafe fn barrier_cta_arrive(barrier_id: u32, thread_count: u32) { /// Signals arrival of the requested number of CTA threads at an aligned numbered barrier without waiting. /// /// # Safety -/// Every participating thread must use a compatible barrier ID and expected thread count. +/// Every participating thread must use a compatible barrier protocol. #[inline(never)] pub unsafe fn barrier_cta_arrive_aligned(barrier_id: u32, thread_count: u32) { let _ = (barrier_id, thread_count); @@ -32,7 +32,7 @@ pub unsafe fn barrier_cta_arrive_aligned(barrier_id: u32, thread_count: u32) { /// Synchronizes the requested number of CTA threads at a numbered barrier. /// /// # Safety -/// Every participating thread must use a compatible barrier ID and expected thread count. +/// Every participating thread must use a compatible barrier protocol. #[inline(never)] pub unsafe fn barrier_cta_sync(barrier_id: u32, thread_count: u32) { let _ = (barrier_id, thread_count); @@ -42,9 +42,19 @@ pub unsafe fn barrier_cta_sync(barrier_id: u32, thread_count: u32) { /// Synchronizes the requested number of CTA threads at an aligned numbered barrier. /// /// # Safety -/// Every participating thread must use a compatible barrier ID and expected thread count. +/// Every participating thread must use a compatible barrier protocol. #[inline(never)] pub unsafe fn barrier_cta_sync_aligned(barrier_id: u32, thread_count: u32) { let _ = (barrier_id, thread_count); unreachable!("barrier_cta_sync_aligned called outside CUDA kernel context") } + +/// Synchronizes all arriving CTA threads at a numbered barrier. +/// +/// # Safety +/// Every participating thread must use a compatible barrier protocol. +#[inline(never)] +pub unsafe fn barrier_cta_sync_all(barrier_id: u32) { + let _ = barrier_id; + unreachable!("barrier_cta_sync_all called outside CUDA kernel context") +} diff --git a/crates/cuda-device/src/generated/debug_control.rs b/crates/cuda-device/src/generated/debug_control.rs index 873ceaafd8..352382f590 100644 --- a/crates/cuda-device/src/generated/debug_control.rs +++ b/crates/cuda-device/src/generated/debug_control.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. // LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. // Included inside `cuda_device::debug` to keep its public API stable. diff --git a/crates/cuda-device/src/generated/debug_sreg.rs b/crates/cuda-device/src/generated/debug_sreg.rs index 75ab6e802a..16064b7a71 100644 --- a/crates/cuda-device/src/generated/debug_sreg.rs +++ b/crates/cuda-device/src/generated/debug_sreg.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. // LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. // Included inside `cuda_device::debug` to keep existing paths stable. diff --git a/crates/cuda-device/src/generated/dotprod.rs b/crates/cuda-device/src/generated/dotprod.rs index 9fd56c6dfa..412832fd23 100644 --- a/crates/cuda-device/src/generated/dotprod.rs +++ b/crates/cuda-device/src/generated/dotprod.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. // LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. // Included inside `cuda_device::dotprod` to keep existing paths stable. diff --git a/crates/cuda-device/src/generated/f16.rs b/crates/cuda-device/src/generated/f16.rs index 9a6dc65665..459087d73f 100644 --- a/crates/cuda-device/src/generated/f16.rs +++ b/crates/cuda-device/src/generated/f16.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. // LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. // Included inside `cuda_device::f16` to keep existing paths stable. diff --git a/crates/cuda-device/src/generated/f16x2.rs b/crates/cuda-device/src/generated/f16x2.rs index 4fccacc281..8c3e19a7fc 100644 --- a/crates/cuda-device/src/generated/f16x2.rs +++ b/crates/cuda-device/src/generated/f16x2.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. // LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. // Included inside `cuda_device::f16x2` to keep existing paths stable. diff --git a/crates/cuda-device/src/generated/f32x2.rs b/crates/cuda-device/src/generated/f32x2.rs index ded5b91222..945b540c2a 100644 --- a/crates/cuda-device/src/generated/f32x2.rs +++ b/crates/cuda-device/src/generated/f32x2.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. // LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. // Included inside `cuda_device::f32x2` to keep existing paths stable. diff --git a/crates/cuda-device/src/generated/fence.rs b/crates/cuda-device/src/generated/fence.rs index feffc30477..870f6fb5cd 100644 --- a/crates/cuda-device/src/generated/fence.rs +++ b/crates/cuda-device/src/generated/fence.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. // LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. // This file is included inside `cuda_device::fence` so existing paths stay stable. diff --git a/crates/cuda-device/src/generated/float.rs b/crates/cuda-device/src/generated/float.rs index 2ffabef93d..7d9263d6d3 100644 --- a/crates/cuda-device/src/generated/float.rs +++ b/crates/cuda-device/src/generated/float.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. // LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. // Included inside `cuda_device::float`. diff --git a/crates/cuda-device/src/generated/grid_dependency.rs b/crates/cuda-device/src/generated/grid_dependency.rs index 5a66908874..9e24a11876 100644 --- a/crates/cuda-device/src/generated/grid_dependency.rs +++ b/crates/cuda-device/src/generated/grid_dependency.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. // LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. // Included inside `cuda_device::grid` to keep its public API stable. diff --git a/crates/cuda-device/src/generated/grid_sreg.rs b/crates/cuda-device/src/generated/grid_sreg.rs index f8f0c863e3..3fd8d35897 100644 --- a/crates/cuda-device/src/generated/grid_sreg.rs +++ b/crates/cuda-device/src/generated/grid_sreg.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. // LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. // Included inside `cuda_device::grid` to keep existing paths stable. diff --git a/crates/cuda-device/src/generated/i16x2.rs b/crates/cuda-device/src/generated/i16x2.rs index 0dfeebf5ac..9a6eb3dd3d 100644 --- a/crates/cuda-device/src/generated/i16x2.rs +++ b/crates/cuda-device/src/generated/i16x2.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. // LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. // Included inside `cuda_device::i16x2` to keep existing paths stable. diff --git a/crates/cuda-device/src/generated/int.rs b/crates/cuda-device/src/generated/int.rs index b7a048ea3d..3ee7ce4c82 100644 --- a/crates/cuda-device/src/generated/int.rs +++ b/crates/cuda-device/src/generated/int.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. // LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. // Included inside `cuda_device::int` to keep existing paths stable. diff --git a/crates/cuda-device/src/generated/ldmatrix.rs b/crates/cuda-device/src/generated/ldmatrix.rs index 4ca2bc0211..87ab83db6d 100644 --- a/crates/cuda-device/src/generated/ldmatrix.rs +++ b/crates/cuda-device/src/generated/ldmatrix.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. // LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. // Included inside `cuda_device::wmma` to keep public paths stable. diff --git a/crates/cuda-device/src/generated/mbarrier_basic.rs b/crates/cuda-device/src/generated/mbarrier_basic.rs index 6613fb4771..36b6848838 100644 --- a/crates/cuda-device/src/generated/mbarrier_basic.rs +++ b/crates/cuda-device/src/generated/mbarrier_basic.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. // LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. // Included inside `cuda_device::barrier` to keep existing paths stable. diff --git a/crates/cuda-device/src/generated/mbarrier_extended.rs b/crates/cuda-device/src/generated/mbarrier_extended.rs index 69e618fda9..a73d77d8be 100644 --- a/crates/cuda-device/src/generated/mbarrier_extended.rs +++ b/crates/cuda-device/src/generated/mbarrier_extended.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. // LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. // Included inside `cuda_device::barrier` to keep existing paths stable. diff --git a/crates/cuda-device/src/generated/movmatrix.rs b/crates/cuda-device/src/generated/movmatrix.rs index f72d284ba4..37eb817a46 100644 --- a/crates/cuda-device/src/generated/movmatrix.rs +++ b/crates/cuda-device/src/generated/movmatrix.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. // LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. // Included inside `cuda_device::wmma` to keep its public API stable. diff --git a/crates/cuda-device/src/generated/prmt.rs b/crates/cuda-device/src/generated/prmt.rs index cd5c1445a7..53030d3da3 100644 --- a/crates/cuda-device/src/generated/prmt.rs +++ b/crates/cuda-device/src/generated/prmt.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. // LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. // Included inside `cuda_device::prmt` to keep the public paths stable. diff --git a/crates/cuda-device/src/generated/register_control.rs b/crates/cuda-device/src/generated/register_control.rs index 40acc6bdcc..3667fc6bd9 100644 --- a/crates/cuda-device/src/generated/register_control.rs +++ b/crates/cuda-device/src/generated/register_control.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. // LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. // Included inside `cuda_device::thread` to keep its public API stable. diff --git a/crates/cuda-device/src/generated/register_mma.rs b/crates/cuda-device/src/generated/register_mma.rs index e843ef12ac..f9234f66d7 100644 --- a/crates/cuda-device/src/generated/register_mma.rs +++ b/crates/cuda-device/src/generated/register_mma.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. // LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. // Included inside `cuda_device::wmma` to keep public paths stable. diff --git a/crates/cuda-device/src/generated/shared_sreg.rs b/crates/cuda-device/src/generated/shared_sreg.rs index 088209f651..d66c98b03b 100644 --- a/crates/cuda-device/src/generated/shared_sreg.rs +++ b/crates/cuda-device/src/generated/shared_sreg.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. // LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. // Included inside `cuda_device::shared` to keep existing paths stable. diff --git a/crates/cuda-device/src/generated/sparse_mma.rs b/crates/cuda-device/src/generated/sparse_mma.rs index 854a3c4cbd..f11c3d8ebf 100644 --- a/crates/cuda-device/src/generated/sparse_mma.rs +++ b/crates/cuda-device/src/generated/sparse_mma.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. // LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. // Included inside `cuda_device::wmma` to keep public paths stable. diff --git a/crates/cuda-device/src/generated/sreg.rs b/crates/cuda-device/src/generated/sreg.rs index b190c4e0fb..5a8f8f3294 100644 --- a/crates/cuda-device/src/generated/sreg.rs +++ b/crates/cuda-device/src/generated/sreg.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. // LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. // This file is included lexically inside `cuda_device::thread` so existing diff --git a/crates/cuda-device/src/generated/stmatrix.rs b/crates/cuda-device/src/generated/stmatrix.rs index 6d7b93b689..960ff0129e 100644 --- a/crates/cuda-device/src/generated/stmatrix.rs +++ b/crates/cuda-device/src/generated/stmatrix.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. // LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. // Included inside `cuda_device::tcgen05` to keep public paths stable. diff --git a/crates/cuda-device/src/generated/tcgen05.rs b/crates/cuda-device/src/generated/tcgen05.rs index 6bc1ec25a2..e4c7d3db47 100644 --- a/crates/cuda-device/src/generated/tcgen05.rs +++ b/crates/cuda-device/src/generated/tcgen05.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. // LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. // Included inside `cuda_device::tcgen05` to keep its public API stable. diff --git a/crates/cuda-device/src/generated/tma.rs b/crates/cuda-device/src/generated/tma.rs index 5932a32256..b0d38bffba 100644 --- a/crates/cuda-device/src/generated/tma.rs +++ b/crates/cuda-device/src/generated/tma.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. // LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. // Included inside `cuda_device::tma` to keep its public API stable. diff --git a/crates/cuda-device/src/generated/warp_sreg.rs b/crates/cuda-device/src/generated/warp_sreg.rs index 0d6fe6ada4..861f60c9c4 100644 --- a/crates/cuda-device/src/generated/warp_sreg.rs +++ b/crates/cuda-device/src/generated/warp_sreg.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. // LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. // Included inside `cuda_device::warp` to keep existing paths stable. diff --git a/crates/cuda-device/src/generated/wgmma_control.rs b/crates/cuda-device/src/generated/wgmma_control.rs index fe9838d5ab..7626f30ca3 100644 --- a/crates/cuda-device/src/generated/wgmma_control.rs +++ b/crates/cuda-device/src/generated/wgmma_control.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. // LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. // Included inside `cuda_device::wgmma` to keep its public API stable. diff --git a/crates/cuda-intrinsics-gen/src/model.rs b/crates/cuda-intrinsics-gen/src/model.rs index 6f7c071693..1fab08d384 100644 --- a/crates/cuda-intrinsics-gen/src/model.rs +++ b/crates/cuda-intrinsics-gen/src/model.rs @@ -1826,6 +1826,7 @@ pub enum ExecutionControlOperation { BarrierCtaSyncAligned, BarrierCtaArrive, BarrierCtaArriveAligned, + BarrierCtaSyncAll, GridDependencyLaunchDependents, GridDependencyWait, SetMaxNRegInc, @@ -1839,6 +1840,7 @@ impl ExecutionControlOperation { "barrier_cta_sync_aligned" => Self::BarrierCtaSyncAligned, "barrier_cta_arrive" => Self::BarrierCtaArrive, "barrier_cta_arrive_aligned" => Self::BarrierCtaArriveAligned, + "barrier_cta_sync_all" => Self::BarrierCtaSyncAll, "grid_dependency_launch_dependents" => Self::GridDependencyLaunchDependents, "grid_dependency_wait" => Self::GridDependencyWait, "setmaxnreg_inc" => Self::SetMaxNRegInc, @@ -1853,6 +1855,7 @@ impl ExecutionControlOperation { | Self::BarrierCtaSyncAligned | Self::BarrierCtaArrive | Self::BarrierCtaArriveAligned => "counted_barrier", + Self::BarrierCtaSyncAll => "counted_barrier", Self::GridDependencyLaunchDependents | Self::GridDependencyWait => "grid_dependency", Self::SetMaxNRegInc | Self::SetMaxNRegDec => "register_control", } @@ -1864,6 +1867,7 @@ impl ExecutionControlOperation { | Self::BarrierCtaSyncAligned | Self::BarrierCtaArrive | Self::BarrierCtaArriveAligned => 2, + Self::BarrierCtaSyncAll => 1, Self::GridDependencyLaunchDependents | Self::GridDependencyWait => 0, Self::SetMaxNRegInc | Self::SetMaxNRegDec => 1, } diff --git a/crates/cuda-intrinsics-gen/src/probe.rs b/crates/cuda-intrinsics-gen/src/probe.rs index a063908ca8..80b953da72 100644 --- a/crates/cuda-intrinsics-gen/src/probe.rs +++ b/crates/cuda-intrinsics-gen/src/probe.rs @@ -748,7 +748,18 @@ fn validate_probe_instructions(record: &CatalogIntrinsic, ptx: &str) -> Result<( validate_register_and_immediate_forms(&record.expected_ptx, 1, "-1", ptx)?; } if record.family == "counted_barrier" { - validate_two_register_and_immediate_forms(&record.expected_ptx, 0, "1", 1, "32", ptx)?; + if record.id == "barrier_cta_sync_all" { + validate_register_and_immediate_forms(&record.expected_ptx, 0, "1", ptx)?; + } else { + validate_two_register_and_immediate_forms(&record.expected_ptx, 0, "1", 1, "32", ptx)?; + } + } + if record.family == "barrier_reduction" { + if record.rust.arguments.len() == 2 { + validate_register_and_immediate_forms(&record.expected_ptx, 1, "1", ptx)?; + } else { + validate_two_register_and_immediate_forms(&record.expected_ptx, 1, "1", 2, "32", ptx)?; + } } if record.warp_barrier.is_some() { validate_register_and_immediate_forms(&record.expected_ptx, 0, "-1", ptx)?; diff --git a/crates/cuda-intrinsics-gen/src/render.rs b/crates/cuda-intrinsics-gen/src/render.rs index 482ee17bf3..ef3c6b1ef7 100644 --- a/crates/cuda-intrinsics-gen/src/render.rs +++ b/crates/cuda-intrinsics-gen/src/render.rs @@ -353,6 +353,16 @@ pub fn all_outputs( "crates/dialect-nvvm/src/ops/generated/vote.rs".into(), render_dialect_vote(catalog, catalog_sha256), ); + if barrier_reductions(catalog).next().is_some() { + outputs.insert( + "crates/cuda-device/src/generated/barrier_reduction.rs".into(), + render_compat_barrier_reduction(catalog, catalog_sha256), + ); + outputs.insert( + "crates/dialect-nvvm/src/ops/generated/barrier_reduction.rs".into(), + render_dialect_barrier_reduction(catalog, catalog_sha256), + ); + } outputs.insert( "crates/dialect-nvvm/src/ops/generated/active_mask.rs".into(), render_dialect_active_mask(catalog, catalog_sha256), @@ -477,6 +487,7 @@ fn validate_renderable(catalog: &CatalogFile) -> Result<()> { record.family.as_str(), "counted_barrier" | "grid_dependency" | "register_control" ) + || record.family == "barrier_reduction" || record.family == "sync", "{} is unsafe but has no dedicated family safety renderer", record.id @@ -1350,6 +1361,12 @@ fn validate_renderable(catalog: &CatalogFile) -> Result<()> { llvm.arguments == ["i32", "i32"] }) } + ExecutionControlOperation::BarrierCtaSyncAll => { + record.rust.module == "barrier" + && record.rust.arguments == ["u32"] + && record.dialect.operands == ["i32"] + && record.llvm.as_ref().is_some_and(|llvm| llvm.arguments == ["i32"]) + } ExecutionControlOperation::GridDependencyLaunchDependents | ExecutionControlOperation::GridDependencyWait => { record.rust.module == "grid" @@ -1375,6 +1392,16 @@ fn validate_renderable(catalog: &CatalogFile) -> Result<()> { "{} is outside the closed generated execution-control recipe", record.id ), + "barrier_reduction" => ensure!( + record.rust.module == "barrier" + && !record.rust.safe + && record.rust.must_use + && record.dialect.results.len() == 1 + && record.llvm.as_ref().is_some_and(|llvm| llvm.results.len() == 1) + && record.lowering == "generated_barrier_reduction", + "{} is outside the closed barrier-reduction recipe", + record.id + ), "tcgen05" => ensure!( tcgen05_render_contract(record), "{} is outside the closed generated tcgen05 recipe", @@ -2382,6 +2409,13 @@ fn execution_controls(catalog: &CatalogFile) -> impl Iterator impl Iterator { + catalog + .intrinsics + .iter() + .filter(|record| record.family == "barrier_reduction") +} + fn execution_control_family<'a>( catalog: &'a CatalogFile, family: &'a str, @@ -5009,6 +5043,9 @@ fn render_raw_abi(catalog: &CatalogFile, hash: &str) -> String { | ExecutionControlOperation::BarrierCtaArriveAligned => output.push_str( "/// `_arg0` must identify a CTA barrier and `_arg1` must be the compatible expected thread count used by every participant.\n", ), + ExecutionControlOperation::BarrierCtaSyncAll => output.push_str( + "/// `_arg0` must identify the same CTA barrier used by every arriving thread.\n", + ), ExecutionControlOperation::GridDependencyLaunchDependents | ExecutionControlOperation::GridDependencyWait => output.push_str( "/// The kernel launch must participate in a valid programmatic dependent-launch protocol.\n", @@ -5988,22 +6025,30 @@ fn render_compat_clc(catalog: &CatalogFile, hash: &str) -> String { fn render_compat_counted_barrier(catalog: &CatalogFile, hash: &str) -> String { assert_eq!( execution_control_family(catalog, "counted_barrier").count(), - 4 + 5 ); let mut output = rust_header(catalog, hash); output.push_str("// Included inside `cuda_device::barrier` to keep its public API stable.\n\n"); for record in execution_control_family(catalog, "counted_barrier") { writeln!(output, "/// {}", record.summary).unwrap(); - output.push_str( - "///\n/// # Safety\n/// Every participating thread must use a compatible barrier ID and expected thread count.\n#[inline(never)]\n", - ); - writeln!( - output, - "pub unsafe fn {}(barrier_id: u32, thread_count: u32) {{", - record.rust.name - ) - .unwrap(); - output.push_str(" let _ = (barrier_id, thread_count);\n"); + output.push_str("///\n/// # Safety\n/// Every participating thread must use a compatible barrier protocol.\n#[inline(never)]\n"); + if record.rust.arguments.len() == 1 { + writeln!( + output, + "pub unsafe fn {}(barrier_id: u32) {{", + record.rust.name + ) + .unwrap(); + output.push_str(" let _ = barrier_id;\n"); + } else { + writeln!( + output, + "pub unsafe fn {}(barrier_id: u32, thread_count: u32) {{", + record.rust.name + ) + .unwrap(); + output.push_str(" let _ = (barrier_id, thread_count);\n"); + } writeln!( output, " unreachable!(\"{} called outside CUDA kernel context\")", @@ -7602,6 +7647,21 @@ fn render_dialect_mod(catalog: &CatalogFile, hash: &str) -> String { " dotprod::register(ctx);\n execution_control::register(ctx);", ); } + if barrier_reductions(catalog).next().is_some() { + output = output + .replace( + "mod active_mask;", + "mod active_mask;\nmod barrier_reduction;", + ) + .replace( + "pub use active_mask::*;", + "pub use active_mask::*;\npub use barrier_reduction::*;", + ) + .replace( + " active_mask::register(ctx);", + " active_mask::register(ctx);\n barrier_reduction::register(ctx);", + ); + } if tma_intrinsics(catalog).next().is_some() { output = output .replace("mod sync;", "mod sync;\nmod tma;") @@ -11284,7 +11344,7 @@ fn render_dialect_clc(catalog: &CatalogFile, hash: &str) -> String { } fn render_dialect_execution_control(catalog: &CatalogFile, hash: &str) -> String { - assert_eq!(execution_controls(catalog).count(), 8); + assert_eq!(execution_controls(catalog).count(), 9); let mut output = rust_header(catalog, hash); output.push_str( "//! Generated counted-barrier, grid-dependency, and register-control operations.\n\nuse pliron::{\n builtin::{attributes::IntegerAttr, op_interfaces::{NOpdsInterface, NResultsInterface}, types::{IntegerType, Signedness}},\n common_traits::Verify,\n context::{Context, Ptr},\n identifier::Identifier,\n location::Located,\n op::Op,\n operation::Operation,\n result::Error,\n verify_err,\n};\nuse pliron::utils::apint::APInt;\nuse pliron_derive::pliron_op;\nuse std::num::NonZeroUsize;\n\n", @@ -11328,6 +11388,60 @@ fn render_dialect_execution_control(catalog: &CatalogFile, hash: &str) -> String output } +fn render_dialect_barrier_reduction(catalog: &CatalogFile, hash: &str) -> String { + assert_eq!(barrier_reductions(catalog).count(), 12); + let mut output = rust_header(catalog, hash); + output.push_str("//! Generated CTA barrier-reduction operations.\n\nuse pliron::{builtin::op_interfaces::{NOpdsInterface, NResultsInterface}, context::{Context, Ptr}, op::Op, operation::Operation};\nuse pliron_derive::pliron_op;\n\n"); + for record in barrier_reductions(catalog) { + let operand_count = record.dialect.operands.len(); + writeln!(output, "/// {}", record.summary).unwrap(); + writeln!(output, "#[pliron_op(\n name = {:?},\n format,\n verifier = \"succ\",\n interfaces = [NOpdsInterface<{operand_count}>, NResultsInterface<1>],\n)]", record.dialect.op_name).unwrap(); + writeln!(output, "pub struct {};", record.dialect.op_type).unwrap(); + writeln!( + output, + "\nimpl {} {{\n pub fn new(op: Ptr) -> Self {{ Self {{ op }} }}\n}}\n", + record.dialect.op_type + ) + .unwrap(); + } + output.push_str("pub(super) fn register(ctx: &mut Context) {\n"); + for record in barrier_reductions(catalog) { + writeln!(output, " {}::register(ctx);", record.dialect.op_type).unwrap(); + } + output.push_str("}\n"); + output +} + +fn render_compat_barrier_reduction(catalog: &CatalogFile, hash: &str) -> String { + let mut output = rust_header(catalog, hash); + output.push_str("// Included inside `cuda_device::barrier`.\n\n"); + for record in barrier_reductions(catalog) { + writeln!(output, "/// {}\n///\n/// # Safety\n/// All participating threads must use a compatible barrier protocol.\n#[inline(never)]", record.summary).unwrap(); + let args = if record.rust.arguments.len() == 3 { + "barrier_id: u32, thread_count: u32, predicate: bool" + } else { + "barrier_id: u32, predicate: bool" + }; + writeln!( + output, + "pub unsafe fn {}({args}) -> {} {{", + record.rust.name, record.rust.result + ) + .unwrap(); + output.push_str(" let _ = (barrier_id, predicate);\n"); + if record.rust.arguments.len() == 3 { + output.push_str(" let _ = thread_count;\n"); + } + writeln!( + output, + " unreachable!(\"{} called outside CUDA kernel context\")\n}}\n", + record.rust.name + ) + .unwrap(); + } + output +} + fn render_dialect_tma(catalog: &CatalogFile, hash: &str) -> String { let mut output = rust_header(catalog, hash); output.push_str( @@ -12252,6 +12366,10 @@ fn render_importer(catalog: &CatalogFile, hash: &str) -> String { output.push_str(", "); output.push_str(&record.dialect.op_type); } + for record in barrier_reductions(catalog) { + output.push_str(", "); + output.push_str(&record.dialect.op_type); + } if wgmma_controls(catalog).next().is_some() { output.push_str( ", WgmmaCommitGroupSyncAlignedOp, WgmmaFenceSyncAlignedOp, WgmmaWaitGroupSyncAlignedOp", @@ -12945,6 +13063,37 @@ fn render_importer(catalog: &CatalogFile, hash: &str) -> String { .unwrap(); output.push_str(" }\n"); } + for record in barrier_reductions(catalog) { + let mut path_refs = vec![record.rust.canonical_path.as_str()]; + path_refs.extend(record.rust.compatibility_paths.iter().map(String::as_str)); + output.push_str(" "); + render_inline_patterns(&mut output, &path_refs); + output.push_str(" => {\n"); + writeln!( + output, + " require_arity(name, args.len(), {}, &loc)?;", + record.rust.arguments.len() + ) + .unwrap(); + output.push_str(" let mut last_op = prev_op;\n let mut operands = Vec::with_capacity(args.len());\n for arg in args {\n let (value, translated) = rvalue::translate_operand(ctx, body, arg, value_map, block_ptr, last_op, loc.clone())?;\n last_op = translated;\n operands.push(value);\n }\n"); + let (width, signedness) = if record.rust.result == "bool" { + (1, "Signless") + } else { + (32, "Unsigned") + }; + writeln!(output, " let result_ty = pliron::builtin::types::IntegerType::get(ctx, {width}, pliron::builtin::types::Signedness::{signedness});").unwrap(); + writeln!(output, " let reduction = Operation::new(ctx, {}::get_concrete_op_info(), vec![result_ty.into()], operands, vec![], 0);", record.dialect.op_type).unwrap(); + output.push_str(" reduction.deref_mut(ctx).set_loc(loc.clone());\n"); + writeln!( + output, + " helpers::set_generated_intrinsic_marker(ctx, reduction, {:?});", + intrinsic_marker(catalog, record) + ) + .unwrap(); + output.push_str(" helpers::insert_op(ctx, reduction, block_ptr, last_op);\n let result = reduction.deref(ctx).get_result(0);\n"); + writeln!(output, " Ok(Some(helpers::emit_store_result_and_goto(ctx, destination, result, target, block_ptr, reduction, value_map, block_map, loc, {:?})?))", format!("{} call without target block", record.rust.name)).unwrap(); + output.push_str(" }\n"); + } for record in warp_matches(catalog) { let mut path_refs = vec![record.rust.canonical_path.as_str()]; path_refs.extend(record.rust.compatibility_paths.iter().map(String::as_str)); @@ -14966,6 +15115,12 @@ fn render_lowering(catalog: &CatalogFile, hash: &str) -> String { "dotprod::convert_generated_dot_product, execution_control::{convert_counted_barrier, convert_grid_dependency, convert_setmaxnreg}, ", ); } + if barrier_reductions(catalog).next().is_some() { + output = output.replace( + "atomic::convert_packed_atom_add, ", + "atomic::convert_packed_atom_add, barrier_reduction::convert_barrier_reduction, ", + ); + } if scalar_conversions(catalog).next().is_some() { output = output.replace( "prmt::convert_generated_prmt, ", @@ -15254,6 +15409,10 @@ fn render_lowering(catalog: &CatalogFile, hash: &str) -> String { output.push_str(", "); output.push_str(&record.dialect.op_type); } + for record in barrier_reductions(catalog) { + output.push_str(", "); + output.push_str(&record.dialect.op_type); + } output.push_str( "};\nuse llvm_export::{ops::AsmKind, types as llvm_types};\nuse pliron::{\n builtin::types::{IntegerType, Signedness},\n context::{Context, Ptr},\n derive::op_interface_impl,\n irbuild::{\n dialect_conversion::{DialectConversionRewriter, OperandsInfo},\n rewriter::Rewriter,\n },\n op::Op,\n operation::Operation,\n result::Result,\n};\n\n", ); @@ -16526,6 +16685,22 @@ fn convert_generated_tcgen05_load( } output.push_str(" }\n}\n\n"); } + for record in barrier_reductions(catalog) { + let template = format!( + "{}.{}", + record.expected_ptx.mnemonic, + record.expected_ptx.modifiers.join(".") + ); + writeln!( + output, + "#[op_interface_impl]\nimpl MirToLlvmConversion for {} {{", + record.dialect.op_type + ) + .unwrap(); + output.push_str(" fn convert(&self, ctx: &mut Context, rewriter: &mut DialectConversionRewriter, operands_info: &OperandsInfo) -> Result<()> {\n"); + writeln!(output, " convert_barrier_reduction(ctx, rewriter, self.get_operation(), operands_info, {:?}, {template:?}, {})", record.llvm_identifier(), record.rust.result == "bool").unwrap(); + output.push_str(" }\n}\n\n"); + } for record in execution_controls(catalog) { let operation = ExecutionControlOperation::from_catalog_id(&record.id) .expect("closed execution-control record"); @@ -16555,6 +16730,14 @@ fn convert_generated_tcgen05_load( ) .unwrap(); } + ExecutionControlOperation::BarrierCtaSyncAll => { + let template = format!( + "{}.{} $0;", + record.expected_ptx.mnemonic, + record.expected_ptx.modifiers.join(".") + ); + writeln!(output, " convert_counted_barrier(ctx, rewriter, self.get_operation(), operands_info, {:?}, {template:?})", record.llvm_identifier()).unwrap(); + } ExecutionControlOperation::GridDependencyLaunchDependents | ExecutionControlOperation::GridDependencyWait => { let template = format!( @@ -18315,6 +18498,22 @@ fn render_execution_control_probe( } output.push_str("attributes #0 = { convergent }\n"); } + ExecutionControlOperation::BarrierCtaSyncAll => { + writeln!(output, "declare void @{symbol}(i32)\n").unwrap(); + for (suffix, parameters, barrier_id) in + [("r", "i32 %barrier_id", "%barrier_id"), ("i", "", "1")] + { + writeln!( + output, + "define void @probe_{}_{suffix}({parameters}) #0 {{", + record.id + ) + .unwrap(); + writeln!(output, " call void @{symbol}(i32 {barrier_id})").unwrap(); + output.push_str(" ret void\n}\n\n"); + } + output.push_str("attributes #0 = { convergent }\n"); + } ExecutionControlOperation::GridDependencyLaunchDependents | ExecutionControlOperation::GridDependencyWait => { writeln!(output, "declare void @{symbol}()\n").unwrap(); @@ -18777,6 +18976,69 @@ pub(crate) fn render_probe(catalog: &CatalogFile, record: &CatalogIntrinsic, has if ExecutionControlOperation::from_catalog_id(&record.id).is_some() { return render_execution_control_probe(catalog, record, hash); } + if record.family == "barrier_reduction" { + let mut output = llvm_header(catalog, hash); + output.push_str("target triple = \"nvptx64-nvidia-cuda\"\n\n"); + let result = &record.llvm.as_ref().unwrap().results[0]; + let arguments = record.llvm.as_ref().unwrap().arguments.join(", "); + let symbol = &llvm(record).symbol; + writeln!(output, "declare {result} @{symbol}({arguments})\n").unwrap(); + let forms: Vec<(&str, &str, Vec<&str>)> = if record.rust.arguments.len() == 2 { + vec![ + ( + "r", + "i32 %barrier_id, i1 %predicate", + vec!["%barrier_id", "%predicate"], + ), + ("i", "i1 %predicate", vec!["1", "%predicate"]), + ] + } else { + vec![ + ( + "rr", + "i32 %barrier_id, i32 %thread_count, i1 %predicate", + vec!["%barrier_id", "%thread_count", "%predicate"], + ), + ( + "ri", + "i32 %barrier_id, i1 %predicate", + vec!["%barrier_id", "32", "%predicate"], + ), + ( + "ir", + "i32 %thread_count, i1 %predicate", + vec!["1", "%thread_count", "%predicate"], + ), + ("ii", "i1 %predicate", vec!["1", "32", "%predicate"]), + ] + }; + for (suffix, parameters, values) in forms { + let call_arguments = record + .llvm + .as_ref() + .unwrap() + .arguments + .iter() + .zip(values) + .map(|(ty, value)| format!("{ty} {value}")) + .collect::>() + .join(", "); + writeln!( + output, + "define {result} @probe_{}_{suffix}({parameters}) #0 {{", + record.id + ) + .unwrap(); + writeln!( + output, + " %result = call {result} @{symbol}({call_arguments})" + ) + .unwrap(); + writeln!(output, " ret {result} %result\n}}\n").unwrap(); + } + output.push_str("attributes #0 = { convergent }\n"); + return output; + } if record.tcgen05.is_some() { return render_tcgen05_probe(catalog, record, hash); } @@ -22789,7 +23051,7 @@ mod tests { let repo_root = Path::new(env!("CARGO_MANIFEST_DIR")).join("../.."); let catalog = crate::resolve::resolve(&repo_root).unwrap(); validate_renderable(&catalog).unwrap(); - assert_eq!(catalog.intrinsics.len(), 1015); + assert_eq!(catalog.intrinsics.len(), 1028); let records: Vec<_> = register_mmas(&catalog).collect(); assert_eq!(records.len(), 154); let generated_records = records diff --git a/crates/cuda-intrinsics-gen/src/resolve.rs b/crates/cuda-intrinsics-gen/src/resolve.rs index eea4165b57..62a6b694e1 100644 --- a/crates/cuda-intrinsics-gen/src/resolve.rs +++ b/crates/cuda-intrinsics-gen/src/resolve.rs @@ -79,9 +79,9 @@ use std::collections::{BTreeMap, BTreeSet}; use std::fs; use std::path::{Component, Path, PathBuf}; -const OVERLAY_SCHEMA: u32 = 44; +const OVERLAY_SCHEMA: u32 = 45; const MINIMUM_OVERLAY_SHARD_SCHEMA: u32 = 26; -const OVERLAY_SHARD_SCHEMA: u32 = 62; +const OVERLAY_SHARD_SCHEMA: u32 = 63; const REGISTER_MMA_F8F6F4_SHARD_SCHEMA: u32 = 46; const REGISTER_MMA_F8F6F4_F16_SHARD_SCHEMA: u32 = 47; const REGISTER_MMA_MXF8F6F4_SHARD_SCHEMA: u32 = 60; @@ -179,6 +179,7 @@ fn primary_evidence_profile<'a>( default_profile: &'a str, ) -> Result<&'a str> { let needs_family_profile = policy.tma.is_some() + || policy.family == "barrier_reduction" || ExecutionControlOperation::from_catalog_id(&policy.id).is_some() || policy .tcgen05 @@ -2117,6 +2118,10 @@ fn validate_policy( declaration.context("execution-control requires imported LLVM declaration")?, )? } + "barrier_reduction" => validate_barrier_reduction_policy( + policy, + declaration.context("barrier_reduction requires imported LLVM declaration")?, + )?, "tcgen05" => validate_tcgen05_policy( policy, declaration.context("tcgen05 requires imported LLVM declaration")?, @@ -2378,7 +2383,20 @@ fn validate_policy( "vote" | "warp_barrier" | "elect" => 2, "warp_match" => 4, "warp_shuffle" => 8, - "counted_barrier" => 4, + "counted_barrier" => { + if policy.id == "barrier_cta_sync_all" { + 2 + } else { + 4 + } + } + "barrier_reduction" => { + if policy.id.ends_with("_count") { + 4 + } else { + 2 + } + } "packed_conversion" | "prmt" | "stmatrix" => 0, "tma" if policy.tma.as_ref().is_some_and(|tma| { @@ -3797,11 +3815,109 @@ fn validate_clc_policy(policy: &OverlayIntrinsic, declaration: &ImportedIntrinsi Ok(()) } -const EXECUTION_CONTROL_OPERATIONS: [ExecutionControlOperation; 8] = [ +fn validate_barrier_reduction_policy( + policy: &OverlayIntrinsic, + declaration: &ImportedIntrinsic, +) -> Result<()> { + let aligned = policy.id.contains("_aligned_"); + let count = policy.id.ends_with("_count"); + let operation = ["and", "or", "popc"] + .into_iter() + .find(|operation| policy.id.contains(&format!("_red_{operation}_"))) + .with_context(|| format!("{} has no closed barrier reduction operation", policy.id))?; + let predicate_result = operation != "popc"; + let rust_arguments = if count { + vec!["u32", "u32", "bool"] + } else { + vec!["u32", "bool"] + }; + let llvm_arguments = if count { + vec!["i32", "i32", "i1"] + } else { + vec!["i32", "i1"] + }; + let llvm_result = if predicate_result { "i1" } else { "i32" }; + let rust_result = if predicate_result { "bool" } else { "u32" }; + let mnemonic = if aligned { "bar" } else { "barrier" }; + let expected_id = format!( + "barrier_cta_red_{operation}_{}{}", + if aligned { "aligned_" } else { "" }, + if count { "count" } else { "all" } + ); + ensure!( + policy.id == expected_id + && policy.family == "barrier_reduction" + && policy.source_record.as_deref() == Some(declaration.source_record.as_str()) + && policy.llvm_symbol.as_deref() == Some(declaration.llvm_name.as_str()) + && policy.rust_module == "barrier" + && policy.rust_name == policy.id + && policy.rust_arguments == rust_arguments + && policy.rust_result == rust_result + && !policy.safe + && policy.must_use + && policy.compatibility_rust_paths == [format!("cuda_device::barrier::{}", policy.id)] + && policy.dialect_operands == llvm_arguments + && policy.dialect_results == [llvm_result] + && policy.llvm_arguments == llvm_arguments + && policy.llvm_results == [llvm_result] + && declaration.arguments == llvm_arguments + && declaration.results == [llvm_result] + && policy.lowering == "generated_barrier_reduction", + "{} barrier-reduction identity or carrier changed", + policy.id + ); + ensure!( + !policy.pure + && policy.memory == "read_write" + && policy.convergent + && policy.execution_scope == "cta" + && policy.minimum_ptx == if aligned { "1.0" } else { "6.0" } + && policy.minimum_sm.as_deref() == if aligned { None } else { Some("sm_30") } + && policy.targets == "all" + && policy.expected_ptx.mnemonic == mnemonic + && policy.expected_ptx.modifiers + == [ + "red", + operation, + if predicate_result { "pred" } else { "u32" } + ], + "{} barrier-reduction semantic or PTX contract changed", + policy.id + ); + ensure!( + declaration.classes == ["SDPatternOperator", "Intrinsic"] + && declaration.properties == ["IntrConvergent", "IntrNoCallback"] + && declaration.selections.len() == if count { 4 } else { 2 }, + "{} imported barrier-reduction declaration changed", + policy.id + ); + ensure!( + policy.backend_lowerings.len() == 2 + && policy.backend_lowerings.iter().any(|route| { + route.backend == IntrinsicBackend::LlvmNvptx + && route.mechanism == BackendLoweringMechanism::TypedNvvm + && route.minimum_ptx.as_deref() == Some(if aligned { "3.2" } else { "6.0" }) + && route.minimum_sm.as_deref() == Some(if aligned { "sm_20" } else { "sm_30" }) + }) + && policy.backend_lowerings.iter().any(|route| { + route.backend == IntrinsicBackend::LibNvvm + && route.mechanism == BackendLoweringMechanism::InlinePtx + && route.minimum_ptx.as_deref() == Some(if aligned { "1.0" } else { "6.0" }) + && route.minimum_sm.as_deref() == Some("sm_75") + }), + "{} barrier-reduction backend route changed", + policy.id + ); + ensure_no_other_family_contract(policy, "barrier reduction")?; + Ok(()) +} + +const EXECUTION_CONTROL_OPERATIONS: [ExecutionControlOperation; 9] = [ ExecutionControlOperation::BarrierCtaSync, ExecutionControlOperation::BarrierCtaSyncAligned, ExecutionControlOperation::BarrierCtaArrive, ExecutionControlOperation::BarrierCtaArriveAligned, + ExecutionControlOperation::BarrierCtaSyncAll, ExecutionControlOperation::GridDependencyLaunchDependents, ExecutionControlOperation::GridDependencyWait, ExecutionControlOperation::SetMaxNRegInc, @@ -3827,7 +3943,7 @@ fn validate_execution_control_family_completeness(intrinsics: &[OverlayIntrinsic .collect::>(); ensure!( actual == expected, - "execution-control overlay must admit all four counted barriers, both grid-dependency controls, and both setmaxnreg operations" + "execution-control overlay must admit all five counted barriers, both grid-dependency controls, and both setmaxnreg operations" ); for family in ["counted_barrier", "grid_dependency", "register_control"] { ensure!( @@ -3900,6 +4016,7 @@ fn execution_control_recipe(operation: ExecutionControlOperation) -> ExecutionCo OperandPattern::RegisterOrImmediate, OperandPattern::RegisterOrImmediate, ]; + const ONE_REGISTER_OR_IMMEDIATE: &[OperandPattern] = &[OperandPattern::RegisterOrImmediate]; const ONE_IMMEDIATE: &[OperandPattern] = &[OperandPattern::Immediate]; const NO_OPERANDS: &[OperandPattern] = &[]; const BARRIER_SYNC_SELECTIONS: &[&str] = &[ @@ -3926,6 +4043,8 @@ fn execution_control_recipe(operation: ExecutionControlOperation) -> ExecutionCo "BARRIER_CTA_ARRIVE_ALIGNED_ri", "BARRIER_CTA_ARRIVE_ALIGNED_rr", ]; + const BARRIER_SYNC_ALL_SELECTIONS: &[&str] = + &["BARRIER_CTA_SYNC_ALL_i", "BARRIER_CTA_SYNC_ALL_r"]; const PTX_60: &[&str] = &["Subtarget->getPTXVersion() >= 60"]; const GRID_PREDICATES: &[&str] = &[ "Subtarget->getSmVersion() >= 90", @@ -4106,6 +4225,37 @@ fn execution_control_recipe(operation: ExecutionControlOperation) -> ExecutionCo EMPTY, "Signals arrival of the requested number of CTA threads at an aligned numbered barrier without waiting.", ), + BarrierCtaSyncAll => ( + "i1028", + "barrier_cta_sync_all", + "synchronization.cta.barrier.all", + "int_nvvm_barrier_cta_sync_all", + "llvm.nvvm.barrier.cta.sync.all", + "barrier", + U32, + "cuda_device::barrier::barrier_cta_sync_all", + "BarrierCtaSyncAllOp", + "nvvm.barrier_cta_sync_all", + I32, + I32, + BASE_CLASSES, + BARRIER_PROPERTIES, + "read_write", + true, + "cta", + "6.0", + Some("sm_30"), + "all", + BAR_SECTION, + BAR_URL, + "barrier", + SYNC_MODIFIERS, + ONE_REGISTER_OR_IMMEDIATE, + BARRIER_SYNC_ALL_SELECTIONS, + "barrier.sync \t$i;", + PTX_60, + "Synchronizes all arriving CTA threads at a numbered barrier.", + ), GridDependencyLaunchDependents => ( "i0913", "grid_dependency_launch_dependents", @@ -4272,8 +4422,12 @@ fn execution_control_backend_floor( use ExecutionControlOperation::*; match (operation, backend) { - (BarrierCtaSync | BarrierCtaArrive, IntrinsicBackend::LlvmNvptx) => ("6.0", Some("sm_30")), - (BarrierCtaSync | BarrierCtaArrive, IntrinsicBackend::LibNvvm) => ("6.0", Some("sm_75")), + (BarrierCtaSync | BarrierCtaArrive | BarrierCtaSyncAll, IntrinsicBackend::LlvmNvptx) => { + ("6.0", Some("sm_30")) + } + (BarrierCtaSync | BarrierCtaArrive | BarrierCtaSyncAll, IntrinsicBackend::LibNvvm) => { + ("6.0", Some("sm_75")) + } (BarrierCtaSyncAligned | BarrierCtaArriveAligned, IntrinsicBackend::LlvmNvptx) => { ("3.2", Some("sm_20")) } @@ -31467,8 +31621,8 @@ mod tests { let (overlay, hash) = read_overlay(&repo_root, &repo_root.join("intrinsics/overlay.toml")).unwrap(); assert_eq!(overlay.schema, OVERLAY_SCHEMA); - assert_eq!(overlay.shards.len(), 64); - assert_eq!(overlay.intrinsics.len(), 1015); + assert_eq!(overlay.shards.len(), 65); + assert_eq!(overlay.intrinsics.len(), 1028); assert_eq!( overlay .intrinsics diff --git a/crates/cuda-intrinsics/src/generated/abi_v1.rs b/crates/cuda-intrinsics/src/generated/abi_v1.rs index 653f4eff91..a7ac63d542 100644 --- a/crates/cuda-intrinsics/src/generated/abi_v1.rs +++ b/crates/cuda-intrinsics/src/generated/abi_v1.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. // LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. //! Raw ABI functions recognized by cuda-oxide. @@ -526,6 +526,210 @@ pub unsafe fn i0886(_arg0: u32, _arg1: u32) -> () { ) } +/// Reduces predicates with AND while synchronizing all arriving CTA threads at an aligned numbered barrier. +/// +/// Catalog ID: `barrier_cta_red_and_aligned_all`. Source: LLVM `llvm.nvvm.barrier.cta.red.and.aligned.all` from `int_nvvm_barrier_cta_red_and_aligned_all`; expects PTX `bar.red.and.pred , , ;`. +/// Available on `all` targets from PTX 1.0. +/// +/// # Safety +/// `addr` must designate four writable bytes in global memory and be naturally aligned to four bytes. +/// Do not overlap this operation with a whole-word atomic or any non-atomic access to either 16-bit lane. +/// Racing atomics must use scopes that include each other; this relaxed GPU-scope operation is not atomic with host/system access. +#[must_use] +#[inline(never)] +pub unsafe fn i1018(_arg0: u32, _arg1: bool) -> bool { + unreachable!( + "generated CUDA intrinsic `cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i1018` executed outside device compilation" + ) +} + +/// Reduces predicates with AND while synchronizing the requested number of CTA threads at an aligned numbered barrier. +/// +/// Catalog ID: `barrier_cta_red_and_aligned_count`. Source: LLVM `llvm.nvvm.barrier.cta.red.and.aligned.count` from `int_nvvm_barrier_cta_red_and_aligned_count`; expects PTX `bar.red.and.pred , , , ;`. +/// Available on `all` targets from PTX 1.0. +/// +/// # Safety +/// `addr` must designate four writable bytes in global memory and be naturally aligned to four bytes. +/// Do not overlap this operation with a whole-word atomic or any non-atomic access to either 16-bit lane. +/// Racing atomics must use scopes that include each other; this relaxed GPU-scope operation is not atomic with host/system access. +#[must_use] +#[inline(never)] +pub unsafe fn i1019(_arg0: u32, _arg1: u32, _arg2: bool) -> bool { + unreachable!( + "generated CUDA intrinsic `cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i1019` executed outside device compilation" + ) +} + +/// Reduces predicates with AND while synchronizing all arriving CTA threads at a numbered barrier. +/// +/// Catalog ID: `barrier_cta_red_and_all`. Source: LLVM `llvm.nvvm.barrier.cta.red.and.all` from `int_nvvm_barrier_cta_red_and_all`; expects PTX `barrier.red.and.pred , , ;`. +/// Available on `sm_30+` targets from PTX 6.0. +/// +/// # Safety +/// `addr` must designate four writable bytes in global memory and be naturally aligned to four bytes. +/// Do not overlap this operation with a whole-word atomic or any non-atomic access to either 16-bit lane. +/// Racing atomics must use scopes that include each other; this relaxed GPU-scope operation is not atomic with host/system access. +#[must_use] +#[inline(never)] +pub unsafe fn i1016(_arg0: u32, _arg1: bool) -> bool { + unreachable!( + "generated CUDA intrinsic `cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i1016` executed outside device compilation" + ) +} + +/// Reduces predicates with AND while synchronizing the requested number of CTA threads at a numbered barrier. +/// +/// Catalog ID: `barrier_cta_red_and_count`. Source: LLVM `llvm.nvvm.barrier.cta.red.and.count` from `int_nvvm_barrier_cta_red_and_count`; expects PTX `barrier.red.and.pred , , , ;`. +/// Available on `sm_30+` targets from PTX 6.0. +/// +/// # Safety +/// `addr` must designate four writable bytes in global memory and be naturally aligned to four bytes. +/// Do not overlap this operation with a whole-word atomic or any non-atomic access to either 16-bit lane. +/// Racing atomics must use scopes that include each other; this relaxed GPU-scope operation is not atomic with host/system access. +#[must_use] +#[inline(never)] +pub unsafe fn i1017(_arg0: u32, _arg1: u32, _arg2: bool) -> bool { + unreachable!( + "generated CUDA intrinsic `cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i1017` executed outside device compilation" + ) +} + +/// Reduces predicates with OR while synchronizing all arriving CTA threads at an aligned numbered barrier. +/// +/// Catalog ID: `barrier_cta_red_or_aligned_all`. Source: LLVM `llvm.nvvm.barrier.cta.red.or.aligned.all` from `int_nvvm_barrier_cta_red_or_aligned_all`; expects PTX `bar.red.or.pred , , ;`. +/// Available on `all` targets from PTX 1.0. +/// +/// # Safety +/// `addr` must designate four writable bytes in global memory and be naturally aligned to four bytes. +/// Do not overlap this operation with a whole-word atomic or any non-atomic access to either 16-bit lane. +/// Racing atomics must use scopes that include each other; this relaxed GPU-scope operation is not atomic with host/system access. +#[must_use] +#[inline(never)] +pub unsafe fn i1022(_arg0: u32, _arg1: bool) -> bool { + unreachable!( + "generated CUDA intrinsic `cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i1022` executed outside device compilation" + ) +} + +/// Reduces predicates with OR while synchronizing the requested number of CTA threads at an aligned numbered barrier. +/// +/// Catalog ID: `barrier_cta_red_or_aligned_count`. Source: LLVM `llvm.nvvm.barrier.cta.red.or.aligned.count` from `int_nvvm_barrier_cta_red_or_aligned_count`; expects PTX `bar.red.or.pred , , , ;`. +/// Available on `all` targets from PTX 1.0. +/// +/// # Safety +/// `addr` must designate four writable bytes in global memory and be naturally aligned to four bytes. +/// Do not overlap this operation with a whole-word atomic or any non-atomic access to either 16-bit lane. +/// Racing atomics must use scopes that include each other; this relaxed GPU-scope operation is not atomic with host/system access. +#[must_use] +#[inline(never)] +pub unsafe fn i1023(_arg0: u32, _arg1: u32, _arg2: bool) -> bool { + unreachable!( + "generated CUDA intrinsic `cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i1023` executed outside device compilation" + ) +} + +/// Reduces predicates with OR while synchronizing all arriving CTA threads at a numbered barrier. +/// +/// Catalog ID: `barrier_cta_red_or_all`. Source: LLVM `llvm.nvvm.barrier.cta.red.or.all` from `int_nvvm_barrier_cta_red_or_all`; expects PTX `barrier.red.or.pred , , ;`. +/// Available on `sm_30+` targets from PTX 6.0. +/// +/// # Safety +/// `addr` must designate four writable bytes in global memory and be naturally aligned to four bytes. +/// Do not overlap this operation with a whole-word atomic or any non-atomic access to either 16-bit lane. +/// Racing atomics must use scopes that include each other; this relaxed GPU-scope operation is not atomic with host/system access. +#[must_use] +#[inline(never)] +pub unsafe fn i1020(_arg0: u32, _arg1: bool) -> bool { + unreachable!( + "generated CUDA intrinsic `cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i1020` executed outside device compilation" + ) +} + +/// Reduces predicates with OR while synchronizing the requested number of CTA threads at a numbered barrier. +/// +/// Catalog ID: `barrier_cta_red_or_count`. Source: LLVM `llvm.nvvm.barrier.cta.red.or.count` from `int_nvvm_barrier_cta_red_or_count`; expects PTX `barrier.red.or.pred , , , ;`. +/// Available on `sm_30+` targets from PTX 6.0. +/// +/// # Safety +/// `addr` must designate four writable bytes in global memory and be naturally aligned to four bytes. +/// Do not overlap this operation with a whole-word atomic or any non-atomic access to either 16-bit lane. +/// Racing atomics must use scopes that include each other; this relaxed GPU-scope operation is not atomic with host/system access. +#[must_use] +#[inline(never)] +pub unsafe fn i1021(_arg0: u32, _arg1: u32, _arg2: bool) -> bool { + unreachable!( + "generated CUDA intrinsic `cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i1021` executed outside device compilation" + ) +} + +/// Counts true predicates while synchronizing all arriving CTA threads at an aligned numbered barrier. +/// +/// Catalog ID: `barrier_cta_red_popc_aligned_all`. Source: LLVM `llvm.nvvm.barrier.cta.red.popc.aligned.all` from `int_nvvm_barrier_cta_red_popc_aligned_all`; expects PTX `bar.red.popc.u32 , , ;`. +/// Available on `all` targets from PTX 1.0. +/// +/// # Safety +/// `addr` must designate four writable bytes in global memory and be naturally aligned to four bytes. +/// Do not overlap this operation with a whole-word atomic or any non-atomic access to either 16-bit lane. +/// Racing atomics must use scopes that include each other; this relaxed GPU-scope operation is not atomic with host/system access. +#[must_use] +#[inline(never)] +pub unsafe fn i1026(_arg0: u32, _arg1: bool) -> u32 { + unreachable!( + "generated CUDA intrinsic `cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i1026` executed outside device compilation" + ) +} + +/// Counts true predicates while synchronizing the requested number of CTA threads at an aligned numbered barrier. +/// +/// Catalog ID: `barrier_cta_red_popc_aligned_count`. Source: LLVM `llvm.nvvm.barrier.cta.red.popc.aligned.count` from `int_nvvm_barrier_cta_red_popc_aligned_count`; expects PTX `bar.red.popc.u32 , , , ;`. +/// Available on `all` targets from PTX 1.0. +/// +/// # Safety +/// `addr` must designate four writable bytes in global memory and be naturally aligned to four bytes. +/// Do not overlap this operation with a whole-word atomic or any non-atomic access to either 16-bit lane. +/// Racing atomics must use scopes that include each other; this relaxed GPU-scope operation is not atomic with host/system access. +#[must_use] +#[inline(never)] +pub unsafe fn i1027(_arg0: u32, _arg1: u32, _arg2: bool) -> u32 { + unreachable!( + "generated CUDA intrinsic `cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i1027` executed outside device compilation" + ) +} + +/// Counts true predicates while synchronizing all arriving CTA threads at a numbered barrier. +/// +/// Catalog ID: `barrier_cta_red_popc_all`. Source: LLVM `llvm.nvvm.barrier.cta.red.popc.all` from `int_nvvm_barrier_cta_red_popc_all`; expects PTX `barrier.red.popc.u32 , , ;`. +/// Available on `sm_30+` targets from PTX 6.0. +/// +/// # Safety +/// `addr` must designate four writable bytes in global memory and be naturally aligned to four bytes. +/// Do not overlap this operation with a whole-word atomic or any non-atomic access to either 16-bit lane. +/// Racing atomics must use scopes that include each other; this relaxed GPU-scope operation is not atomic with host/system access. +#[must_use] +#[inline(never)] +pub unsafe fn i1024(_arg0: u32, _arg1: bool) -> u32 { + unreachable!( + "generated CUDA intrinsic `cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i1024` executed outside device compilation" + ) +} + +/// Counts true predicates while synchronizing the requested number of CTA threads at a numbered barrier. +/// +/// Catalog ID: `barrier_cta_red_popc_count`. Source: LLVM `llvm.nvvm.barrier.cta.red.popc.count` from `int_nvvm_barrier_cta_red_popc_count`; expects PTX `barrier.red.popc.u32 , , , ;`. +/// Available on `sm_30+` targets from PTX 6.0. +/// +/// # Safety +/// `addr` must designate four writable bytes in global memory and be naturally aligned to four bytes. +/// Do not overlap this operation with a whole-word atomic or any non-atomic access to either 16-bit lane. +/// Racing atomics must use scopes that include each other; this relaxed GPU-scope operation is not atomic with host/system access. +#[must_use] +#[inline(never)] +pub unsafe fn i1025(_arg0: u32, _arg1: u32, _arg2: bool) -> u32 { + unreachable!( + "generated CUDA intrinsic `cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i1025` executed outside device compilation" + ) +} + /// Synchronizes the requested number of CTA threads at a numbered barrier. /// /// Catalog ID: `barrier_cta_sync`. Source: LLVM `llvm.nvvm.barrier.cta.sync.count` from `int_nvvm_barrier_cta_sync_count`; expects PTX `barrier.sync , ;`. @@ -554,6 +758,20 @@ pub unsafe fn i0884(_arg0: u32, _arg1: u32) -> () { ) } +/// Synchronizes all arriving CTA threads at a numbered barrier. +/// +/// Catalog ID: `barrier_cta_sync_all`. Source: LLVM `llvm.nvvm.barrier.cta.sync.all` from `int_nvvm_barrier_cta_sync_all`; expects PTX `barrier.sync ;`. +/// Available on `sm_30+` targets from PTX 6.0. +/// +/// # Safety +/// `_arg0` must identify the same CTA barrier used by every arriving thread. +#[inline(never)] +pub unsafe fn i1028(_arg0: u32) -> () { + unreachable!( + "generated CUDA intrinsic `cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i1028` executed outside device compilation" + ) +} + /// Returns the X dimension of the current cooperative thread array (CTA). /// /// Catalog ID: `block_dim_x`. Source: LLVM `llvm.nvvm.read.ptx.sreg.ntid.x` from `int_nvvm_read_ptx_sreg_ntid_x`; expects PTX `mov.u32 , %ntid.x;`. diff --git a/crates/cuda-intrinsics/src/generated/mod.rs b/crates/cuda-intrinsics/src/generated/mod.rs index 443e2f899a..015b3b62fc 100644 --- a/crates/cuda-intrinsics/src/generated/mod.rs +++ b/crates/cuda-intrinsics/src/generated/mod.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. // LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. #[doc(hidden)] @@ -57,6 +57,19 @@ pub mod barrier { pub use crate::__cuda_oxide_intrinsic_abi_v1::i0884 as barrier_cta_sync_aligned; pub use crate::__cuda_oxide_intrinsic_abi_v1::i0885 as barrier_cta_arrive; pub use crate::__cuda_oxide_intrinsic_abi_v1::i0886 as barrier_cta_arrive_aligned; + pub use crate::__cuda_oxide_intrinsic_abi_v1::i1016 as barrier_cta_red_and_all; + pub use crate::__cuda_oxide_intrinsic_abi_v1::i1017 as barrier_cta_red_and_count; + pub use crate::__cuda_oxide_intrinsic_abi_v1::i1018 as barrier_cta_red_and_aligned_all; + pub use crate::__cuda_oxide_intrinsic_abi_v1::i1019 as barrier_cta_red_and_aligned_count; + pub use crate::__cuda_oxide_intrinsic_abi_v1::i1020 as barrier_cta_red_or_all; + pub use crate::__cuda_oxide_intrinsic_abi_v1::i1021 as barrier_cta_red_or_count; + pub use crate::__cuda_oxide_intrinsic_abi_v1::i1022 as barrier_cta_red_or_aligned_all; + pub use crate::__cuda_oxide_intrinsic_abi_v1::i1023 as barrier_cta_red_or_aligned_count; + pub use crate::__cuda_oxide_intrinsic_abi_v1::i1024 as barrier_cta_red_popc_all; + pub use crate::__cuda_oxide_intrinsic_abi_v1::i1025 as barrier_cta_red_popc_count; + pub use crate::__cuda_oxide_intrinsic_abi_v1::i1026 as barrier_cta_red_popc_aligned_all; + pub use crate::__cuda_oxide_intrinsic_abi_v1::i1027 as barrier_cta_red_popc_aligned_count; + pub use crate::__cuda_oxide_intrinsic_abi_v1::i1028 as barrier_cta_sync_all; } /// Generated `bf16` intrinsic source API. @@ -1366,6 +1379,87 @@ mod tests { assert_eq!(public as usize, canonical as usize); } #[test] + fn public_barrier_cta_red_and_aligned_all_reexports_abi_i1018() { + let public: unsafe fn(u32, bool) -> bool = super::barrier::barrier_cta_red_and_aligned_all; + let canonical: unsafe fn(u32, bool) -> bool = super::__cuda_oxide_intrinsic_abi_v1::i1018; + assert_eq!(public as usize, canonical as usize); + } + #[test] + fn public_barrier_cta_red_and_aligned_count_reexports_abi_i1019() { + let public: unsafe fn(u32, u32, bool) -> bool = + super::barrier::barrier_cta_red_and_aligned_count; + let canonical: unsafe fn(u32, u32, bool) -> bool = + super::__cuda_oxide_intrinsic_abi_v1::i1019; + assert_eq!(public as usize, canonical as usize); + } + #[test] + fn public_barrier_cta_red_and_all_reexports_abi_i1016() { + let public: unsafe fn(u32, bool) -> bool = super::barrier::barrier_cta_red_and_all; + let canonical: unsafe fn(u32, bool) -> bool = super::__cuda_oxide_intrinsic_abi_v1::i1016; + assert_eq!(public as usize, canonical as usize); + } + #[test] + fn public_barrier_cta_red_and_count_reexports_abi_i1017() { + let public: unsafe fn(u32, u32, bool) -> bool = super::barrier::barrier_cta_red_and_count; + let canonical: unsafe fn(u32, u32, bool) -> bool = + super::__cuda_oxide_intrinsic_abi_v1::i1017; + assert_eq!(public as usize, canonical as usize); + } + #[test] + fn public_barrier_cta_red_or_aligned_all_reexports_abi_i1022() { + let public: unsafe fn(u32, bool) -> bool = super::barrier::barrier_cta_red_or_aligned_all; + let canonical: unsafe fn(u32, bool) -> bool = super::__cuda_oxide_intrinsic_abi_v1::i1022; + assert_eq!(public as usize, canonical as usize); + } + #[test] + fn public_barrier_cta_red_or_aligned_count_reexports_abi_i1023() { + let public: unsafe fn(u32, u32, bool) -> bool = + super::barrier::barrier_cta_red_or_aligned_count; + let canonical: unsafe fn(u32, u32, bool) -> bool = + super::__cuda_oxide_intrinsic_abi_v1::i1023; + assert_eq!(public as usize, canonical as usize); + } + #[test] + fn public_barrier_cta_red_or_all_reexports_abi_i1020() { + let public: unsafe fn(u32, bool) -> bool = super::barrier::barrier_cta_red_or_all; + let canonical: unsafe fn(u32, bool) -> bool = super::__cuda_oxide_intrinsic_abi_v1::i1020; + assert_eq!(public as usize, canonical as usize); + } + #[test] + fn public_barrier_cta_red_or_count_reexports_abi_i1021() { + let public: unsafe fn(u32, u32, bool) -> bool = super::barrier::barrier_cta_red_or_count; + let canonical: unsafe fn(u32, u32, bool) -> bool = + super::__cuda_oxide_intrinsic_abi_v1::i1021; + assert_eq!(public as usize, canonical as usize); + } + #[test] + fn public_barrier_cta_red_popc_aligned_all_reexports_abi_i1026() { + let public: unsafe fn(u32, bool) -> u32 = super::barrier::barrier_cta_red_popc_aligned_all; + let canonical: unsafe fn(u32, bool) -> u32 = super::__cuda_oxide_intrinsic_abi_v1::i1026; + assert_eq!(public as usize, canonical as usize); + } + #[test] + fn public_barrier_cta_red_popc_aligned_count_reexports_abi_i1027() { + let public: unsafe fn(u32, u32, bool) -> u32 = + super::barrier::barrier_cta_red_popc_aligned_count; + let canonical: unsafe fn(u32, u32, bool) -> u32 = + super::__cuda_oxide_intrinsic_abi_v1::i1027; + assert_eq!(public as usize, canonical as usize); + } + #[test] + fn public_barrier_cta_red_popc_all_reexports_abi_i1024() { + let public: unsafe fn(u32, bool) -> u32 = super::barrier::barrier_cta_red_popc_all; + let canonical: unsafe fn(u32, bool) -> u32 = super::__cuda_oxide_intrinsic_abi_v1::i1024; + assert_eq!(public as usize, canonical as usize); + } + #[test] + fn public_barrier_cta_red_popc_count_reexports_abi_i1025() { + let public: unsafe fn(u32, u32, bool) -> u32 = super::barrier::barrier_cta_red_popc_count; + let canonical: unsafe fn(u32, u32, bool) -> u32 = + super::__cuda_oxide_intrinsic_abi_v1::i1025; + assert_eq!(public as usize, canonical as usize); + } + #[test] fn public_barrier_cta_sync_reexports_abi_i0883() { let public: unsafe fn(u32, u32) -> () = super::barrier::barrier_cta_sync; let canonical: unsafe fn(u32, u32) -> () = super::__cuda_oxide_intrinsic_abi_v1::i0883; @@ -1378,6 +1472,12 @@ mod tests { assert_eq!(public as usize, canonical as usize); } #[test] + fn public_barrier_cta_sync_all_reexports_abi_i1028() { + let public: unsafe fn(u32) -> () = super::barrier::barrier_cta_sync_all; + let canonical: unsafe fn(u32) -> () = super::__cuda_oxide_intrinsic_abi_v1::i1028; + assert_eq!(public as usize, canonical as usize); + } + #[test] fn public_block_dim_x_reexports_abi_i0003() { let public: fn() -> u32 = super::sreg::block_dim_x; let canonical: fn() -> u32 = super::__cuda_oxide_intrinsic_abi_v1::i0003; diff --git a/crates/cuda-oxide-codegen/src/generated_intrinsic_targets.rs b/crates/cuda-oxide-codegen/src/generated_intrinsic_targets.rs index d146f6e2d6..2c69f29826 100644 --- a/crates/cuda-oxide-codegen/src/generated_intrinsic_targets.rs +++ b/crates/cuda-oxide-codegen/src/generated_intrinsic_targets.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. // LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. //! Generated target requirements and separately imported LLVM/selection facts. @@ -69887,6 +69887,856 @@ pub const GENERATED_INTRINSIC_TARGETS: &[GeneratedIntrinsicTarget] = &[ result_range: None, }), }, + GeneratedIntrinsicTarget { + marker: "v1:i1016", + id: "barrier_cta_red_and_all", + abi_id: "i1016", + dialect_op: "nvvm.barrier_cta_red_and_all", + variant: GeneratedIntrinsicVariant::Scalar, + requirement: GeneratedTargetRequirement { + minimum_ptx: GeneratedPtxVersion::from_encoded(60), + hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm( + 30, + )]), + }, + backend_requirements: &[ + GeneratedBackendRequirement { + backend: GeneratedIntrinsicBackend::LlvmNvptx, + requirement: GeneratedTargetRequirement { + minimum_ptx: GeneratedPtxVersion::from_encoded(60), + hardware: GeneratedHardwareTarget::AnyOf(&[ + GeneratedHardwareAlternative::MinimumSm(30), + ]), + }, + }, + GeneratedBackendRequirement { + backend: GeneratedIntrinsicBackend::LibNvvm, + requirement: GeneratedTargetRequirement { + minimum_ptx: GeneratedPtxVersion::from_encoded(60), + hardware: GeneratedHardwareTarget::AnyOf(&[ + GeneratedHardwareAlternative::MinimumSm(75), + ]), + }, + }, + ], + selections: &[ + GeneratedSelectionAlternative { + source_record: "BARRIER_CTA_RED_AND_ALL_ip", + asm: "barrier.red.and.pred \t$dest, $i, $pred;", + predicates: &["Subtarget->getPTXVersion() >= 60"], + constraints: GeneratedSelectionConstraints { + address_space: None, + immediate_bindings: &[], + }, + }, + GeneratedSelectionAlternative { + source_record: "BARRIER_CTA_RED_AND_ALL_rp", + asm: "barrier.red.and.pred \t$dest, $i, $pred;", + predicates: &["Subtarget->getPTXVersion() >= 60"], + constraints: GeneratedSelectionConstraints { + address_space: None, + immediate_bindings: &[], + }, + }, + ], + llvm: Some(GeneratedLlvmFacts { + properties: &["IntrConvergent", "IntrNoCallback"], + result_no_undef: false, + result_range: None, + }), + }, + GeneratedIntrinsicTarget { + marker: "v1:i1017", + id: "barrier_cta_red_and_count", + abi_id: "i1017", + dialect_op: "nvvm.barrier_cta_red_and_count", + variant: GeneratedIntrinsicVariant::Scalar, + requirement: GeneratedTargetRequirement { + minimum_ptx: GeneratedPtxVersion::from_encoded(60), + hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm( + 30, + )]), + }, + backend_requirements: &[ + GeneratedBackendRequirement { + backend: GeneratedIntrinsicBackend::LlvmNvptx, + requirement: GeneratedTargetRequirement { + minimum_ptx: GeneratedPtxVersion::from_encoded(60), + hardware: GeneratedHardwareTarget::AnyOf(&[ + GeneratedHardwareAlternative::MinimumSm(30), + ]), + }, + }, + GeneratedBackendRequirement { + backend: GeneratedIntrinsicBackend::LibNvvm, + requirement: GeneratedTargetRequirement { + minimum_ptx: GeneratedPtxVersion::from_encoded(60), + hardware: GeneratedHardwareTarget::AnyOf(&[ + GeneratedHardwareAlternative::MinimumSm(75), + ]), + }, + }, + ], + selections: &[ + GeneratedSelectionAlternative { + source_record: "BARRIER_CTA_RED_AND_COUNT_iip", + asm: "barrier.red.and.pred \t$dest, $i, $j, $pred;", + predicates: &["Subtarget->getPTXVersion() >= 60"], + constraints: GeneratedSelectionConstraints { + address_space: None, + immediate_bindings: &[], + }, + }, + GeneratedSelectionAlternative { + source_record: "BARRIER_CTA_RED_AND_COUNT_irp", + asm: "barrier.red.and.pred \t$dest, $i, $j, $pred;", + predicates: &["Subtarget->getPTXVersion() >= 60"], + constraints: GeneratedSelectionConstraints { + address_space: None, + immediate_bindings: &[], + }, + }, + GeneratedSelectionAlternative { + source_record: "BARRIER_CTA_RED_AND_COUNT_rip", + asm: "barrier.red.and.pred \t$dest, $i, $j, $pred;", + predicates: &["Subtarget->getPTXVersion() >= 60"], + constraints: GeneratedSelectionConstraints { + address_space: None, + immediate_bindings: &[], + }, + }, + GeneratedSelectionAlternative { + source_record: "BARRIER_CTA_RED_AND_COUNT_rrp", + asm: "barrier.red.and.pred \t$dest, $i, $j, $pred;", + predicates: &["Subtarget->getPTXVersion() >= 60"], + constraints: GeneratedSelectionConstraints { + address_space: None, + immediate_bindings: &[], + }, + }, + ], + llvm: Some(GeneratedLlvmFacts { + properties: &["IntrConvergent", "IntrNoCallback"], + result_no_undef: false, + result_range: None, + }), + }, + GeneratedIntrinsicTarget { + marker: "v1:i1018", + id: "barrier_cta_red_and_aligned_all", + abi_id: "i1018", + dialect_op: "nvvm.barrier_cta_red_and_aligned_all", + variant: GeneratedIntrinsicVariant::Scalar, + requirement: GeneratedTargetRequirement { + minimum_ptx: GeneratedPtxVersion::from_encoded(10), + hardware: GeneratedHardwareTarget::All, + }, + backend_requirements: &[ + GeneratedBackendRequirement { + backend: GeneratedIntrinsicBackend::LlvmNvptx, + requirement: GeneratedTargetRequirement { + minimum_ptx: GeneratedPtxVersion::from_encoded(32), + hardware: GeneratedHardwareTarget::AnyOf(&[ + GeneratedHardwareAlternative::MinimumSm(20), + ]), + }, + }, + GeneratedBackendRequirement { + backend: GeneratedIntrinsicBackend::LibNvvm, + requirement: GeneratedTargetRequirement { + minimum_ptx: GeneratedPtxVersion::from_encoded(10), + hardware: GeneratedHardwareTarget::AnyOf(&[ + GeneratedHardwareAlternative::MinimumSm(75), + ]), + }, + }, + ], + selections: &[ + GeneratedSelectionAlternative { + source_record: "BARRIER_CTA_RED_AND_ALIGNED_ALL_ip", + asm: "bar.red.and.pred \t$dest, $i, $pred;", + predicates: &[], + constraints: GeneratedSelectionConstraints { + address_space: None, + immediate_bindings: &[], + }, + }, + GeneratedSelectionAlternative { + source_record: "BARRIER_CTA_RED_AND_ALIGNED_ALL_rp", + asm: "bar.red.and.pred \t$dest, $i, $pred;", + predicates: &[], + constraints: GeneratedSelectionConstraints { + address_space: None, + immediate_bindings: &[], + }, + }, + ], + llvm: Some(GeneratedLlvmFacts { + properties: &["IntrConvergent", "IntrNoCallback"], + result_no_undef: false, + result_range: None, + }), + }, + GeneratedIntrinsicTarget { + marker: "v1:i1019", + id: "barrier_cta_red_and_aligned_count", + abi_id: "i1019", + dialect_op: "nvvm.barrier_cta_red_and_aligned_count", + variant: GeneratedIntrinsicVariant::Scalar, + requirement: GeneratedTargetRequirement { + minimum_ptx: GeneratedPtxVersion::from_encoded(10), + hardware: GeneratedHardwareTarget::All, + }, + backend_requirements: &[ + GeneratedBackendRequirement { + backend: GeneratedIntrinsicBackend::LlvmNvptx, + requirement: GeneratedTargetRequirement { + minimum_ptx: GeneratedPtxVersion::from_encoded(32), + hardware: GeneratedHardwareTarget::AnyOf(&[ + GeneratedHardwareAlternative::MinimumSm(20), + ]), + }, + }, + GeneratedBackendRequirement { + backend: GeneratedIntrinsicBackend::LibNvvm, + requirement: GeneratedTargetRequirement { + minimum_ptx: GeneratedPtxVersion::from_encoded(10), + hardware: GeneratedHardwareTarget::AnyOf(&[ + GeneratedHardwareAlternative::MinimumSm(75), + ]), + }, + }, + ], + selections: &[ + GeneratedSelectionAlternative { + source_record: "BARRIER_CTA_RED_AND_ALIGNED_iip", + asm: "bar.red.and.pred \t$dest, $i, $j, $pred;", + predicates: &[], + constraints: GeneratedSelectionConstraints { + address_space: None, + immediate_bindings: &[], + }, + }, + GeneratedSelectionAlternative { + source_record: "BARRIER_CTA_RED_AND_ALIGNED_irp", + asm: "bar.red.and.pred \t$dest, $i, $j, $pred;", + predicates: &[], + constraints: GeneratedSelectionConstraints { + address_space: None, + immediate_bindings: &[], + }, + }, + GeneratedSelectionAlternative { + source_record: "BARRIER_CTA_RED_AND_ALIGNED_rip", + asm: "bar.red.and.pred \t$dest, $i, $j, $pred;", + predicates: &[], + constraints: GeneratedSelectionConstraints { + address_space: None, + immediate_bindings: &[], + }, + }, + GeneratedSelectionAlternative { + source_record: "BARRIER_CTA_RED_AND_ALIGNED_rrp", + asm: "bar.red.and.pred \t$dest, $i, $j, $pred;", + predicates: &[], + constraints: GeneratedSelectionConstraints { + address_space: None, + immediate_bindings: &[], + }, + }, + ], + llvm: Some(GeneratedLlvmFacts { + properties: &["IntrConvergent", "IntrNoCallback"], + result_no_undef: false, + result_range: None, + }), + }, + GeneratedIntrinsicTarget { + marker: "v1:i1020", + id: "barrier_cta_red_or_all", + abi_id: "i1020", + dialect_op: "nvvm.barrier_cta_red_or_all", + variant: GeneratedIntrinsicVariant::Scalar, + requirement: GeneratedTargetRequirement { + minimum_ptx: GeneratedPtxVersion::from_encoded(60), + hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm( + 30, + )]), + }, + backend_requirements: &[ + GeneratedBackendRequirement { + backend: GeneratedIntrinsicBackend::LlvmNvptx, + requirement: GeneratedTargetRequirement { + minimum_ptx: GeneratedPtxVersion::from_encoded(60), + hardware: GeneratedHardwareTarget::AnyOf(&[ + GeneratedHardwareAlternative::MinimumSm(30), + ]), + }, + }, + GeneratedBackendRequirement { + backend: GeneratedIntrinsicBackend::LibNvvm, + requirement: GeneratedTargetRequirement { + minimum_ptx: GeneratedPtxVersion::from_encoded(60), + hardware: GeneratedHardwareTarget::AnyOf(&[ + GeneratedHardwareAlternative::MinimumSm(75), + ]), + }, + }, + ], + selections: &[ + GeneratedSelectionAlternative { + source_record: "BARRIER_CTA_RED_OR_ALL_ip", + asm: "barrier.red.or.pred \t$dest, $i, $pred;", + predicates: &["Subtarget->getPTXVersion() >= 60"], + constraints: GeneratedSelectionConstraints { + address_space: None, + immediate_bindings: &[], + }, + }, + GeneratedSelectionAlternative { + source_record: "BARRIER_CTA_RED_OR_ALL_rp", + asm: "barrier.red.or.pred \t$dest, $i, $pred;", + predicates: &["Subtarget->getPTXVersion() >= 60"], + constraints: GeneratedSelectionConstraints { + address_space: None, + immediate_bindings: &[], + }, + }, + ], + llvm: Some(GeneratedLlvmFacts { + properties: &["IntrConvergent", "IntrNoCallback"], + result_no_undef: false, + result_range: None, + }), + }, + GeneratedIntrinsicTarget { + marker: "v1:i1021", + id: "barrier_cta_red_or_count", + abi_id: "i1021", + dialect_op: "nvvm.barrier_cta_red_or_count", + variant: GeneratedIntrinsicVariant::Scalar, + requirement: GeneratedTargetRequirement { + minimum_ptx: GeneratedPtxVersion::from_encoded(60), + hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm( + 30, + )]), + }, + backend_requirements: &[ + GeneratedBackendRequirement { + backend: GeneratedIntrinsicBackend::LlvmNvptx, + requirement: GeneratedTargetRequirement { + minimum_ptx: GeneratedPtxVersion::from_encoded(60), + hardware: GeneratedHardwareTarget::AnyOf(&[ + GeneratedHardwareAlternative::MinimumSm(30), + ]), + }, + }, + GeneratedBackendRequirement { + backend: GeneratedIntrinsicBackend::LibNvvm, + requirement: GeneratedTargetRequirement { + minimum_ptx: GeneratedPtxVersion::from_encoded(60), + hardware: GeneratedHardwareTarget::AnyOf(&[ + GeneratedHardwareAlternative::MinimumSm(75), + ]), + }, + }, + ], + selections: &[ + GeneratedSelectionAlternative { + source_record: "BARRIER_CTA_RED_OR_COUNT_iip", + asm: "barrier.red.or.pred \t$dest, $i, $j, $pred;", + predicates: &["Subtarget->getPTXVersion() >= 60"], + constraints: GeneratedSelectionConstraints { + address_space: None, + immediate_bindings: &[], + }, + }, + GeneratedSelectionAlternative { + source_record: "BARRIER_CTA_RED_OR_COUNT_irp", + asm: "barrier.red.or.pred \t$dest, $i, $j, $pred;", + predicates: &["Subtarget->getPTXVersion() >= 60"], + constraints: GeneratedSelectionConstraints { + address_space: None, + immediate_bindings: &[], + }, + }, + GeneratedSelectionAlternative { + source_record: "BARRIER_CTA_RED_OR_COUNT_rip", + asm: "barrier.red.or.pred \t$dest, $i, $j, $pred;", + predicates: &["Subtarget->getPTXVersion() >= 60"], + constraints: GeneratedSelectionConstraints { + address_space: None, + immediate_bindings: &[], + }, + }, + GeneratedSelectionAlternative { + source_record: "BARRIER_CTA_RED_OR_COUNT_rrp", + asm: "barrier.red.or.pred \t$dest, $i, $j, $pred;", + predicates: &["Subtarget->getPTXVersion() >= 60"], + constraints: GeneratedSelectionConstraints { + address_space: None, + immediate_bindings: &[], + }, + }, + ], + llvm: Some(GeneratedLlvmFacts { + properties: &["IntrConvergent", "IntrNoCallback"], + result_no_undef: false, + result_range: None, + }), + }, + GeneratedIntrinsicTarget { + marker: "v1:i1022", + id: "barrier_cta_red_or_aligned_all", + abi_id: "i1022", + dialect_op: "nvvm.barrier_cta_red_or_aligned_all", + variant: GeneratedIntrinsicVariant::Scalar, + requirement: GeneratedTargetRequirement { + minimum_ptx: GeneratedPtxVersion::from_encoded(10), + hardware: GeneratedHardwareTarget::All, + }, + backend_requirements: &[ + GeneratedBackendRequirement { + backend: GeneratedIntrinsicBackend::LlvmNvptx, + requirement: GeneratedTargetRequirement { + minimum_ptx: GeneratedPtxVersion::from_encoded(32), + hardware: GeneratedHardwareTarget::AnyOf(&[ + GeneratedHardwareAlternative::MinimumSm(20), + ]), + }, + }, + GeneratedBackendRequirement { + backend: GeneratedIntrinsicBackend::LibNvvm, + requirement: GeneratedTargetRequirement { + minimum_ptx: GeneratedPtxVersion::from_encoded(10), + hardware: GeneratedHardwareTarget::AnyOf(&[ + GeneratedHardwareAlternative::MinimumSm(75), + ]), + }, + }, + ], + selections: &[ + GeneratedSelectionAlternative { + source_record: "BARRIER_CTA_RED_OR_ALIGNED_ALL_ip", + asm: "bar.red.or.pred \t$dest, $i, $pred;", + predicates: &[], + constraints: GeneratedSelectionConstraints { + address_space: None, + immediate_bindings: &[], + }, + }, + GeneratedSelectionAlternative { + source_record: "BARRIER_CTA_RED_OR_ALIGNED_ALL_rp", + asm: "bar.red.or.pred \t$dest, $i, $pred;", + predicates: &[], + constraints: GeneratedSelectionConstraints { + address_space: None, + immediate_bindings: &[], + }, + }, + ], + llvm: Some(GeneratedLlvmFacts { + properties: &["IntrConvergent", "IntrNoCallback"], + result_no_undef: false, + result_range: None, + }), + }, + GeneratedIntrinsicTarget { + marker: "v1:i1023", + id: "barrier_cta_red_or_aligned_count", + abi_id: "i1023", + dialect_op: "nvvm.barrier_cta_red_or_aligned_count", + variant: GeneratedIntrinsicVariant::Scalar, + requirement: GeneratedTargetRequirement { + minimum_ptx: GeneratedPtxVersion::from_encoded(10), + hardware: GeneratedHardwareTarget::All, + }, + backend_requirements: &[ + GeneratedBackendRequirement { + backend: GeneratedIntrinsicBackend::LlvmNvptx, + requirement: GeneratedTargetRequirement { + minimum_ptx: GeneratedPtxVersion::from_encoded(32), + hardware: GeneratedHardwareTarget::AnyOf(&[ + GeneratedHardwareAlternative::MinimumSm(20), + ]), + }, + }, + GeneratedBackendRequirement { + backend: GeneratedIntrinsicBackend::LibNvvm, + requirement: GeneratedTargetRequirement { + minimum_ptx: GeneratedPtxVersion::from_encoded(10), + hardware: GeneratedHardwareTarget::AnyOf(&[ + GeneratedHardwareAlternative::MinimumSm(75), + ]), + }, + }, + ], + selections: &[ + GeneratedSelectionAlternative { + source_record: "BARRIER_CTA_RED_OR_ALIGNED_iip", + asm: "bar.red.or.pred \t$dest, $i, $j, $pred;", + predicates: &[], + constraints: GeneratedSelectionConstraints { + address_space: None, + immediate_bindings: &[], + }, + }, + GeneratedSelectionAlternative { + source_record: "BARRIER_CTA_RED_OR_ALIGNED_irp", + asm: "bar.red.or.pred \t$dest, $i, $j, $pred;", + predicates: &[], + constraints: GeneratedSelectionConstraints { + address_space: None, + immediate_bindings: &[], + }, + }, + GeneratedSelectionAlternative { + source_record: "BARRIER_CTA_RED_OR_ALIGNED_rip", + asm: "bar.red.or.pred \t$dest, $i, $j, $pred;", + predicates: &[], + constraints: GeneratedSelectionConstraints { + address_space: None, + immediate_bindings: &[], + }, + }, + GeneratedSelectionAlternative { + source_record: "BARRIER_CTA_RED_OR_ALIGNED_rrp", + asm: "bar.red.or.pred \t$dest, $i, $j, $pred;", + predicates: &[], + constraints: GeneratedSelectionConstraints { + address_space: None, + immediate_bindings: &[], + }, + }, + ], + llvm: Some(GeneratedLlvmFacts { + properties: &["IntrConvergent", "IntrNoCallback"], + result_no_undef: false, + result_range: None, + }), + }, + GeneratedIntrinsicTarget { + marker: "v1:i1024", + id: "barrier_cta_red_popc_all", + abi_id: "i1024", + dialect_op: "nvvm.barrier_cta_red_popc_all", + variant: GeneratedIntrinsicVariant::Scalar, + requirement: GeneratedTargetRequirement { + minimum_ptx: GeneratedPtxVersion::from_encoded(60), + hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm( + 30, + )]), + }, + backend_requirements: &[ + GeneratedBackendRequirement { + backend: GeneratedIntrinsicBackend::LlvmNvptx, + requirement: GeneratedTargetRequirement { + minimum_ptx: GeneratedPtxVersion::from_encoded(60), + hardware: GeneratedHardwareTarget::AnyOf(&[ + GeneratedHardwareAlternative::MinimumSm(30), + ]), + }, + }, + GeneratedBackendRequirement { + backend: GeneratedIntrinsicBackend::LibNvvm, + requirement: GeneratedTargetRequirement { + minimum_ptx: GeneratedPtxVersion::from_encoded(60), + hardware: GeneratedHardwareTarget::AnyOf(&[ + GeneratedHardwareAlternative::MinimumSm(75), + ]), + }, + }, + ], + selections: &[ + GeneratedSelectionAlternative { + source_record: "BARRIER_CTA_RED_POPC_ALL_ip", + asm: "barrier.red.popc.u32 \t$dest, $i, $pred;", + predicates: &["Subtarget->getPTXVersion() >= 60"], + constraints: GeneratedSelectionConstraints { + address_space: None, + immediate_bindings: &[], + }, + }, + GeneratedSelectionAlternative { + source_record: "BARRIER_CTA_RED_POPC_ALL_rp", + asm: "barrier.red.popc.u32 \t$dest, $i, $pred;", + predicates: &["Subtarget->getPTXVersion() >= 60"], + constraints: GeneratedSelectionConstraints { + address_space: None, + immediate_bindings: &[], + }, + }, + ], + llvm: Some(GeneratedLlvmFacts { + properties: &["IntrConvergent", "IntrNoCallback"], + result_no_undef: false, + result_range: None, + }), + }, + GeneratedIntrinsicTarget { + marker: "v1:i1025", + id: "barrier_cta_red_popc_count", + abi_id: "i1025", + dialect_op: "nvvm.barrier_cta_red_popc_count", + variant: GeneratedIntrinsicVariant::Scalar, + requirement: GeneratedTargetRequirement { + minimum_ptx: GeneratedPtxVersion::from_encoded(60), + hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm( + 30, + )]), + }, + backend_requirements: &[ + GeneratedBackendRequirement { + backend: GeneratedIntrinsicBackend::LlvmNvptx, + requirement: GeneratedTargetRequirement { + minimum_ptx: GeneratedPtxVersion::from_encoded(60), + hardware: GeneratedHardwareTarget::AnyOf(&[ + GeneratedHardwareAlternative::MinimumSm(30), + ]), + }, + }, + GeneratedBackendRequirement { + backend: GeneratedIntrinsicBackend::LibNvvm, + requirement: GeneratedTargetRequirement { + minimum_ptx: GeneratedPtxVersion::from_encoded(60), + hardware: GeneratedHardwareTarget::AnyOf(&[ + GeneratedHardwareAlternative::MinimumSm(75), + ]), + }, + }, + ], + selections: &[ + GeneratedSelectionAlternative { + source_record: "BARRIER_CTA_RED_POPC_COUNT_iip", + asm: "barrier.red.popc.u32 \t$dest, $i, $j, $pred;", + predicates: &["Subtarget->getPTXVersion() >= 60"], + constraints: GeneratedSelectionConstraints { + address_space: None, + immediate_bindings: &[], + }, + }, + GeneratedSelectionAlternative { + source_record: "BARRIER_CTA_RED_POPC_COUNT_irp", + asm: "barrier.red.popc.u32 \t$dest, $i, $j, $pred;", + predicates: &["Subtarget->getPTXVersion() >= 60"], + constraints: GeneratedSelectionConstraints { + address_space: None, + immediate_bindings: &[], + }, + }, + GeneratedSelectionAlternative { + source_record: "BARRIER_CTA_RED_POPC_COUNT_rip", + asm: "barrier.red.popc.u32 \t$dest, $i, $j, $pred;", + predicates: &["Subtarget->getPTXVersion() >= 60"], + constraints: GeneratedSelectionConstraints { + address_space: None, + immediate_bindings: &[], + }, + }, + GeneratedSelectionAlternative { + source_record: "BARRIER_CTA_RED_POPC_COUNT_rrp", + asm: "barrier.red.popc.u32 \t$dest, $i, $j, $pred;", + predicates: &["Subtarget->getPTXVersion() >= 60"], + constraints: GeneratedSelectionConstraints { + address_space: None, + immediate_bindings: &[], + }, + }, + ], + llvm: Some(GeneratedLlvmFacts { + properties: &["IntrConvergent", "IntrNoCallback"], + result_no_undef: false, + result_range: None, + }), + }, + GeneratedIntrinsicTarget { + marker: "v1:i1026", + id: "barrier_cta_red_popc_aligned_all", + abi_id: "i1026", + dialect_op: "nvvm.barrier_cta_red_popc_aligned_all", + variant: GeneratedIntrinsicVariant::Scalar, + requirement: GeneratedTargetRequirement { + minimum_ptx: GeneratedPtxVersion::from_encoded(10), + hardware: GeneratedHardwareTarget::All, + }, + backend_requirements: &[ + GeneratedBackendRequirement { + backend: GeneratedIntrinsicBackend::LlvmNvptx, + requirement: GeneratedTargetRequirement { + minimum_ptx: GeneratedPtxVersion::from_encoded(32), + hardware: GeneratedHardwareTarget::AnyOf(&[ + GeneratedHardwareAlternative::MinimumSm(20), + ]), + }, + }, + GeneratedBackendRequirement { + backend: GeneratedIntrinsicBackend::LibNvvm, + requirement: GeneratedTargetRequirement { + minimum_ptx: GeneratedPtxVersion::from_encoded(10), + hardware: GeneratedHardwareTarget::AnyOf(&[ + GeneratedHardwareAlternative::MinimumSm(75), + ]), + }, + }, + ], + selections: &[ + GeneratedSelectionAlternative { + source_record: "BARRIER_CTA_RED_POPC_ALIGNED_ALL_ip", + asm: "bar.red.popc.u32 \t$dest, $i, $pred;", + predicates: &[], + constraints: GeneratedSelectionConstraints { + address_space: None, + immediate_bindings: &[], + }, + }, + GeneratedSelectionAlternative { + source_record: "BARRIER_CTA_RED_POPC_ALIGNED_ALL_rp", + asm: "bar.red.popc.u32 \t$dest, $i, $pred;", + predicates: &[], + constraints: GeneratedSelectionConstraints { + address_space: None, + immediate_bindings: &[], + }, + }, + ], + llvm: Some(GeneratedLlvmFacts { + properties: &["IntrConvergent", "IntrNoCallback"], + result_no_undef: false, + result_range: None, + }), + }, + GeneratedIntrinsicTarget { + marker: "v1:i1027", + id: "barrier_cta_red_popc_aligned_count", + abi_id: "i1027", + dialect_op: "nvvm.barrier_cta_red_popc_aligned_count", + variant: GeneratedIntrinsicVariant::Scalar, + requirement: GeneratedTargetRequirement { + minimum_ptx: GeneratedPtxVersion::from_encoded(10), + hardware: GeneratedHardwareTarget::All, + }, + backend_requirements: &[ + GeneratedBackendRequirement { + backend: GeneratedIntrinsicBackend::LlvmNvptx, + requirement: GeneratedTargetRequirement { + minimum_ptx: GeneratedPtxVersion::from_encoded(32), + hardware: GeneratedHardwareTarget::AnyOf(&[ + GeneratedHardwareAlternative::MinimumSm(20), + ]), + }, + }, + GeneratedBackendRequirement { + backend: GeneratedIntrinsicBackend::LibNvvm, + requirement: GeneratedTargetRequirement { + minimum_ptx: GeneratedPtxVersion::from_encoded(10), + hardware: GeneratedHardwareTarget::AnyOf(&[ + GeneratedHardwareAlternative::MinimumSm(75), + ]), + }, + }, + ], + selections: &[ + GeneratedSelectionAlternative { + source_record: "BARRIER_CTA_RED_POPC_ALIGNED_iip", + asm: "bar.red.popc.u32 \t$dest, $i, $j, $pred;", + predicates: &[], + constraints: GeneratedSelectionConstraints { + address_space: None, + immediate_bindings: &[], + }, + }, + GeneratedSelectionAlternative { + source_record: "BARRIER_CTA_RED_POPC_ALIGNED_irp", + asm: "bar.red.popc.u32 \t$dest, $i, $j, $pred;", + predicates: &[], + constraints: GeneratedSelectionConstraints { + address_space: None, + immediate_bindings: &[], + }, + }, + GeneratedSelectionAlternative { + source_record: "BARRIER_CTA_RED_POPC_ALIGNED_rip", + asm: "bar.red.popc.u32 \t$dest, $i, $j, $pred;", + predicates: &[], + constraints: GeneratedSelectionConstraints { + address_space: None, + immediate_bindings: &[], + }, + }, + GeneratedSelectionAlternative { + source_record: "BARRIER_CTA_RED_POPC_ALIGNED_rrp", + asm: "bar.red.popc.u32 \t$dest, $i, $j, $pred;", + predicates: &[], + constraints: GeneratedSelectionConstraints { + address_space: None, + immediate_bindings: &[], + }, + }, + ], + llvm: Some(GeneratedLlvmFacts { + properties: &["IntrConvergent", "IntrNoCallback"], + result_no_undef: false, + result_range: None, + }), + }, + GeneratedIntrinsicTarget { + marker: "v1:i1028", + id: "barrier_cta_sync_all", + abi_id: "i1028", + dialect_op: "nvvm.barrier_cta_sync_all", + variant: GeneratedIntrinsicVariant::Scalar, + requirement: GeneratedTargetRequirement { + minimum_ptx: GeneratedPtxVersion::from_encoded(60), + hardware: GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm( + 30, + )]), + }, + backend_requirements: &[ + GeneratedBackendRequirement { + backend: GeneratedIntrinsicBackend::LlvmNvptx, + requirement: GeneratedTargetRequirement { + minimum_ptx: GeneratedPtxVersion::from_encoded(60), + hardware: GeneratedHardwareTarget::AnyOf(&[ + GeneratedHardwareAlternative::MinimumSm(30), + ]), + }, + }, + GeneratedBackendRequirement { + backend: GeneratedIntrinsicBackend::LibNvvm, + requirement: GeneratedTargetRequirement { + minimum_ptx: GeneratedPtxVersion::from_encoded(60), + hardware: GeneratedHardwareTarget::AnyOf(&[ + GeneratedHardwareAlternative::MinimumSm(75), + ]), + }, + }, + ], + selections: &[ + GeneratedSelectionAlternative { + source_record: "BARRIER_CTA_SYNC_ALL_i", + asm: "barrier.sync \t$i;", + predicates: &["Subtarget->getPTXVersion() >= 60"], + constraints: GeneratedSelectionConstraints { + address_space: None, + immediate_bindings: &[], + }, + }, + GeneratedSelectionAlternative { + source_record: "BARRIER_CTA_SYNC_ALL_r", + asm: "barrier.sync \t$i;", + predicates: &["Subtarget->getPTXVersion() >= 60"], + constraints: GeneratedSelectionConstraints { + address_space: None, + immediate_bindings: &[], + }, + }, + ], + llvm: Some(GeneratedLlvmFacts { + properties: &["IntrConvergent", "IntrNoCallback"], + result_no_undef: false, + result_range: None, + }), + }, ]; fn generated_intrinsic_compatibility_marker_by_op_name(op_name: &str) -> Option<&'static str> { @@ -147180,6 +148030,920 @@ mod tests { "WriteOnly" ] as &[&str] ); + let target = generated_intrinsic_target_by_marker("v1:i1016").unwrap(); + assert_eq!(target.id, "barrier_cta_red_and_all"); + assert_eq!(target.abi_id, "i1016"); + assert_eq!(target.dialect_op, "nvvm.barrier_cta_red_and_all"); + assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar); + assert_eq!(target.requirement.minimum_ptx.encoded(), 60); + assert_eq!( + target.requirement.hardware, + const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(30)]) } + ); + assert_eq!( + target.backend_requirements, + const { + &[ + GeneratedBackendRequirement { + backend: GeneratedIntrinsicBackend::LlvmNvptx, + requirement: GeneratedTargetRequirement { + minimum_ptx: GeneratedPtxVersion::from_encoded(60), + hardware: GeneratedHardwareTarget::AnyOf(&[ + GeneratedHardwareAlternative::MinimumSm(30), + ]), + }, + }, + GeneratedBackendRequirement { + backend: GeneratedIntrinsicBackend::LibNvvm, + requirement: GeneratedTargetRequirement { + minimum_ptx: GeneratedPtxVersion::from_encoded(60), + hardware: GeneratedHardwareTarget::AnyOf(&[ + GeneratedHardwareAlternative::MinimumSm(75), + ]), + }, + }, + ] + } + ); + assert_eq!( + target.selections, + &[ + GeneratedSelectionAlternative { + source_record: "BARRIER_CTA_RED_AND_ALL_ip", + asm: "barrier.red.and.pred \t$dest, $i, $pred;", + predicates: &["Subtarget->getPTXVersion() >= 60"], + constraints: GeneratedSelectionConstraints { + address_space: None, + immediate_bindings: &[] + } + }, + GeneratedSelectionAlternative { + source_record: "BARRIER_CTA_RED_AND_ALL_rp", + asm: "barrier.red.and.pred \t$dest, $i, $pred;", + predicates: &["Subtarget->getPTXVersion() >= 60"], + constraints: GeneratedSelectionConstraints { + address_space: None, + immediate_bindings: &[] + } + }, + ] + ); + assert_eq!( + target.llvm.unwrap().properties, + &["IntrConvergent", "IntrNoCallback"] as &[&str] + ); + let target = generated_intrinsic_target_by_marker("v1:i1017").unwrap(); + assert_eq!(target.id, "barrier_cta_red_and_count"); + assert_eq!(target.abi_id, "i1017"); + assert_eq!(target.dialect_op, "nvvm.barrier_cta_red_and_count"); + assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar); + assert_eq!(target.requirement.minimum_ptx.encoded(), 60); + assert_eq!( + target.requirement.hardware, + const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(30)]) } + ); + assert_eq!( + target.backend_requirements, + const { + &[ + GeneratedBackendRequirement { + backend: GeneratedIntrinsicBackend::LlvmNvptx, + requirement: GeneratedTargetRequirement { + minimum_ptx: GeneratedPtxVersion::from_encoded(60), + hardware: GeneratedHardwareTarget::AnyOf(&[ + GeneratedHardwareAlternative::MinimumSm(30), + ]), + }, + }, + GeneratedBackendRequirement { + backend: GeneratedIntrinsicBackend::LibNvvm, + requirement: GeneratedTargetRequirement { + minimum_ptx: GeneratedPtxVersion::from_encoded(60), + hardware: GeneratedHardwareTarget::AnyOf(&[ + GeneratedHardwareAlternative::MinimumSm(75), + ]), + }, + }, + ] + } + ); + assert_eq!( + target.selections, + &[ + GeneratedSelectionAlternative { + source_record: "BARRIER_CTA_RED_AND_COUNT_iip", + asm: "barrier.red.and.pred \t$dest, $i, $j, $pred;", + predicates: &["Subtarget->getPTXVersion() >= 60"], + constraints: GeneratedSelectionConstraints { + address_space: None, + immediate_bindings: &[] + } + }, + GeneratedSelectionAlternative { + source_record: "BARRIER_CTA_RED_AND_COUNT_irp", + asm: "barrier.red.and.pred \t$dest, $i, $j, $pred;", + predicates: &["Subtarget->getPTXVersion() >= 60"], + constraints: GeneratedSelectionConstraints { + address_space: None, + immediate_bindings: &[] + } + }, + GeneratedSelectionAlternative { + source_record: "BARRIER_CTA_RED_AND_COUNT_rip", + asm: "barrier.red.and.pred \t$dest, $i, $j, $pred;", + predicates: &["Subtarget->getPTXVersion() >= 60"], + constraints: GeneratedSelectionConstraints { + address_space: None, + immediate_bindings: &[] + } + }, + GeneratedSelectionAlternative { + source_record: "BARRIER_CTA_RED_AND_COUNT_rrp", + asm: "barrier.red.and.pred \t$dest, $i, $j, $pred;", + predicates: &["Subtarget->getPTXVersion() >= 60"], + constraints: GeneratedSelectionConstraints { + address_space: None, + immediate_bindings: &[] + } + }, + ] + ); + assert_eq!( + target.llvm.unwrap().properties, + &["IntrConvergent", "IntrNoCallback"] as &[&str] + ); + let target = generated_intrinsic_target_by_marker("v1:i1018").unwrap(); + assert_eq!(target.id, "barrier_cta_red_and_aligned_all"); + assert_eq!(target.abi_id, "i1018"); + assert_eq!(target.dialect_op, "nvvm.barrier_cta_red_and_aligned_all"); + assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar); + assert_eq!(target.requirement.minimum_ptx.encoded(), 10); + assert_eq!( + target.requirement.hardware, + const { GeneratedHardwareTarget::All } + ); + assert_eq!( + target.backend_requirements, + const { + &[ + GeneratedBackendRequirement { + backend: GeneratedIntrinsicBackend::LlvmNvptx, + requirement: GeneratedTargetRequirement { + minimum_ptx: GeneratedPtxVersion::from_encoded(32), + hardware: GeneratedHardwareTarget::AnyOf(&[ + GeneratedHardwareAlternative::MinimumSm(20), + ]), + }, + }, + GeneratedBackendRequirement { + backend: GeneratedIntrinsicBackend::LibNvvm, + requirement: GeneratedTargetRequirement { + minimum_ptx: GeneratedPtxVersion::from_encoded(10), + hardware: GeneratedHardwareTarget::AnyOf(&[ + GeneratedHardwareAlternative::MinimumSm(75), + ]), + }, + }, + ] + } + ); + assert_eq!( + target.selections, + &[ + GeneratedSelectionAlternative { + source_record: "BARRIER_CTA_RED_AND_ALIGNED_ALL_ip", + asm: "bar.red.and.pred \t$dest, $i, $pred;", + predicates: &[], + constraints: GeneratedSelectionConstraints { + address_space: None, + immediate_bindings: &[] + } + }, + GeneratedSelectionAlternative { + source_record: "BARRIER_CTA_RED_AND_ALIGNED_ALL_rp", + asm: "bar.red.and.pred \t$dest, $i, $pred;", + predicates: &[], + constraints: GeneratedSelectionConstraints { + address_space: None, + immediate_bindings: &[] + } + }, + ] + ); + assert_eq!( + target.llvm.unwrap().properties, + &["IntrConvergent", "IntrNoCallback"] as &[&str] + ); + let target = generated_intrinsic_target_by_marker("v1:i1019").unwrap(); + assert_eq!(target.id, "barrier_cta_red_and_aligned_count"); + assert_eq!(target.abi_id, "i1019"); + assert_eq!(target.dialect_op, "nvvm.barrier_cta_red_and_aligned_count"); + assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar); + assert_eq!(target.requirement.minimum_ptx.encoded(), 10); + assert_eq!( + target.requirement.hardware, + const { GeneratedHardwareTarget::All } + ); + assert_eq!( + target.backend_requirements, + const { + &[ + GeneratedBackendRequirement { + backend: GeneratedIntrinsicBackend::LlvmNvptx, + requirement: GeneratedTargetRequirement { + minimum_ptx: GeneratedPtxVersion::from_encoded(32), + hardware: GeneratedHardwareTarget::AnyOf(&[ + GeneratedHardwareAlternative::MinimumSm(20), + ]), + }, + }, + GeneratedBackendRequirement { + backend: GeneratedIntrinsicBackend::LibNvvm, + requirement: GeneratedTargetRequirement { + minimum_ptx: GeneratedPtxVersion::from_encoded(10), + hardware: GeneratedHardwareTarget::AnyOf(&[ + GeneratedHardwareAlternative::MinimumSm(75), + ]), + }, + }, + ] + } + ); + assert_eq!( + target.selections, + &[ + GeneratedSelectionAlternative { + source_record: "BARRIER_CTA_RED_AND_ALIGNED_iip", + asm: "bar.red.and.pred \t$dest, $i, $j, $pred;", + predicates: &[], + constraints: GeneratedSelectionConstraints { + address_space: None, + immediate_bindings: &[] + } + }, + GeneratedSelectionAlternative { + source_record: "BARRIER_CTA_RED_AND_ALIGNED_irp", + asm: "bar.red.and.pred \t$dest, $i, $j, $pred;", + predicates: &[], + constraints: GeneratedSelectionConstraints { + address_space: None, + immediate_bindings: &[] + } + }, + GeneratedSelectionAlternative { + source_record: "BARRIER_CTA_RED_AND_ALIGNED_rip", + asm: "bar.red.and.pred \t$dest, $i, $j, $pred;", + predicates: &[], + constraints: GeneratedSelectionConstraints { + address_space: None, + immediate_bindings: &[] + } + }, + GeneratedSelectionAlternative { + source_record: "BARRIER_CTA_RED_AND_ALIGNED_rrp", + asm: "bar.red.and.pred \t$dest, $i, $j, $pred;", + predicates: &[], + constraints: GeneratedSelectionConstraints { + address_space: None, + immediate_bindings: &[] + } + }, + ] + ); + assert_eq!( + target.llvm.unwrap().properties, + &["IntrConvergent", "IntrNoCallback"] as &[&str] + ); + let target = generated_intrinsic_target_by_marker("v1:i1020").unwrap(); + assert_eq!(target.id, "barrier_cta_red_or_all"); + assert_eq!(target.abi_id, "i1020"); + assert_eq!(target.dialect_op, "nvvm.barrier_cta_red_or_all"); + assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar); + assert_eq!(target.requirement.minimum_ptx.encoded(), 60); + assert_eq!( + target.requirement.hardware, + const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(30)]) } + ); + assert_eq!( + target.backend_requirements, + const { + &[ + GeneratedBackendRequirement { + backend: GeneratedIntrinsicBackend::LlvmNvptx, + requirement: GeneratedTargetRequirement { + minimum_ptx: GeneratedPtxVersion::from_encoded(60), + hardware: GeneratedHardwareTarget::AnyOf(&[ + GeneratedHardwareAlternative::MinimumSm(30), + ]), + }, + }, + GeneratedBackendRequirement { + backend: GeneratedIntrinsicBackend::LibNvvm, + requirement: GeneratedTargetRequirement { + minimum_ptx: GeneratedPtxVersion::from_encoded(60), + hardware: GeneratedHardwareTarget::AnyOf(&[ + GeneratedHardwareAlternative::MinimumSm(75), + ]), + }, + }, + ] + } + ); + assert_eq!( + target.selections, + &[ + GeneratedSelectionAlternative { + source_record: "BARRIER_CTA_RED_OR_ALL_ip", + asm: "barrier.red.or.pred \t$dest, $i, $pred;", + predicates: &["Subtarget->getPTXVersion() >= 60"], + constraints: GeneratedSelectionConstraints { + address_space: None, + immediate_bindings: &[] + } + }, + GeneratedSelectionAlternative { + source_record: "BARRIER_CTA_RED_OR_ALL_rp", + asm: "barrier.red.or.pred \t$dest, $i, $pred;", + predicates: &["Subtarget->getPTXVersion() >= 60"], + constraints: GeneratedSelectionConstraints { + address_space: None, + immediate_bindings: &[] + } + }, + ] + ); + assert_eq!( + target.llvm.unwrap().properties, + &["IntrConvergent", "IntrNoCallback"] as &[&str] + ); + let target = generated_intrinsic_target_by_marker("v1:i1021").unwrap(); + assert_eq!(target.id, "barrier_cta_red_or_count"); + assert_eq!(target.abi_id, "i1021"); + assert_eq!(target.dialect_op, "nvvm.barrier_cta_red_or_count"); + assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar); + assert_eq!(target.requirement.minimum_ptx.encoded(), 60); + assert_eq!( + target.requirement.hardware, + const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(30)]) } + ); + assert_eq!( + target.backend_requirements, + const { + &[ + GeneratedBackendRequirement { + backend: GeneratedIntrinsicBackend::LlvmNvptx, + requirement: GeneratedTargetRequirement { + minimum_ptx: GeneratedPtxVersion::from_encoded(60), + hardware: GeneratedHardwareTarget::AnyOf(&[ + GeneratedHardwareAlternative::MinimumSm(30), + ]), + }, + }, + GeneratedBackendRequirement { + backend: GeneratedIntrinsicBackend::LibNvvm, + requirement: GeneratedTargetRequirement { + minimum_ptx: GeneratedPtxVersion::from_encoded(60), + hardware: GeneratedHardwareTarget::AnyOf(&[ + GeneratedHardwareAlternative::MinimumSm(75), + ]), + }, + }, + ] + } + ); + assert_eq!( + target.selections, + &[ + GeneratedSelectionAlternative { + source_record: "BARRIER_CTA_RED_OR_COUNT_iip", + asm: "barrier.red.or.pred \t$dest, $i, $j, $pred;", + predicates: &["Subtarget->getPTXVersion() >= 60"], + constraints: GeneratedSelectionConstraints { + address_space: None, + immediate_bindings: &[] + } + }, + GeneratedSelectionAlternative { + source_record: "BARRIER_CTA_RED_OR_COUNT_irp", + asm: "barrier.red.or.pred \t$dest, $i, $j, $pred;", + predicates: &["Subtarget->getPTXVersion() >= 60"], + constraints: GeneratedSelectionConstraints { + address_space: None, + immediate_bindings: &[] + } + }, + GeneratedSelectionAlternative { + source_record: "BARRIER_CTA_RED_OR_COUNT_rip", + asm: "barrier.red.or.pred \t$dest, $i, $j, $pred;", + predicates: &["Subtarget->getPTXVersion() >= 60"], + constraints: GeneratedSelectionConstraints { + address_space: None, + immediate_bindings: &[] + } + }, + GeneratedSelectionAlternative { + source_record: "BARRIER_CTA_RED_OR_COUNT_rrp", + asm: "barrier.red.or.pred \t$dest, $i, $j, $pred;", + predicates: &["Subtarget->getPTXVersion() >= 60"], + constraints: GeneratedSelectionConstraints { + address_space: None, + immediate_bindings: &[] + } + }, + ] + ); + assert_eq!( + target.llvm.unwrap().properties, + &["IntrConvergent", "IntrNoCallback"] as &[&str] + ); + let target = generated_intrinsic_target_by_marker("v1:i1022").unwrap(); + assert_eq!(target.id, "barrier_cta_red_or_aligned_all"); + assert_eq!(target.abi_id, "i1022"); + assert_eq!(target.dialect_op, "nvvm.barrier_cta_red_or_aligned_all"); + assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar); + assert_eq!(target.requirement.minimum_ptx.encoded(), 10); + assert_eq!( + target.requirement.hardware, + const { GeneratedHardwareTarget::All } + ); + assert_eq!( + target.backend_requirements, + const { + &[ + GeneratedBackendRequirement { + backend: GeneratedIntrinsicBackend::LlvmNvptx, + requirement: GeneratedTargetRequirement { + minimum_ptx: GeneratedPtxVersion::from_encoded(32), + hardware: GeneratedHardwareTarget::AnyOf(&[ + GeneratedHardwareAlternative::MinimumSm(20), + ]), + }, + }, + GeneratedBackendRequirement { + backend: GeneratedIntrinsicBackend::LibNvvm, + requirement: GeneratedTargetRequirement { + minimum_ptx: GeneratedPtxVersion::from_encoded(10), + hardware: GeneratedHardwareTarget::AnyOf(&[ + GeneratedHardwareAlternative::MinimumSm(75), + ]), + }, + }, + ] + } + ); + assert_eq!( + target.selections, + &[ + GeneratedSelectionAlternative { + source_record: "BARRIER_CTA_RED_OR_ALIGNED_ALL_ip", + asm: "bar.red.or.pred \t$dest, $i, $pred;", + predicates: &[], + constraints: GeneratedSelectionConstraints { + address_space: None, + immediate_bindings: &[] + } + }, + GeneratedSelectionAlternative { + source_record: "BARRIER_CTA_RED_OR_ALIGNED_ALL_rp", + asm: "bar.red.or.pred \t$dest, $i, $pred;", + predicates: &[], + constraints: GeneratedSelectionConstraints { + address_space: None, + immediate_bindings: &[] + } + }, + ] + ); + assert_eq!( + target.llvm.unwrap().properties, + &["IntrConvergent", "IntrNoCallback"] as &[&str] + ); + let target = generated_intrinsic_target_by_marker("v1:i1023").unwrap(); + assert_eq!(target.id, "barrier_cta_red_or_aligned_count"); + assert_eq!(target.abi_id, "i1023"); + assert_eq!(target.dialect_op, "nvvm.barrier_cta_red_or_aligned_count"); + assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar); + assert_eq!(target.requirement.minimum_ptx.encoded(), 10); + assert_eq!( + target.requirement.hardware, + const { GeneratedHardwareTarget::All } + ); + assert_eq!( + target.backend_requirements, + const { + &[ + GeneratedBackendRequirement { + backend: GeneratedIntrinsicBackend::LlvmNvptx, + requirement: GeneratedTargetRequirement { + minimum_ptx: GeneratedPtxVersion::from_encoded(32), + hardware: GeneratedHardwareTarget::AnyOf(&[ + GeneratedHardwareAlternative::MinimumSm(20), + ]), + }, + }, + GeneratedBackendRequirement { + backend: GeneratedIntrinsicBackend::LibNvvm, + requirement: GeneratedTargetRequirement { + minimum_ptx: GeneratedPtxVersion::from_encoded(10), + hardware: GeneratedHardwareTarget::AnyOf(&[ + GeneratedHardwareAlternative::MinimumSm(75), + ]), + }, + }, + ] + } + ); + assert_eq!( + target.selections, + &[ + GeneratedSelectionAlternative { + source_record: "BARRIER_CTA_RED_OR_ALIGNED_iip", + asm: "bar.red.or.pred \t$dest, $i, $j, $pred;", + predicates: &[], + constraints: GeneratedSelectionConstraints { + address_space: None, + immediate_bindings: &[] + } + }, + GeneratedSelectionAlternative { + source_record: "BARRIER_CTA_RED_OR_ALIGNED_irp", + asm: "bar.red.or.pred \t$dest, $i, $j, $pred;", + predicates: &[], + constraints: GeneratedSelectionConstraints { + address_space: None, + immediate_bindings: &[] + } + }, + GeneratedSelectionAlternative { + source_record: "BARRIER_CTA_RED_OR_ALIGNED_rip", + asm: "bar.red.or.pred \t$dest, $i, $j, $pred;", + predicates: &[], + constraints: GeneratedSelectionConstraints { + address_space: None, + immediate_bindings: &[] + } + }, + GeneratedSelectionAlternative { + source_record: "BARRIER_CTA_RED_OR_ALIGNED_rrp", + asm: "bar.red.or.pred \t$dest, $i, $j, $pred;", + predicates: &[], + constraints: GeneratedSelectionConstraints { + address_space: None, + immediate_bindings: &[] + } + }, + ] + ); + assert_eq!( + target.llvm.unwrap().properties, + &["IntrConvergent", "IntrNoCallback"] as &[&str] + ); + let target = generated_intrinsic_target_by_marker("v1:i1024").unwrap(); + assert_eq!(target.id, "barrier_cta_red_popc_all"); + assert_eq!(target.abi_id, "i1024"); + assert_eq!(target.dialect_op, "nvvm.barrier_cta_red_popc_all"); + assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar); + assert_eq!(target.requirement.minimum_ptx.encoded(), 60); + assert_eq!( + target.requirement.hardware, + const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(30)]) } + ); + assert_eq!( + target.backend_requirements, + const { + &[ + GeneratedBackendRequirement { + backend: GeneratedIntrinsicBackend::LlvmNvptx, + requirement: GeneratedTargetRequirement { + minimum_ptx: GeneratedPtxVersion::from_encoded(60), + hardware: GeneratedHardwareTarget::AnyOf(&[ + GeneratedHardwareAlternative::MinimumSm(30), + ]), + }, + }, + GeneratedBackendRequirement { + backend: GeneratedIntrinsicBackend::LibNvvm, + requirement: GeneratedTargetRequirement { + minimum_ptx: GeneratedPtxVersion::from_encoded(60), + hardware: GeneratedHardwareTarget::AnyOf(&[ + GeneratedHardwareAlternative::MinimumSm(75), + ]), + }, + }, + ] + } + ); + assert_eq!( + target.selections, + &[ + GeneratedSelectionAlternative { + source_record: "BARRIER_CTA_RED_POPC_ALL_ip", + asm: "barrier.red.popc.u32 \t$dest, $i, $pred;", + predicates: &["Subtarget->getPTXVersion() >= 60"], + constraints: GeneratedSelectionConstraints { + address_space: None, + immediate_bindings: &[] + } + }, + GeneratedSelectionAlternative { + source_record: "BARRIER_CTA_RED_POPC_ALL_rp", + asm: "barrier.red.popc.u32 \t$dest, $i, $pred;", + predicates: &["Subtarget->getPTXVersion() >= 60"], + constraints: GeneratedSelectionConstraints { + address_space: None, + immediate_bindings: &[] + } + }, + ] + ); + assert_eq!( + target.llvm.unwrap().properties, + &["IntrConvergent", "IntrNoCallback"] as &[&str] + ); + let target = generated_intrinsic_target_by_marker("v1:i1025").unwrap(); + assert_eq!(target.id, "barrier_cta_red_popc_count"); + assert_eq!(target.abi_id, "i1025"); + assert_eq!(target.dialect_op, "nvvm.barrier_cta_red_popc_count"); + assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar); + assert_eq!(target.requirement.minimum_ptx.encoded(), 60); + assert_eq!( + target.requirement.hardware, + const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(30)]) } + ); + assert_eq!( + target.backend_requirements, + const { + &[ + GeneratedBackendRequirement { + backend: GeneratedIntrinsicBackend::LlvmNvptx, + requirement: GeneratedTargetRequirement { + minimum_ptx: GeneratedPtxVersion::from_encoded(60), + hardware: GeneratedHardwareTarget::AnyOf(&[ + GeneratedHardwareAlternative::MinimumSm(30), + ]), + }, + }, + GeneratedBackendRequirement { + backend: GeneratedIntrinsicBackend::LibNvvm, + requirement: GeneratedTargetRequirement { + minimum_ptx: GeneratedPtxVersion::from_encoded(60), + hardware: GeneratedHardwareTarget::AnyOf(&[ + GeneratedHardwareAlternative::MinimumSm(75), + ]), + }, + }, + ] + } + ); + assert_eq!( + target.selections, + &[ + GeneratedSelectionAlternative { + source_record: "BARRIER_CTA_RED_POPC_COUNT_iip", + asm: "barrier.red.popc.u32 \t$dest, $i, $j, $pred;", + predicates: &["Subtarget->getPTXVersion() >= 60"], + constraints: GeneratedSelectionConstraints { + address_space: None, + immediate_bindings: &[] + } + }, + GeneratedSelectionAlternative { + source_record: "BARRIER_CTA_RED_POPC_COUNT_irp", + asm: "barrier.red.popc.u32 \t$dest, $i, $j, $pred;", + predicates: &["Subtarget->getPTXVersion() >= 60"], + constraints: GeneratedSelectionConstraints { + address_space: None, + immediate_bindings: &[] + } + }, + GeneratedSelectionAlternative { + source_record: "BARRIER_CTA_RED_POPC_COUNT_rip", + asm: "barrier.red.popc.u32 \t$dest, $i, $j, $pred;", + predicates: &["Subtarget->getPTXVersion() >= 60"], + constraints: GeneratedSelectionConstraints { + address_space: None, + immediate_bindings: &[] + } + }, + GeneratedSelectionAlternative { + source_record: "BARRIER_CTA_RED_POPC_COUNT_rrp", + asm: "barrier.red.popc.u32 \t$dest, $i, $j, $pred;", + predicates: &["Subtarget->getPTXVersion() >= 60"], + constraints: GeneratedSelectionConstraints { + address_space: None, + immediate_bindings: &[] + } + }, + ] + ); + assert_eq!( + target.llvm.unwrap().properties, + &["IntrConvergent", "IntrNoCallback"] as &[&str] + ); + let target = generated_intrinsic_target_by_marker("v1:i1026").unwrap(); + assert_eq!(target.id, "barrier_cta_red_popc_aligned_all"); + assert_eq!(target.abi_id, "i1026"); + assert_eq!(target.dialect_op, "nvvm.barrier_cta_red_popc_aligned_all"); + assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar); + assert_eq!(target.requirement.minimum_ptx.encoded(), 10); + assert_eq!( + target.requirement.hardware, + const { GeneratedHardwareTarget::All } + ); + assert_eq!( + target.backend_requirements, + const { + &[ + GeneratedBackendRequirement { + backend: GeneratedIntrinsicBackend::LlvmNvptx, + requirement: GeneratedTargetRequirement { + minimum_ptx: GeneratedPtxVersion::from_encoded(32), + hardware: GeneratedHardwareTarget::AnyOf(&[ + GeneratedHardwareAlternative::MinimumSm(20), + ]), + }, + }, + GeneratedBackendRequirement { + backend: GeneratedIntrinsicBackend::LibNvvm, + requirement: GeneratedTargetRequirement { + minimum_ptx: GeneratedPtxVersion::from_encoded(10), + hardware: GeneratedHardwareTarget::AnyOf(&[ + GeneratedHardwareAlternative::MinimumSm(75), + ]), + }, + }, + ] + } + ); + assert_eq!( + target.selections, + &[ + GeneratedSelectionAlternative { + source_record: "BARRIER_CTA_RED_POPC_ALIGNED_ALL_ip", + asm: "bar.red.popc.u32 \t$dest, $i, $pred;", + predicates: &[], + constraints: GeneratedSelectionConstraints { + address_space: None, + immediate_bindings: &[] + } + }, + GeneratedSelectionAlternative { + source_record: "BARRIER_CTA_RED_POPC_ALIGNED_ALL_rp", + asm: "bar.red.popc.u32 \t$dest, $i, $pred;", + predicates: &[], + constraints: GeneratedSelectionConstraints { + address_space: None, + immediate_bindings: &[] + } + }, + ] + ); + assert_eq!( + target.llvm.unwrap().properties, + &["IntrConvergent", "IntrNoCallback"] as &[&str] + ); + let target = generated_intrinsic_target_by_marker("v1:i1027").unwrap(); + assert_eq!(target.id, "barrier_cta_red_popc_aligned_count"); + assert_eq!(target.abi_id, "i1027"); + assert_eq!(target.dialect_op, "nvvm.barrier_cta_red_popc_aligned_count"); + assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar); + assert_eq!(target.requirement.minimum_ptx.encoded(), 10); + assert_eq!( + target.requirement.hardware, + const { GeneratedHardwareTarget::All } + ); + assert_eq!( + target.backend_requirements, + const { + &[ + GeneratedBackendRequirement { + backend: GeneratedIntrinsicBackend::LlvmNvptx, + requirement: GeneratedTargetRequirement { + minimum_ptx: GeneratedPtxVersion::from_encoded(32), + hardware: GeneratedHardwareTarget::AnyOf(&[ + GeneratedHardwareAlternative::MinimumSm(20), + ]), + }, + }, + GeneratedBackendRequirement { + backend: GeneratedIntrinsicBackend::LibNvvm, + requirement: GeneratedTargetRequirement { + minimum_ptx: GeneratedPtxVersion::from_encoded(10), + hardware: GeneratedHardwareTarget::AnyOf(&[ + GeneratedHardwareAlternative::MinimumSm(75), + ]), + }, + }, + ] + } + ); + assert_eq!( + target.selections, + &[ + GeneratedSelectionAlternative { + source_record: "BARRIER_CTA_RED_POPC_ALIGNED_iip", + asm: "bar.red.popc.u32 \t$dest, $i, $j, $pred;", + predicates: &[], + constraints: GeneratedSelectionConstraints { + address_space: None, + immediate_bindings: &[] + } + }, + GeneratedSelectionAlternative { + source_record: "BARRIER_CTA_RED_POPC_ALIGNED_irp", + asm: "bar.red.popc.u32 \t$dest, $i, $j, $pred;", + predicates: &[], + constraints: GeneratedSelectionConstraints { + address_space: None, + immediate_bindings: &[] + } + }, + GeneratedSelectionAlternative { + source_record: "BARRIER_CTA_RED_POPC_ALIGNED_rip", + asm: "bar.red.popc.u32 \t$dest, $i, $j, $pred;", + predicates: &[], + constraints: GeneratedSelectionConstraints { + address_space: None, + immediate_bindings: &[] + } + }, + GeneratedSelectionAlternative { + source_record: "BARRIER_CTA_RED_POPC_ALIGNED_rrp", + asm: "bar.red.popc.u32 \t$dest, $i, $j, $pred;", + predicates: &[], + constraints: GeneratedSelectionConstraints { + address_space: None, + immediate_bindings: &[] + } + }, + ] + ); + assert_eq!( + target.llvm.unwrap().properties, + &["IntrConvergent", "IntrNoCallback"] as &[&str] + ); + let target = generated_intrinsic_target_by_marker("v1:i1028").unwrap(); + assert_eq!(target.id, "barrier_cta_sync_all"); + assert_eq!(target.abi_id, "i1028"); + assert_eq!(target.dialect_op, "nvvm.barrier_cta_sync_all"); + assert_eq!(target.variant, GeneratedIntrinsicVariant::Scalar); + assert_eq!(target.requirement.minimum_ptx.encoded(), 60); + assert_eq!( + target.requirement.hardware, + const { GeneratedHardwareTarget::AnyOf(&[GeneratedHardwareAlternative::MinimumSm(30)]) } + ); + assert_eq!( + target.backend_requirements, + const { + &[ + GeneratedBackendRequirement { + backend: GeneratedIntrinsicBackend::LlvmNvptx, + requirement: GeneratedTargetRequirement { + minimum_ptx: GeneratedPtxVersion::from_encoded(60), + hardware: GeneratedHardwareTarget::AnyOf(&[ + GeneratedHardwareAlternative::MinimumSm(30), + ]), + }, + }, + GeneratedBackendRequirement { + backend: GeneratedIntrinsicBackend::LibNvvm, + requirement: GeneratedTargetRequirement { + minimum_ptx: GeneratedPtxVersion::from_encoded(60), + hardware: GeneratedHardwareTarget::AnyOf(&[ + GeneratedHardwareAlternative::MinimumSm(75), + ]), + }, + }, + ] + } + ); + assert_eq!( + target.selections, + &[ + GeneratedSelectionAlternative { + source_record: "BARRIER_CTA_SYNC_ALL_i", + asm: "barrier.sync \t$i;", + predicates: &["Subtarget->getPTXVersion() >= 60"], + constraints: GeneratedSelectionConstraints { + address_space: None, + immediate_bindings: &[] + } + }, + GeneratedSelectionAlternative { + source_record: "BARRIER_CTA_SYNC_ALL_r", + asm: "barrier.sync \t$i;", + predicates: &["Subtarget->getPTXVersion() >= 60"], + constraints: GeneratedSelectionConstraints { + address_space: None, + immediate_bindings: &[] + } + }, + ] + ); + assert_eq!( + target.llvm.unwrap().properties, + &["IntrConvergent", "IntrNoCallback"] as &[&str] + ); assert!(generated_intrinsic_target_by_marker("v1:i9999").is_none()); } } diff --git a/crates/dialect-nvvm/src/ops/generated/active_mask.rs b/crates/dialect-nvvm/src/ops/generated/active_mask.rs index cefbb856c1..79eddf74b9 100644 --- a/crates/dialect-nvvm/src/ops/generated/active_mask.rs +++ b/crates/dialect-nvvm/src/ops/generated/active_mask.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. // LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. //! Structural operation for the generated active warp mask. diff --git a/crates/dialect-nvvm/src/ops/generated/barrier_reduction.rs b/crates/dialect-nvvm/src/ops/generated/barrier_reduction.rs new file mode 100644 index 0000000000..e3749df1e1 --- /dev/null +++ b/crates/dialect-nvvm/src/ops/generated/barrier_reduction.rs @@ -0,0 +1,213 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: Apache-2.0 + */ + +// @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. +// LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. + +//! Generated CTA barrier-reduction operations. + +use pliron::{ + builtin::op_interfaces::{NOpdsInterface, NResultsInterface}, + context::{Context, Ptr}, + op::Op, + operation::Operation, +}; +use pliron_derive::pliron_op; + +/// Reduces predicates with AND while synchronizing all arriving CTA threads at an aligned numbered barrier. +#[pliron_op( + name = "nvvm.barrier_cta_red_and_aligned_all", + format, + verifier = "succ", + interfaces = [NOpdsInterface<2>, NResultsInterface<1>], +)] +pub struct BarrierCtaRedAndAlignedAllOp; + +impl BarrierCtaRedAndAlignedAllOp { + pub fn new(op: Ptr) -> Self { + Self { op } + } +} + +/// Reduces predicates with AND while synchronizing the requested number of CTA threads at an aligned numbered barrier. +#[pliron_op( + name = "nvvm.barrier_cta_red_and_aligned_count", + format, + verifier = "succ", + interfaces = [NOpdsInterface<3>, NResultsInterface<1>], +)] +pub struct BarrierCtaRedAndAlignedCountOp; + +impl BarrierCtaRedAndAlignedCountOp { + pub fn new(op: Ptr) -> Self { + Self { op } + } +} + +/// Reduces predicates with AND while synchronizing all arriving CTA threads at a numbered barrier. +#[pliron_op( + name = "nvvm.barrier_cta_red_and_all", + format, + verifier = "succ", + interfaces = [NOpdsInterface<2>, NResultsInterface<1>], +)] +pub struct BarrierCtaRedAndAllOp; + +impl BarrierCtaRedAndAllOp { + pub fn new(op: Ptr) -> Self { + Self { op } + } +} + +/// Reduces predicates with AND while synchronizing the requested number of CTA threads at a numbered barrier. +#[pliron_op( + name = "nvvm.barrier_cta_red_and_count", + format, + verifier = "succ", + interfaces = [NOpdsInterface<3>, NResultsInterface<1>], +)] +pub struct BarrierCtaRedAndCountOp; + +impl BarrierCtaRedAndCountOp { + pub fn new(op: Ptr) -> Self { + Self { op } + } +} + +/// Reduces predicates with OR while synchronizing all arriving CTA threads at an aligned numbered barrier. +#[pliron_op( + name = "nvvm.barrier_cta_red_or_aligned_all", + format, + verifier = "succ", + interfaces = [NOpdsInterface<2>, NResultsInterface<1>], +)] +pub struct BarrierCtaRedOrAlignedAllOp; + +impl BarrierCtaRedOrAlignedAllOp { + pub fn new(op: Ptr) -> Self { + Self { op } + } +} + +/// Reduces predicates with OR while synchronizing the requested number of CTA threads at an aligned numbered barrier. +#[pliron_op( + name = "nvvm.barrier_cta_red_or_aligned_count", + format, + verifier = "succ", + interfaces = [NOpdsInterface<3>, NResultsInterface<1>], +)] +pub struct BarrierCtaRedOrAlignedCountOp; + +impl BarrierCtaRedOrAlignedCountOp { + pub fn new(op: Ptr) -> Self { + Self { op } + } +} + +/// Reduces predicates with OR while synchronizing all arriving CTA threads at a numbered barrier. +#[pliron_op( + name = "nvvm.barrier_cta_red_or_all", + format, + verifier = "succ", + interfaces = [NOpdsInterface<2>, NResultsInterface<1>], +)] +pub struct BarrierCtaRedOrAllOp; + +impl BarrierCtaRedOrAllOp { + pub fn new(op: Ptr) -> Self { + Self { op } + } +} + +/// Reduces predicates with OR while synchronizing the requested number of CTA threads at a numbered barrier. +#[pliron_op( + name = "nvvm.barrier_cta_red_or_count", + format, + verifier = "succ", + interfaces = [NOpdsInterface<3>, NResultsInterface<1>], +)] +pub struct BarrierCtaRedOrCountOp; + +impl BarrierCtaRedOrCountOp { + pub fn new(op: Ptr) -> Self { + Self { op } + } +} + +/// Counts true predicates while synchronizing all arriving CTA threads at an aligned numbered barrier. +#[pliron_op( + name = "nvvm.barrier_cta_red_popc_aligned_all", + format, + verifier = "succ", + interfaces = [NOpdsInterface<2>, NResultsInterface<1>], +)] +pub struct BarrierCtaRedPopcAlignedAllOp; + +impl BarrierCtaRedPopcAlignedAllOp { + pub fn new(op: Ptr) -> Self { + Self { op } + } +} + +/// Counts true predicates while synchronizing the requested number of CTA threads at an aligned numbered barrier. +#[pliron_op( + name = "nvvm.barrier_cta_red_popc_aligned_count", + format, + verifier = "succ", + interfaces = [NOpdsInterface<3>, NResultsInterface<1>], +)] +pub struct BarrierCtaRedPopcAlignedCountOp; + +impl BarrierCtaRedPopcAlignedCountOp { + pub fn new(op: Ptr) -> Self { + Self { op } + } +} + +/// Counts true predicates while synchronizing all arriving CTA threads at a numbered barrier. +#[pliron_op( + name = "nvvm.barrier_cta_red_popc_all", + format, + verifier = "succ", + interfaces = [NOpdsInterface<2>, NResultsInterface<1>], +)] +pub struct BarrierCtaRedPopcAllOp; + +impl BarrierCtaRedPopcAllOp { + pub fn new(op: Ptr) -> Self { + Self { op } + } +} + +/// Counts true predicates while synchronizing the requested number of CTA threads at a numbered barrier. +#[pliron_op( + name = "nvvm.barrier_cta_red_popc_count", + format, + verifier = "succ", + interfaces = [NOpdsInterface<3>, NResultsInterface<1>], +)] +pub struct BarrierCtaRedPopcCountOp; + +impl BarrierCtaRedPopcCountOp { + pub fn new(op: Ptr) -> Self { + Self { op } + } +} + +pub(super) fn register(ctx: &mut Context) { + BarrierCtaRedAndAlignedAllOp::register(ctx); + BarrierCtaRedAndAlignedCountOp::register(ctx); + BarrierCtaRedAndAllOp::register(ctx); + BarrierCtaRedAndCountOp::register(ctx); + BarrierCtaRedOrAlignedAllOp::register(ctx); + BarrierCtaRedOrAlignedCountOp::register(ctx); + BarrierCtaRedOrAllOp::register(ctx); + BarrierCtaRedOrCountOp::register(ctx); + BarrierCtaRedPopcAlignedAllOp::register(ctx); + BarrierCtaRedPopcAlignedCountOp::register(ctx); + BarrierCtaRedPopcAllOp::register(ctx); + BarrierCtaRedPopcCountOp::register(ctx); +} diff --git a/crates/dialect-nvvm/src/ops/generated/clc.rs b/crates/dialect-nvvm/src/ops/generated/clc.rs index 34b45f0f23..3634eb617a 100644 --- a/crates/dialect-nvvm/src/ops/generated/clc.rs +++ b/crates/dialect-nvvm/src/ops/generated/clc.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. // LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. //! Generated Cluster Launch Control operations. diff --git a/crates/dialect-nvvm/src/ops/generated/cluster_barrier.rs b/crates/dialect-nvvm/src/ops/generated/cluster_barrier.rs index 9b1bae978e..0fed1588d1 100644 --- a/crates/dialect-nvvm/src/ops/generated/cluster_barrier.rs +++ b/crates/dialect-nvvm/src/ops/generated/cluster_barrier.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. // LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. //! Generated operations for the closed cluster-barrier family. diff --git a/crates/dialect-nvvm/src/ops/generated/cluster_memory.rs b/crates/dialect-nvvm/src/ops/generated/cluster_memory.rs index 5062f721e5..42f2178b76 100644 --- a/crates/dialect-nvvm/src/ops/generated/cluster_memory.rs +++ b/crates/dialect-nvvm/src/ops/generated/cluster_memory.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. // LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. //! Structural operations for cluster address mapping and remote shared reads. diff --git a/crates/dialect-nvvm/src/ops/generated/cp_async.rs b/crates/dialect-nvvm/src/ops/generated/cp_async.rs index 5e8c5998f1..82a9a185d5 100644 --- a/crates/dialect-nvvm/src/ops/generated/cp_async.rs +++ b/crates/dialect-nvvm/src/ops/generated/cp_async.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. // LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. //! Structural operations for classic `cp.async` instructions. diff --git a/crates/dialect-nvvm/src/ops/generated/debug_control.rs b/crates/dialect-nvvm/src/ops/generated/debug_control.rs index c0ea1c9607..71bc534780 100644 --- a/crates/dialect-nvvm/src/ops/generated/debug_control.rs +++ b/crates/dialect-nvvm/src/ops/generated/debug_control.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. // LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. //! Structural operations for generated PTX debug controls. diff --git a/crates/dialect-nvvm/src/ops/generated/dotprod.rs b/crates/dialect-nvvm/src/ops/generated/dotprod.rs index 6b6214ffcb..b4f3a699d4 100644 --- a/crates/dialect-nvvm/src/ops/generated/dotprod.rs +++ b/crates/dialect-nvvm/src/ops/generated/dotprod.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. // LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. //! Structural operations for generated packed integer dot products. diff --git a/crates/dialect-nvvm/src/ops/generated/elect.rs b/crates/dialect-nvvm/src/ops/generated/elect.rs index f36b79f2b4..6ba1e89d66 100644 --- a/crates/dialect-nvvm/src/ops/generated/elect.rs +++ b/crates/dialect-nvvm/src/ops/generated/elect.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. // LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. //! Generated warp leader-election operation. diff --git a/crates/dialect-nvvm/src/ops/generated/execution_control.rs b/crates/dialect-nvvm/src/ops/generated/execution_control.rs index 7824ca6895..e2f7a24549 100644 --- a/crates/dialect-nvvm/src/ops/generated/execution_control.rs +++ b/crates/dialect-nvvm/src/ops/generated/execution_control.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. // LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. //! Generated counted-barrier, grid-dependency, and register-control operations. @@ -88,6 +88,21 @@ impl BarrierCtaSyncAlignedCountOp { } } +/// Synchronizes all arriving CTA threads at a numbered barrier. +#[pliron_op( + name = "nvvm.barrier_cta_sync_all", + format, + verifier = "succ", + interfaces = [NOpdsInterface<1>, NResultsInterface<0>], +)] +pub struct BarrierCtaSyncAllOp; + +impl BarrierCtaSyncAllOp { + pub fn new(op: Ptr) -> Self { + Self { op } + } +} + /// Makes dependent grids eligible to launch before the current grid completes. #[pliron_op( name = "nvvm.grid_dependency_launch_dependents", @@ -227,6 +242,7 @@ pub(super) fn register(ctx: &mut Context) { BarrierCtaArriveAlignedCountOp::register(ctx); BarrierCtaSyncCountOp::register(ctx); BarrierCtaSyncAlignedCountOp::register(ctx); + BarrierCtaSyncAllOp::register(ctx); GridDependencyLaunchDependentsOp::register(ctx); GridDependencyWaitOp::register(ctx); SetMaxNRegDecOp::register(ctx); diff --git a/crates/dialect-nvvm/src/ops/generated/extended_minmax.rs b/crates/dialect-nvvm/src/ops/generated/extended_minmax.rs index 19a029d7f7..5befcd5e04 100644 --- a/crates/dialect-nvvm/src/ops/generated/extended_minmax.rs +++ b/crates/dialect-nvvm/src/ops/generated/extended_minmax.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. // LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. //! One structural operation for extended floating-point min/max. diff --git a/crates/dialect-nvvm/src/ops/generated/integer_minmax.rs b/crates/dialect-nvvm/src/ops/generated/integer_minmax.rs index d2de03f5e5..b5d4b0ea56 100644 --- a/crates/dialect-nvvm/src/ops/generated/integer_minmax.rs +++ b/crates/dialect-nvvm/src/ops/generated/integer_minmax.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. // LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. //! Structural operations for generated extended integer min/max. diff --git a/crates/dialect-nvvm/src/ops/generated/ldmatrix.rs b/crates/dialect-nvvm/src/ops/generated/ldmatrix.rs index e8264e07ea..97a70a84d9 100644 --- a/crates/dialect-nvvm/src/ops/generated/ldmatrix.rs +++ b/crates/dialect-nvvm/src/ops/generated/ldmatrix.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. // LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. //! Structural operation and compatibility carriers for generated `ldmatrix`. diff --git a/crates/dialect-nvvm/src/ops/generated/mbarrier_basic.rs b/crates/dialect-nvvm/src/ops/generated/mbarrier_basic.rs index dfbc22706c..366dd18313 100644 --- a/crates/dialect-nvvm/src/ops/generated/mbarrier_basic.rs +++ b/crates/dialect-nvvm/src/ops/generated/mbarrier_basic.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. // LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. //! Structural operations for the basic shared-memory mbarrier lifecycle. diff --git a/crates/dialect-nvvm/src/ops/generated/mbarrier_extended.rs b/crates/dialect-nvvm/src/ops/generated/mbarrier_extended.rs index 264428f117..7a373c6590 100644 --- a/crates/dialect-nvvm/src/ops/generated/mbarrier_extended.rs +++ b/crates/dialect-nvvm/src/ops/generated/mbarrier_extended.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. // LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. //! Structural operations for extended mbarrier and async-proxy instructions. diff --git a/crates/dialect-nvvm/src/ops/generated/mod.rs b/crates/dialect-nvvm/src/ops/generated/mod.rs index bedc33d14c..055db68969 100644 --- a/crates/dialect-nvvm/src/ops/generated/mod.rs +++ b/crates/dialect-nvvm/src/ops/generated/mod.rs @@ -4,10 +4,11 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. // LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. mod active_mask; +mod barrier_reduction; mod clc; mod cluster_barrier; mod cluster_memory; @@ -44,6 +45,7 @@ mod warp_shuffle; mod wgmma_control; pub use active_mask::*; +pub use barrier_reduction::*; pub use clc::*; pub use cluster_barrier::*; pub use cluster_memory::*; @@ -83,6 +85,7 @@ use pliron::context::Context; pub(super) fn register(ctx: &mut Context) { active_mask::register(ctx); + barrier_reduction::register(ctx); clc::register(ctx); cluster_barrier::register(ctx); cluster_memory::register(ctx); diff --git a/crates/dialect-nvvm/src/ops/generated/movmatrix.rs b/crates/dialect-nvvm/src/ops/generated/movmatrix.rs index c0c2d41192..a7caea47af 100644 --- a/crates/dialect-nvvm/src/ops/generated/movmatrix.rs +++ b/crates/dialect-nvvm/src/ops/generated/movmatrix.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. // LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. //! Structural operation for generated in-register matrix transpose. diff --git a/crates/dialect-nvvm/src/ops/generated/packed_alu.rs b/crates/dialect-nvvm/src/ops/generated/packed_alu.rs index 82b9828c2a..4835919538 100644 --- a/crates/dialect-nvvm/src/ops/generated/packed_alu.rs +++ b/crates/dialect-nvvm/src/ops/generated/packed_alu.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. // LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. //! Structural operations for generated packed floating-point arithmetic. diff --git a/crates/dialect-nvvm/src/ops/generated/packed_atomic.rs b/crates/dialect-nvvm/src/ops/generated/packed_atomic.rs index 4bd821ec0b..845b8e4789 100644 --- a/crates/dialect-nvvm/src/ops/generated/packed_atomic.rs +++ b/crates/dialect-nvvm/src/ops/generated/packed_atomic.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. // LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. //! One structural operation for the closed generated packed-atomic family. diff --git a/crates/dialect-nvvm/src/ops/generated/packed_conversion.rs b/crates/dialect-nvvm/src/ops/generated/packed_conversion.rs index 5bbeb5568e..299f97fb2f 100644 --- a/crates/dialect-nvvm/src/ops/generated/packed_conversion.rs +++ b/crates/dialect-nvvm/src/ops/generated/packed_conversion.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. // LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. //! Structural operation for generated packed conversion. diff --git a/crates/dialect-nvvm/src/ops/generated/prmt.rs b/crates/dialect-nvvm/src/ops/generated/prmt.rs index 16a8ef864d..d3a60d50a3 100644 --- a/crates/dialect-nvvm/src/ops/generated/prmt.rs +++ b/crates/dialect-nvvm/src/ops/generated/prmt.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. // LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. //! One structural operation for the closed generated `prmt` family. diff --git a/crates/dialect-nvvm/src/ops/generated/redux.rs b/crates/dialect-nvvm/src/ops/generated/redux.rs index 26aa02f1be..46c86ca832 100644 --- a/crates/dialect-nvvm/src/ops/generated/redux.rs +++ b/crates/dialect-nvvm/src/ops/generated/redux.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. // LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. //! Structural NVVM operations for the closed generated `redux.sync` family. diff --git a/crates/dialect-nvvm/src/ops/generated/register_mma.rs b/crates/dialect-nvvm/src/ops/generated/register_mma.rs index 0005701fc4..c6311b9f88 100644 --- a/crates/dialect-nvvm/src/ops/generated/register_mma.rs +++ b/crates/dialect-nvvm/src/ops/generated/register_mma.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. // LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. //! One structural operation for generated register-only `mma.sync` variants. diff --git a/crates/dialect-nvvm/src/ops/generated/scalar_arithmetic.rs b/crates/dialect-nvvm/src/ops/generated/scalar_arithmetic.rs index fb6d7dc829..34681857d5 100644 --- a/crates/dialect-nvvm/src/ops/generated/scalar_arithmetic.rs +++ b/crates/dialect-nvvm/src/ops/generated/scalar_arithmetic.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. // LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. //! One structural operation for generated scalar arithmetic. diff --git a/crates/dialect-nvvm/src/ops/generated/scalar_conversion.rs b/crates/dialect-nvvm/src/ops/generated/scalar_conversion.rs index 0f772f80c3..cec0540caf 100644 --- a/crates/dialect-nvvm/src/ops/generated/scalar_conversion.rs +++ b/crates/dialect-nvvm/src/ops/generated/scalar_conversion.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. // LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. //! One structural operation for generated `f32` to TF32 conversions. diff --git a/crates/dialect-nvvm/src/ops/generated/scalar_math.rs b/crates/dialect-nvvm/src/ops/generated/scalar_math.rs index d1fa811561..2717ba9d2a 100644 --- a/crates/dialect-nvvm/src/ops/generated/scalar_math.rs +++ b/crates/dialect-nvvm/src/ops/generated/scalar_math.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. // LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. //! One structural operation for generated scalar math. diff --git a/crates/dialect-nvvm/src/ops/generated/sparse_mma.rs b/crates/dialect-nvvm/src/ops/generated/sparse_mma.rs index 1e1efaf416..44c1265fe7 100644 --- a/crates/dialect-nvvm/src/ops/generated/sparse_mma.rs +++ b/crates/dialect-nvvm/src/ops/generated/sparse_mma.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. // LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. //! One structural operation for generated sparse MMA variants. diff --git a/crates/dialect-nvvm/src/ops/generated/sreg.rs b/crates/dialect-nvvm/src/ops/generated/sreg.rs index 90116f51be..c676a2e348 100644 --- a/crates/dialect-nvvm/src/ops/generated/sreg.rs +++ b/crates/dialect-nvvm/src/ops/generated/sreg.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. // LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. //! Structural NVVM operations for generated special-register reads. diff --git a/crates/dialect-nvvm/src/ops/generated/stmatrix.rs b/crates/dialect-nvvm/src/ops/generated/stmatrix.rs index fd7ed497ac..0176b65e82 100644 --- a/crates/dialect-nvvm/src/ops/generated/stmatrix.rs +++ b/crates/dialect-nvvm/src/ops/generated/stmatrix.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. // LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. //! Structural operations for the four generated `stmatrix` stores. diff --git a/crates/dialect-nvvm/src/ops/generated/sync.rs b/crates/dialect-nvvm/src/ops/generated/sync.rs index 457f2e6198..b7cdf765ca 100644 --- a/crates/dialect-nvvm/src/ops/generated/sync.rs +++ b/crates/dialect-nvvm/src/ops/generated/sync.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. // LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. //! Structural operation for generated CTA synchronization. diff --git a/crates/dialect-nvvm/src/ops/generated/tcgen05.rs b/crates/dialect-nvvm/src/ops/generated/tcgen05.rs index 4e5b495968..535e7f46d0 100644 --- a/crates/dialect-nvvm/src/ops/generated/tcgen05.rs +++ b/crates/dialect-nvvm/src/ops/generated/tcgen05.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. // LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. //! Generated Tensor Core Generation 5 operations. diff --git a/crates/dialect-nvvm/src/ops/generated/tma.rs b/crates/dialect-nvvm/src/ops/generated/tma.rs index 0f050d5a60..e80349a517 100644 --- a/crates/dialect-nvvm/src/ops/generated/tma.rs +++ b/crates/dialect-nvvm/src/ops/generated/tma.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. // LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. //! Generated Tensor Memory Accelerator operations. diff --git a/crates/dialect-nvvm/src/ops/generated/vote.rs b/crates/dialect-nvvm/src/ops/generated/vote.rs index f84ef50ec9..0538700568 100644 --- a/crates/dialect-nvvm/src/ops/generated/vote.rs +++ b/crates/dialect-nvvm/src/ops/generated/vote.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. // LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. //! Structural operations for the generated `vote.sync` family. diff --git a/crates/dialect-nvvm/src/ops/generated/warp_barrier.rs b/crates/dialect-nvvm/src/ops/generated/warp_barrier.rs index 39c80fc7e4..f3c9eabf63 100644 --- a/crates/dialect-nvvm/src/ops/generated/warp_barrier.rs +++ b/crates/dialect-nvvm/src/ops/generated/warp_barrier.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. // LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. //! Structural operation for generated warp synchronization. diff --git a/crates/dialect-nvvm/src/ops/generated/warp_match.rs b/crates/dialect-nvvm/src/ops/generated/warp_match.rs index 4a7c6535ec..6317ab66e0 100644 --- a/crates/dialect-nvvm/src/ops/generated/warp_match.rs +++ b/crates/dialect-nvvm/src/ops/generated/warp_match.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. // LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. //! Structural operations for the generated `match.sync` family. diff --git a/crates/dialect-nvvm/src/ops/generated/warp_shuffle.rs b/crates/dialect-nvvm/src/ops/generated/warp_shuffle.rs index ae606ed465..4560f6cc71 100644 --- a/crates/dialect-nvvm/src/ops/generated/warp_shuffle.rs +++ b/crates/dialect-nvvm/src/ops/generated/warp_shuffle.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. // LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. //! Structural operations for the generated `shfl.sync` family. diff --git a/crates/dialect-nvvm/src/ops/generated/wgmma_control.rs b/crates/dialect-nvvm/src/ops/generated/wgmma_control.rs index 547f51cafa..4fbb6023ea 100644 --- a/crates/dialect-nvvm/src/ops/generated/wgmma_control.rs +++ b/crates/dialect-nvvm/src/ops/generated/wgmma_control.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. // LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. //! Structural operations for generated WGMMA controls. diff --git a/crates/mir-importer/src/translator/terminator/intrinsics/generated.rs b/crates/mir-importer/src/translator/terminator/intrinsics/generated.rs index df8b6d5277..fea338d177 100644 --- a/crates/mir-importer/src/translator/terminator/intrinsics/generated.rs +++ b/crates/mir-importer/src/translator/terminator/intrinsics/generated.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. // LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. //! Generated raw/compatibility path dispatch for CUDA intrinsics. @@ -15,11 +15,15 @@ use crate::translator::{rvalue, terminator::helpers, types}; use dialect_nvvm::ops::{ AbsBf16x2Op, AbsF16x2Op, ActiveMaskOp, AddBf16x2Op, AddF16x2Op, AddF32x2Op, AddFtzF32x2Op, BarWarpSyncOp, Barrier0Op, BarrierCtaArriveAlignedCountOp, BarrierCtaArriveCountOp, - BarrierCtaSyncAlignedCountOp, BarrierCtaSyncCountOp, BreakpointOp, ClcQueryGetFirstCtaidXOp, - ClcQueryGetFirstCtaidYOp, ClcQueryGetFirstCtaidZOp, ClcQueryIsCanceledOp, - ClcTryCancelMulticastOp, ClcTryCancelOp, ClusterBarrierModeAttr, ClusterBarrierOp, - CpAsyncCa4Op, CpAsyncCa8Op, CpAsyncCa16Op, CpAsyncCaZfill4Op, CpAsyncCaZfill8Op, - CpAsyncCaZfill16Op, CpAsyncCg16Op, CpAsyncCgZfill16Op, CpAsyncCommitGroupOp, + BarrierCtaRedAndAlignedAllOp, BarrierCtaRedAndAlignedCountOp, BarrierCtaRedAndAllOp, + BarrierCtaRedAndCountOp, BarrierCtaRedOrAlignedAllOp, BarrierCtaRedOrAlignedCountOp, + BarrierCtaRedOrAllOp, BarrierCtaRedOrCountOp, BarrierCtaRedPopcAlignedAllOp, + BarrierCtaRedPopcAlignedCountOp, BarrierCtaRedPopcAllOp, BarrierCtaRedPopcCountOp, + BarrierCtaSyncAlignedCountOp, BarrierCtaSyncAllOp, BarrierCtaSyncCountOp, BreakpointOp, + ClcQueryGetFirstCtaidXOp, ClcQueryGetFirstCtaidYOp, ClcQueryGetFirstCtaidZOp, + ClcQueryIsCanceledOp, ClcTryCancelMulticastOp, ClcTryCancelOp, ClusterBarrierModeAttr, + ClusterBarrierOp, CpAsyncCa4Op, CpAsyncCa8Op, CpAsyncCa16Op, CpAsyncCaZfill4Op, + CpAsyncCaZfill8Op, CpAsyncCaZfill16Op, CpAsyncCg16Op, CpAsyncCgZfill16Op, CpAsyncCommitGroupOp, CpAsyncMbarrierArriveNoIncOp, CpAsyncMbarrierArriveNoIncSharedOp, CpAsyncMbarrierArriveOp, CpAsyncMbarrierArriveSharedOp, CpAsyncWaitAllOp, CpAsyncWaitGroupOp, CvtF16x2F32Op, CvtF32x2Bf16x2Op, CvtRnF16x2E4m3x2Op, CvtRnF16x2E5m2x2Op, CvtRnReluBf16x2F32Op, @@ -327,10 +331,36 @@ pub fn is_generated_intrinsic_path(name: &str) -> bool { | "cuda_device::barrier::barrier_cta_arrive" | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0886" | "cuda_device::barrier::barrier_cta_arrive_aligned" + | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i1018" + | "cuda_device::barrier::barrier_cta_red_and_aligned_all" + | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i1019" + | "cuda_device::barrier::barrier_cta_red_and_aligned_count" + | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i1016" + | "cuda_device::barrier::barrier_cta_red_and_all" + | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i1017" + | "cuda_device::barrier::barrier_cta_red_and_count" + | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i1022" + | "cuda_device::barrier::barrier_cta_red_or_aligned_all" + | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i1023" + | "cuda_device::barrier::barrier_cta_red_or_aligned_count" + | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i1020" + | "cuda_device::barrier::barrier_cta_red_or_all" + | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i1021" + | "cuda_device::barrier::barrier_cta_red_or_count" + | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i1026" + | "cuda_device::barrier::barrier_cta_red_popc_aligned_all" + | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i1027" + | "cuda_device::barrier::barrier_cta_red_popc_aligned_count" + | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i1024" + | "cuda_device::barrier::barrier_cta_red_popc_all" + | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i1025" + | "cuda_device::barrier::barrier_cta_red_popc_count" | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0883" | "cuda_device::barrier::barrier_cta_sync" | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0884" | "cuda_device::barrier::barrier_cta_sync_aligned" + | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i1028" + | "cuda_device::barrier::barrier_cta_sync_all" | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0003" | "cuda_device::thread::blockDim_x" | "cuda_device::blockDim_x" @@ -2332,8 +2362,21 @@ pub fn is_raw_generated_intrinsic_path(name: &str) -> bool { | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0282" | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0885" | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0886" + | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i1018" + | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i1019" + | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i1016" + | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i1017" + | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i1022" + | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i1023" + | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i1020" + | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i1021" + | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i1026" + | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i1027" + | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i1024" + | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i1025" | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0883" | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0884" + | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i1028" | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0003" | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0007" | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0011" @@ -3393,10 +3436,36 @@ pub fn generated_intrinsic_marker(name: &str) -> Option<&'static str> { | "cuda_device::barrier::barrier_cta_arrive" => Some("v1:i0885"), "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0886" | "cuda_device::barrier::barrier_cta_arrive_aligned" => Some("v1:i0886"), + "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i1018" + | "cuda_device::barrier::barrier_cta_red_and_aligned_all" => Some("v1:i1018"), + "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i1019" + | "cuda_device::barrier::barrier_cta_red_and_aligned_count" => Some("v1:i1019"), + "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i1016" + | "cuda_device::barrier::barrier_cta_red_and_all" => Some("v1:i1016"), + "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i1017" + | "cuda_device::barrier::barrier_cta_red_and_count" => Some("v1:i1017"), + "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i1022" + | "cuda_device::barrier::barrier_cta_red_or_aligned_all" => Some("v1:i1022"), + "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i1023" + | "cuda_device::barrier::barrier_cta_red_or_aligned_count" => Some("v1:i1023"), + "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i1020" + | "cuda_device::barrier::barrier_cta_red_or_all" => Some("v1:i1020"), + "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i1021" + | "cuda_device::barrier::barrier_cta_red_or_count" => Some("v1:i1021"), + "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i1026" + | "cuda_device::barrier::barrier_cta_red_popc_aligned_all" => Some("v1:i1026"), + "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i1027" + | "cuda_device::barrier::barrier_cta_red_popc_aligned_count" => Some("v1:i1027"), + "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i1024" + | "cuda_device::barrier::barrier_cta_red_popc_all" => Some("v1:i1024"), + "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i1025" + | "cuda_device::barrier::barrier_cta_red_popc_count" => Some("v1:i1025"), "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0883" | "cuda_device::barrier::barrier_cta_sync" => Some("v1:i0883"), "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0884" | "cuda_device::barrier::barrier_cta_sync_aligned" => Some("v1:i0884"), + "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i1028" + | "cuda_device::barrier::barrier_cta_sync_all" => Some("v1:i1028"), "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0003" | "cuda_device::thread::blockDim_x" | "cuda_device::blockDim_x" => Some("v1:i0003"), @@ -24585,6 +24654,582 @@ pub fn try_dispatch_generated_intrinsic( "uni_sync call without target block", )?)) } + "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i1018" + | "cuda_device::barrier::barrier_cta_red_and_aligned_all" => { + require_arity(name, args.len(), 2, &loc)?; + let mut last_op = prev_op; + let mut operands = Vec::with_capacity(args.len()); + for arg in args { + let (value, translated) = rvalue::translate_operand( + ctx, + body, + arg, + value_map, + block_ptr, + last_op, + loc.clone(), + )?; + last_op = translated; + operands.push(value); + } + let result_ty = pliron::builtin::types::IntegerType::get( + ctx, + 1, + pliron::builtin::types::Signedness::Signless, + ); + let reduction = Operation::new( + ctx, + BarrierCtaRedAndAlignedAllOp::get_concrete_op_info(), + vec![result_ty.into()], + operands, + vec![], + 0, + ); + reduction.deref_mut(ctx).set_loc(loc.clone()); + helpers::set_generated_intrinsic_marker(ctx, reduction, "v1:i1018"); + helpers::insert_op(ctx, reduction, block_ptr, last_op); + let result = reduction.deref(ctx).get_result(0); + Ok(Some(helpers::emit_store_result_and_goto( + ctx, + destination, + result, + target, + block_ptr, + reduction, + value_map, + block_map, + loc, + "barrier_cta_red_and_aligned_all call without target block", + )?)) + } + "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i1019" + | "cuda_device::barrier::barrier_cta_red_and_aligned_count" => { + require_arity(name, args.len(), 3, &loc)?; + let mut last_op = prev_op; + let mut operands = Vec::with_capacity(args.len()); + for arg in args { + let (value, translated) = rvalue::translate_operand( + ctx, + body, + arg, + value_map, + block_ptr, + last_op, + loc.clone(), + )?; + last_op = translated; + operands.push(value); + } + let result_ty = pliron::builtin::types::IntegerType::get( + ctx, + 1, + pliron::builtin::types::Signedness::Signless, + ); + let reduction = Operation::new( + ctx, + BarrierCtaRedAndAlignedCountOp::get_concrete_op_info(), + vec![result_ty.into()], + operands, + vec![], + 0, + ); + reduction.deref_mut(ctx).set_loc(loc.clone()); + helpers::set_generated_intrinsic_marker(ctx, reduction, "v1:i1019"); + helpers::insert_op(ctx, reduction, block_ptr, last_op); + let result = reduction.deref(ctx).get_result(0); + Ok(Some(helpers::emit_store_result_and_goto( + ctx, + destination, + result, + target, + block_ptr, + reduction, + value_map, + block_map, + loc, + "barrier_cta_red_and_aligned_count call without target block", + )?)) + } + "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i1016" + | "cuda_device::barrier::barrier_cta_red_and_all" => { + require_arity(name, args.len(), 2, &loc)?; + let mut last_op = prev_op; + let mut operands = Vec::with_capacity(args.len()); + for arg in args { + let (value, translated) = rvalue::translate_operand( + ctx, + body, + arg, + value_map, + block_ptr, + last_op, + loc.clone(), + )?; + last_op = translated; + operands.push(value); + } + let result_ty = pliron::builtin::types::IntegerType::get( + ctx, + 1, + pliron::builtin::types::Signedness::Signless, + ); + let reduction = Operation::new( + ctx, + BarrierCtaRedAndAllOp::get_concrete_op_info(), + vec![result_ty.into()], + operands, + vec![], + 0, + ); + reduction.deref_mut(ctx).set_loc(loc.clone()); + helpers::set_generated_intrinsic_marker(ctx, reduction, "v1:i1016"); + helpers::insert_op(ctx, reduction, block_ptr, last_op); + let result = reduction.deref(ctx).get_result(0); + Ok(Some(helpers::emit_store_result_and_goto( + ctx, + destination, + result, + target, + block_ptr, + reduction, + value_map, + block_map, + loc, + "barrier_cta_red_and_all call without target block", + )?)) + } + "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i1017" + | "cuda_device::barrier::barrier_cta_red_and_count" => { + require_arity(name, args.len(), 3, &loc)?; + let mut last_op = prev_op; + let mut operands = Vec::with_capacity(args.len()); + for arg in args { + let (value, translated) = rvalue::translate_operand( + ctx, + body, + arg, + value_map, + block_ptr, + last_op, + loc.clone(), + )?; + last_op = translated; + operands.push(value); + } + let result_ty = pliron::builtin::types::IntegerType::get( + ctx, + 1, + pliron::builtin::types::Signedness::Signless, + ); + let reduction = Operation::new( + ctx, + BarrierCtaRedAndCountOp::get_concrete_op_info(), + vec![result_ty.into()], + operands, + vec![], + 0, + ); + reduction.deref_mut(ctx).set_loc(loc.clone()); + helpers::set_generated_intrinsic_marker(ctx, reduction, "v1:i1017"); + helpers::insert_op(ctx, reduction, block_ptr, last_op); + let result = reduction.deref(ctx).get_result(0); + Ok(Some(helpers::emit_store_result_and_goto( + ctx, + destination, + result, + target, + block_ptr, + reduction, + value_map, + block_map, + loc, + "barrier_cta_red_and_count call without target block", + )?)) + } + "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i1022" + | "cuda_device::barrier::barrier_cta_red_or_aligned_all" => { + require_arity(name, args.len(), 2, &loc)?; + let mut last_op = prev_op; + let mut operands = Vec::with_capacity(args.len()); + for arg in args { + let (value, translated) = rvalue::translate_operand( + ctx, + body, + arg, + value_map, + block_ptr, + last_op, + loc.clone(), + )?; + last_op = translated; + operands.push(value); + } + let result_ty = pliron::builtin::types::IntegerType::get( + ctx, + 1, + pliron::builtin::types::Signedness::Signless, + ); + let reduction = Operation::new( + ctx, + BarrierCtaRedOrAlignedAllOp::get_concrete_op_info(), + vec![result_ty.into()], + operands, + vec![], + 0, + ); + reduction.deref_mut(ctx).set_loc(loc.clone()); + helpers::set_generated_intrinsic_marker(ctx, reduction, "v1:i1022"); + helpers::insert_op(ctx, reduction, block_ptr, last_op); + let result = reduction.deref(ctx).get_result(0); + Ok(Some(helpers::emit_store_result_and_goto( + ctx, + destination, + result, + target, + block_ptr, + reduction, + value_map, + block_map, + loc, + "barrier_cta_red_or_aligned_all call without target block", + )?)) + } + "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i1023" + | "cuda_device::barrier::barrier_cta_red_or_aligned_count" => { + require_arity(name, args.len(), 3, &loc)?; + let mut last_op = prev_op; + let mut operands = Vec::with_capacity(args.len()); + for arg in args { + let (value, translated) = rvalue::translate_operand( + ctx, + body, + arg, + value_map, + block_ptr, + last_op, + loc.clone(), + )?; + last_op = translated; + operands.push(value); + } + let result_ty = pliron::builtin::types::IntegerType::get( + ctx, + 1, + pliron::builtin::types::Signedness::Signless, + ); + let reduction = Operation::new( + ctx, + BarrierCtaRedOrAlignedCountOp::get_concrete_op_info(), + vec![result_ty.into()], + operands, + vec![], + 0, + ); + reduction.deref_mut(ctx).set_loc(loc.clone()); + helpers::set_generated_intrinsic_marker(ctx, reduction, "v1:i1023"); + helpers::insert_op(ctx, reduction, block_ptr, last_op); + let result = reduction.deref(ctx).get_result(0); + Ok(Some(helpers::emit_store_result_and_goto( + ctx, + destination, + result, + target, + block_ptr, + reduction, + value_map, + block_map, + loc, + "barrier_cta_red_or_aligned_count call without target block", + )?)) + } + "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i1020" + | "cuda_device::barrier::barrier_cta_red_or_all" => { + require_arity(name, args.len(), 2, &loc)?; + let mut last_op = prev_op; + let mut operands = Vec::with_capacity(args.len()); + for arg in args { + let (value, translated) = rvalue::translate_operand( + ctx, + body, + arg, + value_map, + block_ptr, + last_op, + loc.clone(), + )?; + last_op = translated; + operands.push(value); + } + let result_ty = pliron::builtin::types::IntegerType::get( + ctx, + 1, + pliron::builtin::types::Signedness::Signless, + ); + let reduction = Operation::new( + ctx, + BarrierCtaRedOrAllOp::get_concrete_op_info(), + vec![result_ty.into()], + operands, + vec![], + 0, + ); + reduction.deref_mut(ctx).set_loc(loc.clone()); + helpers::set_generated_intrinsic_marker(ctx, reduction, "v1:i1020"); + helpers::insert_op(ctx, reduction, block_ptr, last_op); + let result = reduction.deref(ctx).get_result(0); + Ok(Some(helpers::emit_store_result_and_goto( + ctx, + destination, + result, + target, + block_ptr, + reduction, + value_map, + block_map, + loc, + "barrier_cta_red_or_all call without target block", + )?)) + } + "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i1021" + | "cuda_device::barrier::barrier_cta_red_or_count" => { + require_arity(name, args.len(), 3, &loc)?; + let mut last_op = prev_op; + let mut operands = Vec::with_capacity(args.len()); + for arg in args { + let (value, translated) = rvalue::translate_operand( + ctx, + body, + arg, + value_map, + block_ptr, + last_op, + loc.clone(), + )?; + last_op = translated; + operands.push(value); + } + let result_ty = pliron::builtin::types::IntegerType::get( + ctx, + 1, + pliron::builtin::types::Signedness::Signless, + ); + let reduction = Operation::new( + ctx, + BarrierCtaRedOrCountOp::get_concrete_op_info(), + vec![result_ty.into()], + operands, + vec![], + 0, + ); + reduction.deref_mut(ctx).set_loc(loc.clone()); + helpers::set_generated_intrinsic_marker(ctx, reduction, "v1:i1021"); + helpers::insert_op(ctx, reduction, block_ptr, last_op); + let result = reduction.deref(ctx).get_result(0); + Ok(Some(helpers::emit_store_result_and_goto( + ctx, + destination, + result, + target, + block_ptr, + reduction, + value_map, + block_map, + loc, + "barrier_cta_red_or_count call without target block", + )?)) + } + "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i1026" + | "cuda_device::barrier::barrier_cta_red_popc_aligned_all" => { + require_arity(name, args.len(), 2, &loc)?; + let mut last_op = prev_op; + let mut operands = Vec::with_capacity(args.len()); + for arg in args { + let (value, translated) = rvalue::translate_operand( + ctx, + body, + arg, + value_map, + block_ptr, + last_op, + loc.clone(), + )?; + last_op = translated; + operands.push(value); + } + let result_ty = pliron::builtin::types::IntegerType::get( + ctx, + 32, + pliron::builtin::types::Signedness::Unsigned, + ); + let reduction = Operation::new( + ctx, + BarrierCtaRedPopcAlignedAllOp::get_concrete_op_info(), + vec![result_ty.into()], + operands, + vec![], + 0, + ); + reduction.deref_mut(ctx).set_loc(loc.clone()); + helpers::set_generated_intrinsic_marker(ctx, reduction, "v1:i1026"); + helpers::insert_op(ctx, reduction, block_ptr, last_op); + let result = reduction.deref(ctx).get_result(0); + Ok(Some(helpers::emit_store_result_and_goto( + ctx, + destination, + result, + target, + block_ptr, + reduction, + value_map, + block_map, + loc, + "barrier_cta_red_popc_aligned_all call without target block", + )?)) + } + "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i1027" + | "cuda_device::barrier::barrier_cta_red_popc_aligned_count" => { + require_arity(name, args.len(), 3, &loc)?; + let mut last_op = prev_op; + let mut operands = Vec::with_capacity(args.len()); + for arg in args { + let (value, translated) = rvalue::translate_operand( + ctx, + body, + arg, + value_map, + block_ptr, + last_op, + loc.clone(), + )?; + last_op = translated; + operands.push(value); + } + let result_ty = pliron::builtin::types::IntegerType::get( + ctx, + 32, + pliron::builtin::types::Signedness::Unsigned, + ); + let reduction = Operation::new( + ctx, + BarrierCtaRedPopcAlignedCountOp::get_concrete_op_info(), + vec![result_ty.into()], + operands, + vec![], + 0, + ); + reduction.deref_mut(ctx).set_loc(loc.clone()); + helpers::set_generated_intrinsic_marker(ctx, reduction, "v1:i1027"); + helpers::insert_op(ctx, reduction, block_ptr, last_op); + let result = reduction.deref(ctx).get_result(0); + Ok(Some(helpers::emit_store_result_and_goto( + ctx, + destination, + result, + target, + block_ptr, + reduction, + value_map, + block_map, + loc, + "barrier_cta_red_popc_aligned_count call without target block", + )?)) + } + "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i1024" + | "cuda_device::barrier::barrier_cta_red_popc_all" => { + require_arity(name, args.len(), 2, &loc)?; + let mut last_op = prev_op; + let mut operands = Vec::with_capacity(args.len()); + for arg in args { + let (value, translated) = rvalue::translate_operand( + ctx, + body, + arg, + value_map, + block_ptr, + last_op, + loc.clone(), + )?; + last_op = translated; + operands.push(value); + } + let result_ty = pliron::builtin::types::IntegerType::get( + ctx, + 32, + pliron::builtin::types::Signedness::Unsigned, + ); + let reduction = Operation::new( + ctx, + BarrierCtaRedPopcAllOp::get_concrete_op_info(), + vec![result_ty.into()], + operands, + vec![], + 0, + ); + reduction.deref_mut(ctx).set_loc(loc.clone()); + helpers::set_generated_intrinsic_marker(ctx, reduction, "v1:i1024"); + helpers::insert_op(ctx, reduction, block_ptr, last_op); + let result = reduction.deref(ctx).get_result(0); + Ok(Some(helpers::emit_store_result_and_goto( + ctx, + destination, + result, + target, + block_ptr, + reduction, + value_map, + block_map, + loc, + "barrier_cta_red_popc_all call without target block", + )?)) + } + "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i1025" + | "cuda_device::barrier::barrier_cta_red_popc_count" => { + require_arity(name, args.len(), 3, &loc)?; + let mut last_op = prev_op; + let mut operands = Vec::with_capacity(args.len()); + for arg in args { + let (value, translated) = rvalue::translate_operand( + ctx, + body, + arg, + value_map, + block_ptr, + last_op, + loc.clone(), + )?; + last_op = translated; + operands.push(value); + } + let result_ty = pliron::builtin::types::IntegerType::get( + ctx, + 32, + pliron::builtin::types::Signedness::Unsigned, + ); + let reduction = Operation::new( + ctx, + BarrierCtaRedPopcCountOp::get_concrete_op_info(), + vec![result_ty.into()], + operands, + vec![], + 0, + ); + reduction.deref_mut(ctx).set_loc(loc.clone()); + helpers::set_generated_intrinsic_marker(ctx, reduction, "v1:i1025"); + helpers::insert_op(ctx, reduction, block_ptr, last_op); + let result = reduction.deref(ctx).get_result(0); + Ok(Some(helpers::emit_store_result_and_goto( + ctx, + destination, + result, + target, + block_ptr, + reduction, + value_map, + block_map, + loc, + "barrier_cta_red_popc_count call without target block", + )?)) + } "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0048" | "cuda_device::warp::match_all_i64_sync" => { require_arity(name, args.len(), 2, &loc)?; @@ -37766,6 +38411,52 @@ pub fn try_dispatch_generated_intrinsic( ) } } + "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i1028" + | "cuda_device::barrier::barrier_cta_sync_all" => { + require_arity(name, args.len(), 1, &loc)?; + let mut last_op = prev_op; + let mut operands = Vec::with_capacity(args.len()); + for arg in args { + let (value, translated) = rvalue::translate_operand( + ctx, + body, + arg, + value_map, + block_ptr, + last_op, + loc.clone(), + )?; + last_op = translated; + operands.push(value); + } + let control = Operation::new( + ctx, + BarrierCtaSyncAllOp::get_concrete_op_info(), + vec![], + operands, + vec![], + 0, + ); + control.deref_mut(ctx).set_loc(loc.clone()); + helpers::set_generated_intrinsic_marker(ctx, control, "v1:i1028"); + helpers::insert_op(ctx, control, block_ptr, last_op); + if let Some(target_idx) = target { + Ok(Some(helpers::emit_goto( + ctx, + *target_idx, + control, + block_map, + loc, + ))) + } else { + input_err!( + loc, + TranslationErr::unsupported( + "barrier_cta_sync_all call without target block".to_owned() + ) + ) + } + } "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0913" | "cuda_device::grid::dependency::trigger_dependents" => { require_arity(name, args.len(), 0, &loc)?; @@ -58966,6 +59657,438 @@ mod tests { )); } #[test] + fn barrier_cta_red_and_aligned_all_uses_only_canonical_or_compatibility_defpaths() { + assert!(is_generated_intrinsic_path( + "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i1018" + )); + assert!(is_raw_generated_intrinsic_path( + "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i1018" + )); + assert_eq!( + generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i1018"), + Some("v1:i1018") + ); + assert!(matches!( + classify_raw_intrinsic_path( + "cuda_intrinsics", + "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i1018".into() + ), + RawIntrinsicIdentity::Known(_) + )); + assert!(!is_generated_intrinsic_path( + "cuda_intrinsics::barrier::barrier_cta_red_and_aligned_all" + )); + assert!(is_generated_intrinsic_path( + "cuda_device::barrier::barrier_cta_red_and_aligned_all" + )); + assert!(!is_raw_generated_intrinsic_path( + "cuda_device::barrier::barrier_cta_red_and_aligned_all" + )); + assert_eq!( + generated_intrinsic_marker("cuda_device::barrier::barrier_cta_red_and_aligned_all"), + Some("v1:i1018") + ); + assert!(!is_generated_intrinsic_path( + "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i1018" + )); + } + #[test] + fn barrier_cta_red_and_aligned_count_uses_only_canonical_or_compatibility_defpaths() { + assert!(is_generated_intrinsic_path( + "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i1019" + )); + assert!(is_raw_generated_intrinsic_path( + "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i1019" + )); + assert_eq!( + generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i1019"), + Some("v1:i1019") + ); + assert!(matches!( + classify_raw_intrinsic_path( + "cuda_intrinsics", + "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i1019".into() + ), + RawIntrinsicIdentity::Known(_) + )); + assert!(!is_generated_intrinsic_path( + "cuda_intrinsics::barrier::barrier_cta_red_and_aligned_count" + )); + assert!(is_generated_intrinsic_path( + "cuda_device::barrier::barrier_cta_red_and_aligned_count" + )); + assert!(!is_raw_generated_intrinsic_path( + "cuda_device::barrier::barrier_cta_red_and_aligned_count" + )); + assert_eq!( + generated_intrinsic_marker("cuda_device::barrier::barrier_cta_red_and_aligned_count"), + Some("v1:i1019") + ); + assert!(!is_generated_intrinsic_path( + "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i1019" + )); + } + #[test] + fn barrier_cta_red_and_all_uses_only_canonical_or_compatibility_defpaths() { + assert!(is_generated_intrinsic_path( + "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i1016" + )); + assert!(is_raw_generated_intrinsic_path( + "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i1016" + )); + assert_eq!( + generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i1016"), + Some("v1:i1016") + ); + assert!(matches!( + classify_raw_intrinsic_path( + "cuda_intrinsics", + "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i1016".into() + ), + RawIntrinsicIdentity::Known(_) + )); + assert!(!is_generated_intrinsic_path( + "cuda_intrinsics::barrier::barrier_cta_red_and_all" + )); + assert!(is_generated_intrinsic_path( + "cuda_device::barrier::barrier_cta_red_and_all" + )); + assert!(!is_raw_generated_intrinsic_path( + "cuda_device::barrier::barrier_cta_red_and_all" + )); + assert_eq!( + generated_intrinsic_marker("cuda_device::barrier::barrier_cta_red_and_all"), + Some("v1:i1016") + ); + assert!(!is_generated_intrinsic_path( + "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i1016" + )); + } + #[test] + fn barrier_cta_red_and_count_uses_only_canonical_or_compatibility_defpaths() { + assert!(is_generated_intrinsic_path( + "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i1017" + )); + assert!(is_raw_generated_intrinsic_path( + "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i1017" + )); + assert_eq!( + generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i1017"), + Some("v1:i1017") + ); + assert!(matches!( + classify_raw_intrinsic_path( + "cuda_intrinsics", + "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i1017".into() + ), + RawIntrinsicIdentity::Known(_) + )); + assert!(!is_generated_intrinsic_path( + "cuda_intrinsics::barrier::barrier_cta_red_and_count" + )); + assert!(is_generated_intrinsic_path( + "cuda_device::barrier::barrier_cta_red_and_count" + )); + assert!(!is_raw_generated_intrinsic_path( + "cuda_device::barrier::barrier_cta_red_and_count" + )); + assert_eq!( + generated_intrinsic_marker("cuda_device::barrier::barrier_cta_red_and_count"), + Some("v1:i1017") + ); + assert!(!is_generated_intrinsic_path( + "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i1017" + )); + } + #[test] + fn barrier_cta_red_or_aligned_all_uses_only_canonical_or_compatibility_defpaths() { + assert!(is_generated_intrinsic_path( + "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i1022" + )); + assert!(is_raw_generated_intrinsic_path( + "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i1022" + )); + assert_eq!( + generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i1022"), + Some("v1:i1022") + ); + assert!(matches!( + classify_raw_intrinsic_path( + "cuda_intrinsics", + "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i1022".into() + ), + RawIntrinsicIdentity::Known(_) + )); + assert!(!is_generated_intrinsic_path( + "cuda_intrinsics::barrier::barrier_cta_red_or_aligned_all" + )); + assert!(is_generated_intrinsic_path( + "cuda_device::barrier::barrier_cta_red_or_aligned_all" + )); + assert!(!is_raw_generated_intrinsic_path( + "cuda_device::barrier::barrier_cta_red_or_aligned_all" + )); + assert_eq!( + generated_intrinsic_marker("cuda_device::barrier::barrier_cta_red_or_aligned_all"), + Some("v1:i1022") + ); + assert!(!is_generated_intrinsic_path( + "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i1022" + )); + } + #[test] + fn barrier_cta_red_or_aligned_count_uses_only_canonical_or_compatibility_defpaths() { + assert!(is_generated_intrinsic_path( + "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i1023" + )); + assert!(is_raw_generated_intrinsic_path( + "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i1023" + )); + assert_eq!( + generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i1023"), + Some("v1:i1023") + ); + assert!(matches!( + classify_raw_intrinsic_path( + "cuda_intrinsics", + "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i1023".into() + ), + RawIntrinsicIdentity::Known(_) + )); + assert!(!is_generated_intrinsic_path( + "cuda_intrinsics::barrier::barrier_cta_red_or_aligned_count" + )); + assert!(is_generated_intrinsic_path( + "cuda_device::barrier::barrier_cta_red_or_aligned_count" + )); + assert!(!is_raw_generated_intrinsic_path( + "cuda_device::barrier::barrier_cta_red_or_aligned_count" + )); + assert_eq!( + generated_intrinsic_marker("cuda_device::barrier::barrier_cta_red_or_aligned_count"), + Some("v1:i1023") + ); + assert!(!is_generated_intrinsic_path( + "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i1023" + )); + } + #[test] + fn barrier_cta_red_or_all_uses_only_canonical_or_compatibility_defpaths() { + assert!(is_generated_intrinsic_path( + "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i1020" + )); + assert!(is_raw_generated_intrinsic_path( + "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i1020" + )); + assert_eq!( + generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i1020"), + Some("v1:i1020") + ); + assert!(matches!( + classify_raw_intrinsic_path( + "cuda_intrinsics", + "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i1020".into() + ), + RawIntrinsicIdentity::Known(_) + )); + assert!(!is_generated_intrinsic_path( + "cuda_intrinsics::barrier::barrier_cta_red_or_all" + )); + assert!(is_generated_intrinsic_path( + "cuda_device::barrier::barrier_cta_red_or_all" + )); + assert!(!is_raw_generated_intrinsic_path( + "cuda_device::barrier::barrier_cta_red_or_all" + )); + assert_eq!( + generated_intrinsic_marker("cuda_device::barrier::barrier_cta_red_or_all"), + Some("v1:i1020") + ); + assert!(!is_generated_intrinsic_path( + "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i1020" + )); + } + #[test] + fn barrier_cta_red_or_count_uses_only_canonical_or_compatibility_defpaths() { + assert!(is_generated_intrinsic_path( + "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i1021" + )); + assert!(is_raw_generated_intrinsic_path( + "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i1021" + )); + assert_eq!( + generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i1021"), + Some("v1:i1021") + ); + assert!(matches!( + classify_raw_intrinsic_path( + "cuda_intrinsics", + "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i1021".into() + ), + RawIntrinsicIdentity::Known(_) + )); + assert!(!is_generated_intrinsic_path( + "cuda_intrinsics::barrier::barrier_cta_red_or_count" + )); + assert!(is_generated_intrinsic_path( + "cuda_device::barrier::barrier_cta_red_or_count" + )); + assert!(!is_raw_generated_intrinsic_path( + "cuda_device::barrier::barrier_cta_red_or_count" + )); + assert_eq!( + generated_intrinsic_marker("cuda_device::barrier::barrier_cta_red_or_count"), + Some("v1:i1021") + ); + assert!(!is_generated_intrinsic_path( + "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i1021" + )); + } + #[test] + fn barrier_cta_red_popc_aligned_all_uses_only_canonical_or_compatibility_defpaths() { + assert!(is_generated_intrinsic_path( + "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i1026" + )); + assert!(is_raw_generated_intrinsic_path( + "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i1026" + )); + assert_eq!( + generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i1026"), + Some("v1:i1026") + ); + assert!(matches!( + classify_raw_intrinsic_path( + "cuda_intrinsics", + "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i1026".into() + ), + RawIntrinsicIdentity::Known(_) + )); + assert!(!is_generated_intrinsic_path( + "cuda_intrinsics::barrier::barrier_cta_red_popc_aligned_all" + )); + assert!(is_generated_intrinsic_path( + "cuda_device::barrier::barrier_cta_red_popc_aligned_all" + )); + assert!(!is_raw_generated_intrinsic_path( + "cuda_device::barrier::barrier_cta_red_popc_aligned_all" + )); + assert_eq!( + generated_intrinsic_marker("cuda_device::barrier::barrier_cta_red_popc_aligned_all"), + Some("v1:i1026") + ); + assert!(!is_generated_intrinsic_path( + "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i1026" + )); + } + #[test] + fn barrier_cta_red_popc_aligned_count_uses_only_canonical_or_compatibility_defpaths() { + assert!(is_generated_intrinsic_path( + "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i1027" + )); + assert!(is_raw_generated_intrinsic_path( + "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i1027" + )); + assert_eq!( + generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i1027"), + Some("v1:i1027") + ); + assert!(matches!( + classify_raw_intrinsic_path( + "cuda_intrinsics", + "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i1027".into() + ), + RawIntrinsicIdentity::Known(_) + )); + assert!(!is_generated_intrinsic_path( + "cuda_intrinsics::barrier::barrier_cta_red_popc_aligned_count" + )); + assert!(is_generated_intrinsic_path( + "cuda_device::barrier::barrier_cta_red_popc_aligned_count" + )); + assert!(!is_raw_generated_intrinsic_path( + "cuda_device::barrier::barrier_cta_red_popc_aligned_count" + )); + assert_eq!( + generated_intrinsic_marker("cuda_device::barrier::barrier_cta_red_popc_aligned_count"), + Some("v1:i1027") + ); + assert!(!is_generated_intrinsic_path( + "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i1027" + )); + } + #[test] + fn barrier_cta_red_popc_all_uses_only_canonical_or_compatibility_defpaths() { + assert!(is_generated_intrinsic_path( + "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i1024" + )); + assert!(is_raw_generated_intrinsic_path( + "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i1024" + )); + assert_eq!( + generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i1024"), + Some("v1:i1024") + ); + assert!(matches!( + classify_raw_intrinsic_path( + "cuda_intrinsics", + "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i1024".into() + ), + RawIntrinsicIdentity::Known(_) + )); + assert!(!is_generated_intrinsic_path( + "cuda_intrinsics::barrier::barrier_cta_red_popc_all" + )); + assert!(is_generated_intrinsic_path( + "cuda_device::barrier::barrier_cta_red_popc_all" + )); + assert!(!is_raw_generated_intrinsic_path( + "cuda_device::barrier::barrier_cta_red_popc_all" + )); + assert_eq!( + generated_intrinsic_marker("cuda_device::barrier::barrier_cta_red_popc_all"), + Some("v1:i1024") + ); + assert!(!is_generated_intrinsic_path( + "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i1024" + )); + } + #[test] + fn barrier_cta_red_popc_count_uses_only_canonical_or_compatibility_defpaths() { + assert!(is_generated_intrinsic_path( + "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i1025" + )); + assert!(is_raw_generated_intrinsic_path( + "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i1025" + )); + assert_eq!( + generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i1025"), + Some("v1:i1025") + ); + assert!(matches!( + classify_raw_intrinsic_path( + "cuda_intrinsics", + "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i1025".into() + ), + RawIntrinsicIdentity::Known(_) + )); + assert!(!is_generated_intrinsic_path( + "cuda_intrinsics::barrier::barrier_cta_red_popc_count" + )); + assert!(is_generated_intrinsic_path( + "cuda_device::barrier::barrier_cta_red_popc_count" + )); + assert!(!is_raw_generated_intrinsic_path( + "cuda_device::barrier::barrier_cta_red_popc_count" + )); + assert_eq!( + generated_intrinsic_marker("cuda_device::barrier::barrier_cta_red_popc_count"), + Some("v1:i1025") + ); + assert!(!is_generated_intrinsic_path( + "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i1025" + )); + } + #[test] fn barrier_cta_sync_uses_only_canonical_or_compatibility_defpaths() { assert!(is_generated_intrinsic_path( "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0883" @@ -59038,6 +60161,42 @@ mod tests { )); } #[test] + fn barrier_cta_sync_all_uses_only_canonical_or_compatibility_defpaths() { + assert!(is_generated_intrinsic_path( + "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i1028" + )); + assert!(is_raw_generated_intrinsic_path( + "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i1028" + )); + assert_eq!( + generated_intrinsic_marker("cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i1028"), + Some("v1:i1028") + ); + assert!(matches!( + classify_raw_intrinsic_path( + "cuda_intrinsics", + "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i1028".into() + ), + RawIntrinsicIdentity::Known(_) + )); + assert!(!is_generated_intrinsic_path( + "cuda_intrinsics::barrier::barrier_cta_sync_all" + )); + assert!(is_generated_intrinsic_path( + "cuda_device::barrier::barrier_cta_sync_all" + )); + assert!(!is_raw_generated_intrinsic_path( + "cuda_device::barrier::barrier_cta_sync_all" + )); + assert_eq!( + generated_intrinsic_marker("cuda_device::barrier::barrier_cta_sync_all"), + Some("v1:i1028") + ); + assert!(!is_generated_intrinsic_path( + "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v2::i1028" + )); + } + #[test] fn block_dim_x_uses_only_canonical_or_compatibility_defpaths() { assert!(is_generated_intrinsic_path( "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0003" diff --git a/crates/mir-lower/src/convert/generated_intrinsics.rs b/crates/mir-lower/src/convert/generated_intrinsics.rs index 4a76f39fd9..3e21698957 100644 --- a/crates/mir-lower/src/convert/generated_intrinsics.rs +++ b/crates/mir-lower/src/convert/generated_intrinsics.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. // LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. //! Generated conversion interfaces for admitted CUDA intrinsic families. @@ -12,6 +12,7 @@ use crate::conversion_interface::MirToLlvmConversion; use crate::convert::intrinsics::{ atomic::convert_packed_atom_add, + barrier_reduction::convert_barrier_reduction, basic::convert_sreg_read_inline, clc::{convert_generated_clc_query, convert_generated_clc_try_cancel}, common::{ @@ -52,15 +53,20 @@ use crate::{IntrinsicBackend, context}; use dialect_nvvm::ops::{ AbsBf16x2Op, AbsF16x2Op, ActiveMaskOp, AddBf16x2Op, AddF16x2Op, AddF32x2Op, AddFtzF32x2Op, BarWarpSyncOp, Barrier0Op, BarrierCtaArriveAlignedCountOp, BarrierCtaArriveCountOp, - BarrierCtaSyncAlignedCountOp, BarrierCtaSyncCountOp, BreakpointOp, ClcQueryGetFirstCtaidXOp, - ClcQueryGetFirstCtaidYOp, ClcQueryGetFirstCtaidZOp, ClcQueryIsCanceledOp, - ClcTryCancelMulticastOp, ClcTryCancelOp, ClusterBarrierModeAttr, ClusterBarrierOp, - ClusterSyncOp, CpAsyncBulkCommitGroupOp, CpAsyncBulkPrefetchTensor1dL2CacheHintOp, - CpAsyncBulkPrefetchTensor1dL2Op, CpAsyncBulkPrefetchTensor2dL2CacheHintOp, - CpAsyncBulkPrefetchTensor2dL2Op, CpAsyncBulkPrefetchTensor3dL2CacheHintOp, - CpAsyncBulkPrefetchTensor3dL2Op, CpAsyncBulkPrefetchTensor4dL2CacheHintOp, - CpAsyncBulkPrefetchTensor4dL2Op, CpAsyncBulkPrefetchTensor5dL2CacheHintOp, - CpAsyncBulkPrefetchTensor5dL2Op, CpAsyncBulkPrefetchTensorGather4TwoDimensionalL2CacheHintOp, + BarrierCtaRedAndAlignedAllOp, BarrierCtaRedAndAlignedCountOp, BarrierCtaRedAndAllOp, + BarrierCtaRedAndCountOp, BarrierCtaRedOrAlignedAllOp, BarrierCtaRedOrAlignedCountOp, + BarrierCtaRedOrAllOp, BarrierCtaRedOrCountOp, BarrierCtaRedPopcAlignedAllOp, + BarrierCtaRedPopcAlignedCountOp, BarrierCtaRedPopcAllOp, BarrierCtaRedPopcCountOp, + BarrierCtaSyncAlignedCountOp, BarrierCtaSyncAllOp, BarrierCtaSyncCountOp, BreakpointOp, + ClcQueryGetFirstCtaidXOp, ClcQueryGetFirstCtaidYOp, ClcQueryGetFirstCtaidZOp, + ClcQueryIsCanceledOp, ClcTryCancelMulticastOp, ClcTryCancelOp, ClusterBarrierModeAttr, + ClusterBarrierOp, ClusterSyncOp, CpAsyncBulkCommitGroupOp, + CpAsyncBulkPrefetchTensor1dL2CacheHintOp, CpAsyncBulkPrefetchTensor1dL2Op, + CpAsyncBulkPrefetchTensor2dL2CacheHintOp, CpAsyncBulkPrefetchTensor2dL2Op, + CpAsyncBulkPrefetchTensor3dL2CacheHintOp, CpAsyncBulkPrefetchTensor3dL2Op, + CpAsyncBulkPrefetchTensor4dL2CacheHintOp, CpAsyncBulkPrefetchTensor4dL2Op, + CpAsyncBulkPrefetchTensor5dL2CacheHintOp, CpAsyncBulkPrefetchTensor5dL2Op, + CpAsyncBulkPrefetchTensorGather4TwoDimensionalL2CacheHintOp, CpAsyncBulkPrefetchTensorGather4TwoDimensionalL2Op, CpAsyncBulkTensorG2sTile1dOp, CpAsyncBulkTensorG2sTile2dMulticastCg2Op, CpAsyncBulkTensorG2sTile2dMulticastOp, CpAsyncBulkTensorG2sTile2dOp, CpAsyncBulkTensorG2sTile3dOp, CpAsyncBulkTensorG2sTile4dOp, @@ -10688,6 +10694,246 @@ impl MirToLlvmConversion for ClcTryCancelMulticastOp { } } +#[op_interface_impl] +impl MirToLlvmConversion for BarrierCtaRedAndAlignedAllOp { + fn convert( + &self, + ctx: &mut Context, + rewriter: &mut DialectConversionRewriter, + operands_info: &OperandsInfo, + ) -> Result<()> { + convert_barrier_reduction( + ctx, + rewriter, + self.get_operation(), + operands_info, + "llvm_nvvm_barrier_cta_red_and_aligned_all", + "bar.red.and.pred", + true, + ) + } +} + +#[op_interface_impl] +impl MirToLlvmConversion for BarrierCtaRedAndAlignedCountOp { + fn convert( + &self, + ctx: &mut Context, + rewriter: &mut DialectConversionRewriter, + operands_info: &OperandsInfo, + ) -> Result<()> { + convert_barrier_reduction( + ctx, + rewriter, + self.get_operation(), + operands_info, + "llvm_nvvm_barrier_cta_red_and_aligned_count", + "bar.red.and.pred", + true, + ) + } +} + +#[op_interface_impl] +impl MirToLlvmConversion for BarrierCtaRedAndAllOp { + fn convert( + &self, + ctx: &mut Context, + rewriter: &mut DialectConversionRewriter, + operands_info: &OperandsInfo, + ) -> Result<()> { + convert_barrier_reduction( + ctx, + rewriter, + self.get_operation(), + operands_info, + "llvm_nvvm_barrier_cta_red_and_all", + "barrier.red.and.pred", + true, + ) + } +} + +#[op_interface_impl] +impl MirToLlvmConversion for BarrierCtaRedAndCountOp { + fn convert( + &self, + ctx: &mut Context, + rewriter: &mut DialectConversionRewriter, + operands_info: &OperandsInfo, + ) -> Result<()> { + convert_barrier_reduction( + ctx, + rewriter, + self.get_operation(), + operands_info, + "llvm_nvvm_barrier_cta_red_and_count", + "barrier.red.and.pred", + true, + ) + } +} + +#[op_interface_impl] +impl MirToLlvmConversion for BarrierCtaRedOrAlignedAllOp { + fn convert( + &self, + ctx: &mut Context, + rewriter: &mut DialectConversionRewriter, + operands_info: &OperandsInfo, + ) -> Result<()> { + convert_barrier_reduction( + ctx, + rewriter, + self.get_operation(), + operands_info, + "llvm_nvvm_barrier_cta_red_or_aligned_all", + "bar.red.or.pred", + true, + ) + } +} + +#[op_interface_impl] +impl MirToLlvmConversion for BarrierCtaRedOrAlignedCountOp { + fn convert( + &self, + ctx: &mut Context, + rewriter: &mut DialectConversionRewriter, + operands_info: &OperandsInfo, + ) -> Result<()> { + convert_barrier_reduction( + ctx, + rewriter, + self.get_operation(), + operands_info, + "llvm_nvvm_barrier_cta_red_or_aligned_count", + "bar.red.or.pred", + true, + ) + } +} + +#[op_interface_impl] +impl MirToLlvmConversion for BarrierCtaRedOrAllOp { + fn convert( + &self, + ctx: &mut Context, + rewriter: &mut DialectConversionRewriter, + operands_info: &OperandsInfo, + ) -> Result<()> { + convert_barrier_reduction( + ctx, + rewriter, + self.get_operation(), + operands_info, + "llvm_nvvm_barrier_cta_red_or_all", + "barrier.red.or.pred", + true, + ) + } +} + +#[op_interface_impl] +impl MirToLlvmConversion for BarrierCtaRedOrCountOp { + fn convert( + &self, + ctx: &mut Context, + rewriter: &mut DialectConversionRewriter, + operands_info: &OperandsInfo, + ) -> Result<()> { + convert_barrier_reduction( + ctx, + rewriter, + self.get_operation(), + operands_info, + "llvm_nvvm_barrier_cta_red_or_count", + "barrier.red.or.pred", + true, + ) + } +} + +#[op_interface_impl] +impl MirToLlvmConversion for BarrierCtaRedPopcAlignedAllOp { + fn convert( + &self, + ctx: &mut Context, + rewriter: &mut DialectConversionRewriter, + operands_info: &OperandsInfo, + ) -> Result<()> { + convert_barrier_reduction( + ctx, + rewriter, + self.get_operation(), + operands_info, + "llvm_nvvm_barrier_cta_red_popc_aligned_all", + "bar.red.popc.u32", + false, + ) + } +} + +#[op_interface_impl] +impl MirToLlvmConversion for BarrierCtaRedPopcAlignedCountOp { + fn convert( + &self, + ctx: &mut Context, + rewriter: &mut DialectConversionRewriter, + operands_info: &OperandsInfo, + ) -> Result<()> { + convert_barrier_reduction( + ctx, + rewriter, + self.get_operation(), + operands_info, + "llvm_nvvm_barrier_cta_red_popc_aligned_count", + "bar.red.popc.u32", + false, + ) + } +} + +#[op_interface_impl] +impl MirToLlvmConversion for BarrierCtaRedPopcAllOp { + fn convert( + &self, + ctx: &mut Context, + rewriter: &mut DialectConversionRewriter, + operands_info: &OperandsInfo, + ) -> Result<()> { + convert_barrier_reduction( + ctx, + rewriter, + self.get_operation(), + operands_info, + "llvm_nvvm_barrier_cta_red_popc_all", + "barrier.red.popc.u32", + false, + ) + } +} + +#[op_interface_impl] +impl MirToLlvmConversion for BarrierCtaRedPopcCountOp { + fn convert( + &self, + ctx: &mut Context, + rewriter: &mut DialectConversionRewriter, + operands_info: &OperandsInfo, + ) -> Result<()> { + convert_barrier_reduction( + ctx, + rewriter, + self.get_operation(), + operands_info, + "llvm_nvvm_barrier_cta_red_popc_count", + "barrier.red.popc.u32", + false, + ) + } +} + #[op_interface_impl] impl MirToLlvmConversion for BarrierCtaArriveCountOp { fn convert( @@ -10764,6 +11010,25 @@ impl MirToLlvmConversion for BarrierCtaSyncAlignedCountOp { } } +#[op_interface_impl] +impl MirToLlvmConversion for BarrierCtaSyncAllOp { + fn convert( + &self, + ctx: &mut Context, + rewriter: &mut DialectConversionRewriter, + operands_info: &OperandsInfo, + ) -> Result<()> { + convert_counted_barrier( + ctx, + rewriter, + self.get_operation(), + operands_info, + "llvm_nvvm_barrier_cta_sync_all", + "barrier.sync $0;", + ) + } +} + #[op_interface_impl] impl MirToLlvmConversion for GridDependencyLaunchDependentsOp { fn convert( diff --git a/crates/mir-lower/src/convert/intrinsics/barrier_reduction.rs b/crates/mir-lower/src/convert/intrinsics/barrier_reduction.rs new file mode 100644 index 0000000000..f137e5c6d6 --- /dev/null +++ b/crates/mir-lower/src/convert/intrinsics/barrier_reduction.rs @@ -0,0 +1,124 @@ +/* + * SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + * SPDX-License-Identifier: Apache-2.0 + */ + +//! Lowering for CTA barrier reductions. + +use crate::convert::intrinsics::common::{call_intrinsic, inline_asm_convergent, trunc_to_i1}; +use crate::{IntrinsicBackend, context}; +use llvm_export::types as llvm_types; +use pliron::builtin::types::{IntegerType, Signedness}; +use pliron::context::{Context, Ptr}; +use pliron::irbuild::dialect_conversion::{DialectConversionRewriter, OperandsInfo}; +use pliron::irbuild::rewriter::Rewriter; +use pliron::operation::Operation; +use pliron::result::Result; + +pub(crate) fn convert_barrier_reduction( + ctx: &mut Context, + rewriter: &mut DialectConversionRewriter, + op: Ptr, + _operands_info: &OperandsInfo, + intrinsic_name: &str, + ptx_instruction: &str, + predicate_result: bool, +) -> Result<()> { + let operands: Vec<_> = op.deref(ctx).operands().collect(); + if !matches!(operands.len(), 2 | 3) || op.deref(ctx).get_num_results() != 1 { + return pliron::input_err_noloc!( + "CTA barrier reduction requires two or three operands and one result" + ); + } + let i32_ty = IntegerType::get(ctx, 32, Signedness::Signless); + let i1_ty = IntegerType::get(ctx, 1, Signedness::Signless); + if context::lowering_options(ctx).intrinsic_backend == IntrinsicBackend::LlvmNvptx { + let result_ty = if predicate_result { i1_ty } else { i32_ty }; + let mut argument_types = vec![i32_ty.into()]; + if operands.len() == 3 { + argument_types.push(i32_ty.into()); + } + argument_types.push(i1_ty.into()); + let function_ty = llvm_types::FuncType::get(ctx, result_ty.into(), argument_types, false); + let call = call_intrinsic(ctx, rewriter, op, intrinsic_name, function_ty, operands)?; + rewriter.replace_operation(ctx, op, call); + return Ok(()); + } + + let (template, constraints) = + barrier_reduction_inline_recipe(ptx_instruction, operands.len(), predicate_result); + if predicate_result { + let asm = inline_asm_convergent( + ctx, + rewriter, + op, + i32_ty.into(), + operands, + &template, + constraints, + ); + let materialized = asm.deref(ctx).get_result(0); + let result = trunc_to_i1(ctx, rewriter, materialized); + rewriter.replace_operation_with_values(ctx, op, vec![result]); + } else { + let asm = inline_asm_convergent( + ctx, + rewriter, + op, + i32_ty.into(), + operands, + &template, + constraints, + ); + rewriter.replace_operation(ctx, op, asm); + } + Ok(()) +} + +fn barrier_reduction_inline_recipe( + ptx_instruction: &str, + operand_count: usize, + predicate_result: bool, +) -> (String, &'static str) { + debug_assert!(matches!(operand_count, 2 | 3)); + let input_refs = (1..=operand_count) + .map(|index| format!("${index}")) + .collect::>() + .join(", "); + let constraints = if operand_count == 3 { + "=r,r,r,b,~{memory}" + } else { + "=r,r,b,~{memory}" + }; + if predicate_result { + ( + format!("{{ .reg .pred p; {ptx_instruction} p, {input_refs}; selp.b32 $0, 1, 0, p; }}"), + constraints, + ) + } else { + (format!("{ptx_instruction} $0, {input_refs};"), constraints) + } +} + +#[cfg(test)] +mod tests { + use super::barrier_reduction_inline_recipe; + + #[test] + fn predicate_recipe_materializes_predicate_through_selp() { + let (template, constraints) = + barrier_reduction_inline_recipe("barrier.red.and.pred", 3, true); + assert_eq!( + template, + "{ .reg .pred p; barrier.red.and.pred p, $1, $2, $3; selp.b32 $0, 1, 0, p; }" + ); + assert_eq!(constraints, "=r,r,r,b,~{memory}"); + } + + #[test] + fn popc_recipe_returns_the_direct_u32_result() { + let (template, constraints) = barrier_reduction_inline_recipe("bar.red.popc.u32", 2, false); + assert_eq!(template, "bar.red.popc.u32 $0, $1, $2;"); + assert_eq!(constraints, "=r,r,b,~{memory}"); + } +} diff --git a/crates/mir-lower/src/convert/intrinsics/execution_control.rs b/crates/mir-lower/src/convert/intrinsics/execution_control.rs index f9d2bfda45..27adfedb33 100644 --- a/crates/mir-lower/src/convert/intrinsics/execution_control.rs +++ b/crates/mir-lower/src/convert/intrinsics/execution_control.rs @@ -26,9 +26,9 @@ pub(crate) fn convert_counted_barrier( ptx: &str, ) -> Result<()> { let operands: Vec<_> = op.deref(ctx).operands().collect(); - if operands.len() != 2 || op.deref(ctx).get_num_results() != 0 { + if !matches!(operands.len(), 1 | 2) || op.deref(ctx).get_num_results() != 0 { return pliron::input_err_noloc!( - "counted CTA barrier requires two operands and no results" + "counted CTA barrier requires one or two operands and no results" ); } let void_ty = llvm_types::VoidType::get(ctx); @@ -47,7 +47,7 @@ pub(crate) fn convert_counted_barrier( let function_ty = llvm_types::FuncType::get( ctx, void_ty.into(), - vec![i32_ty.into(), i32_ty.into()], + vec![i32_ty.into(); operands.len()], false, ); call_intrinsic(ctx, rewriter, op, intrinsic_name, function_ty, operands)?; diff --git a/crates/mir-lower/src/convert/intrinsics/mod.rs b/crates/mir-lower/src/convert/intrinsics/mod.rs index 460c8de290..98fbb0cabb 100644 --- a/crates/mir-lower/src/convert/intrinsics/mod.rs +++ b/crates/mir-lower/src/convert/intrinsics/mod.rs @@ -65,6 +65,7 @@ //! |--------------------------|---------------------------------------------------------------------------| //! | [`asm`] | User-authored inline PTX lowering | //! | [`atomic`] | Atomic operation conversion: NVVM atomic dialect → LLVM atomic instructions| +//! | [`barrier_reduction`] | Lower CTA barrier reductions through typed NVVM or inline PTX | //! | [`basic`] | Basic NVVM intrinsic conversion for special registers | //! | [`clc`] | Lower generated Cluster Launch Control operations through typed NVVM calls| //! | [`cluster`] | Compatibility lowering for derived cluster-grid values | @@ -97,6 +98,7 @@ pub mod asm; pub mod atomic; +pub mod barrier_reduction; pub mod basic; pub mod clc; pub mod cluster; diff --git a/crates/mir-lower/tests/lowering_test.rs b/crates/mir-lower/tests/lowering_test.rs index 06a47809bc..4bb0e779f6 100644 --- a/crates/mir-lower/tests/lowering_test.rs +++ b/crates/mir-lower/tests/lowering_test.rs @@ -6276,6 +6276,301 @@ fn lowered_kernel_body( panic!("lowered kernel function not found") } +#[derive(Clone, Copy)] +enum BarrierReductionTestOp { + AndAll, + AndCount, + OrAll, + OrCount, + PopcAll, + PopcCount, +} + +struct BarrierReductionTestCase { + operation: BarrierReductionTestOp, + intrinsic: &'static str, + instruction: &'static str, + predicate_result: bool, + operand_count: usize, +} + +const BARRIER_REDUCTION_CASES: [BarrierReductionTestCase; 6] = [ + BarrierReductionTestCase { + operation: BarrierReductionTestOp::AndAll, + intrinsic: "llvm_nvvm_barrier_cta_red_and_all", + instruction: "barrier.red.and.pred", + predicate_result: true, + operand_count: 2, + }, + BarrierReductionTestCase { + operation: BarrierReductionTestOp::AndCount, + intrinsic: "llvm_nvvm_barrier_cta_red_and_count", + instruction: "barrier.red.and.pred", + predicate_result: true, + operand_count: 3, + }, + BarrierReductionTestCase { + operation: BarrierReductionTestOp::OrAll, + intrinsic: "llvm_nvvm_barrier_cta_red_or_all", + instruction: "barrier.red.or.pred", + predicate_result: true, + operand_count: 2, + }, + BarrierReductionTestCase { + operation: BarrierReductionTestOp::OrCount, + intrinsic: "llvm_nvvm_barrier_cta_red_or_count", + instruction: "barrier.red.or.pred", + predicate_result: true, + operand_count: 3, + }, + BarrierReductionTestCase { + operation: BarrierReductionTestOp::PopcAll, + intrinsic: "llvm_nvvm_barrier_cta_red_popc_all", + instruction: "barrier.red.popc.u32", + predicate_result: false, + operand_count: 2, + }, + BarrierReductionTestCase { + operation: BarrierReductionTestOp::PopcCount, + intrinsic: "llvm_nvvm_barrier_cta_red_popc_count", + instruction: "barrier.red.popc.u32", + predicate_result: false, + operand_count: 3, + }, +]; + +fn lower_barrier_reduction_case( + case: &BarrierReductionTestCase, + backend: mir_lower::IntrinsicBackend, +) -> Result<(Context, pliron::context::Ptr), anyhow::Error> { + use pliron::builtin::types::{IntegerType, Signedness}; + + let mut ctx = make_test_ctx(); + let u32_ty = IntegerType::get(&ctx, 32, Signedness::Unsigned); + let i1_ty = IntegerType::get(&ctx, 1, Signedness::Signless); + let mut argument_types = vec![u32_ty.into()]; + if case.operand_count == 3 { + argument_types.push(u32_ty.into()); + } + argument_types.push(i1_ty.into()); + let (module_ptr, entry) = build_test_kernel(&mut ctx, argument_types); + let operands = entry.deref(&ctx).arguments().collect::>(); + let result_ty = if case.predicate_result { + i1_ty.into() + } else { + u32_ty.into() + }; + + macro_rules! build { + ($op:ty) => { + Operation::new( + &mut ctx, + <$op>::get_concrete_op_info(), + vec![result_ty], + operands, + vec![], + 0, + ) + }; + } + let reduction = match case.operation { + BarrierReductionTestOp::AndAll => build!(nvvm::BarrierCtaRedAndAllOp), + BarrierReductionTestOp::AndCount => build!(nvvm::BarrierCtaRedAndCountOp), + BarrierReductionTestOp::OrAll => build!(nvvm::BarrierCtaRedOrAllOp), + BarrierReductionTestOp::OrCount => build!(nvvm::BarrierCtaRedOrCountOp), + BarrierReductionTestOp::PopcAll => build!(nvvm::BarrierCtaRedPopcAllOp), + BarrierReductionTestOp::PopcCount => build!(nvvm::BarrierCtaRedPopcCountOp), + }; + reduction.insert_at_back(entry, &ctx); + append_return(&mut ctx, entry); + + mir_lower::lower_mir_to_llvm_with_options( + &mut ctx, + module_ptr, + mir_lower::LoweringOptions { + intrinsic_backend: backend, + ..Default::default() + }, + ) + .map_err(|error| anyhow::anyhow!("{error}"))?; + Ok((ctx, module_ptr)) +} + +#[test] +fn test_barrier_reductions_llvm_nvptx_use_exact_typed_calls() -> Result<(), anyhow::Error> { + use pliron::builtin::types::IntegerType; + use pliron::r#type::Typed; + + for case in &BARRIER_REDUCTION_CASES { + let (ctx, module_ptr) = + lower_barrier_reduction_case(case, mir_lower::IntrinsicBackend::LlvmNvptx)?; + let body = lowered_kernel_body(&ctx, module_ptr); + assert!( + body.iter() + .all(|op| Operation::get_op::(*op, &ctx).is_none()), + "{} must use its typed LLVM route", + case.intrinsic + ); + let calls = body + .iter() + .filter_map(|op| Operation::get_op::(*op, &ctx)) + .filter(|call| { + matches!(call.callee(&ctx), CallOpCallable::Direct(ref callee) if callee.to_string() == case.intrinsic) + }) + .collect::>(); + assert_eq!(calls.len(), 1, "exact typed call for {}", case.intrinsic); + let call = &calls[0]; + let call_op = call.get_operation(); + assert_eq!(call_op.deref(&ctx).get_num_operands(), case.operand_count); + assert_eq!(call_op.deref(&ctx).get_num_results(), 1); + let block = call_op.deref(&ctx).get_parent_block().unwrap(); + let expected_operands = block.deref(&ctx).arguments().collect::>(); + assert_eq!( + call_op.deref(&ctx).operands().collect::>(), + expected_operands, + "typed operand order for {}", + case.intrinsic + ); + let expected_widths = if case.operand_count == 2 { + vec![32, 1] + } else { + vec![32, 32, 1] + }; + let operand_widths = call_op + .deref(&ctx) + .operands() + .map(|value| { + value + .get_type(&ctx) + .deref(&ctx) + .downcast_ref::() + .expect("typed barrier operand is integer") + .width() + }) + .collect::>(); + assert_eq!( + operand_widths, expected_widths, + "{} signature", + case.intrinsic + ); + let result_width = call_op + .deref(&ctx) + .get_result(0) + .get_type(&ctx) + .deref(&ctx) + .downcast_ref::() + .expect("typed barrier result is integer") + .width(); + assert_eq!(result_width, if case.predicate_result { 1 } else { 32 }); + } + Ok(()) +} + +#[test] +fn test_barrier_reductions_libnvvm_use_exact_convergent_inline_ptx() -> Result<(), anyhow::Error> { + use pliron::builtin::types::IntegerType; + use pliron::r#type::Typed; + + for case in &BARRIER_REDUCTION_CASES { + let (ctx, module_ptr) = + lower_barrier_reduction_case(case, mir_lower::IntrinsicBackend::LibNvvm)?; + let body = lowered_kernel_body(&ctx, module_ptr); + assert!( + body.iter() + .all(|op| Operation::get_op::(*op, &ctx).is_none()), + "{} must not use a typed call on libNVVM", + case.intrinsic + ); + let asms = body + .iter() + .filter_map(|op| Operation::get_op::(*op, &ctx)) + .collect::>(); + assert_eq!(asms.len(), 1, "one inline asm for {}", case.intrinsic); + let asm = &asms[0]; + let input_refs = (1..=case.operand_count) + .map(|index| format!("${index}")) + .collect::>() + .join(", "); + let expected_template = if case.predicate_result { + format!( + "{{ .reg .pred p; {} p, {input_refs}; selp.b32 $0, 1, 0, p; }}", + case.instruction + ) + } else { + format!("{} $0, {input_refs};", case.instruction) + }; + assert_eq!( + asm.get_attr_inline_asm_template(&ctx) + .map(|value| String::from((*value).clone())) + .as_deref(), + Some(expected_template.as_str()) + ); + let expected_constraints = if case.operand_count == 2 { + "=r,r,b,~{memory}" + } else { + "=r,r,r,b,~{memory}" + }; + assert_eq!( + asm.get_attr_inline_asm_constraints(&ctx) + .map(|value| String::from((*value).clone())) + .as_deref(), + Some(expected_constraints) + ); + assert_eq!(llvm::asm_kind(&ctx, asm), llvm::AsmKind::Convergent); + assert_eq!( + asm.get_operation().deref(&ctx).get_num_operands(), + case.operand_count, + "operand order/arity for {}", + case.intrinsic + ); + let block = asm.get_operation().deref(&ctx).get_parent_block().unwrap(); + let expected_operands = block.deref(&ctx).arguments().collect::>(); + assert_eq!( + asm.get_operation() + .deref(&ctx) + .operands() + .collect::>(), + expected_operands, + "inline-asm operand order for {}", + case.intrinsic + ); + let asm_result = asm.get_operation().deref(&ctx).get_result(0); + assert_eq!( + asm_result + .get_type(&ctx) + .deref(&ctx) + .downcast_ref::() + .expect("asm result is i32") + .width(), + 32 + ); + let truncs = body + .iter() + .filter_map(|op| Operation::get_op::(*op, &ctx)) + .filter(|trunc| trunc.get_operation().deref(&ctx).get_operand(0) == asm_result) + .collect::>(); + assert_eq!( + truncs.len(), + usize::from(case.predicate_result), + "predicate materialization for {}", + case.intrinsic + ); + if let Some(trunc) = truncs.first() { + let width = trunc + .get_operation() + .deref(&ctx) + .get_result(0) + .get_type(&ctx) + .deref(&ctx) + .downcast_ref::() + .expect("predicate trunc result is i1") + .width(); + assert_eq!(width, 1); + } + } + Ok(()) +} + fn assert_ldmatrix_producer_result_shape( ctx: &Context, op: pliron::context::Ptr, diff --git a/crates/rustc-codegen-cuda/src/generated_intrinsics.rs b/crates/rustc-codegen-cuda/src/generated_intrinsics.rs index d5aad0af7a..881e66a026 100644 --- a/crates/rustc-codegen-cuda/src/generated_intrinsics.rs +++ b/crates/rustc-codegen-cuda/src/generated_intrinsics.rs @@ -4,7 +4,7 @@ */ // @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +// Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. // LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. //! Generated collector predicates for intrinsic placeholder functions. @@ -52,8 +52,21 @@ pub(crate) const GENERATED_INTRINSIC_CANONICAL_PATHS: &[&str] = &[ "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0282", "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0885", "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0886", + "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i1018", + "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i1019", + "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i1016", + "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i1017", + "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i1022", + "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i1023", + "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i1020", + "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i1021", + "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i1026", + "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i1027", + "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i1024", + "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i1025", "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0883", "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0884", + "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i1028", "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0003", "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0007", "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0011", @@ -1070,8 +1083,21 @@ pub(crate) const GENERATED_INTRINSIC_PUBLIC_PATHS: &[&str] = &[ "cuda_intrinsics::cluster::barrier_cluster_wait_aligned", "cuda_intrinsics::barrier::barrier_cta_arrive", "cuda_intrinsics::barrier::barrier_cta_arrive_aligned", + "cuda_intrinsics::barrier::barrier_cta_red_and_aligned_all", + "cuda_intrinsics::barrier::barrier_cta_red_and_aligned_count", + "cuda_intrinsics::barrier::barrier_cta_red_and_all", + "cuda_intrinsics::barrier::barrier_cta_red_and_count", + "cuda_intrinsics::barrier::barrier_cta_red_or_aligned_all", + "cuda_intrinsics::barrier::barrier_cta_red_or_aligned_count", + "cuda_intrinsics::barrier::barrier_cta_red_or_all", + "cuda_intrinsics::barrier::barrier_cta_red_or_count", + "cuda_intrinsics::barrier::barrier_cta_red_popc_aligned_all", + "cuda_intrinsics::barrier::barrier_cta_red_popc_aligned_count", + "cuda_intrinsics::barrier::barrier_cta_red_popc_all", + "cuda_intrinsics::barrier::barrier_cta_red_popc_count", "cuda_intrinsics::barrier::barrier_cta_sync", "cuda_intrinsics::barrier::barrier_cta_sync_aligned", + "cuda_intrinsics::barrier::barrier_cta_sync_all", "cuda_intrinsics::sreg::block_dim_x", "cuda_intrinsics::sreg::block_dim_y", "cuda_intrinsics::sreg::block_dim_z", @@ -2094,8 +2120,21 @@ pub(crate) fn is_generated_intrinsic_canonical_path(path: &str) -> bool { | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0282" | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0885" | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0886" + | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i1018" + | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i1019" + | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i1016" + | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i1017" + | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i1022" + | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i1023" + | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i1020" + | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i1021" + | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i1026" + | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i1027" + | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i1024" + | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i1025" | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0883" | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0884" + | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i1028" | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0003" | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0007" | "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0011" @@ -3115,8 +3154,21 @@ pub(crate) fn is_generated_intrinsic_compatibility_path(path: &str) -> bool { | "cuda_device::cluster::barrier_cluster_wait_aligned" | "cuda_device::barrier::barrier_cta_arrive" | "cuda_device::barrier::barrier_cta_arrive_aligned" + | "cuda_device::barrier::barrier_cta_red_and_aligned_all" + | "cuda_device::barrier::barrier_cta_red_and_aligned_count" + | "cuda_device::barrier::barrier_cta_red_and_all" + | "cuda_device::barrier::barrier_cta_red_and_count" + | "cuda_device::barrier::barrier_cta_red_or_aligned_all" + | "cuda_device::barrier::barrier_cta_red_or_aligned_count" + | "cuda_device::barrier::barrier_cta_red_or_all" + | "cuda_device::barrier::barrier_cta_red_or_count" + | "cuda_device::barrier::barrier_cta_red_popc_aligned_all" + | "cuda_device::barrier::barrier_cta_red_popc_aligned_count" + | "cuda_device::barrier::barrier_cta_red_popc_all" + | "cuda_device::barrier::barrier_cta_red_popc_count" | "cuda_device::barrier::barrier_cta_sync" | "cuda_device::barrier::barrier_cta_sync_aligned" + | "cuda_device::barrier::barrier_cta_sync_all" | "cuda_device::thread::blockDim_x" | "cuda_device::blockDim_x" | "cuda_device::thread::blockDim_y" diff --git a/intrinsics/abi-v1.toml b/intrinsics/abi-v1.toml index ef18163ce1..d5f818278e 100644 --- a/intrinsics/abi-v1.toml +++ b/intrinsics/abi-v1.toml @@ -7075,3 +7075,94 @@ status = "active" catalog_id = "tcgen05_mma_e2m1" operation_key = "tcgen05.mma.shared.e2m1" raw_rust_signature = { safe = false, arguments = ["u32", "u64", "u64", "u32", "bool"], result = "()" } + +[[entry]] +abi_id = "i1016" +status = "active" +catalog_id = "barrier_cta_red_and_all" +operation_key = "synchronization.cta.barrier.reduction.and.all" +raw_rust_signature = { safe = false, arguments = ["u32","bool"], result = "bool" } + +[[entry]] +abi_id = "i1017" +status = "active" +catalog_id = "barrier_cta_red_and_count" +operation_key = "synchronization.cta.barrier.reduction.and.count" +raw_rust_signature = { safe = false, arguments = ["u32","u32","bool"], result = "bool" } + +[[entry]] +abi_id = "i1018" +status = "active" +catalog_id = "barrier_cta_red_and_aligned_all" +operation_key = "synchronization.cta.bar.reduction.and.all" +raw_rust_signature = { safe = false, arguments = ["u32","bool"], result = "bool" } + +[[entry]] +abi_id = "i1019" +status = "active" +catalog_id = "barrier_cta_red_and_aligned_count" +operation_key = "synchronization.cta.bar.reduction.and.count" +raw_rust_signature = { safe = false, arguments = ["u32","u32","bool"], result = "bool" } + +[[entry]] +abi_id = "i1020" +status = "active" +catalog_id = "barrier_cta_red_or_all" +operation_key = "synchronization.cta.barrier.reduction.or.all" +raw_rust_signature = { safe = false, arguments = ["u32","bool"], result = "bool" } + +[[entry]] +abi_id = "i1021" +status = "active" +catalog_id = "barrier_cta_red_or_count" +operation_key = "synchronization.cta.barrier.reduction.or.count" +raw_rust_signature = { safe = false, arguments = ["u32","u32","bool"], result = "bool" } + +[[entry]] +abi_id = "i1022" +status = "active" +catalog_id = "barrier_cta_red_or_aligned_all" +operation_key = "synchronization.cta.bar.reduction.or.all" +raw_rust_signature = { safe = false, arguments = ["u32","bool"], result = "bool" } + +[[entry]] +abi_id = "i1023" +status = "active" +catalog_id = "barrier_cta_red_or_aligned_count" +operation_key = "synchronization.cta.bar.reduction.or.count" +raw_rust_signature = { safe = false, arguments = ["u32","u32","bool"], result = "bool" } + +[[entry]] +abi_id = "i1024" +status = "active" +catalog_id = "barrier_cta_red_popc_all" +operation_key = "synchronization.cta.barrier.reduction.popc.all" +raw_rust_signature = { safe = false, arguments = ["u32","bool"], result = "u32" } + +[[entry]] +abi_id = "i1025" +status = "active" +catalog_id = "barrier_cta_red_popc_count" +operation_key = "synchronization.cta.barrier.reduction.popc.count" +raw_rust_signature = { safe = false, arguments = ["u32","u32","bool"], result = "u32" } + +[[entry]] +abi_id = "i1026" +status = "active" +catalog_id = "barrier_cta_red_popc_aligned_all" +operation_key = "synchronization.cta.bar.reduction.popc.all" +raw_rust_signature = { safe = false, arguments = ["u32","bool"], result = "u32" } + +[[entry]] +abi_id = "i1027" +status = "active" +catalog_id = "barrier_cta_red_popc_aligned_count" +operation_key = "synchronization.cta.bar.reduction.popc.count" +raw_rust_signature = { safe = false, arguments = ["u32","u32","bool"], result = "u32" } + +[[entry]] +abi_id = "i1028" +status = "active" +catalog_id = "barrier_cta_sync_all" +operation_key = "synchronization.cta.barrier.all" +raw_rust_signature = { safe = false, arguments = ["u32"], result = "()" } diff --git a/intrinsics/catalog.json b/intrinsics/catalog.json index fd84d0abe8..9c6584d34a 100644 --- a/intrinsics/catalog.json +++ b/intrinsics/catalog.json @@ -11,9 +11,11 @@ }, "inputs": { "imported_sha256": "7fc84823d448f56192e265a6c057ea72155c84df2b6575b0235199d445db6a2f", - "overlay_sha256": "d3c17b80372635c8a8eb6b26abcdbacf59755c7a2d880abc2cc925cecf2fc538", - "abi_ledger_sha256": "47c1f9c8fce67ea775bd51f2fd3312288eb1c039ce65523c548e36052f284a6d", + "overlay_sha256": "410255e461915b84ad47b9ff5deea80d372e62060ff98dfa40889aa04c79c8ac", + "abi_ledger_sha256": "ed0f3364094ef94cae9cbfcdfae5faeaa9afe1c521442aa2d4fb405129be29bb", "evidence_sha256": [ + "cuda-12.9-libnvvm-12.9.86-barrier-reduction.json:dd03e183fea6a89a1d1b0ea8d58d5d63d8367906952cbe54ffcd956bfa61a45b", + "cuda-12.9-libnvvm-12.9.86-execution-control.json:7c0105677a95503bf620455c62a70d009fa35e16d1bad9ab8dfa669f08207a6b", "cuda-12.9-libnvvm-12.9.86-f32x2.json:bc5bb505677989affa9ac1044da772b4eb349700dc65e16f09fffffa1f5c493e", "cuda-13.3-libnvvm-13.3.33-blackwell-ldmatrix.json:806155f5468d672b6bd969b72d9821155cc6a1c4422eb210ca0fc0a78eb295fb", "cuda-13.3-libnvvm-13.3.33-clc.json:0a3e049a8b606276302acf6d2f3dd1d41b632b04dd72799a7def8ebbec414752", @@ -70,6 +72,7 @@ "cuda-13.3-libnvvm-13.3.73-tma-descriptor-control.json:ac44f485122404f9a900cfb94bff658160a6c23d9e2f8ef74bb751f044b848fc", "cuda-13.3-libnvvm-13.3.73-tma-reduce.json:f5df5bb51068966594660cb01b1b28c3b72cb004c456fcd8dff377ff0bee4fc0", "cuda-13.3-libnvvm-13.3.73-tma.json:8607f93605f215858a98075a0ea1394f2718d090538bcaf0a795e11b4cb66d47", + "rust-llvm-22.1.2-1cb4e383-barrier-reduction.json:27f833bb1783ad007137d9d8e205c69b64ec93ecada81151e96d496ec6532016", "rust-llvm-22.1.2-1cb4e383-blackwell-ldmatrix.json:11c4c1ad6a23362bcdb6f1155d888498eb548f8fd07c03d52bf22d4780278c34", "rust-llvm-22.1.2-1cb4e383-clc.json:3cff4d4dbf0c505db87979c021de292395ef6383a72f610cb0d30196f644692f", "rust-llvm-22.1.2-1cb4e383-cluster-barrier.json:10b857690722e43670121d16b356ea0074105968388aa91f5012e7aaa63fd795", @@ -79,7 +82,7 @@ "rust-llvm-22.1.2-1cb4e383-cp-async.json:e6b2160e920c7f0bf00151a6bc3409e505bcac62df74395387a8f2f32c05bd5c", "rust-llvm-22.1.2-1cb4e383-debug-control.json:eaee9dadc7aa4d82eae6fe1d4a557cddc6cadc770de670dd9be3c16c6478bc48", "rust-llvm-22.1.2-1cb4e383-elect.json:42323b89102e76bc816ba694ae0a9a07dc3957289fb8debed6887097556c3c7f", - "rust-llvm-22.1.2-1cb4e383-execution-control.json:e39a53adecc39282a8f0d98e995dc15dce3097bfefa328fc7a8321a0c3052b8c", + "rust-llvm-22.1.2-1cb4e383-execution-control.json:d4fe31bbb058db5f14cf84f8175751cc46d98e80896b697d7478c30bcd5c6fea", "rust-llvm-22.1.2-1cb4e383-extended-minmax.json:4429a02bbf14abf8fe8d3b6be28dbbb6f2142e84aefea52f15cb514b1bb8df93", "rust-llvm-22.1.2-1cb4e383-f32x2.json:69567be54898fd4faf23aaf59ca01ab07ec529dae8b884cb1cbdf7f5ef82f712", "rust-llvm-22.1.2-1cb4e383-integer-minmax.json:e07bc847365cd71d0d20502f225508d48e2de47866c865f09b696caf984a97e3", @@ -9357,6 +9360,2514 @@ }, "summary": "Signals arrival of the requested number of CTA threads at an aligned numbered barrier without waiting." }, + { + "id": "barrier_cta_red_and_aligned_all", + "operation_key": "synchronization.cta.bar.reduction.and.all", + "family": "barrier_reduction", + "source": { + "kind": "llvm_imported", + "source_record": "int_nvvm_barrier_cta_red_and_aligned_all" + }, + "selections": [ + { + "source_record": "BARRIER_CTA_RED_AND_ALIGNED_ALL_ip", + "asm": "bar.red.and.pred \t$dest, $i, $pred;", + "predicates": [] + }, + { + "source_record": "BARRIER_CTA_RED_AND_ALIGNED_ALL_rp", + "asm": "bar.red.and.pred \t$dest, $i, $pred;", + "predicates": [] + } + ], + "rust": { + "abi_id": "i1018", + "module": "barrier", + "name": "barrier_cta_red_and_aligned_all", + "arguments": [ + "u32", + "bool" + ], + "result": "bool", + "safe": false, + "must_use": true, + "safe_allowlist_reason": null, + "canonical_path": "cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i1018", + "public_path": "cuda_intrinsics::barrier::barrier_cta_red_and_aligned_all", + "compatibility_paths": [ + "cuda_device::barrier::barrier_cta_red_and_aligned_all" + ] + }, + "dialect": { + "op_type": "BarrierCtaRedAndAlignedAllOp", + "op_name": "nvvm.barrier_cta_red_and_aligned_all", + "operands": [ + "i32", + "i1" + ], + "results": [ + "i1" + ] + }, + "llvm": { + "symbol": "llvm.nvvm.barrier.cta.red.and.aligned.all", + "arguments": [ + "i32", + "i1" + ], + "results": [ + "i1" + ], + "properties": [ + "IntrConvergent", + "IntrNoCallback" + ], + "result_facts": { + "no_undef": false, + "range": null + } + }, + "semantics": { + "pure": false, + "memory": "read_write", + "convergent": true, + "execution_scope": "cta" + }, + "target": { + "minimum_ptx": "1.0", + "hardware": { + "kind": "all" + }, + "ptx_result": "bool", + "targets": "all", + "ptx_isa_version": "9.3", + "ptx_isa_section": "9.7.14.1 Parallel Synchronization and Communication Instructions: bar, barrier", + "ptx_isa_url": "https://docs.nvidia.com/cuda/parallel-thread-execution/#parallel-synchronization-and-communication-instructions-bar-barrier" + }, + "backend": { + "profile": "rust-llvm-22.1.2-1cb4e383-barrier-reduction", + "version": "LLVM version 22.1.2-rust-1.96.0-nightly", + "sha256": "ff1dcdc18a5441003d43c5df267b43e2b6dd3efccca38c20bb2801885626331e", + "status": "lowered", + "target_triple": "nvptx64-nvidia-cuda", + "gpu_target": "sm_20", + "ptx_feature": "+ptx32" + }, + "backend_lowerings": [ + { + "backend": "llvm_nvptx", + "mechanism": "typed_nvvm", + "evidence_profile": "rust-llvm-22.1.2-1cb4e383-barrier-reduction", + "target": { + "minimum_ptx": "3.2", + "hardware": { + "kind": "any_of", + "alternatives": [ + { + "kind": "minimum_sm", + "sm": 20 + } + ] + } + }, + "version": "LLVM version 22.1.2-rust-1.96.0-nightly", + "sha256": "ff1dcdc18a5441003d43c5df267b43e2b6dd3efccca38c20bb2801885626331e", + "artifact_path": null, + "build_id_prefix": null, + "status": "lowered", + "stages": [ + { + "targets": [ + "sm_20", + "ptx32" + ], + "representation": "typed NVVM declaration compiled in the combined CTA barrier-reduction floor probe", + "stage": "backend_codegen", + "mechanism": "typed_nvvm", + "outcome": "succeeded", + "detail": "Pinned LLVM 22.1.2 selected the reviewed bar[rier].red instruction; combined source and emitted PTX artifacts are preserved in the design scratchpad.", + "artifact_kind": null, + "tool_path": null, + "tool_version": null, + "tool_sha256": null + } + ] + }, + { + "backend": "lib_nvvm", + "mechanism": "inline_ptx", + "evidence_profile": "cuda-12.9-libnvvm-12.9.86-barrier-reduction", + "target": { + "minimum_ptx": "1.0", + "hardware": { + "kind": "any_of", + "alternatives": [ + { + "kind": "minimum_sm", + "sm": 75 + } + ] + } + }, + "version": "CUDA 12.9 libNVVM package V12.9.86; NVVM IR 2.0", + "sha256": "79729301061c2abe547c749073ad658a1582d33fb5d003e2c097285e5ddafb2e", + "artifact_path": "/home/sam/Workspaces/dinov3-candle/.pixi/envs/default/nvvm/lib64/libnvvm.so.4.0.0", + "build_id_prefix": null, + "status": "lowered", + "stages": [ + { + "targets": [ + "sm_75", + "ptx88" + ], + "representation": "NVVM IR 2.0 combined inline-PTX barrier-reduction fixture using predicate selp.b32 materialization", + "stage": "backend_codegen", + "mechanism": "inline_ptx", + "outcome": "succeeded", + "detail": "CUDA 12.9.86 libNVVM compiled the 1,156-byte combined source SHA-256 11bd0ada26128692365b334162e9bfc26bfb713c0a89404b342e522894410c31 to 2,708-byte PTX SHA-256 6bf4e457e1f8d9624deb76df2cdab36c07e062676b2a45c69f081aa42fc5d4ed; CUDA 12.9.86 ptxas accepted that PTX and produced cubin SHA-256 2c09dd490b9157429babbf5fb9119df702f2bd9a5a6255464d9431366c0b318c.", + "artifact_kind": null, + "tool_path": null, + "tool_version": null, + "tool_sha256": null + } + ] + } + ], + "lowering": "generated_barrier_reduction", + "expected_ptx": { + "mnemonic": "bar", + "modifiers": [ + "red", + "and", + "pred" + ], + "operands": [ + { + "kind": "register" + }, + { + "kind": "register_or_immediate" + }, + { + "kind": "register" + } + ] + }, + "summary": "Reduces predicates with AND while synchronizing all arriving CTA threads at an aligned numbered barrier." + }, + { + "id": "barrier_cta_red_and_aligned_count", + "operation_key": "synchronization.cta.bar.reduction.and.count", + "family": "barrier_reduction", + "source": { + "kind": "llvm_imported", + "source_record": "int_nvvm_barrier_cta_red_and_aligned_count" + }, + "selections": [ + { + "source_record": "BARRIER_CTA_RED_AND_ALIGNED_iip", + "asm": "bar.red.and.pred \t$dest, $i, $j, $pred;", + "predicates": [] + }, + { + "source_record": "BARRIER_CTA_RED_AND_ALIGNED_irp", + "asm": "bar.red.and.pred \t$dest, $i, $j, $pred;", + "predicates": [] + }, + { + "source_record": "BARRIER_CTA_RED_AND_ALIGNED_rip", + "asm": "bar.red.and.pred \t$dest, $i, $j, $pred;", + "predicates": [] + }, + { + "source_record": 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2c09dd490b9157429babbf5fb9119df702f2bd9a5a6255464d9431366c0b318c.", + "artifact_kind": null, + "tool_path": null, + "tool_version": null, + "tool_sha256": null + } + ] + } + ], + "lowering": "generated_barrier_reduction", + "expected_ptx": { + "mnemonic": "barrier", + "modifiers": [ + "red", + "popc", + "u32" + ], + "operands": [ + { + "kind": "register" + }, + { + "kind": "register_or_immediate" + }, + { + "kind": "register_or_immediate" + }, + { + "kind": "register" + } + ] + }, + "summary": "Counts true predicates while synchronizing the requested number of CTA threads at a numbered barrier." + }, { "id": "barrier_cta_sync", "operation_key": "synchronization.cta.barrier.count", @@ -9851,6 +12362,196 @@ }, "summary": "Synchronizes the requested number of CTA threads at an aligned numbered barrier." }, + { + "id": "barrier_cta_sync_all", + "operation_key": "synchronization.cta.barrier.all", + "family": "counted_barrier", + "source": { + "kind": "llvm_imported", + "source_record": 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"detail": "Pinned LLVM 22.1.2 selected the reviewed bar[rier].red instruction; combined source and emitted PTX artifacts are preserved in the design scratchpad." + } + ], + "declaration_attributes_canonicalized": true, + "runtime_validation": "unexecuted", + "expected_ptx": { + "mnemonic": "bar", + "modifiers": [ + "red", + "and", + "pred" + ], + "operands": [ + { + "kind": "register" + }, + { + "kind": "register_or_immediate" + }, + { + "kind": "register_or_immediate" + }, + { + "kind": "register" + } + ] + } + }, + { + "id": "barrier_cta_red_or_all", + "source_record": "int_nvvm_barrier_cta_red_or_all", + "llvm_symbol": "llvm.nvvm.barrier.cta.red.or.all", + "llvm_arguments": [ + "i32", + "i1" + ], + "llvm_results": [ + "i1" + ], + "concrete_llvm_arguments": [ + "i32", + "i1" + ], + "concrete_llvm_results": [ + "i1" + ], + "target_triple": "nvptx64-nvidia-cuda", + "gpu_target": "sm_30", + "ptx_feature": "+ptx60", + "status": "lowered", + "stages": [ + { + "targets": [ + "sm_30", + "ptx60" + ], + "representation": "typed NVVM declaration compiled in the combined CTA barrier-reduction floor probe", + "stage": "backend_codegen", + "mechanism": "typed_nvvm", + "outcome": "succeeded", + "detail": "Pinned LLVM 22.1.2 selected the reviewed bar[rier].red instruction; combined source and emitted PTX artifacts are preserved in the design scratchpad." + } + ], + "declaration_attributes_canonicalized": true, + "runtime_validation": "unexecuted", + "expected_ptx": { + "mnemonic": "barrier", + "modifiers": [ + "red", + "or", + "pred" + ], + "operands": [ + { + "kind": "register" + }, + { + "kind": "register_or_immediate" + }, + { + "kind": "register" + } + ] + } + }, + { + "id": "barrier_cta_red_or_count", + "source_record": "int_nvvm_barrier_cta_red_or_count", + "llvm_symbol": "llvm.nvvm.barrier.cta.red.or.count", + "llvm_arguments": [ + "i32", + "i32", + "i1" + ], + "llvm_results": [ + "i1" + ], + "concrete_llvm_arguments": [ + "i32", + "i32", + "i1" + ], + "concrete_llvm_results": [ + "i1" + ], + "target_triple": "nvptx64-nvidia-cuda", + "gpu_target": "sm_30", + "ptx_feature": "+ptx60", + "status": "lowered", + "stages": [ + { + "targets": [ + "sm_30", + "ptx60" + ], + "representation": "typed NVVM declaration compiled in the combined CTA barrier-reduction floor probe", + "stage": "backend_codegen", + "mechanism": "typed_nvvm", + "outcome": "succeeded", + "detail": "Pinned LLVM 22.1.2 selected the reviewed bar[rier].red instruction; combined source and emitted PTX artifacts are preserved in the design scratchpad." + } + ], + "declaration_attributes_canonicalized": true, + "runtime_validation": "unexecuted", + "expected_ptx": { + "mnemonic": "barrier", + "modifiers": [ + "red", + "or", + "pred" + ], + "operands": [ + { + "kind": "register" + }, + { + "kind": "register_or_immediate" + }, + { + "kind": "register_or_immediate" + }, + { + "kind": "register" + } + ] + } + }, + { + "id": "barrier_cta_red_or_aligned_all", + "source_record": "int_nvvm_barrier_cta_red_or_aligned_all", + "llvm_symbol": "llvm.nvvm.barrier.cta.red.or.aligned.all", + "llvm_arguments": [ + "i32", + "i1" + ], + "llvm_results": [ + "i1" + ], + "concrete_llvm_arguments": [ + "i32", + "i1" + ], + "concrete_llvm_results": [ + "i1" + ], + "target_triple": "nvptx64-nvidia-cuda", + "gpu_target": "sm_20", + "ptx_feature": "+ptx32", + "status": "lowered", + "stages": [ + { + "targets": [ + "sm_20", + "ptx32" + ], + "representation": "typed NVVM declaration compiled in the combined CTA barrier-reduction floor probe", + "stage": "backend_codegen", + "mechanism": "typed_nvvm", + "outcome": "succeeded", + "detail": "Pinned LLVM 22.1.2 selected the reviewed bar[rier].red instruction; combined source and emitted PTX artifacts are preserved in the design scratchpad." + } + ], + "declaration_attributes_canonicalized": true, + "runtime_validation": "unexecuted", + "expected_ptx": { + "mnemonic": "bar", + "modifiers": [ + "red", + "or", + "pred" + ], + "operands": [ + { + "kind": "register" + }, + { + "kind": "register_or_immediate" + }, + { + "kind": "register" + } + ] + } + }, + { + "id": "barrier_cta_red_or_aligned_count", + "source_record": "int_nvvm_barrier_cta_red_or_aligned_count", + "llvm_symbol": "llvm.nvvm.barrier.cta.red.or.aligned.count", + "llvm_arguments": [ + "i32", + "i32", + "i1" + ], + "llvm_results": [ + "i1" + ], + "concrete_llvm_arguments": [ + "i32", + "i32", + "i1" + ], + "concrete_llvm_results": [ + "i1" + ], + "target_triple": "nvptx64-nvidia-cuda", + "gpu_target": "sm_20", + "ptx_feature": "+ptx32", + "status": "lowered", + "stages": [ + { + "targets": [ + "sm_20", + "ptx32" + ], + "representation": "typed NVVM declaration compiled in the combined CTA barrier-reduction floor probe", + "stage": "backend_codegen", + "mechanism": "typed_nvvm", + "outcome": "succeeded", + "detail": "Pinned LLVM 22.1.2 selected the reviewed bar[rier].red instruction; combined source and emitted PTX artifacts are preserved in the design scratchpad." + } + ], + "declaration_attributes_canonicalized": true, + "runtime_validation": "unexecuted", + "expected_ptx": { + "mnemonic": "bar", + "modifiers": [ + "red", + "or", + "pred" + ], + "operands": [ + { + "kind": "register" + }, + { + "kind": "register_or_immediate" + }, + { + "kind": "register_or_immediate" + }, + { + "kind": "register" + } + ] + } + }, + { + "id": "barrier_cta_red_popc_all", + "source_record": "int_nvvm_barrier_cta_red_popc_all", + "llvm_symbol": "llvm.nvvm.barrier.cta.red.popc.all", + "llvm_arguments": [ + "i32", + "i1" + ], + "llvm_results": [ + "i32" + ], + "concrete_llvm_arguments": [ + "i32", + "i1" + ], + "concrete_llvm_results": [ + "i32" + ], + "target_triple": "nvptx64-nvidia-cuda", + "gpu_target": "sm_30", + "ptx_feature": "+ptx60", + "status": "lowered", + "stages": [ + { + "targets": [ + "sm_30", + "ptx60" + ], + "representation": "typed NVVM declaration compiled in the combined CTA barrier-reduction floor probe", + "stage": "backend_codegen", + "mechanism": "typed_nvvm", + "outcome": "succeeded", + "detail": "Pinned LLVM 22.1.2 selected the reviewed bar[rier].red instruction; combined source and emitted PTX artifacts are preserved in the design scratchpad." + } + ], + "declaration_attributes_canonicalized": true, + "runtime_validation": "unexecuted", + "expected_ptx": { + "mnemonic": "barrier", + "modifiers": [ + "red", + "popc", + "u32" + ], + "operands": [ + { + "kind": "register" + }, + { + "kind": "register_or_immediate" + }, + { + "kind": "register" + } + ] + } + }, + { + "id": "barrier_cta_red_popc_count", + "source_record": "int_nvvm_barrier_cta_red_popc_count", + "llvm_symbol": "llvm.nvvm.barrier.cta.red.popc.count", + "llvm_arguments": [ + "i32", + "i32", + "i1" + ], + "llvm_results": [ + "i32" + ], + "concrete_llvm_arguments": [ + "i32", + "i32", + "i1" + ], + "concrete_llvm_results": [ + "i32" + ], + "target_triple": "nvptx64-nvidia-cuda", + "gpu_target": "sm_30", + "ptx_feature": "+ptx60", + "status": "lowered", + "stages": [ + { + "targets": [ + "sm_30", + "ptx60" + ], + "representation": "typed NVVM declaration compiled in the combined CTA barrier-reduction floor probe", + "stage": "backend_codegen", + "mechanism": "typed_nvvm", + "outcome": "succeeded", + "detail": "Pinned LLVM 22.1.2 selected the reviewed bar[rier].red instruction; combined source and emitted PTX artifacts are preserved in the design scratchpad." + } + ], + "declaration_attributes_canonicalized": true, + "runtime_validation": "unexecuted", + "expected_ptx": { + "mnemonic": "barrier", + "modifiers": [ + "red", + "popc", + "u32" + ], + "operands": [ + { + "kind": "register" + }, + { + "kind": "register_or_immediate" + }, + { + "kind": "register_or_immediate" + }, + { + "kind": "register" + } + ] + } + }, + { + "id": "barrier_cta_red_popc_aligned_all", + "source_record": "int_nvvm_barrier_cta_red_popc_aligned_all", + "llvm_symbol": "llvm.nvvm.barrier.cta.red.popc.aligned.all", + "llvm_arguments": [ + "i32", + "i1" + ], + "llvm_results": [ + "i32" + ], + "concrete_llvm_arguments": [ + "i32", + "i1" + ], + "concrete_llvm_results": [ + "i32" + ], + "target_triple": "nvptx64-nvidia-cuda", + "gpu_target": "sm_20", + "ptx_feature": "+ptx32", + "status": "lowered", + "stages": [ + { + "targets": [ + "sm_20", + "ptx32" + ], + "representation": "typed NVVM declaration compiled in the combined CTA barrier-reduction floor probe", + "stage": "backend_codegen", + "mechanism": "typed_nvvm", + "outcome": "succeeded", + "detail": "Pinned LLVM 22.1.2 selected the reviewed bar[rier].red instruction; combined source and emitted PTX artifacts are preserved in the design scratchpad." + } + ], + "declaration_attributes_canonicalized": true, + "runtime_validation": "unexecuted", + "expected_ptx": { + "mnemonic": "bar", + "modifiers": [ + "red", + "popc", + "u32" + ], + "operands": [ + { + "kind": "register" + }, + { + "kind": "register_or_immediate" + }, + { + "kind": "register" + } + ] + } + }, + { + "id": "barrier_cta_red_popc_aligned_count", + "source_record": "int_nvvm_barrier_cta_red_popc_aligned_count", + "llvm_symbol": "llvm.nvvm.barrier.cta.red.popc.aligned.count", + "llvm_arguments": [ + "i32", + "i32", + "i1" + ], + "llvm_results": [ + "i32" + ], + "concrete_llvm_arguments": [ + "i32", + "i32", + "i1" + ], + "concrete_llvm_results": [ + "i32" + ], + "target_triple": "nvptx64-nvidia-cuda", + "gpu_target": "sm_20", + "ptx_feature": "+ptx32", + "status": "lowered", + "stages": [ + { + "targets": [ + "sm_20", + "ptx32" + ], + "representation": "typed NVVM declaration compiled in the combined CTA barrier-reduction floor probe", + "stage": "backend_codegen", + "mechanism": "typed_nvvm", + "outcome": "succeeded", + "detail": "Pinned LLVM 22.1.2 selected the reviewed bar[rier].red instruction; combined source and emitted PTX artifacts are preserved in the design scratchpad." + } + ], + "declaration_attributes_canonicalized": true, + "runtime_validation": "unexecuted", + "expected_ptx": { + "mnemonic": "bar", + "modifiers": [ + "red", + "popc", + "u32" + ], + "operands": [ + { + "kind": "register" + }, + { + "kind": "register_or_immediate" + }, + { + "kind": "register_or_immediate" + }, + { + "kind": "register" + } + ] + } + } + ] +} diff --git a/intrinsics/evidence/rust-llvm-22.1.2-1cb4e383-execution-control.json b/intrinsics/evidence/rust-llvm-22.1.2-1cb4e383-execution-control.json index 9be8cc6d24..b1e61d085c 100644 --- a/intrinsics/evidence/rust-llvm-22.1.2-1cb4e383-execution-control.json +++ b/intrinsics/evidence/rust-llvm-22.1.2-1cb4e383-execution-control.json @@ -417,6 +417,36 @@ "modifiers": ["dec", "sync", "aligned", "u32"], "operands": [{"kind": "immediate"}] } + }, + { + "id": "barrier_cta_sync_all", + "source_record": "int_nvvm_barrier_cta_sync_all", + "llvm_symbol": "llvm.nvvm.barrier.cta.sync.all", + "llvm_arguments": ["i32"], + "llvm_results": [], + "target_triple": "nvptx64-nvidia-cuda", + "status": "lowered", + "runtime_validation": "unexecuted", + "expected_ptx": { + "mnemonic": "barrier", + "modifiers": ["sync"], + "operands": [{"kind": "register_or_immediate"}] + }, + "concrete_llvm_arguments": ["i32"], + "concrete_llvm_results": [], + "gpu_target": "sm_30", + "ptx_feature": "+ptx60", + "stages": [ + { + "targets": ["sm_30", "ptx60"], + "representation": "typed barrier.cta.sync.all declaration in combined floor probe", + "stage": "backend_codegen", + "mechanism": "typed_nvvm", + "outcome": "succeeded", + "detail": "Pinned LLVM emitted barrier.sync for both reviewed register/immediate selection records." + } + ], + "declaration_attributes_canonicalized": true } ] } diff --git a/intrinsics/generated-reference.md b/intrinsics/generated-reference.md index b678c5682e..85c54985ea 100644 --- a/intrinsics/generated-reference.md +++ b/intrinsics/generated-reference.md @@ -2,7 +2,7 @@ SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. SPDX-License-Identifier: Apache-2.0 @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. --> @@ -50,8 +50,21 @@ This table is generated from the resolved catalog. Evidence stages below disting | `cuda_intrinsics::cluster::barrier_cluster_wait_aligned` | `nvvm.cluster_barrier` | LLVM `llvm.nvvm.barrier.cluster.wait.aligned` from `int_nvvm_barrier_cluster_wait_aligned` | unsafe; scope cluster; impure; memory read_write; convergent true | PTX 7.8 on sm_90+ ([PTX ISA 9.3, Parallel Synchronization and Communication Instructions: barrier.cluster](https://docs.nvidia.com/cuda/parallel-thread-execution/#parallel-synchronization-and-communication-instructions-barrier-cluster)) | validated on `rust-llvm-22.1.2-1cb4e383`; expects `barrier.cluster.wait.aligned;` (`LLVM version 22.1.2-rust-1.96.0-nightly`, SHA-256 `ff1dcdc18a5441003d43c5df267b43e2b6dd3efccca38c20bb2801885626331e`) | | `cuda_intrinsics::barrier::barrier_cta_arrive` | `nvvm.barrier_cta_arrive_count` | LLVM `llvm.nvvm.barrier.cta.arrive.count` from `int_nvvm_barrier_cta_arrive_count` | unsafe; scope cta; impure; memory read_write; convergent true | PTX 6.0 on sm_30+ ([PTX ISA 9.3, 9.7.14.1 Parallel Synchronization and Communication Instructions: bar, barrier](https://docs.nvidia.com/cuda/parallel-thread-execution/#parallel-synchronization-and-communication-instructions-bar-barrier)) | validated on `rust-llvm-22.1.2-1cb4e383-execution-control`; expects `barrier.arrive , ;` (`LLVM version 22.1.2-rust-1.96.0-nightly`, SHA-256 `ff1dcdc18a5441003d43c5df267b43e2b6dd3efccca38c20bb2801885626331e`) | | `cuda_intrinsics::barrier::barrier_cta_arrive_aligned` | `nvvm.barrier_cta_arrive_aligned_count` | LLVM `llvm.nvvm.barrier.cta.arrive.aligned.count` from `int_nvvm_barrier_cta_arrive_aligned_count` | unsafe; scope cta; impure; memory read_write; convergent true | PTX 1.0 on all ([PTX ISA 9.3, 9.7.14.1 Parallel Synchronization and Communication Instructions: bar, barrier](https://docs.nvidia.com/cuda/parallel-thread-execution/#parallel-synchronization-and-communication-instructions-bar-barrier)) | validated on `rust-llvm-22.1.2-1cb4e383-execution-control`; expects `bar.arrive , ;` (`LLVM version 22.1.2-rust-1.96.0-nightly`, SHA-256 `ff1dcdc18a5441003d43c5df267b43e2b6dd3efccca38c20bb2801885626331e`) | +| `cuda_intrinsics::barrier::barrier_cta_red_and_aligned_all` | `nvvm.barrier_cta_red_and_aligned_all` | LLVM `llvm.nvvm.barrier.cta.red.and.aligned.all` from `int_nvvm_barrier_cta_red_and_aligned_all` | unsafe; scope cta; impure; memory read_write; convergent true | PTX 1.0 on all ([PTX ISA 9.3, 9.7.14.1 Parallel Synchronization and Communication Instructions: bar, barrier](https://docs.nvidia.com/cuda/parallel-thread-execution/#parallel-synchronization-and-communication-instructions-bar-barrier)) | lowered on `rust-llvm-22.1.2-1cb4e383-barrier-reduction`; expects `bar.red.and.pred , , ;` (`LLVM version 22.1.2-rust-1.96.0-nightly`, SHA-256 `ff1dcdc18a5441003d43c5df267b43e2b6dd3efccca38c20bb2801885626331e`) | +| `cuda_intrinsics::barrier::barrier_cta_red_and_aligned_count` | `nvvm.barrier_cta_red_and_aligned_count` | LLVM `llvm.nvvm.barrier.cta.red.and.aligned.count` from `int_nvvm_barrier_cta_red_and_aligned_count` | unsafe; scope cta; impure; memory read_write; convergent true | PTX 1.0 on all ([PTX ISA 9.3, 9.7.14.1 Parallel Synchronization and Communication Instructions: bar, barrier](https://docs.nvidia.com/cuda/parallel-thread-execution/#parallel-synchronization-and-communication-instructions-bar-barrier)) | lowered on `rust-llvm-22.1.2-1cb4e383-barrier-reduction`; expects `bar.red.and.pred , , , ;` (`LLVM version 22.1.2-rust-1.96.0-nightly`, SHA-256 `ff1dcdc18a5441003d43c5df267b43e2b6dd3efccca38c20bb2801885626331e`) | +| `cuda_intrinsics::barrier::barrier_cta_red_and_all` | `nvvm.barrier_cta_red_and_all` | LLVM `llvm.nvvm.barrier.cta.red.and.all` from `int_nvvm_barrier_cta_red_and_all` | unsafe; scope cta; impure; memory read_write; convergent true | PTX 6.0 on sm_30+ ([PTX ISA 9.3, 9.7.14.1 Parallel Synchronization and Communication Instructions: bar, barrier](https://docs.nvidia.com/cuda/parallel-thread-execution/#parallel-synchronization-and-communication-instructions-bar-barrier)) | lowered on `rust-llvm-22.1.2-1cb4e383-barrier-reduction`; expects `barrier.red.and.pred , , ;` (`LLVM version 22.1.2-rust-1.96.0-nightly`, SHA-256 `ff1dcdc18a5441003d43c5df267b43e2b6dd3efccca38c20bb2801885626331e`) | +| `cuda_intrinsics::barrier::barrier_cta_red_and_count` | `nvvm.barrier_cta_red_and_count` | LLVM `llvm.nvvm.barrier.cta.red.and.count` from `int_nvvm_barrier_cta_red_and_count` | unsafe; scope cta; impure; memory read_write; convergent true | PTX 6.0 on sm_30+ ([PTX ISA 9.3, 9.7.14.1 Parallel Synchronization and Communication Instructions: bar, barrier](https://docs.nvidia.com/cuda/parallel-thread-execution/#parallel-synchronization-and-communication-instructions-bar-barrier)) | lowered on `rust-llvm-22.1.2-1cb4e383-barrier-reduction`; expects `barrier.red.and.pred , , , ;` (`LLVM version 22.1.2-rust-1.96.0-nightly`, SHA-256 `ff1dcdc18a5441003d43c5df267b43e2b6dd3efccca38c20bb2801885626331e`) | +| `cuda_intrinsics::barrier::barrier_cta_red_or_aligned_all` | `nvvm.barrier_cta_red_or_aligned_all` | LLVM `llvm.nvvm.barrier.cta.red.or.aligned.all` from `int_nvvm_barrier_cta_red_or_aligned_all` | unsafe; scope cta; impure; memory read_write; convergent true | PTX 1.0 on all ([PTX ISA 9.3, 9.7.14.1 Parallel Synchronization and Communication Instructions: bar, barrier](https://docs.nvidia.com/cuda/parallel-thread-execution/#parallel-synchronization-and-communication-instructions-bar-barrier)) | lowered on `rust-llvm-22.1.2-1cb4e383-barrier-reduction`; expects `bar.red.or.pred , , ;` (`LLVM version 22.1.2-rust-1.96.0-nightly`, SHA-256 `ff1dcdc18a5441003d43c5df267b43e2b6dd3efccca38c20bb2801885626331e`) | +| `cuda_intrinsics::barrier::barrier_cta_red_or_aligned_count` | `nvvm.barrier_cta_red_or_aligned_count` | LLVM `llvm.nvvm.barrier.cta.red.or.aligned.count` from `int_nvvm_barrier_cta_red_or_aligned_count` | unsafe; scope cta; impure; memory read_write; convergent true | PTX 1.0 on all ([PTX ISA 9.3, 9.7.14.1 Parallel Synchronization and Communication Instructions: bar, barrier](https://docs.nvidia.com/cuda/parallel-thread-execution/#parallel-synchronization-and-communication-instructions-bar-barrier)) | lowered on `rust-llvm-22.1.2-1cb4e383-barrier-reduction`; expects `bar.red.or.pred , , , ;` (`LLVM version 22.1.2-rust-1.96.0-nightly`, SHA-256 `ff1dcdc18a5441003d43c5df267b43e2b6dd3efccca38c20bb2801885626331e`) | +| `cuda_intrinsics::barrier::barrier_cta_red_or_all` | `nvvm.barrier_cta_red_or_all` | LLVM `llvm.nvvm.barrier.cta.red.or.all` from `int_nvvm_barrier_cta_red_or_all` | unsafe; scope cta; impure; memory read_write; convergent true | PTX 6.0 on sm_30+ ([PTX ISA 9.3, 9.7.14.1 Parallel Synchronization and Communication Instructions: bar, barrier](https://docs.nvidia.com/cuda/parallel-thread-execution/#parallel-synchronization-and-communication-instructions-bar-barrier)) | lowered on `rust-llvm-22.1.2-1cb4e383-barrier-reduction`; expects `barrier.red.or.pred , , ;` (`LLVM version 22.1.2-rust-1.96.0-nightly`, SHA-256 `ff1dcdc18a5441003d43c5df267b43e2b6dd3efccca38c20bb2801885626331e`) | +| `cuda_intrinsics::barrier::barrier_cta_red_or_count` | `nvvm.barrier_cta_red_or_count` | LLVM `llvm.nvvm.barrier.cta.red.or.count` from `int_nvvm_barrier_cta_red_or_count` | unsafe; scope cta; impure; memory read_write; convergent true | PTX 6.0 on sm_30+ ([PTX ISA 9.3, 9.7.14.1 Parallel Synchronization and Communication Instructions: bar, barrier](https://docs.nvidia.com/cuda/parallel-thread-execution/#parallel-synchronization-and-communication-instructions-bar-barrier)) | lowered on `rust-llvm-22.1.2-1cb4e383-barrier-reduction`; expects `barrier.red.or.pred , , , ;` (`LLVM version 22.1.2-rust-1.96.0-nightly`, SHA-256 `ff1dcdc18a5441003d43c5df267b43e2b6dd3efccca38c20bb2801885626331e`) | +| `cuda_intrinsics::barrier::barrier_cta_red_popc_aligned_all` | `nvvm.barrier_cta_red_popc_aligned_all` | LLVM `llvm.nvvm.barrier.cta.red.popc.aligned.all` from `int_nvvm_barrier_cta_red_popc_aligned_all` | unsafe; scope cta; impure; memory read_write; convergent true | PTX 1.0 on all ([PTX ISA 9.3, 9.7.14.1 Parallel Synchronization and Communication Instructions: bar, barrier](https://docs.nvidia.com/cuda/parallel-thread-execution/#parallel-synchronization-and-communication-instructions-bar-barrier)) | lowered on `rust-llvm-22.1.2-1cb4e383-barrier-reduction`; expects `bar.red.popc.u32 , , ;` (`LLVM version 22.1.2-rust-1.96.0-nightly`, SHA-256 `ff1dcdc18a5441003d43c5df267b43e2b6dd3efccca38c20bb2801885626331e`) | +| `cuda_intrinsics::barrier::barrier_cta_red_popc_aligned_count` | `nvvm.barrier_cta_red_popc_aligned_count` | LLVM `llvm.nvvm.barrier.cta.red.popc.aligned.count` from `int_nvvm_barrier_cta_red_popc_aligned_count` | unsafe; scope cta; impure; memory read_write; convergent true | PTX 1.0 on all ([PTX ISA 9.3, 9.7.14.1 Parallel Synchronization and Communication Instructions: bar, barrier](https://docs.nvidia.com/cuda/parallel-thread-execution/#parallel-synchronization-and-communication-instructions-bar-barrier)) | lowered on `rust-llvm-22.1.2-1cb4e383-barrier-reduction`; expects `bar.red.popc.u32 , , , ;` (`LLVM version 22.1.2-rust-1.96.0-nightly`, SHA-256 `ff1dcdc18a5441003d43c5df267b43e2b6dd3efccca38c20bb2801885626331e`) | +| `cuda_intrinsics::barrier::barrier_cta_red_popc_all` | `nvvm.barrier_cta_red_popc_all` | LLVM `llvm.nvvm.barrier.cta.red.popc.all` from `int_nvvm_barrier_cta_red_popc_all` | unsafe; scope cta; impure; memory read_write; convergent true | PTX 6.0 on sm_30+ ([PTX ISA 9.3, 9.7.14.1 Parallel Synchronization and Communication Instructions: bar, barrier](https://docs.nvidia.com/cuda/parallel-thread-execution/#parallel-synchronization-and-communication-instructions-bar-barrier)) | lowered on `rust-llvm-22.1.2-1cb4e383-barrier-reduction`; expects `barrier.red.popc.u32 , , ;` (`LLVM version 22.1.2-rust-1.96.0-nightly`, SHA-256 `ff1dcdc18a5441003d43c5df267b43e2b6dd3efccca38c20bb2801885626331e`) | +| `cuda_intrinsics::barrier::barrier_cta_red_popc_count` | `nvvm.barrier_cta_red_popc_count` | LLVM `llvm.nvvm.barrier.cta.red.popc.count` from `int_nvvm_barrier_cta_red_popc_count` | unsafe; scope cta; impure; memory read_write; convergent true | PTX 6.0 on sm_30+ ([PTX ISA 9.3, 9.7.14.1 Parallel Synchronization and Communication Instructions: bar, barrier](https://docs.nvidia.com/cuda/parallel-thread-execution/#parallel-synchronization-and-communication-instructions-bar-barrier)) | lowered on `rust-llvm-22.1.2-1cb4e383-barrier-reduction`; expects `barrier.red.popc.u32 , , , ;` (`LLVM version 22.1.2-rust-1.96.0-nightly`, SHA-256 `ff1dcdc18a5441003d43c5df267b43e2b6dd3efccca38c20bb2801885626331e`) | | `cuda_intrinsics::barrier::barrier_cta_sync` | `nvvm.barrier_cta_sync_count` | LLVM `llvm.nvvm.barrier.cta.sync.count` from `int_nvvm_barrier_cta_sync_count` | unsafe; scope cta; impure; memory read_write; convergent true | PTX 6.0 on sm_30+ ([PTX ISA 9.3, 9.7.14.1 Parallel Synchronization and Communication Instructions: bar, barrier](https://docs.nvidia.com/cuda/parallel-thread-execution/#parallel-synchronization-and-communication-instructions-bar-barrier)) | validated on `rust-llvm-22.1.2-1cb4e383-execution-control`; expects `barrier.sync , ;` (`LLVM version 22.1.2-rust-1.96.0-nightly`, SHA-256 `ff1dcdc18a5441003d43c5df267b43e2b6dd3efccca38c20bb2801885626331e`) | | `cuda_intrinsics::barrier::barrier_cta_sync_aligned` | `nvvm.barrier_cta_sync_aligned_count` | LLVM `llvm.nvvm.barrier.cta.sync.aligned.count` from `int_nvvm_barrier_cta_sync_aligned_count` | unsafe; scope cta; impure; memory read_write; convergent true | PTX 1.0 on all ([PTX ISA 9.3, 9.7.14.1 Parallel Synchronization and Communication Instructions: bar, barrier](https://docs.nvidia.com/cuda/parallel-thread-execution/#parallel-synchronization-and-communication-instructions-bar-barrier)) | validated on `rust-llvm-22.1.2-1cb4e383-execution-control`; expects `bar.sync , ;` (`LLVM version 22.1.2-rust-1.96.0-nightly`, SHA-256 `ff1dcdc18a5441003d43c5df267b43e2b6dd3efccca38c20bb2801885626331e`) | +| `cuda_intrinsics::barrier::barrier_cta_sync_all` | `nvvm.barrier_cta_sync_all` | LLVM `llvm.nvvm.barrier.cta.sync.all` from `int_nvvm_barrier_cta_sync_all` | unsafe; scope cta; impure; memory read_write; convergent true | PTX 6.0 on sm_30+ ([PTX ISA 9.3, 9.7.14.1 Parallel Synchronization and Communication Instructions: bar, barrier](https://docs.nvidia.com/cuda/parallel-thread-execution/#parallel-synchronization-and-communication-instructions-bar-barrier)) | lowered on `rust-llvm-22.1.2-1cb4e383-execution-control`; expects `barrier.sync ;` (`LLVM version 22.1.2-rust-1.96.0-nightly`, SHA-256 `ff1dcdc18a5441003d43c5df267b43e2b6dd3efccca38c20bb2801885626331e`) | | `cuda_intrinsics::sreg::block_dim_x` | `nvvm.read_ptx_sreg_ntid_x` | LLVM `llvm.nvvm.read.ptx.sreg.ntid.x` from `int_nvvm_read_ptx_sreg_ntid_x` | safe; scope cta; pure; memory none; convergent false | PTX 2.0 on all ([PTX ISA 9.3, 10.2 Special Registers: %ntid](https://docs.nvidia.com/cuda/parallel-thread-execution/#special-registers-ntid)) | lowered on `rust-llvm-22.1.2-1cb4e383`; expects `mov.u32 , %ntid.x;` (`LLVM version 22.1.2-rust-1.96.0-nightly`, SHA-256 `ff1dcdc18a5441003d43c5df267b43e2b6dd3efccca38c20bb2801885626331e`) | | `cuda_intrinsics::sreg::block_dim_y` | `nvvm.read_ptx_sreg_ntid_y` | LLVM `llvm.nvvm.read.ptx.sreg.ntid.y` from `int_nvvm_read_ptx_sreg_ntid_y` | safe; scope cta; pure; memory none; convergent false | PTX 2.0 on all ([PTX ISA 9.3, 10.2 Special Registers: %ntid](https://docs.nvidia.com/cuda/parallel-thread-execution/#special-registers-ntid)) | lowered on `rust-llvm-22.1.2-1cb4e383`; expects `mov.u32 , %ntid.y;` (`LLVM version 22.1.2-rust-1.96.0-nightly`, SHA-256 `ff1dcdc18a5441003d43c5df267b43e2b6dd3efccca38c20bb2801885626331e`) | | `cuda_intrinsics::sreg::block_dim_z` | `nvvm.read_ptx_sreg_ntid_z` | LLVM `llvm.nvvm.read.ptx.sreg.ntid.z` from `int_nvvm_read_ptx_sreg_ntid_z` | safe; scope cta; pure; memory none; convergent false | PTX 2.0 on all ([PTX ISA 9.3, 10.2 Special Registers: %ntid](https://docs.nvidia.com/cuda/parallel-thread-execution/#special-registers-ntid)) | lowered on `rust-llvm-22.1.2-1cb4e383`; expects `mov.u32 , %ntid.z;` (`LLVM version 22.1.2-rust-1.96.0-nightly`, SHA-256 `ff1dcdc18a5441003d43c5df267b43e2b6dd3efccca38c20bb2801885626331e`) | @@ -1182,6 +1195,54 @@ This table is generated from the resolved catalog. Evidence stages below disting - canonical compiler path: `cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0886` - public source path: `cuda_intrinsics::barrier::barrier_cta_arrive_aligned` - compatibility compiler path: `cuda_device::barrier::barrier_cta_arrive_aligned` +- `barrier_cta_red_and_aligned_all` (`i1018`) + - canonical compiler path: `cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i1018` + - public source path: `cuda_intrinsics::barrier::barrier_cta_red_and_aligned_all` + - compatibility compiler path: `cuda_device::barrier::barrier_cta_red_and_aligned_all` +- `barrier_cta_red_and_aligned_count` (`i1019`) + - canonical compiler path: `cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i1019` + - public source path: `cuda_intrinsics::barrier::barrier_cta_red_and_aligned_count` + - compatibility compiler path: `cuda_device::barrier::barrier_cta_red_and_aligned_count` +- `barrier_cta_red_and_all` (`i1016`) + - canonical compiler path: `cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i1016` + - public source path: `cuda_intrinsics::barrier::barrier_cta_red_and_all` + - compatibility compiler path: `cuda_device::barrier::barrier_cta_red_and_all` +- `barrier_cta_red_and_count` (`i1017`) + - canonical compiler path: `cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i1017` + - public source path: `cuda_intrinsics::barrier::barrier_cta_red_and_count` + - compatibility compiler path: `cuda_device::barrier::barrier_cta_red_and_count` +- `barrier_cta_red_or_aligned_all` (`i1022`) + - canonical compiler path: `cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i1022` + - public source path: `cuda_intrinsics::barrier::barrier_cta_red_or_aligned_all` + - compatibility compiler path: `cuda_device::barrier::barrier_cta_red_or_aligned_all` +- `barrier_cta_red_or_aligned_count` (`i1023`) + - canonical compiler path: `cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i1023` + - public source path: `cuda_intrinsics::barrier::barrier_cta_red_or_aligned_count` + - compatibility compiler path: `cuda_device::barrier::barrier_cta_red_or_aligned_count` +- `barrier_cta_red_or_all` (`i1020`) + - canonical compiler path: `cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i1020` + - public source path: `cuda_intrinsics::barrier::barrier_cta_red_or_all` + - compatibility compiler path: `cuda_device::barrier::barrier_cta_red_or_all` +- `barrier_cta_red_or_count` (`i1021`) + - canonical compiler path: `cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i1021` + - public source path: `cuda_intrinsics::barrier::barrier_cta_red_or_count` + - compatibility compiler path: `cuda_device::barrier::barrier_cta_red_or_count` +- `barrier_cta_red_popc_aligned_all` (`i1026`) + - canonical compiler path: `cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i1026` + - public source path: `cuda_intrinsics::barrier::barrier_cta_red_popc_aligned_all` + - compatibility compiler path: `cuda_device::barrier::barrier_cta_red_popc_aligned_all` +- `barrier_cta_red_popc_aligned_count` (`i1027`) + - canonical compiler path: `cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i1027` + - public source path: `cuda_intrinsics::barrier::barrier_cta_red_popc_aligned_count` + - compatibility compiler path: `cuda_device::barrier::barrier_cta_red_popc_aligned_count` +- `barrier_cta_red_popc_all` (`i1024`) + - canonical compiler path: `cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i1024` + - public source path: `cuda_intrinsics::barrier::barrier_cta_red_popc_all` + - compatibility compiler path: `cuda_device::barrier::barrier_cta_red_popc_all` +- `barrier_cta_red_popc_count` (`i1025`) + - canonical compiler path: `cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i1025` + - public source path: `cuda_intrinsics::barrier::barrier_cta_red_popc_count` + - compatibility compiler path: `cuda_device::barrier::barrier_cta_red_popc_count` - `barrier_cta_sync` (`i0883`) - canonical compiler path: `cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0883` - public source path: `cuda_intrinsics::barrier::barrier_cta_sync` @@ -1190,6 +1251,10 @@ This table is generated from the resolved catalog. Evidence stages below disting - canonical compiler path: `cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0884` - public source path: `cuda_intrinsics::barrier::barrier_cta_sync_aligned` - compatibility compiler path: `cuda_device::barrier::barrier_cta_sync_aligned` +- `barrier_cta_sync_all` (`i1028`) + - canonical compiler path: `cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i1028` + - public source path: `cuda_intrinsics::barrier::barrier_cta_sync_all` + - compatibility compiler path: `cuda_device::barrier::barrier_cta_sync_all` - `block_dim_x` (`i0003`) - canonical compiler path: `cuda_intrinsics::__cuda_oxide_intrinsic_abi_v1::i0003` - public source path: `cuda_intrinsics::sreg::block_dim_x` @@ -5667,8 +5732,21 @@ This table is generated from the resolved catalog. Evidence stages below disting - `barrier_cluster_wait_aligned`: properties `IntrConvergent`, `IntrNoCallback`; result `NoUndef` false; half-open result range `none`; selection records `barrier_cluster_wait_aligned`; selection predicates `Subtarget->getPTXVersion() >= 78`, `Subtarget->getSmVersion() >= 90` - `barrier_cta_arrive`: properties `IntrConvergent`, `IntrNoCallback`; result `NoUndef` false; half-open result range `none`; selection records `BARRIER_CTA_ARRIVE_ii`, `BARRIER_CTA_ARRIVE_ir`, `BARRIER_CTA_ARRIVE_ri`, `BARRIER_CTA_ARRIVE_rr`; selection predicates `Subtarget->getPTXVersion() >= 60` - `barrier_cta_arrive_aligned`: properties `IntrConvergent`, `IntrNoCallback`; result `NoUndef` false; half-open result range `none`; selection records `BARRIER_CTA_ARRIVE_ALIGNED_ii`, `BARRIER_CTA_ARRIVE_ALIGNED_ir`, `BARRIER_CTA_ARRIVE_ALIGNED_ri`, `BARRIER_CTA_ARRIVE_ALIGNED_rr`; selection predicates none +- `barrier_cta_red_and_aligned_all`: properties `IntrConvergent`, `IntrNoCallback`; result `NoUndef` false; half-open result range `none`; selection records `BARRIER_CTA_RED_AND_ALIGNED_ALL_ip`, `BARRIER_CTA_RED_AND_ALIGNED_ALL_rp`; selection predicates none +- `barrier_cta_red_and_aligned_count`: properties `IntrConvergent`, `IntrNoCallback`; result `NoUndef` false; half-open result range `none`; selection records `BARRIER_CTA_RED_AND_ALIGNED_iip`, `BARRIER_CTA_RED_AND_ALIGNED_irp`, `BARRIER_CTA_RED_AND_ALIGNED_rip`, `BARRIER_CTA_RED_AND_ALIGNED_rrp`; selection predicates none +- `barrier_cta_red_and_all`: properties `IntrConvergent`, `IntrNoCallback`; result `NoUndef` false; half-open result range `none`; selection records `BARRIER_CTA_RED_AND_ALL_ip`, `BARRIER_CTA_RED_AND_ALL_rp`; selection predicates `Subtarget->getPTXVersion() >= 60` +- `barrier_cta_red_and_count`: properties `IntrConvergent`, `IntrNoCallback`; result `NoUndef` false; half-open result range `none`; selection records `BARRIER_CTA_RED_AND_COUNT_iip`, `BARRIER_CTA_RED_AND_COUNT_irp`, `BARRIER_CTA_RED_AND_COUNT_rip`, `BARRIER_CTA_RED_AND_COUNT_rrp`; selection predicates `Subtarget->getPTXVersion() >= 60` +- `barrier_cta_red_or_aligned_all`: properties `IntrConvergent`, `IntrNoCallback`; result `NoUndef` false; half-open result range `none`; selection records `BARRIER_CTA_RED_OR_ALIGNED_ALL_ip`, `BARRIER_CTA_RED_OR_ALIGNED_ALL_rp`; selection predicates none +- `barrier_cta_red_or_aligned_count`: properties `IntrConvergent`, `IntrNoCallback`; result `NoUndef` false; half-open result range `none`; selection records `BARRIER_CTA_RED_OR_ALIGNED_iip`, `BARRIER_CTA_RED_OR_ALIGNED_irp`, `BARRIER_CTA_RED_OR_ALIGNED_rip`, `BARRIER_CTA_RED_OR_ALIGNED_rrp`; selection predicates none +- `barrier_cta_red_or_all`: properties `IntrConvergent`, `IntrNoCallback`; result `NoUndef` false; half-open result range `none`; selection records `BARRIER_CTA_RED_OR_ALL_ip`, `BARRIER_CTA_RED_OR_ALL_rp`; selection predicates `Subtarget->getPTXVersion() >= 60` +- `barrier_cta_red_or_count`: properties `IntrConvergent`, `IntrNoCallback`; result `NoUndef` false; half-open result range `none`; selection records `BARRIER_CTA_RED_OR_COUNT_iip`, `BARRIER_CTA_RED_OR_COUNT_irp`, `BARRIER_CTA_RED_OR_COUNT_rip`, `BARRIER_CTA_RED_OR_COUNT_rrp`; selection predicates `Subtarget->getPTXVersion() >= 60` +- `barrier_cta_red_popc_aligned_all`: properties `IntrConvergent`, `IntrNoCallback`; result `NoUndef` false; half-open result range `none`; selection records `BARRIER_CTA_RED_POPC_ALIGNED_ALL_ip`, `BARRIER_CTA_RED_POPC_ALIGNED_ALL_rp`; selection predicates none +- `barrier_cta_red_popc_aligned_count`: properties `IntrConvergent`, `IntrNoCallback`; result `NoUndef` false; half-open result range `none`; selection records `BARRIER_CTA_RED_POPC_ALIGNED_iip`, `BARRIER_CTA_RED_POPC_ALIGNED_irp`, `BARRIER_CTA_RED_POPC_ALIGNED_rip`, `BARRIER_CTA_RED_POPC_ALIGNED_rrp`; selection predicates none +- `barrier_cta_red_popc_all`: properties `IntrConvergent`, `IntrNoCallback`; result `NoUndef` false; half-open result range `none`; selection records `BARRIER_CTA_RED_POPC_ALL_ip`, `BARRIER_CTA_RED_POPC_ALL_rp`; selection predicates `Subtarget->getPTXVersion() >= 60` +- `barrier_cta_red_popc_count`: properties `IntrConvergent`, `IntrNoCallback`; result `NoUndef` false; half-open result range `none`; selection records `BARRIER_CTA_RED_POPC_COUNT_iip`, `BARRIER_CTA_RED_POPC_COUNT_irp`, `BARRIER_CTA_RED_POPC_COUNT_rip`, `BARRIER_CTA_RED_POPC_COUNT_rrp`; selection predicates `Subtarget->getPTXVersion() >= 60` - `barrier_cta_sync`: properties `IntrConvergent`, `IntrNoCallback`; result `NoUndef` false; half-open result range `none`; selection records `BARRIER_CTA_SYNC_ii`, `BARRIER_CTA_SYNC_ir`, `BARRIER_CTA_SYNC_ri`, `BARRIER_CTA_SYNC_rr`; selection predicates `Subtarget->getPTXVersion() >= 60` - `barrier_cta_sync_aligned`: properties `IntrConvergent`, `IntrNoCallback`; result `NoUndef` false; half-open result range `none`; selection records `BARRIER_CTA_SYNC_ALIGNED_ii`, `BARRIER_CTA_SYNC_ALIGNED_ir`, `BARRIER_CTA_SYNC_ALIGNED_ri`, `BARRIER_CTA_SYNC_ALIGNED_rr`; selection predicates none +- `barrier_cta_sync_all`: properties `IntrConvergent`, `IntrNoCallback`; result `NoUndef` false; half-open result range `none`; selection records `BARRIER_CTA_SYNC_ALL_i`, `BARRIER_CTA_SYNC_ALL_r`; selection predicates `Subtarget->getPTXVersion() >= 60` - `block_dim_x`: properties `IntrNoMem`, `IntrSpeculatable`, `NoUndef`, `Range`; result `NoUndef` true; half-open result range `[1, 1025)`; selection records `INT_PTX_SREG_NTID_x`; selection predicates none - `block_dim_y`: properties `IntrNoMem`, `IntrSpeculatable`, `NoUndef`, `Range`; result `NoUndef` true; half-open result range `[1, 1025)`; selection records `INT_PTX_SREG_NTID_y`; selection predicates none - `block_dim_z`: properties `IntrNoMem`, `IntrSpeculatable`, `NoUndef`, `Range`; result `NoUndef` true; half-open result range `[1, 65)`; selection records `INT_PTX_SREG_NTID_z`; selection predicates none @@ -6952,6 +7030,66 @@ This table is generated from the resolved catalog. Evidence stages below disting - `lib_nvvm` uses `inline_ptx` from profile `cuda-13.3-libnvvm-13.3.73-execution-control` at PTX 1.0 / sm_75+: status `validated` (`CUDA 13.3 libNVVM package 13.3.73; libNVVM API 2.0`, SHA-256 `5317a9fb3c8b719198e89e27fd60e2b59f2702fe6b1eab357167c920b52be9cc`) - backend codegen on `sm_75, ptx93`: `succeeded` — libNVVM compiled source IR SHA-256 6f4a98ea80bfcad48693cdfd222167642dbc916957e2f2dd74bcd5b2ee8550e8 to LTOIR SHA-256 60404c53823ad015a8a1ea47c3bb8d705d833f6bd8184b569933c17e74d98710; nvJitLink emitted matching PTX SHA-256 130dc6b1c3ac18204ed037ec7ada696f28829255d62ff2f3971c32bdbdec86af. - device link on `sm_75, ptx93`: `succeeded` — nvJitLink produced cubin SHA-256 a73a41d6b67c452bd0b5d73dcb28e01a81c01cc91d27a6e98f499a409d4f6001; cuobjdump retained BAR.ARV. Tool `libnvJitLink.so.13.3.33` reports `CUDA 13.3 nvJitLink 13.3.33` (SHA-256 `f84abd240b428825c3ef16632deb1026b208252fe19cef225a9f4ad06a39d1aa`). Artifact `cubin`. +- `barrier_cta_red_and_aligned_all`: runtime `not recorded` + - `llvm_nvptx` uses `typed_nvvm` from profile `rust-llvm-22.1.2-1cb4e383-barrier-reduction` at PTX 3.2 / sm_20+: status `lowered` (`LLVM version 22.1.2-rust-1.96.0-nightly`, SHA-256 `ff1dcdc18a5441003d43c5df267b43e2b6dd3efccca38c20bb2801885626331e`) + - backend codegen on `sm_20, ptx32`: `succeeded` — Pinned LLVM 22.1.2 selected the reviewed bar[rier].red instruction; combined source and emitted PTX artifacts are preserved in the design scratchpad. + - `lib_nvvm` uses `inline_ptx` from profile `cuda-12.9-libnvvm-12.9.86-barrier-reduction` at PTX 1.0 / sm_75+: status `lowered` (`CUDA 12.9 libNVVM package V12.9.86; NVVM IR 2.0`, SHA-256 `79729301061c2abe547c749073ad658a1582d33fb5d003e2c097285e5ddafb2e`) + - backend codegen on `sm_75, ptx88`: `succeeded` — CUDA 12.9.86 libNVVM compiled the 1,156-byte combined source SHA-256 11bd0ada26128692365b334162e9bfc26bfb713c0a89404b342e522894410c31 to 2,708-byte PTX SHA-256 6bf4e457e1f8d9624deb76df2cdab36c07e062676b2a45c69f081aa42fc5d4ed; CUDA 12.9.86 ptxas accepted that PTX and produced cubin SHA-256 2c09dd490b9157429babbf5fb9119df702f2bd9a5a6255464d9431366c0b318c. +- `barrier_cta_red_and_aligned_count`: runtime `not recorded` + - `llvm_nvptx` uses `typed_nvvm` from profile `rust-llvm-22.1.2-1cb4e383-barrier-reduction` at PTX 3.2 / sm_20+: status `lowered` (`LLVM version 22.1.2-rust-1.96.0-nightly`, SHA-256 `ff1dcdc18a5441003d43c5df267b43e2b6dd3efccca38c20bb2801885626331e`) + - backend codegen on `sm_20, ptx32`: `succeeded` — Pinned LLVM 22.1.2 selected the reviewed bar[rier].red instruction; combined source and emitted PTX artifacts are preserved in the design scratchpad. + - `lib_nvvm` uses `inline_ptx` from profile `cuda-12.9-libnvvm-12.9.86-barrier-reduction` at PTX 1.0 / sm_75+: status `lowered` (`CUDA 12.9 libNVVM package V12.9.86; NVVM IR 2.0`, SHA-256 `79729301061c2abe547c749073ad658a1582d33fb5d003e2c097285e5ddafb2e`) + - backend codegen on `sm_75, ptx88`: `succeeded` — CUDA 12.9.86 libNVVM compiled the 1,156-byte combined source SHA-256 11bd0ada26128692365b334162e9bfc26bfb713c0a89404b342e522894410c31 to 2,708-byte PTX SHA-256 6bf4e457e1f8d9624deb76df2cdab36c07e062676b2a45c69f081aa42fc5d4ed; CUDA 12.9.86 ptxas accepted that PTX and produced cubin SHA-256 2c09dd490b9157429babbf5fb9119df702f2bd9a5a6255464d9431366c0b318c. +- `barrier_cta_red_and_all`: runtime `not recorded` + - `llvm_nvptx` uses `typed_nvvm` from profile `rust-llvm-22.1.2-1cb4e383-barrier-reduction` at PTX 6.0 / sm_30+: status `lowered` (`LLVM version 22.1.2-rust-1.96.0-nightly`, SHA-256 `ff1dcdc18a5441003d43c5df267b43e2b6dd3efccca38c20bb2801885626331e`) + - backend codegen on `sm_30, ptx60`: `succeeded` — Pinned LLVM 22.1.2 selected the reviewed bar[rier].red instruction; combined source and emitted PTX artifacts are preserved in the design scratchpad. + - `lib_nvvm` uses `inline_ptx` from profile `cuda-12.9-libnvvm-12.9.86-barrier-reduction` at PTX 6.0 / sm_75+: status `lowered` (`CUDA 12.9 libNVVM package V12.9.86; NVVM IR 2.0`, SHA-256 `79729301061c2abe547c749073ad658a1582d33fb5d003e2c097285e5ddafb2e`) + - backend codegen on `sm_75, ptx88`: `succeeded` — CUDA 12.9.86 libNVVM compiled the 1,156-byte combined source SHA-256 11bd0ada26128692365b334162e9bfc26bfb713c0a89404b342e522894410c31 to 2,708-byte PTX SHA-256 6bf4e457e1f8d9624deb76df2cdab36c07e062676b2a45c69f081aa42fc5d4ed; CUDA 12.9.86 ptxas accepted that PTX and produced cubin SHA-256 2c09dd490b9157429babbf5fb9119df702f2bd9a5a6255464d9431366c0b318c. +- `barrier_cta_red_and_count`: runtime `not recorded` + - `llvm_nvptx` uses `typed_nvvm` from profile `rust-llvm-22.1.2-1cb4e383-barrier-reduction` at PTX 6.0 / sm_30+: status `lowered` (`LLVM version 22.1.2-rust-1.96.0-nightly`, SHA-256 `ff1dcdc18a5441003d43c5df267b43e2b6dd3efccca38c20bb2801885626331e`) + - backend codegen on `sm_30, ptx60`: `succeeded` — Pinned LLVM 22.1.2 selected the reviewed bar[rier].red instruction; combined source and emitted PTX artifacts are preserved in the design scratchpad. + - `lib_nvvm` uses `inline_ptx` from profile `cuda-12.9-libnvvm-12.9.86-barrier-reduction` at PTX 6.0 / sm_75+: status `lowered` (`CUDA 12.9 libNVVM package V12.9.86; NVVM IR 2.0`, SHA-256 `79729301061c2abe547c749073ad658a1582d33fb5d003e2c097285e5ddafb2e`) + - backend codegen on `sm_75, ptx88`: `succeeded` — CUDA 12.9.86 libNVVM compiled the 1,156-byte combined source SHA-256 11bd0ada26128692365b334162e9bfc26bfb713c0a89404b342e522894410c31 to 2,708-byte PTX SHA-256 6bf4e457e1f8d9624deb76df2cdab36c07e062676b2a45c69f081aa42fc5d4ed; CUDA 12.9.86 ptxas accepted that PTX and produced cubin SHA-256 2c09dd490b9157429babbf5fb9119df702f2bd9a5a6255464d9431366c0b318c. +- `barrier_cta_red_or_aligned_all`: runtime `not recorded` + - `llvm_nvptx` uses `typed_nvvm` from profile `rust-llvm-22.1.2-1cb4e383-barrier-reduction` at PTX 3.2 / sm_20+: status `lowered` (`LLVM version 22.1.2-rust-1.96.0-nightly`, SHA-256 `ff1dcdc18a5441003d43c5df267b43e2b6dd3efccca38c20bb2801885626331e`) + - backend codegen on `sm_20, ptx32`: `succeeded` — Pinned LLVM 22.1.2 selected the reviewed bar[rier].red instruction; combined source and emitted PTX artifacts are preserved in the design scratchpad. + - `lib_nvvm` uses `inline_ptx` from profile `cuda-12.9-libnvvm-12.9.86-barrier-reduction` at PTX 1.0 / sm_75+: status `lowered` (`CUDA 12.9 libNVVM package V12.9.86; NVVM IR 2.0`, SHA-256 `79729301061c2abe547c749073ad658a1582d33fb5d003e2c097285e5ddafb2e`) + - backend codegen on `sm_75, ptx88`: `succeeded` — CUDA 12.9.86 libNVVM compiled the 1,156-byte combined source SHA-256 11bd0ada26128692365b334162e9bfc26bfb713c0a89404b342e522894410c31 to 2,708-byte PTX SHA-256 6bf4e457e1f8d9624deb76df2cdab36c07e062676b2a45c69f081aa42fc5d4ed; CUDA 12.9.86 ptxas accepted that PTX and produced cubin SHA-256 2c09dd490b9157429babbf5fb9119df702f2bd9a5a6255464d9431366c0b318c. +- `barrier_cta_red_or_aligned_count`: runtime `not recorded` + - `llvm_nvptx` uses `typed_nvvm` from profile `rust-llvm-22.1.2-1cb4e383-barrier-reduction` at PTX 3.2 / sm_20+: status `lowered` (`LLVM version 22.1.2-rust-1.96.0-nightly`, SHA-256 `ff1dcdc18a5441003d43c5df267b43e2b6dd3efccca38c20bb2801885626331e`) + - backend codegen on `sm_20, ptx32`: `succeeded` — Pinned LLVM 22.1.2 selected the reviewed bar[rier].red instruction; combined source and emitted PTX artifacts are preserved in the design scratchpad. + - `lib_nvvm` uses `inline_ptx` from profile `cuda-12.9-libnvvm-12.9.86-barrier-reduction` at PTX 1.0 / sm_75+: status `lowered` (`CUDA 12.9 libNVVM package V12.9.86; NVVM IR 2.0`, SHA-256 `79729301061c2abe547c749073ad658a1582d33fb5d003e2c097285e5ddafb2e`) + - backend codegen on `sm_75, ptx88`: `succeeded` — CUDA 12.9.86 libNVVM compiled the 1,156-byte combined source SHA-256 11bd0ada26128692365b334162e9bfc26bfb713c0a89404b342e522894410c31 to 2,708-byte PTX SHA-256 6bf4e457e1f8d9624deb76df2cdab36c07e062676b2a45c69f081aa42fc5d4ed; CUDA 12.9.86 ptxas accepted that PTX and produced cubin SHA-256 2c09dd490b9157429babbf5fb9119df702f2bd9a5a6255464d9431366c0b318c. +- `barrier_cta_red_or_all`: runtime `not recorded` + - `llvm_nvptx` uses `typed_nvvm` from profile `rust-llvm-22.1.2-1cb4e383-barrier-reduction` at PTX 6.0 / sm_30+: status `lowered` (`LLVM version 22.1.2-rust-1.96.0-nightly`, SHA-256 `ff1dcdc18a5441003d43c5df267b43e2b6dd3efccca38c20bb2801885626331e`) + - backend codegen on `sm_30, ptx60`: `succeeded` — Pinned LLVM 22.1.2 selected the reviewed bar[rier].red instruction; combined source and emitted PTX artifacts are preserved in the design scratchpad. + - `lib_nvvm` uses `inline_ptx` from profile `cuda-12.9-libnvvm-12.9.86-barrier-reduction` at PTX 6.0 / sm_75+: status `lowered` (`CUDA 12.9 libNVVM package V12.9.86; NVVM IR 2.0`, SHA-256 `79729301061c2abe547c749073ad658a1582d33fb5d003e2c097285e5ddafb2e`) + - backend codegen on `sm_75, ptx88`: `succeeded` — CUDA 12.9.86 libNVVM compiled the 1,156-byte combined source SHA-256 11bd0ada26128692365b334162e9bfc26bfb713c0a89404b342e522894410c31 to 2,708-byte PTX SHA-256 6bf4e457e1f8d9624deb76df2cdab36c07e062676b2a45c69f081aa42fc5d4ed; CUDA 12.9.86 ptxas accepted that PTX and produced cubin SHA-256 2c09dd490b9157429babbf5fb9119df702f2bd9a5a6255464d9431366c0b318c. +- `barrier_cta_red_or_count`: runtime `not recorded` + - `llvm_nvptx` uses `typed_nvvm` from profile `rust-llvm-22.1.2-1cb4e383-barrier-reduction` at PTX 6.0 / sm_30+: status `lowered` (`LLVM version 22.1.2-rust-1.96.0-nightly`, SHA-256 `ff1dcdc18a5441003d43c5df267b43e2b6dd3efccca38c20bb2801885626331e`) + - backend codegen on `sm_30, ptx60`: `succeeded` — Pinned LLVM 22.1.2 selected the reviewed bar[rier].red instruction; combined source and emitted PTX artifacts are preserved in the design scratchpad. + - `lib_nvvm` uses `inline_ptx` from profile `cuda-12.9-libnvvm-12.9.86-barrier-reduction` at PTX 6.0 / sm_75+: status `lowered` (`CUDA 12.9 libNVVM package V12.9.86; NVVM IR 2.0`, SHA-256 `79729301061c2abe547c749073ad658a1582d33fb5d003e2c097285e5ddafb2e`) + - backend codegen on `sm_75, ptx88`: `succeeded` — CUDA 12.9.86 libNVVM compiled the 1,156-byte combined source SHA-256 11bd0ada26128692365b334162e9bfc26bfb713c0a89404b342e522894410c31 to 2,708-byte PTX SHA-256 6bf4e457e1f8d9624deb76df2cdab36c07e062676b2a45c69f081aa42fc5d4ed; CUDA 12.9.86 ptxas accepted that PTX and produced cubin SHA-256 2c09dd490b9157429babbf5fb9119df702f2bd9a5a6255464d9431366c0b318c. +- `barrier_cta_red_popc_aligned_all`: runtime `not recorded` + - `llvm_nvptx` uses `typed_nvvm` from profile `rust-llvm-22.1.2-1cb4e383-barrier-reduction` at PTX 3.2 / sm_20+: status `lowered` (`LLVM version 22.1.2-rust-1.96.0-nightly`, SHA-256 `ff1dcdc18a5441003d43c5df267b43e2b6dd3efccca38c20bb2801885626331e`) + - backend codegen on `sm_20, ptx32`: `succeeded` — Pinned LLVM 22.1.2 selected the reviewed bar[rier].red instruction; combined source and emitted PTX artifacts are preserved in the design scratchpad. + - `lib_nvvm` uses `inline_ptx` from profile `cuda-12.9-libnvvm-12.9.86-barrier-reduction` at PTX 1.0 / sm_75+: status `lowered` (`CUDA 12.9 libNVVM package V12.9.86; NVVM IR 2.0`, SHA-256 `79729301061c2abe547c749073ad658a1582d33fb5d003e2c097285e5ddafb2e`) + - backend codegen on `sm_75, ptx88`: `succeeded` — CUDA 12.9.86 libNVVM compiled the 1,156-byte combined source SHA-256 11bd0ada26128692365b334162e9bfc26bfb713c0a89404b342e522894410c31 to 2,708-byte PTX SHA-256 6bf4e457e1f8d9624deb76df2cdab36c07e062676b2a45c69f081aa42fc5d4ed; CUDA 12.9.86 ptxas accepted that PTX and produced cubin SHA-256 2c09dd490b9157429babbf5fb9119df702f2bd9a5a6255464d9431366c0b318c. +- `barrier_cta_red_popc_aligned_count`: runtime `not recorded` + - `llvm_nvptx` uses `typed_nvvm` from profile `rust-llvm-22.1.2-1cb4e383-barrier-reduction` at PTX 3.2 / sm_20+: status `lowered` (`LLVM version 22.1.2-rust-1.96.0-nightly`, SHA-256 `ff1dcdc18a5441003d43c5df267b43e2b6dd3efccca38c20bb2801885626331e`) + - backend codegen on `sm_20, ptx32`: `succeeded` — Pinned LLVM 22.1.2 selected the reviewed bar[rier].red instruction; combined source and emitted PTX artifacts are preserved in the design scratchpad. + - `lib_nvvm` uses `inline_ptx` from profile `cuda-12.9-libnvvm-12.9.86-barrier-reduction` at PTX 1.0 / sm_75+: status `lowered` (`CUDA 12.9 libNVVM package V12.9.86; NVVM IR 2.0`, SHA-256 `79729301061c2abe547c749073ad658a1582d33fb5d003e2c097285e5ddafb2e`) + - backend codegen on `sm_75, ptx88`: `succeeded` — CUDA 12.9.86 libNVVM compiled the 1,156-byte combined source SHA-256 11bd0ada26128692365b334162e9bfc26bfb713c0a89404b342e522894410c31 to 2,708-byte PTX SHA-256 6bf4e457e1f8d9624deb76df2cdab36c07e062676b2a45c69f081aa42fc5d4ed; CUDA 12.9.86 ptxas accepted that PTX and produced cubin SHA-256 2c09dd490b9157429babbf5fb9119df702f2bd9a5a6255464d9431366c0b318c. +- `barrier_cta_red_popc_all`: runtime `not recorded` + - `llvm_nvptx` uses `typed_nvvm` from profile `rust-llvm-22.1.2-1cb4e383-barrier-reduction` at PTX 6.0 / sm_30+: status `lowered` (`LLVM version 22.1.2-rust-1.96.0-nightly`, SHA-256 `ff1dcdc18a5441003d43c5df267b43e2b6dd3efccca38c20bb2801885626331e`) + - backend codegen on `sm_30, ptx60`: `succeeded` — Pinned LLVM 22.1.2 selected the reviewed bar[rier].red instruction; combined source and emitted PTX artifacts are preserved in the design scratchpad. + - `lib_nvvm` uses `inline_ptx` from profile `cuda-12.9-libnvvm-12.9.86-barrier-reduction` at PTX 6.0 / sm_75+: status `lowered` (`CUDA 12.9 libNVVM package V12.9.86; NVVM IR 2.0`, SHA-256 `79729301061c2abe547c749073ad658a1582d33fb5d003e2c097285e5ddafb2e`) + - backend codegen on `sm_75, ptx88`: `succeeded` — CUDA 12.9.86 libNVVM compiled the 1,156-byte combined source SHA-256 11bd0ada26128692365b334162e9bfc26bfb713c0a89404b342e522894410c31 to 2,708-byte PTX SHA-256 6bf4e457e1f8d9624deb76df2cdab36c07e062676b2a45c69f081aa42fc5d4ed; CUDA 12.9.86 ptxas accepted that PTX and produced cubin SHA-256 2c09dd490b9157429babbf5fb9119df702f2bd9a5a6255464d9431366c0b318c. +- `barrier_cta_red_popc_count`: runtime `not recorded` + - `llvm_nvptx` uses `typed_nvvm` from profile `rust-llvm-22.1.2-1cb4e383-barrier-reduction` at PTX 6.0 / sm_30+: status `lowered` (`LLVM version 22.1.2-rust-1.96.0-nightly`, SHA-256 `ff1dcdc18a5441003d43c5df267b43e2b6dd3efccca38c20bb2801885626331e`) + - backend codegen on `sm_30, ptx60`: `succeeded` — Pinned LLVM 22.1.2 selected the reviewed bar[rier].red instruction; combined source and emitted PTX artifacts are preserved in the design scratchpad. + - `lib_nvvm` uses `inline_ptx` from profile `cuda-12.9-libnvvm-12.9.86-barrier-reduction` at PTX 6.0 / sm_75+: status `lowered` (`CUDA 12.9 libNVVM package V12.9.86; NVVM IR 2.0`, SHA-256 `79729301061c2abe547c749073ad658a1582d33fb5d003e2c097285e5ddafb2e`) + - backend codegen on `sm_75, ptx88`: `succeeded` — CUDA 12.9.86 libNVVM compiled the 1,156-byte combined source SHA-256 11bd0ada26128692365b334162e9bfc26bfb713c0a89404b342e522894410c31 to 2,708-byte PTX SHA-256 6bf4e457e1f8d9624deb76df2cdab36c07e062676b2a45c69f081aa42fc5d4ed; CUDA 12.9.86 ptxas accepted that PTX and produced cubin SHA-256 2c09dd490b9157429babbf5fb9119df702f2bd9a5a6255464d9431366c0b318c. - `barrier_cta_sync`: runtime `not recorded` - `llvm_nvptx` uses `typed_nvvm` from profile `rust-llvm-22.1.2-1cb4e383-execution-control` at PTX 6.0 / sm_30+: status `validated` (`LLVM version 22.1.2-rust-1.96.0-nightly`, SHA-256 `ff1dcdc18a5441003d43c5df267b43e2b6dd3efccca38c20bb2801885626331e`) - declaration canonicalization on `sm_30`: `succeeded` — llvm-as and llvm-dis canonicalized source IR SHA-256 73bcf70a8647d141dea6d68aba4ab626818aef73c25eaf85b9c415814dcf0e71, bitcode SHA-256 50b842e412973300a1b0c67190c173f7f5f744db15efc9d639daa3b5c7ec33c6, and canonical IR SHA-256 d068e7a4ff32510dd439f5e92e97374a319e4ba6c1a6380cff5c855a0cde6a3f. @@ -6968,6 +7106,11 @@ This table is generated from the resolved catalog. Evidence stages below disting - `lib_nvvm` uses `inline_ptx` from profile `cuda-13.3-libnvvm-13.3.73-execution-control` at PTX 1.0 / sm_75+: status `validated` (`CUDA 13.3 libNVVM package 13.3.73; libNVVM API 2.0`, SHA-256 `5317a9fb3c8b719198e89e27fd60e2b59f2702fe6b1eab357167c920b52be9cc`) - backend codegen on `sm_75, ptx93`: `succeeded` — libNVVM compiled source IR SHA-256 579466b9aa311ff37495c4e7f604bdf107ae171d820b25105feb84258152f7f0 to LTOIR SHA-256 94e983ade64421ea5a8d44d8453affd15dc765762667343044f76efea8e1aa16; nvJitLink emitted matching PTX SHA-256 6b10b5c6a1248b83b5f4518bdbb8876e15730cc1b7b2b2796da142ece753b0ef. - device link on `sm_75, ptx93`: `succeeded` — nvJitLink produced cubin SHA-256 2ed2b6758f44f5bfe3414a3f0051f915709eddd6b4054401ec85aa3afbcc942f; cuobjdump retained BAR.SYNC. Tool `libnvJitLink.so.13.3.33` reports `CUDA 13.3 nvJitLink 13.3.33` (SHA-256 `f84abd240b428825c3ef16632deb1026b208252fe19cef225a9f4ad06a39d1aa`). Artifact `cubin`. +- `barrier_cta_sync_all`: runtime `not recorded` + - `llvm_nvptx` uses `typed_nvvm` from profile `rust-llvm-22.1.2-1cb4e383-execution-control` at PTX 6.0 / sm_30+: status `lowered` (`LLVM version 22.1.2-rust-1.96.0-nightly`, SHA-256 `ff1dcdc18a5441003d43c5df267b43e2b6dd3efccca38c20bb2801885626331e`) + - backend codegen on `sm_30, ptx60`: `succeeded` — Pinned LLVM emitted barrier.sync for both reviewed register/immediate selection records. + - `lib_nvvm` uses `inline_ptx` from profile `cuda-12.9-libnvvm-12.9.86-execution-control` at PTX 6.0 / sm_75+: status `lowered` (`CUDA 12.9 libNVVM package V12.9.86; NVVM IR 2.0`, SHA-256 `79729301061c2abe547c749073ad658a1582d33fb5d003e2c097285e5ddafb2e`) + - backend codegen on `sm_75, ptx88`: `succeeded` — CUDA 12.9.86 libNVVM compiled source SHA-256 11bd0ada26128692365b334162e9bfc26bfb713c0a89404b342e522894410c31 to PTX SHA-256 6bf4e457e1f8d9624deb76df2cdab36c07e062676b2a45c69f081aa42fc5d4ed retaining barrier.sync; CUDA 12.9.86 ptxas accepted it. - `breakpoint`: runtime `unexecuted` - `llvm_nvptx` uses `inline_ptx` from profile `rust-llvm-22.1.2-1cb4e383-debug-control` at PTX 3.2 / sm_20+: status `validated` (`LLVM version 22.1.2-rust-1.96.0-nightly`, SHA-256 `ff1dcdc18a5441003d43c5df267b43e2b6dd3efccca38c20bb2801885626331e`) - backend codegen on `sm_20, ptx32`: `succeeded` — The pinned Rust LLVM emitted PTX 3.2 containing all three instructions; source SHA-256 cbe8cd68385d281ecb4edeb5458a63f1e851ee0ab2539c7b5d335b79e91e543e and PTX SHA-256 df263240edffc345f2c5a65b953c362a49878e08e9fdf1c2a06858829643dad5. diff --git a/intrinsics/overlay.toml b/intrinsics/overlay.toml index 0ea596da27..5ce518f0ae 100644 --- a/intrinsics/overlay.toml +++ b/intrinsics/overlay.toml @@ -1,9 +1,10 @@ -schema = 44 +schema = 45 catalog_version = "0.1.0" intrinsic_abi = 1 backend_profile = "rust-llvm-22.1.2-1cb4e383" shards = [ "overlay/active_mask.toml", + "overlay/barrier_reduction.toml", "overlay/clc.toml", "overlay/cluster_barrier.toml", "overlay/cluster_memory.toml", diff --git a/intrinsics/overlay/barrier_reduction.toml b/intrinsics/overlay/barrier_reduction.toml new file mode 100644 index 0000000000..1c503eb4ce --- /dev/null +++ b/intrinsics/overlay/barrier_reduction.toml @@ -0,0 +1,478 @@ +# Reviewed CTA barrier reduction instruction family. + +schema = 63 +family = "barrier_reduction" + +[[intrinsic]] +id = "barrier_cta_red_and_all" +abi_id = "i1016" +operation_key = "synchronization.cta.barrier.reduction.and.all" +family = "barrier_reduction" +source_record = "int_nvvm_barrier_cta_red_and_all" +rust_module = "barrier" +rust_name = "barrier_cta_red_and_all" +rust_arguments = ["u32","bool"] +rust_result = "bool" +safe = false +must_use = true +public_rust_path = "cuda_intrinsics::barrier::barrier_cta_red_and_all" +compatibility_rust_paths = ["cuda_device::barrier::barrier_cta_red_and_all"] +dialect_op_type = "BarrierCtaRedAndAllOp" +dialect_op_name = "nvvm.barrier_cta_red_and_all" +dialect_operands = ["i32","i1"] +dialect_results = ["i1"] +llvm_symbol = "llvm.nvvm.barrier.cta.red.and.all" +llvm_arguments = ["i32","i1"] +llvm_results = ["i1"] +pure = false +memory = "read_write" +convergent = true +execution_scope = "cta" +minimum_ptx = "6.0" +minimum_sm = "sm_30" +ptx_result = "bool" +targets = "all" +ptx_isa_version = "9.3" +ptx_isa_section = "9.7.14.1 Parallel Synchronization and Communication Instructions: bar, barrier" +ptx_isa_url = "https://docs.nvidia.com/cuda/parallel-thread-execution/#parallel-synchronization-and-communication-instructions-bar-barrier" +lowering = "generated_barrier_reduction" +backend_lowerings = [ + { backend = "llvm_nvptx", mechanism = "typed_nvvm", evidence_profile = "rust-llvm-22.1.2-1cb4e383-barrier-reduction", minimum_ptx = "6.0", minimum_sm = "sm_30" }, + { backend = "lib_nvvm", mechanism = "inline_ptx", evidence_profile = "cuda-12.9-libnvvm-12.9.86-barrier-reduction", minimum_ptx = "6.0", minimum_sm = "sm_75" }, +] +expected_ptx = { mnemonic = "barrier", modifiers = ["red","and","pred"], operands = [{ kind = "register" }, { kind = "register_or_immediate" }, { kind = "register" }] } +summary = "Reduces predicates with AND while synchronizing all arriving CTA threads at a numbered barrier." + +[[intrinsic]] +id = "barrier_cta_red_and_count" +abi_id = "i1017" +operation_key = "synchronization.cta.barrier.reduction.and.count" +family = "barrier_reduction" +source_record = "int_nvvm_barrier_cta_red_and_count" +rust_module = "barrier" +rust_name = "barrier_cta_red_and_count" +rust_arguments = ["u32","u32","bool"] +rust_result = "bool" +safe = false +must_use = true +public_rust_path = "cuda_intrinsics::barrier::barrier_cta_red_and_count" +compatibility_rust_paths = ["cuda_device::barrier::barrier_cta_red_and_count"] +dialect_op_type = "BarrierCtaRedAndCountOp" +dialect_op_name = "nvvm.barrier_cta_red_and_count" +dialect_operands = ["i32","i32","i1"] +dialect_results = ["i1"] +llvm_symbol = "llvm.nvvm.barrier.cta.red.and.count" +llvm_arguments = ["i32","i32","i1"] +llvm_results = ["i1"] +pure = false +memory = "read_write" +convergent = true +execution_scope = "cta" +minimum_ptx = "6.0" +minimum_sm = "sm_30" +ptx_result = "bool" +targets = "all" +ptx_isa_version = "9.3" +ptx_isa_section = "9.7.14.1 Parallel Synchronization and Communication Instructions: bar, barrier" +ptx_isa_url = "https://docs.nvidia.com/cuda/parallel-thread-execution/#parallel-synchronization-and-communication-instructions-bar-barrier" +lowering = "generated_barrier_reduction" +backend_lowerings = [ + { backend = "llvm_nvptx", mechanism = "typed_nvvm", evidence_profile = "rust-llvm-22.1.2-1cb4e383-barrier-reduction", minimum_ptx = "6.0", minimum_sm = "sm_30" }, + { backend = "lib_nvvm", mechanism = "inline_ptx", evidence_profile = "cuda-12.9-libnvvm-12.9.86-barrier-reduction", minimum_ptx = "6.0", minimum_sm = "sm_75" }, +] +expected_ptx = { mnemonic = "barrier", modifiers = ["red","and","pred"], operands = [{ kind = "register" }, { kind = "register_or_immediate" }, { kind = "register_or_immediate" }, { kind = "register" }] } +summary = "Reduces predicates with AND while synchronizing the requested number of CTA threads at a numbered barrier." + +[[intrinsic]] +id = "barrier_cta_red_and_aligned_all" +abi_id = "i1018" +operation_key = "synchronization.cta.bar.reduction.and.all" +family = "barrier_reduction" +source_record = "int_nvvm_barrier_cta_red_and_aligned_all" +rust_module = "barrier" +rust_name = "barrier_cta_red_and_aligned_all" +rust_arguments = ["u32","bool"] +rust_result = "bool" +safe = false +must_use = true +public_rust_path = "cuda_intrinsics::barrier::barrier_cta_red_and_aligned_all" +compatibility_rust_paths = ["cuda_device::barrier::barrier_cta_red_and_aligned_all"] +dialect_op_type = "BarrierCtaRedAndAlignedAllOp" +dialect_op_name = "nvvm.barrier_cta_red_and_aligned_all" +dialect_operands = ["i32","i1"] +dialect_results = ["i1"] +llvm_symbol = "llvm.nvvm.barrier.cta.red.and.aligned.all" +llvm_arguments = ["i32","i1"] +llvm_results = ["i1"] +pure = false +memory = "read_write" +convergent = true +execution_scope = "cta" +minimum_ptx = "1.0" +ptx_result = "bool" +targets = "all" +ptx_isa_version = "9.3" +ptx_isa_section = "9.7.14.1 Parallel Synchronization and Communication Instructions: bar, barrier" +ptx_isa_url = "https://docs.nvidia.com/cuda/parallel-thread-execution/#parallel-synchronization-and-communication-instructions-bar-barrier" +lowering = "generated_barrier_reduction" +backend_lowerings = [ + { backend = "llvm_nvptx", mechanism = "typed_nvvm", evidence_profile = "rust-llvm-22.1.2-1cb4e383-barrier-reduction", minimum_ptx = "3.2", minimum_sm = "sm_20" }, + { backend = "lib_nvvm", mechanism = "inline_ptx", evidence_profile = "cuda-12.9-libnvvm-12.9.86-barrier-reduction", minimum_ptx = "1.0", minimum_sm = "sm_75" }, +] +expected_ptx = { mnemonic = "bar", modifiers = ["red","and","pred"], operands = [{ kind = "register" }, { kind = "register_or_immediate" }, { kind = "register" }] } +summary = "Reduces predicates with AND while synchronizing all arriving CTA threads at an aligned numbered barrier." + +[[intrinsic]] +id = "barrier_cta_red_and_aligned_count" +abi_id = "i1019" +operation_key = "synchronization.cta.bar.reduction.and.count" +family = "barrier_reduction" +source_record = "int_nvvm_barrier_cta_red_and_aligned_count" +rust_module = "barrier" +rust_name = "barrier_cta_red_and_aligned_count" +rust_arguments = ["u32","u32","bool"] +rust_result = "bool" +safe = false +must_use = true +public_rust_path = "cuda_intrinsics::barrier::barrier_cta_red_and_aligned_count" +compatibility_rust_paths = ["cuda_device::barrier::barrier_cta_red_and_aligned_count"] +dialect_op_type = "BarrierCtaRedAndAlignedCountOp" +dialect_op_name = "nvvm.barrier_cta_red_and_aligned_count" +dialect_operands = ["i32","i32","i1"] +dialect_results = ["i1"] +llvm_symbol = "llvm.nvvm.barrier.cta.red.and.aligned.count" +llvm_arguments = ["i32","i32","i1"] +llvm_results = ["i1"] +pure = false +memory = "read_write" +convergent = true +execution_scope = "cta" +minimum_ptx = "1.0" +ptx_result = "bool" +targets = "all" +ptx_isa_version = "9.3" +ptx_isa_section = "9.7.14.1 Parallel Synchronization and Communication Instructions: bar, barrier" +ptx_isa_url = "https://docs.nvidia.com/cuda/parallel-thread-execution/#parallel-synchronization-and-communication-instructions-bar-barrier" +lowering = "generated_barrier_reduction" +backend_lowerings = [ + { backend = "llvm_nvptx", mechanism = "typed_nvvm", evidence_profile = "rust-llvm-22.1.2-1cb4e383-barrier-reduction", minimum_ptx = "3.2", minimum_sm = "sm_20" }, + { backend = "lib_nvvm", mechanism = "inline_ptx", evidence_profile = "cuda-12.9-libnvvm-12.9.86-barrier-reduction", minimum_ptx = "1.0", minimum_sm = "sm_75" }, +] +expected_ptx = { mnemonic = "bar", modifiers = ["red","and","pred"], operands = [{ kind = "register" }, { kind = "register_or_immediate" }, { kind = "register_or_immediate" }, { kind = "register" }] } +summary = "Reduces predicates with AND while synchronizing the requested number of CTA threads at an aligned numbered barrier." + +[[intrinsic]] +id = "barrier_cta_red_or_all" +abi_id = "i1020" +operation_key = "synchronization.cta.barrier.reduction.or.all" +family = "barrier_reduction" +source_record = "int_nvvm_barrier_cta_red_or_all" +rust_module = "barrier" +rust_name = "barrier_cta_red_or_all" +rust_arguments = ["u32","bool"] +rust_result = "bool" +safe = false +must_use = true +public_rust_path = "cuda_intrinsics::barrier::barrier_cta_red_or_all" +compatibility_rust_paths = ["cuda_device::barrier::barrier_cta_red_or_all"] +dialect_op_type = "BarrierCtaRedOrAllOp" +dialect_op_name = "nvvm.barrier_cta_red_or_all" +dialect_operands = ["i32","i1"] +dialect_results = ["i1"] +llvm_symbol = "llvm.nvvm.barrier.cta.red.or.all" +llvm_arguments = ["i32","i1"] +llvm_results = ["i1"] +pure = false +memory = "read_write" +convergent = true +execution_scope = "cta" +minimum_ptx = "6.0" +minimum_sm = "sm_30" +ptx_result = "bool" +targets = "all" +ptx_isa_version = "9.3" +ptx_isa_section = "9.7.14.1 Parallel Synchronization and Communication Instructions: bar, barrier" +ptx_isa_url = "https://docs.nvidia.com/cuda/parallel-thread-execution/#parallel-synchronization-and-communication-instructions-bar-barrier" +lowering = "generated_barrier_reduction" +backend_lowerings = [ + { backend = "llvm_nvptx", mechanism = "typed_nvvm", evidence_profile = "rust-llvm-22.1.2-1cb4e383-barrier-reduction", minimum_ptx = "6.0", minimum_sm = "sm_30" }, + { backend = "lib_nvvm", mechanism = "inline_ptx", evidence_profile = "cuda-12.9-libnvvm-12.9.86-barrier-reduction", minimum_ptx = "6.0", minimum_sm = "sm_75" }, +] +expected_ptx = { mnemonic = "barrier", modifiers = ["red","or","pred"], operands = [{ kind = "register" }, { kind = "register_or_immediate" }, { kind = "register" }] } +summary = "Reduces predicates with OR while synchronizing all arriving CTA threads at a numbered barrier." + +[[intrinsic]] +id = "barrier_cta_red_or_count" +abi_id = "i1021" +operation_key = "synchronization.cta.barrier.reduction.or.count" +family = "barrier_reduction" +source_record = "int_nvvm_barrier_cta_red_or_count" +rust_module = "barrier" +rust_name = "barrier_cta_red_or_count" +rust_arguments = ["u32","u32","bool"] +rust_result = "bool" +safe = false +must_use = true +public_rust_path = "cuda_intrinsics::barrier::barrier_cta_red_or_count" +compatibility_rust_paths = ["cuda_device::barrier::barrier_cta_red_or_count"] +dialect_op_type = "BarrierCtaRedOrCountOp" +dialect_op_name = "nvvm.barrier_cta_red_or_count" +dialect_operands = ["i32","i32","i1"] +dialect_results = ["i1"] +llvm_symbol = "llvm.nvvm.barrier.cta.red.or.count" +llvm_arguments = ["i32","i32","i1"] +llvm_results = ["i1"] +pure = false +memory = "read_write" +convergent = true +execution_scope = "cta" +minimum_ptx = "6.0" +minimum_sm = "sm_30" +ptx_result = "bool" +targets = "all" +ptx_isa_version = "9.3" +ptx_isa_section = "9.7.14.1 Parallel Synchronization and Communication Instructions: bar, barrier" +ptx_isa_url = "https://docs.nvidia.com/cuda/parallel-thread-execution/#parallel-synchronization-and-communication-instructions-bar-barrier" +lowering = "generated_barrier_reduction" +backend_lowerings = [ + { backend = "llvm_nvptx", mechanism = "typed_nvvm", evidence_profile = "rust-llvm-22.1.2-1cb4e383-barrier-reduction", minimum_ptx = "6.0", minimum_sm = "sm_30" }, + { backend = "lib_nvvm", mechanism = "inline_ptx", evidence_profile = "cuda-12.9-libnvvm-12.9.86-barrier-reduction", minimum_ptx = "6.0", minimum_sm = "sm_75" }, +] +expected_ptx = { mnemonic = "barrier", modifiers = ["red","or","pred"], operands = [{ kind = "register" }, { kind = "register_or_immediate" }, { kind = "register_or_immediate" }, { kind = "register" }] } +summary = "Reduces predicates with OR while synchronizing the requested number of CTA threads at a numbered barrier." + +[[intrinsic]] +id = "barrier_cta_red_or_aligned_all" +abi_id = "i1022" +operation_key = "synchronization.cta.bar.reduction.or.all" +family = "barrier_reduction" +source_record = "int_nvvm_barrier_cta_red_or_aligned_all" +rust_module = "barrier" +rust_name = "barrier_cta_red_or_aligned_all" +rust_arguments = ["u32","bool"] +rust_result = "bool" +safe = false +must_use = true +public_rust_path = "cuda_intrinsics::barrier::barrier_cta_red_or_aligned_all" +compatibility_rust_paths = ["cuda_device::barrier::barrier_cta_red_or_aligned_all"] +dialect_op_type = "BarrierCtaRedOrAlignedAllOp" +dialect_op_name = "nvvm.barrier_cta_red_or_aligned_all" +dialect_operands = ["i32","i1"] +dialect_results = ["i1"] +llvm_symbol = "llvm.nvvm.barrier.cta.red.or.aligned.all" +llvm_arguments = ["i32","i1"] +llvm_results = ["i1"] +pure = false +memory = "read_write" +convergent = true +execution_scope = "cta" +minimum_ptx = "1.0" +ptx_result = "bool" +targets = "all" +ptx_isa_version = "9.3" +ptx_isa_section = "9.7.14.1 Parallel Synchronization and Communication Instructions: bar, barrier" +ptx_isa_url = "https://docs.nvidia.com/cuda/parallel-thread-execution/#parallel-synchronization-and-communication-instructions-bar-barrier" +lowering = "generated_barrier_reduction" +backend_lowerings = [ + { backend = "llvm_nvptx", mechanism = "typed_nvvm", evidence_profile = "rust-llvm-22.1.2-1cb4e383-barrier-reduction", minimum_ptx = "3.2", minimum_sm = "sm_20" }, + { backend = "lib_nvvm", mechanism = "inline_ptx", evidence_profile = "cuda-12.9-libnvvm-12.9.86-barrier-reduction", minimum_ptx = "1.0", minimum_sm = "sm_75" }, +] +expected_ptx = { mnemonic = "bar", modifiers = ["red","or","pred"], operands = [{ kind = "register" }, { kind = "register_or_immediate" }, { kind = "register" }] } +summary = "Reduces predicates with OR while synchronizing all arriving CTA threads at an aligned numbered barrier." + +[[intrinsic]] +id = "barrier_cta_red_or_aligned_count" +abi_id = "i1023" +operation_key = "synchronization.cta.bar.reduction.or.count" +family = "barrier_reduction" +source_record = "int_nvvm_barrier_cta_red_or_aligned_count" +rust_module = "barrier" +rust_name = "barrier_cta_red_or_aligned_count" +rust_arguments = ["u32","u32","bool"] +rust_result = "bool" +safe = false +must_use = true +public_rust_path = "cuda_intrinsics::barrier::barrier_cta_red_or_aligned_count" +compatibility_rust_paths = ["cuda_device::barrier::barrier_cta_red_or_aligned_count"] +dialect_op_type = "BarrierCtaRedOrAlignedCountOp" +dialect_op_name = "nvvm.barrier_cta_red_or_aligned_count" +dialect_operands = ["i32","i32","i1"] +dialect_results = ["i1"] +llvm_symbol = "llvm.nvvm.barrier.cta.red.or.aligned.count" +llvm_arguments = ["i32","i32","i1"] +llvm_results = ["i1"] +pure = false +memory = "read_write" +convergent = true +execution_scope = "cta" +minimum_ptx = "1.0" +ptx_result = "bool" +targets = "all" +ptx_isa_version = "9.3" +ptx_isa_section = "9.7.14.1 Parallel Synchronization and Communication Instructions: bar, barrier" +ptx_isa_url = "https://docs.nvidia.com/cuda/parallel-thread-execution/#parallel-synchronization-and-communication-instructions-bar-barrier" +lowering = "generated_barrier_reduction" +backend_lowerings = [ + { backend = "llvm_nvptx", mechanism = "typed_nvvm", evidence_profile = "rust-llvm-22.1.2-1cb4e383-barrier-reduction", minimum_ptx = "3.2", minimum_sm = "sm_20" }, + { backend = "lib_nvvm", mechanism = "inline_ptx", evidence_profile = "cuda-12.9-libnvvm-12.9.86-barrier-reduction", minimum_ptx = "1.0", minimum_sm = "sm_75" }, +] +expected_ptx = { mnemonic = "bar", modifiers = ["red","or","pred"], operands = [{ kind = "register" }, { kind = "register_or_immediate" }, { kind = "register_or_immediate" }, { kind = "register" }] } +summary = "Reduces predicates with OR while synchronizing the requested number of CTA threads at an aligned numbered barrier." + +[[intrinsic]] +id = "barrier_cta_red_popc_all" +abi_id = "i1024" +operation_key = "synchronization.cta.barrier.reduction.popc.all" +family = "barrier_reduction" +source_record = "int_nvvm_barrier_cta_red_popc_all" +rust_module = "barrier" +rust_name = "barrier_cta_red_popc_all" +rust_arguments = ["u32","bool"] +rust_result = "u32" +safe = false +must_use = true +public_rust_path = "cuda_intrinsics::barrier::barrier_cta_red_popc_all" +compatibility_rust_paths = ["cuda_device::barrier::barrier_cta_red_popc_all"] +dialect_op_type = "BarrierCtaRedPopcAllOp" +dialect_op_name = "nvvm.barrier_cta_red_popc_all" +dialect_operands = ["i32","i1"] +dialect_results = ["i32"] +llvm_symbol = "llvm.nvvm.barrier.cta.red.popc.all" +llvm_arguments = ["i32","i1"] +llvm_results = ["i32"] +pure = false +memory = "read_write" +convergent = true +execution_scope = "cta" +minimum_ptx = "6.0" +minimum_sm = "sm_30" +ptx_result = "u32" +targets = "all" +ptx_isa_version = "9.3" +ptx_isa_section = "9.7.14.1 Parallel Synchronization and Communication Instructions: bar, barrier" +ptx_isa_url = "https://docs.nvidia.com/cuda/parallel-thread-execution/#parallel-synchronization-and-communication-instructions-bar-barrier" +lowering = "generated_barrier_reduction" +backend_lowerings = [ + { backend = "llvm_nvptx", mechanism = "typed_nvvm", evidence_profile = "rust-llvm-22.1.2-1cb4e383-barrier-reduction", minimum_ptx = "6.0", minimum_sm = "sm_30" }, + { backend = "lib_nvvm", mechanism = "inline_ptx", evidence_profile = "cuda-12.9-libnvvm-12.9.86-barrier-reduction", minimum_ptx = "6.0", minimum_sm = "sm_75" }, +] +expected_ptx = { mnemonic = "barrier", modifiers = ["red","popc","u32"], operands = [{ kind = "register" }, { kind = "register_or_immediate" }, { kind = "register" }] } +summary = "Counts true predicates while synchronizing all arriving CTA threads at a numbered barrier." + +[[intrinsic]] +id = "barrier_cta_red_popc_count" +abi_id = "i1025" +operation_key = "synchronization.cta.barrier.reduction.popc.count" +family = "barrier_reduction" +source_record = "int_nvvm_barrier_cta_red_popc_count" +rust_module = "barrier" +rust_name = "barrier_cta_red_popc_count" +rust_arguments = ["u32","u32","bool"] +rust_result = "u32" +safe = false +must_use = true +public_rust_path = "cuda_intrinsics::barrier::barrier_cta_red_popc_count" +compatibility_rust_paths = ["cuda_device::barrier::barrier_cta_red_popc_count"] +dialect_op_type = "BarrierCtaRedPopcCountOp" +dialect_op_name = "nvvm.barrier_cta_red_popc_count" +dialect_operands = ["i32","i32","i1"] +dialect_results = ["i32"] +llvm_symbol = "llvm.nvvm.barrier.cta.red.popc.count" +llvm_arguments = ["i32","i32","i1"] +llvm_results = ["i32"] +pure = false +memory = "read_write" +convergent = true +execution_scope = "cta" +minimum_ptx = "6.0" +minimum_sm = "sm_30" +ptx_result = "u32" +targets = "all" +ptx_isa_version = "9.3" +ptx_isa_section = "9.7.14.1 Parallel Synchronization and Communication Instructions: bar, barrier" +ptx_isa_url = "https://docs.nvidia.com/cuda/parallel-thread-execution/#parallel-synchronization-and-communication-instructions-bar-barrier" +lowering = "generated_barrier_reduction" +backend_lowerings = [ + { backend = "llvm_nvptx", mechanism = "typed_nvvm", evidence_profile = "rust-llvm-22.1.2-1cb4e383-barrier-reduction", minimum_ptx = "6.0", minimum_sm = "sm_30" }, + { backend = "lib_nvvm", mechanism = "inline_ptx", evidence_profile = "cuda-12.9-libnvvm-12.9.86-barrier-reduction", minimum_ptx = "6.0", minimum_sm = "sm_75" }, +] +expected_ptx = { mnemonic = "barrier", modifiers = ["red","popc","u32"], operands = [{ kind = "register" }, { kind = "register_or_immediate" }, { kind = "register_or_immediate" }, { kind = "register" }] } +summary = "Counts true predicates while synchronizing the requested number of CTA threads at a numbered barrier." + +[[intrinsic]] +id = "barrier_cta_red_popc_aligned_all" +abi_id = "i1026" +operation_key = "synchronization.cta.bar.reduction.popc.all" +family = "barrier_reduction" +source_record = "int_nvvm_barrier_cta_red_popc_aligned_all" +rust_module = "barrier" +rust_name = "barrier_cta_red_popc_aligned_all" +rust_arguments = ["u32","bool"] +rust_result = "u32" +safe = false +must_use = true +public_rust_path = "cuda_intrinsics::barrier::barrier_cta_red_popc_aligned_all" +compatibility_rust_paths = ["cuda_device::barrier::barrier_cta_red_popc_aligned_all"] +dialect_op_type = "BarrierCtaRedPopcAlignedAllOp" +dialect_op_name = "nvvm.barrier_cta_red_popc_aligned_all" +dialect_operands = ["i32","i1"] +dialect_results = ["i32"] +llvm_symbol = "llvm.nvvm.barrier.cta.red.popc.aligned.all" +llvm_arguments = ["i32","i1"] +llvm_results = ["i32"] +pure = false +memory = "read_write" +convergent = true +execution_scope = "cta" +minimum_ptx = "1.0" +ptx_result = "u32" +targets = "all" +ptx_isa_version = "9.3" +ptx_isa_section = "9.7.14.1 Parallel Synchronization and Communication Instructions: bar, barrier" +ptx_isa_url = "https://docs.nvidia.com/cuda/parallel-thread-execution/#parallel-synchronization-and-communication-instructions-bar-barrier" +lowering = "generated_barrier_reduction" +backend_lowerings = [ + { backend = "llvm_nvptx", mechanism = "typed_nvvm", evidence_profile = "rust-llvm-22.1.2-1cb4e383-barrier-reduction", minimum_ptx = "3.2", minimum_sm = "sm_20" }, + { backend = "lib_nvvm", mechanism = "inline_ptx", evidence_profile = "cuda-12.9-libnvvm-12.9.86-barrier-reduction", minimum_ptx = "1.0", minimum_sm = "sm_75" }, +] +expected_ptx = { mnemonic = "bar", modifiers = ["red","popc","u32"], operands = [{ kind = "register" }, { kind = "register_or_immediate" }, { kind = "register" }] } +summary = "Counts true predicates while synchronizing all arriving CTA threads at an aligned numbered barrier." + +[[intrinsic]] +id = "barrier_cta_red_popc_aligned_count" +abi_id = "i1027" +operation_key = "synchronization.cta.bar.reduction.popc.count" +family = "barrier_reduction" +source_record = "int_nvvm_barrier_cta_red_popc_aligned_count" +rust_module = "barrier" +rust_name = "barrier_cta_red_popc_aligned_count" +rust_arguments = ["u32","u32","bool"] +rust_result = "u32" +safe = false +must_use = true +public_rust_path = "cuda_intrinsics::barrier::barrier_cta_red_popc_aligned_count" +compatibility_rust_paths = ["cuda_device::barrier::barrier_cta_red_popc_aligned_count"] +dialect_op_type = "BarrierCtaRedPopcAlignedCountOp" +dialect_op_name = "nvvm.barrier_cta_red_popc_aligned_count" +dialect_operands = ["i32","i32","i1"] +dialect_results = ["i32"] +llvm_symbol = "llvm.nvvm.barrier.cta.red.popc.aligned.count" +llvm_arguments = ["i32","i32","i1"] +llvm_results = ["i32"] +pure = false +memory = "read_write" +convergent = true +execution_scope = "cta" +minimum_ptx = "1.0" +ptx_result = "u32" +targets = "all" +ptx_isa_version = "9.3" +ptx_isa_section = "9.7.14.1 Parallel Synchronization and Communication Instructions: bar, barrier" +ptx_isa_url = "https://docs.nvidia.com/cuda/parallel-thread-execution/#parallel-synchronization-and-communication-instructions-bar-barrier" +lowering = "generated_barrier_reduction" +backend_lowerings = [ + { backend = "llvm_nvptx", mechanism = "typed_nvvm", evidence_profile = "rust-llvm-22.1.2-1cb4e383-barrier-reduction", minimum_ptx = "3.2", minimum_sm = "sm_20" }, + { backend = "lib_nvvm", mechanism = "inline_ptx", evidence_profile = "cuda-12.9-libnvvm-12.9.86-barrier-reduction", minimum_ptx = "1.0", minimum_sm = "sm_75" }, +] +expected_ptx = { mnemonic = "bar", modifiers = ["red","popc","u32"], operands = [{ kind = "register" }, { kind = "register_or_immediate" }, { kind = "register_or_immediate" }, { kind = "register" }] } +summary = "Counts true predicates while synchronizing the requested number of CTA threads at an aligned numbered barrier." diff --git a/intrinsics/overlay/counted_barrier.toml b/intrinsics/overlay/counted_barrier.toml index 4421a207f8..db161a5daf 100644 --- a/intrinsics/overlay/counted_barrier.toml +++ b/intrinsics/overlay/counted_barrier.toml @@ -1,6 +1,6 @@ # Reviewed counted CTA barrier instruction family. -schema = 61 +schema = 63 family = "counted_barrier" [[intrinsic]] @@ -160,3 +160,43 @@ backend_lowerings = [ ] expected_ptx = { mnemonic = "bar", modifiers = ["arrive"], operands = [{ kind = "register_or_immediate" }, { kind = "register_or_immediate" }] } summary = "Signals arrival of the requested number of CTA threads at an aligned numbered barrier without waiting." + +[[intrinsic]] +id = "barrier_cta_sync_all" +abi_id = "i1028" +operation_key = "synchronization.cta.barrier.all" +family = "counted_barrier" +source_record = "int_nvvm_barrier_cta_sync_all" +rust_module = "barrier" +rust_name = "barrier_cta_sync_all" +rust_arguments = ["u32"] +rust_result = "()" +safe = false +must_use = false +public_rust_path = "cuda_intrinsics::barrier::barrier_cta_sync_all" +compatibility_rust_paths = ["cuda_device::barrier::barrier_cta_sync_all"] +dialect_op_type = "BarrierCtaSyncAllOp" +dialect_op_name = "nvvm.barrier_cta_sync_all" +dialect_operands = ["i32"] +dialect_results = [] +llvm_symbol = "llvm.nvvm.barrier.cta.sync.all" +llvm_arguments = ["i32"] +llvm_results = [] +pure = false +memory = "read_write" +convergent = true +execution_scope = "cta" +minimum_ptx = "6.0" +minimum_sm = "sm_30" +ptx_result = "()" +targets = "all" +ptx_isa_version = "9.3" +ptx_isa_section = "9.7.14.1 Parallel Synchronization and Communication Instructions: bar, barrier" +ptx_isa_url = "https://docs.nvidia.com/cuda/parallel-thread-execution/#parallel-synchronization-and-communication-instructions-bar-barrier" +lowering = "generated_execution_control" +backend_lowerings = [ + { backend = "llvm_nvptx", mechanism = "typed_nvvm", evidence_profile = "rust-llvm-22.1.2-1cb4e383-execution-control", minimum_ptx = "6.0", minimum_sm = "sm_30" }, + { backend = "lib_nvvm", mechanism = "inline_ptx", evidence_profile = "cuda-12.9-libnvvm-12.9.86-execution-control", minimum_ptx = "6.0", minimum_sm = "sm_75" }, +] +expected_ptx = { mnemonic = "barrier", modifiers = ["sync"], operands = [{ kind = "register_or_immediate" }] } +summary = "Synchronizes all arriving CTA threads at a numbered barrier." diff --git a/intrinsics/probes/abs_bf16x2.ll b/intrinsics/probes/abs_bf16x2.ll index c412114a04..557f96661b 100644 --- a/intrinsics/probes/abs_bf16x2.ll +++ b/intrinsics/probes/abs_bf16x2.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/abs_f16x2.ll b/intrinsics/probes/abs_f16x2.ll index 9282708a2a..aa6c93dceb 100644 --- a/intrinsics/probes/abs_f16x2.ll +++ b/intrinsics/probes/abs_f16x2.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/active_mask.ll b/intrinsics/probes/active_mask.ll index 3dcb4dd7d1..95932cc233 100644 --- a/intrinsics/probes/active_mask.ll +++ b/intrinsics/probes/active_mask.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/add_bf16x2.ll b/intrinsics/probes/add_bf16x2.ll index 77ad4b6617..3772c51368 100644 --- a/intrinsics/probes/add_bf16x2.ll +++ b/intrinsics/probes/add_bf16x2.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/add_f16x2.ll b/intrinsics/probes/add_f16x2.ll index 48286ec346..63ca596e57 100644 --- a/intrinsics/probes/add_f16x2.ll +++ b/intrinsics/probes/add_f16x2.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/add_f32x2.ll b/intrinsics/probes/add_f32x2.ll index c417e49082..11125e10c4 100644 --- a/intrinsics/probes/add_f32x2.ll +++ b/intrinsics/probes/add_f32x2.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/add_ftz_f32x2.ll b/intrinsics/probes/add_ftz_f32x2.ll index e4644a91e5..994f72a7eb 100644 --- a/intrinsics/probes/add_ftz_f32x2.ll +++ b/intrinsics/probes/add_ftz_f32x2.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/add_rm_f32.ll b/intrinsics/probes/add_rm_f32.ll index a3d249a6fa..746747aa15 100644 --- a/intrinsics/probes/add_rm_f32.ll +++ b/intrinsics/probes/add_rm_f32.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/add_rm_f64.ll b/intrinsics/probes/add_rm_f64.ll index 3e9973c1a0..cb03a19192 100644 --- a/intrinsics/probes/add_rm_f64.ll +++ b/intrinsics/probes/add_rm_f64.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/add_rm_ftz_f32.ll b/intrinsics/probes/add_rm_ftz_f32.ll index 1fc7f1748c..c6444f531b 100644 --- a/intrinsics/probes/add_rm_ftz_f32.ll +++ b/intrinsics/probes/add_rm_ftz_f32.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/add_rm_ftz_sat_f32.ll b/intrinsics/probes/add_rm_ftz_sat_f32.ll index 210022d8db..701388d4b2 100644 --- a/intrinsics/probes/add_rm_ftz_sat_f32.ll +++ b/intrinsics/probes/add_rm_ftz_sat_f32.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/add_rm_sat_f32.ll b/intrinsics/probes/add_rm_sat_f32.ll index 08fbe57f5f..17a98eac9e 100644 --- a/intrinsics/probes/add_rm_sat_f32.ll +++ b/intrinsics/probes/add_rm_sat_f32.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/add_rn_f32.ll b/intrinsics/probes/add_rn_f32.ll index 376f5854c0..b810055526 100644 --- a/intrinsics/probes/add_rn_f32.ll +++ b/intrinsics/probes/add_rn_f32.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/add_rn_f64.ll b/intrinsics/probes/add_rn_f64.ll index 97c9213a23..9f97beddb9 100644 --- a/intrinsics/probes/add_rn_f64.ll +++ b/intrinsics/probes/add_rn_f64.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/add_rn_ftz_f32.ll b/intrinsics/probes/add_rn_ftz_f32.ll index baf7313984..0d74c4643b 100644 --- a/intrinsics/probes/add_rn_ftz_f32.ll +++ b/intrinsics/probes/add_rn_ftz_f32.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/add_rn_ftz_sat_f32.ll b/intrinsics/probes/add_rn_ftz_sat_f32.ll index f99e31a789..fb84918879 100644 --- a/intrinsics/probes/add_rn_ftz_sat_f32.ll +++ b/intrinsics/probes/add_rn_ftz_sat_f32.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/add_rn_sat_f32.ll b/intrinsics/probes/add_rn_sat_f32.ll index 99bf976bc3..85fd7175d3 100644 --- a/intrinsics/probes/add_rn_sat_f32.ll +++ b/intrinsics/probes/add_rn_sat_f32.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/add_rp_f32.ll b/intrinsics/probes/add_rp_f32.ll index 4986a9bb5d..7038535573 100644 --- a/intrinsics/probes/add_rp_f32.ll +++ b/intrinsics/probes/add_rp_f32.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/add_rp_f64.ll b/intrinsics/probes/add_rp_f64.ll index 11d5851632..962c8bb969 100644 --- a/intrinsics/probes/add_rp_f64.ll +++ b/intrinsics/probes/add_rp_f64.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/add_rp_ftz_f32.ll b/intrinsics/probes/add_rp_ftz_f32.ll index 68a05c714b..875a7fb1e7 100644 --- a/intrinsics/probes/add_rp_ftz_f32.ll +++ b/intrinsics/probes/add_rp_ftz_f32.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/add_rp_ftz_sat_f32.ll b/intrinsics/probes/add_rp_ftz_sat_f32.ll index c412b956af..42d6ec0d70 100644 --- a/intrinsics/probes/add_rp_ftz_sat_f32.ll +++ b/intrinsics/probes/add_rp_ftz_sat_f32.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/add_rp_sat_f32.ll b/intrinsics/probes/add_rp_sat_f32.ll index f025d1d06e..e9ce6be18c 100644 --- a/intrinsics/probes/add_rp_sat_f32.ll +++ b/intrinsics/probes/add_rp_sat_f32.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/add_rz_f32.ll b/intrinsics/probes/add_rz_f32.ll index 4dcb279280..9cdaa85fe9 100644 --- a/intrinsics/probes/add_rz_f32.ll +++ b/intrinsics/probes/add_rz_f32.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/add_rz_f64.ll b/intrinsics/probes/add_rz_f64.ll index 4a8f21e98c..43a6914b88 100644 --- a/intrinsics/probes/add_rz_f64.ll +++ b/intrinsics/probes/add_rz_f64.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/add_rz_ftz_f32.ll b/intrinsics/probes/add_rz_ftz_f32.ll index 17c960c675..51ba378457 100644 --- a/intrinsics/probes/add_rz_ftz_f32.ll +++ b/intrinsics/probes/add_rz_ftz_f32.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/add_rz_ftz_sat_f32.ll b/intrinsics/probes/add_rz_ftz_sat_f32.ll index 9c23136043..406ef7d2c0 100644 --- a/intrinsics/probes/add_rz_ftz_sat_f32.ll +++ b/intrinsics/probes/add_rz_ftz_sat_f32.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/add_rz_sat_f32.ll b/intrinsics/probes/add_rz_sat_f32.ll index 21cbed1a38..3bde368ec0 100644 --- a/intrinsics/probes/add_rz_sat_f32.ll +++ b/intrinsics/probes/add_rz_sat_f32.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/all_sync.ll b/intrinsics/probes/all_sync.ll index 35795f483c..e7c5282e6b 100644 --- a/intrinsics/probes/all_sync.ll +++ b/intrinsics/probes/all_sync.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/any_sync.ll b/intrinsics/probes/any_sync.ll index 9809275a3c..80adab2520 100644 --- a/intrinsics/probes/any_sync.ll +++ b/intrinsics/probes/any_sync.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/ballot_sync.ll b/intrinsics/probes/ballot_sync.ll index dcac9307ef..c8f2a9a849 100644 --- a/intrinsics/probes/ballot_sync.ll +++ b/intrinsics/probes/ballot_sync.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/barrier_cluster_arrive.ll b/intrinsics/probes/barrier_cluster_arrive.ll index 0748ffff9a..4d08e36395 100644 --- a/intrinsics/probes/barrier_cluster_arrive.ll +++ b/intrinsics/probes/barrier_cluster_arrive.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/barrier_cluster_arrive_aligned.ll b/intrinsics/probes/barrier_cluster_arrive_aligned.ll index 53f5ecc74f..9e877150ac 100644 --- a/intrinsics/probes/barrier_cluster_arrive_aligned.ll +++ b/intrinsics/probes/barrier_cluster_arrive_aligned.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/barrier_cluster_arrive_relaxed.ll b/intrinsics/probes/barrier_cluster_arrive_relaxed.ll index 53392f4b31..418b2ce3ba 100644 --- a/intrinsics/probes/barrier_cluster_arrive_relaxed.ll +++ b/intrinsics/probes/barrier_cluster_arrive_relaxed.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/barrier_cluster_arrive_relaxed_aligned.ll b/intrinsics/probes/barrier_cluster_arrive_relaxed_aligned.ll index a46f4d6bb2..abb5868eaa 100644 --- a/intrinsics/probes/barrier_cluster_arrive_relaxed_aligned.ll +++ b/intrinsics/probes/barrier_cluster_arrive_relaxed_aligned.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/barrier_cluster_wait.ll b/intrinsics/probes/barrier_cluster_wait.ll index e7fc50d3d9..a2a71b5e00 100644 --- a/intrinsics/probes/barrier_cluster_wait.ll +++ b/intrinsics/probes/barrier_cluster_wait.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/barrier_cluster_wait_aligned.ll b/intrinsics/probes/barrier_cluster_wait_aligned.ll index 70f3d30255..3c6e6a96d6 100644 --- a/intrinsics/probes/barrier_cluster_wait_aligned.ll +++ b/intrinsics/probes/barrier_cluster_wait_aligned.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/barrier_cta_arrive.ll b/intrinsics/probes/barrier_cta_arrive.ll index aeeaa8ef65..f8faa5f5b9 100644 --- a/intrinsics/probes/barrier_cta_arrive.ll +++ b/intrinsics/probes/barrier_cta_arrive.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/barrier_cta_arrive_aligned.ll b/intrinsics/probes/barrier_cta_arrive_aligned.ll index 7fa5c7f455..096e8cb8ed 100644 --- a/intrinsics/probes/barrier_cta_arrive_aligned.ll +++ b/intrinsics/probes/barrier_cta_arrive_aligned.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/barrier_cta_red_and_aligned_all.ll b/intrinsics/probes/barrier_cta_red_and_aligned_all.ll new file mode 100644 index 0000000000..354a713f9f --- /dev/null +++ b/intrinsics/probes/barrier_cta_red_and_aligned_all.ll @@ -0,0 +1,21 @@ +; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. +; SPDX-License-Identifier: Apache-2.0 +; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. +; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. + +target triple = "nvptx64-nvidia-cuda" + +declare i1 @llvm.nvvm.barrier.cta.red.and.aligned.all(i32, i1) + +define i1 @probe_barrier_cta_red_and_aligned_all_r(i32 %barrier_id, i1 %predicate) #0 { + %result = call i1 @llvm.nvvm.barrier.cta.red.and.aligned.all(i32 %barrier_id, i1 %predicate) + ret i1 %result +} + +define i1 @probe_barrier_cta_red_and_aligned_all_i(i1 %predicate) #0 { + %result = call i1 @llvm.nvvm.barrier.cta.red.and.aligned.all(i32 1, i1 %predicate) + ret i1 %result +} + +attributes #0 = { convergent } diff --git a/intrinsics/probes/barrier_cta_red_and_aligned_count.ll b/intrinsics/probes/barrier_cta_red_and_aligned_count.ll new file mode 100644 index 0000000000..1379678758 --- /dev/null +++ b/intrinsics/probes/barrier_cta_red_and_aligned_count.ll @@ -0,0 +1,31 @@ +; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. +; SPDX-License-Identifier: Apache-2.0 +; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. +; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. + +target triple = "nvptx64-nvidia-cuda" + +declare i1 @llvm.nvvm.barrier.cta.red.and.aligned.count(i32, i32, i1) + +define i1 @probe_barrier_cta_red_and_aligned_count_rr(i32 %barrier_id, i32 %thread_count, i1 %predicate) #0 { + %result = call i1 @llvm.nvvm.barrier.cta.red.and.aligned.count(i32 %barrier_id, i32 %thread_count, i1 %predicate) + ret i1 %result +} + +define i1 @probe_barrier_cta_red_and_aligned_count_ri(i32 %barrier_id, i1 %predicate) #0 { + %result = call i1 @llvm.nvvm.barrier.cta.red.and.aligned.count(i32 %barrier_id, i32 32, i1 %predicate) + ret i1 %result +} + +define i1 @probe_barrier_cta_red_and_aligned_count_ir(i32 %thread_count, i1 %predicate) #0 { + %result = call i1 @llvm.nvvm.barrier.cta.red.and.aligned.count(i32 1, i32 %thread_count, i1 %predicate) + ret i1 %result +} + +define i1 @probe_barrier_cta_red_and_aligned_count_ii(i1 %predicate) #0 { + %result = call i1 @llvm.nvvm.barrier.cta.red.and.aligned.count(i32 1, i32 32, i1 %predicate) + ret i1 %result +} + +attributes #0 = { convergent } diff --git a/intrinsics/probes/barrier_cta_red_and_all.ll b/intrinsics/probes/barrier_cta_red_and_all.ll new file mode 100644 index 0000000000..2492230017 --- /dev/null +++ b/intrinsics/probes/barrier_cta_red_and_all.ll @@ -0,0 +1,21 @@ +; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. +; SPDX-License-Identifier: Apache-2.0 +; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. +; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. + +target triple = "nvptx64-nvidia-cuda" + +declare i1 @llvm.nvvm.barrier.cta.red.and.all(i32, i1) + +define i1 @probe_barrier_cta_red_and_all_r(i32 %barrier_id, i1 %predicate) #0 { + %result = call i1 @llvm.nvvm.barrier.cta.red.and.all(i32 %barrier_id, i1 %predicate) + ret i1 %result +} + +define i1 @probe_barrier_cta_red_and_all_i(i1 %predicate) #0 { + %result = call i1 @llvm.nvvm.barrier.cta.red.and.all(i32 1, i1 %predicate) + ret i1 %result +} + +attributes #0 = { convergent } diff --git a/intrinsics/probes/barrier_cta_red_and_count.ll b/intrinsics/probes/barrier_cta_red_and_count.ll new file mode 100644 index 0000000000..1d027856f1 --- /dev/null +++ b/intrinsics/probes/barrier_cta_red_and_count.ll @@ -0,0 +1,31 @@ +; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. +; SPDX-License-Identifier: Apache-2.0 +; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. +; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. + +target triple = "nvptx64-nvidia-cuda" + +declare i1 @llvm.nvvm.barrier.cta.red.and.count(i32, i32, i1) + +define i1 @probe_barrier_cta_red_and_count_rr(i32 %barrier_id, i32 %thread_count, i1 %predicate) #0 { + %result = call i1 @llvm.nvvm.barrier.cta.red.and.count(i32 %barrier_id, i32 %thread_count, i1 %predicate) + ret i1 %result +} + +define i1 @probe_barrier_cta_red_and_count_ri(i32 %barrier_id, i1 %predicate) #0 { + %result = call i1 @llvm.nvvm.barrier.cta.red.and.count(i32 %barrier_id, i32 32, i1 %predicate) + ret i1 %result +} + +define i1 @probe_barrier_cta_red_and_count_ir(i32 %thread_count, i1 %predicate) #0 { + %result = call i1 @llvm.nvvm.barrier.cta.red.and.count(i32 1, i32 %thread_count, i1 %predicate) + ret i1 %result +} + +define i1 @probe_barrier_cta_red_and_count_ii(i1 %predicate) #0 { + %result = call i1 @llvm.nvvm.barrier.cta.red.and.count(i32 1, i32 32, i1 %predicate) + ret i1 %result +} + +attributes #0 = { convergent } diff --git a/intrinsics/probes/barrier_cta_red_or_aligned_all.ll b/intrinsics/probes/barrier_cta_red_or_aligned_all.ll new file mode 100644 index 0000000000..5fed9ba1c0 --- /dev/null +++ b/intrinsics/probes/barrier_cta_red_or_aligned_all.ll @@ -0,0 +1,21 @@ +; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. +; SPDX-License-Identifier: Apache-2.0 +; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. +; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. + +target triple = "nvptx64-nvidia-cuda" + +declare i1 @llvm.nvvm.barrier.cta.red.or.aligned.all(i32, i1) + +define i1 @probe_barrier_cta_red_or_aligned_all_r(i32 %barrier_id, i1 %predicate) #0 { + %result = call i1 @llvm.nvvm.barrier.cta.red.or.aligned.all(i32 %barrier_id, i1 %predicate) + ret i1 %result +} + +define i1 @probe_barrier_cta_red_or_aligned_all_i(i1 %predicate) #0 { + %result = call i1 @llvm.nvvm.barrier.cta.red.or.aligned.all(i32 1, i1 %predicate) + ret i1 %result +} + +attributes #0 = { convergent } diff --git a/intrinsics/probes/barrier_cta_red_or_aligned_count.ll b/intrinsics/probes/barrier_cta_red_or_aligned_count.ll new file mode 100644 index 0000000000..bf6319d35c --- /dev/null +++ b/intrinsics/probes/barrier_cta_red_or_aligned_count.ll @@ -0,0 +1,31 @@ +; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. +; SPDX-License-Identifier: Apache-2.0 +; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. +; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. + +target triple = "nvptx64-nvidia-cuda" + +declare i1 @llvm.nvvm.barrier.cta.red.or.aligned.count(i32, i32, i1) + +define i1 @probe_barrier_cta_red_or_aligned_count_rr(i32 %barrier_id, i32 %thread_count, i1 %predicate) #0 { + %result = call i1 @llvm.nvvm.barrier.cta.red.or.aligned.count(i32 %barrier_id, i32 %thread_count, i1 %predicate) + ret i1 %result +} + +define i1 @probe_barrier_cta_red_or_aligned_count_ri(i32 %barrier_id, i1 %predicate) #0 { + %result = call i1 @llvm.nvvm.barrier.cta.red.or.aligned.count(i32 %barrier_id, i32 32, i1 %predicate) + ret i1 %result +} + +define i1 @probe_barrier_cta_red_or_aligned_count_ir(i32 %thread_count, i1 %predicate) #0 { + %result = call i1 @llvm.nvvm.barrier.cta.red.or.aligned.count(i32 1, i32 %thread_count, i1 %predicate) + ret i1 %result +} + +define i1 @probe_barrier_cta_red_or_aligned_count_ii(i1 %predicate) #0 { + %result = call i1 @llvm.nvvm.barrier.cta.red.or.aligned.count(i32 1, i32 32, i1 %predicate) + ret i1 %result +} + +attributes #0 = { convergent } diff --git a/intrinsics/probes/barrier_cta_red_or_all.ll b/intrinsics/probes/barrier_cta_red_or_all.ll new file mode 100644 index 0000000000..d5394b9ba9 --- /dev/null +++ b/intrinsics/probes/barrier_cta_red_or_all.ll @@ -0,0 +1,21 @@ +; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. +; SPDX-License-Identifier: Apache-2.0 +; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. +; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. + +target triple = "nvptx64-nvidia-cuda" + +declare i1 @llvm.nvvm.barrier.cta.red.or.all(i32, i1) + +define i1 @probe_barrier_cta_red_or_all_r(i32 %barrier_id, i1 %predicate) #0 { + %result = call i1 @llvm.nvvm.barrier.cta.red.or.all(i32 %barrier_id, i1 %predicate) + ret i1 %result +} + +define i1 @probe_barrier_cta_red_or_all_i(i1 %predicate) #0 { + %result = call i1 @llvm.nvvm.barrier.cta.red.or.all(i32 1, i1 %predicate) + ret i1 %result +} + +attributes #0 = { convergent } diff --git a/intrinsics/probes/barrier_cta_red_or_count.ll b/intrinsics/probes/barrier_cta_red_or_count.ll new file mode 100644 index 0000000000..1bfa555291 --- /dev/null +++ b/intrinsics/probes/barrier_cta_red_or_count.ll @@ -0,0 +1,31 @@ +; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. +; SPDX-License-Identifier: Apache-2.0 +; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. +; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. + +target triple = "nvptx64-nvidia-cuda" + +declare i1 @llvm.nvvm.barrier.cta.red.or.count(i32, i32, i1) + +define i1 @probe_barrier_cta_red_or_count_rr(i32 %barrier_id, i32 %thread_count, i1 %predicate) #0 { + %result = call i1 @llvm.nvvm.barrier.cta.red.or.count(i32 %barrier_id, i32 %thread_count, i1 %predicate) + ret i1 %result +} + +define i1 @probe_barrier_cta_red_or_count_ri(i32 %barrier_id, i1 %predicate) #0 { + %result = call i1 @llvm.nvvm.barrier.cta.red.or.count(i32 %barrier_id, i32 32, i1 %predicate) + ret i1 %result +} + +define i1 @probe_barrier_cta_red_or_count_ir(i32 %thread_count, i1 %predicate) #0 { + %result = call i1 @llvm.nvvm.barrier.cta.red.or.count(i32 1, i32 %thread_count, i1 %predicate) + ret i1 %result +} + +define i1 @probe_barrier_cta_red_or_count_ii(i1 %predicate) #0 { + %result = call i1 @llvm.nvvm.barrier.cta.red.or.count(i32 1, i32 32, i1 %predicate) + ret i1 %result +} + +attributes #0 = { convergent } diff --git a/intrinsics/probes/barrier_cta_red_popc_aligned_all.ll b/intrinsics/probes/barrier_cta_red_popc_aligned_all.ll new file mode 100644 index 0000000000..a93a4143da --- /dev/null +++ b/intrinsics/probes/barrier_cta_red_popc_aligned_all.ll @@ -0,0 +1,21 @@ +; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. +; SPDX-License-Identifier: Apache-2.0 +; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. +; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. + +target triple = "nvptx64-nvidia-cuda" + +declare i32 @llvm.nvvm.barrier.cta.red.popc.aligned.all(i32, i1) + +define i32 @probe_barrier_cta_red_popc_aligned_all_r(i32 %barrier_id, i1 %predicate) #0 { + %result = call i32 @llvm.nvvm.barrier.cta.red.popc.aligned.all(i32 %barrier_id, i1 %predicate) + ret i32 %result +} + +define i32 @probe_barrier_cta_red_popc_aligned_all_i(i1 %predicate) #0 { + %result = call i32 @llvm.nvvm.barrier.cta.red.popc.aligned.all(i32 1, i1 %predicate) + ret i32 %result +} + +attributes #0 = { convergent } diff --git a/intrinsics/probes/barrier_cta_red_popc_aligned_count.ll b/intrinsics/probes/barrier_cta_red_popc_aligned_count.ll new file mode 100644 index 0000000000..3db35aee12 --- /dev/null +++ b/intrinsics/probes/barrier_cta_red_popc_aligned_count.ll @@ -0,0 +1,31 @@ +; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. +; SPDX-License-Identifier: Apache-2.0 +; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. +; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. + +target triple = "nvptx64-nvidia-cuda" + +declare i32 @llvm.nvvm.barrier.cta.red.popc.aligned.count(i32, i32, i1) + +define i32 @probe_barrier_cta_red_popc_aligned_count_rr(i32 %barrier_id, i32 %thread_count, i1 %predicate) #0 { + %result = call i32 @llvm.nvvm.barrier.cta.red.popc.aligned.count(i32 %barrier_id, i32 %thread_count, i1 %predicate) + ret i32 %result +} + +define i32 @probe_barrier_cta_red_popc_aligned_count_ri(i32 %barrier_id, i1 %predicate) #0 { + %result = call i32 @llvm.nvvm.barrier.cta.red.popc.aligned.count(i32 %barrier_id, i32 32, i1 %predicate) + ret i32 %result +} + +define i32 @probe_barrier_cta_red_popc_aligned_count_ir(i32 %thread_count, i1 %predicate) #0 { + %result = call i32 @llvm.nvvm.barrier.cta.red.popc.aligned.count(i32 1, i32 %thread_count, i1 %predicate) + ret i32 %result +} + +define i32 @probe_barrier_cta_red_popc_aligned_count_ii(i1 %predicate) #0 { + %result = call i32 @llvm.nvvm.barrier.cta.red.popc.aligned.count(i32 1, i32 32, i1 %predicate) + ret i32 %result +} + +attributes #0 = { convergent } diff --git a/intrinsics/probes/barrier_cta_red_popc_all.ll b/intrinsics/probes/barrier_cta_red_popc_all.ll new file mode 100644 index 0000000000..dc092af806 --- /dev/null +++ b/intrinsics/probes/barrier_cta_red_popc_all.ll @@ -0,0 +1,21 @@ +; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. +; SPDX-License-Identifier: Apache-2.0 +; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. +; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. + +target triple = "nvptx64-nvidia-cuda" + +declare i32 @llvm.nvvm.barrier.cta.red.popc.all(i32, i1) + +define i32 @probe_barrier_cta_red_popc_all_r(i32 %barrier_id, i1 %predicate) #0 { + %result = call i32 @llvm.nvvm.barrier.cta.red.popc.all(i32 %barrier_id, i1 %predicate) + ret i32 %result +} + +define i32 @probe_barrier_cta_red_popc_all_i(i1 %predicate) #0 { + %result = call i32 @llvm.nvvm.barrier.cta.red.popc.all(i32 1, i1 %predicate) + ret i32 %result +} + +attributes #0 = { convergent } diff --git a/intrinsics/probes/barrier_cta_red_popc_count.ll b/intrinsics/probes/barrier_cta_red_popc_count.ll new file mode 100644 index 0000000000..4eb43807a1 --- /dev/null +++ b/intrinsics/probes/barrier_cta_red_popc_count.ll @@ -0,0 +1,31 @@ +; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. +; SPDX-License-Identifier: Apache-2.0 +; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. +; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. + +target triple = "nvptx64-nvidia-cuda" + +declare i32 @llvm.nvvm.barrier.cta.red.popc.count(i32, i32, i1) + +define i32 @probe_barrier_cta_red_popc_count_rr(i32 %barrier_id, i32 %thread_count, i1 %predicate) #0 { + %result = call i32 @llvm.nvvm.barrier.cta.red.popc.count(i32 %barrier_id, i32 %thread_count, i1 %predicate) + ret i32 %result +} + +define i32 @probe_barrier_cta_red_popc_count_ri(i32 %barrier_id, i1 %predicate) #0 { + %result = call i32 @llvm.nvvm.barrier.cta.red.popc.count(i32 %barrier_id, i32 32, i1 %predicate) + ret i32 %result +} + +define i32 @probe_barrier_cta_red_popc_count_ir(i32 %thread_count, i1 %predicate) #0 { + %result = call i32 @llvm.nvvm.barrier.cta.red.popc.count(i32 1, i32 %thread_count, i1 %predicate) + ret i32 %result +} + +define i32 @probe_barrier_cta_red_popc_count_ii(i1 %predicate) #0 { + %result = call i32 @llvm.nvvm.barrier.cta.red.popc.count(i32 1, i32 32, i1 %predicate) + ret i32 %result +} + +attributes #0 = { convergent } diff --git a/intrinsics/probes/barrier_cta_sync.ll b/intrinsics/probes/barrier_cta_sync.ll index 0f2c9a5b35..3a8bc5b806 100644 --- a/intrinsics/probes/barrier_cta_sync.ll +++ b/intrinsics/probes/barrier_cta_sync.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/barrier_cta_sync_aligned.ll b/intrinsics/probes/barrier_cta_sync_aligned.ll index e5b5389a6b..7e321d6efa 100644 --- a/intrinsics/probes/barrier_cta_sync_aligned.ll +++ b/intrinsics/probes/barrier_cta_sync_aligned.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/barrier_cta_sync_all.ll b/intrinsics/probes/barrier_cta_sync_all.ll new file mode 100644 index 0000000000..b4b8d75813 --- /dev/null +++ b/intrinsics/probes/barrier_cta_sync_all.ll @@ -0,0 +1,21 @@ +; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. +; SPDX-License-Identifier: Apache-2.0 +; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. +; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. + +target triple = "nvptx64-nvidia-cuda" + +declare void @llvm.nvvm.barrier.cta.sync.all(i32) + +define void @probe_barrier_cta_sync_all_r(i32 %barrier_id) #0 { + call void @llvm.nvvm.barrier.cta.sync.all(i32 %barrier_id) + ret void +} + +define void @probe_barrier_cta_sync_all_i() #0 { + call void @llvm.nvvm.barrier.cta.sync.all(i32 1) + ret void +} + +attributes #0 = { convergent } diff --git a/intrinsics/probes/block_dim_x.ll b/intrinsics/probes/block_dim_x.ll index 43d5d34f2a..1ea2237d29 100644 --- a/intrinsics/probes/block_dim_x.ll +++ b/intrinsics/probes/block_dim_x.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/block_dim_y.ll b/intrinsics/probes/block_dim_y.ll index 13945db775..fb2632c16f 100644 --- a/intrinsics/probes/block_dim_y.ll +++ b/intrinsics/probes/block_dim_y.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/block_dim_z.ll b/intrinsics/probes/block_dim_z.ll index eb46914c5c..9498e6156f 100644 --- a/intrinsics/probes/block_dim_z.ll +++ b/intrinsics/probes/block_dim_z.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/block_idx_x.ll b/intrinsics/probes/block_idx_x.ll index 0c8d89089c..d9fe0a2627 100644 --- a/intrinsics/probes/block_idx_x.ll +++ b/intrinsics/probes/block_idx_x.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/block_idx_y.ll b/intrinsics/probes/block_idx_y.ll index d90e08513d..a09fa84c2e 100644 --- a/intrinsics/probes/block_idx_y.ll +++ b/intrinsics/probes/block_idx_y.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/block_idx_z.ll b/intrinsics/probes/block_idx_z.ll index 60933b8cf1..141aaffd04 100644 --- a/intrinsics/probes/block_idx_z.ll +++ b/intrinsics/probes/block_idx_z.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/breakpoint.ll b/intrinsics/probes/breakpoint.ll index 69c5721eee..3c48449ff6 100644 --- a/intrinsics/probes/breakpoint.ll +++ b/intrinsics/probes/breakpoint.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/clc_query_get_first_ctaid_x.ll b/intrinsics/probes/clc_query_get_first_ctaid_x.ll index b866cfd1cc..0e93f1f5d6 100644 --- a/intrinsics/probes/clc_query_get_first_ctaid_x.ll +++ b/intrinsics/probes/clc_query_get_first_ctaid_x.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/clc_query_get_first_ctaid_y.ll b/intrinsics/probes/clc_query_get_first_ctaid_y.ll index 4d55dae5b6..b3f8e7f8fe 100644 --- a/intrinsics/probes/clc_query_get_first_ctaid_y.ll +++ b/intrinsics/probes/clc_query_get_first_ctaid_y.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/clc_query_get_first_ctaid_z.ll b/intrinsics/probes/clc_query_get_first_ctaid_z.ll index 6ffa8eafb2..c6e947d354 100644 --- a/intrinsics/probes/clc_query_get_first_ctaid_z.ll +++ b/intrinsics/probes/clc_query_get_first_ctaid_z.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/clc_query_is_canceled.ll b/intrinsics/probes/clc_query_is_canceled.ll index cf30a9587c..3ecf180bf2 100644 --- a/intrinsics/probes/clc_query_is_canceled.ll +++ b/intrinsics/probes/clc_query_is_canceled.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/clc_try_cancel.ll b/intrinsics/probes/clc_try_cancel.ll index 4ce17dbf0c..8067089590 100644 --- a/intrinsics/probes/clc_try_cancel.ll +++ b/intrinsics/probes/clc_try_cancel.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/clc_try_cancel_multicast.ll b/intrinsics/probes/clc_try_cancel_multicast.ll index e92a294d00..a7ff04b309 100644 --- a/intrinsics/probes/clc_try_cancel_multicast.ll +++ b/intrinsics/probes/clc_try_cancel_multicast.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/clock.lib_nvvm.ll b/intrinsics/probes/clock.lib_nvvm.ll index 177d34ed0d..1946829f7c 100644 --- a/intrinsics/probes/clock.lib_nvvm.ll +++ b/intrinsics/probes/clock.lib_nvvm.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/clock.llvm_nvptx.ll b/intrinsics/probes/clock.llvm_nvptx.ll index 499566a9ad..a7bc67ab2a 100644 --- a/intrinsics/probes/clock.llvm_nvptx.ll +++ b/intrinsics/probes/clock.llvm_nvptx.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/clock64.lib_nvvm.ll b/intrinsics/probes/clock64.lib_nvvm.ll index bb88ade113..2222c076ce 100644 --- a/intrinsics/probes/clock64.lib_nvvm.ll +++ b/intrinsics/probes/clock64.lib_nvvm.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/clock64.llvm_nvptx.ll b/intrinsics/probes/clock64.llvm_nvptx.ll index fffeafdb69..a63f9dfa49 100644 --- a/intrinsics/probes/clock64.llvm_nvptx.ll +++ b/intrinsics/probes/clock64.llvm_nvptx.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/cluster_block_count.ll b/intrinsics/probes/cluster_block_count.ll index 7fa9786202..0918a3a77c 100644 --- a/intrinsics/probes/cluster_block_count.ll +++ b/intrinsics/probes/cluster_block_count.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/cluster_block_idx_x.ll b/intrinsics/probes/cluster_block_idx_x.ll index 36992a97c5..1893f480a4 100644 --- a/intrinsics/probes/cluster_block_idx_x.ll +++ b/intrinsics/probes/cluster_block_idx_x.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/cluster_block_idx_y.ll b/intrinsics/probes/cluster_block_idx_y.ll index 1441b3297a..0c92b08241 100644 --- a/intrinsics/probes/cluster_block_idx_y.ll +++ b/intrinsics/probes/cluster_block_idx_y.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/cluster_block_idx_z.ll b/intrinsics/probes/cluster_block_idx_z.ll index c34998af37..a325631389 100644 --- a/intrinsics/probes/cluster_block_idx_z.ll +++ b/intrinsics/probes/cluster_block_idx_z.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/cluster_block_rank.ll b/intrinsics/probes/cluster_block_rank.ll index 357da071c5..0715a84acd 100644 --- a/intrinsics/probes/cluster_block_rank.ll +++ b/intrinsics/probes/cluster_block_rank.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/cluster_dim_x.ll b/intrinsics/probes/cluster_dim_x.ll index 4ccc4e8abb..ae94992288 100644 --- a/intrinsics/probes/cluster_dim_x.ll +++ b/intrinsics/probes/cluster_dim_x.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/cluster_dim_y.ll b/intrinsics/probes/cluster_dim_y.ll index e633a7cfb4..da293b4aa4 100644 --- a/intrinsics/probes/cluster_dim_y.ll +++ b/intrinsics/probes/cluster_dim_y.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/cluster_dim_z.ll b/intrinsics/probes/cluster_dim_z.ll index 809ee7eb6c..3af1850756 100644 --- a/intrinsics/probes/cluster_dim_z.ll +++ b/intrinsics/probes/cluster_dim_z.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/cluster_grid_dim_x.ll b/intrinsics/probes/cluster_grid_dim_x.ll index 53cfeff799..b1a9c514e7 100644 --- a/intrinsics/probes/cluster_grid_dim_x.ll +++ b/intrinsics/probes/cluster_grid_dim_x.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/cluster_grid_dim_y.ll b/intrinsics/probes/cluster_grid_dim_y.ll index 6755f8f47e..9dd4ffd524 100644 --- a/intrinsics/probes/cluster_grid_dim_y.ll +++ b/intrinsics/probes/cluster_grid_dim_y.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/cluster_grid_dim_z.ll b/intrinsics/probes/cluster_grid_dim_z.ll index ae58df1f39..094fdf43c3 100644 --- a/intrinsics/probes/cluster_grid_dim_z.ll +++ b/intrinsics/probes/cluster_grid_dim_z.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/cluster_idx_x.ll b/intrinsics/probes/cluster_idx_x.ll index 9d41b9f15d..ca34ed5f5b 100644 --- a/intrinsics/probes/cluster_idx_x.ll +++ b/intrinsics/probes/cluster_idx_x.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/cluster_idx_y.ll b/intrinsics/probes/cluster_idx_y.ll index 17e5143056..a895328be1 100644 --- a/intrinsics/probes/cluster_idx_y.ll +++ b/intrinsics/probes/cluster_idx_y.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/cluster_idx_z.ll b/intrinsics/probes/cluster_idx_z.ll index 76bbb52f53..40df7b06d1 100644 --- a/intrinsics/probes/cluster_idx_z.ll +++ b/intrinsics/probes/cluster_idx_z.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/cos_approx_f32.ll b/intrinsics/probes/cos_approx_f32.ll index b4acb50e44..bd39012aaa 100644 --- a/intrinsics/probes/cos_approx_f32.ll +++ b/intrinsics/probes/cos_approx_f32.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/cos_approx_ftz_f32.ll b/intrinsics/probes/cos_approx_ftz_f32.ll index d1e33b10d8..426a8129a1 100644 --- a/intrinsics/probes/cos_approx_ftz_f32.ll +++ b/intrinsics/probes/cos_approx_ftz_f32.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/cp_async_bulk_commit_group.ll b/intrinsics/probes/cp_async_bulk_commit_group.ll index 2df4a65bff..e51621b4c6 100644 --- a/intrinsics/probes/cp_async_bulk_commit_group.ll +++ b/intrinsics/probes/cp_async_bulk_commit_group.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/cp_async_bulk_prefetch_tensor_1d_l2.ll b/intrinsics/probes/cp_async_bulk_prefetch_tensor_1d_l2.ll index 547f5a879b..6e73932fac 100644 --- a/intrinsics/probes/cp_async_bulk_prefetch_tensor_1d_l2.ll +++ b/intrinsics/probes/cp_async_bulk_prefetch_tensor_1d_l2.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/cp_async_bulk_prefetch_tensor_1d_l2_cache_hint.ll b/intrinsics/probes/cp_async_bulk_prefetch_tensor_1d_l2_cache_hint.ll index 3fa21744a4..8c8bed948b 100644 --- a/intrinsics/probes/cp_async_bulk_prefetch_tensor_1d_l2_cache_hint.ll +++ b/intrinsics/probes/cp_async_bulk_prefetch_tensor_1d_l2_cache_hint.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/cp_async_bulk_prefetch_tensor_2d_l2.ll b/intrinsics/probes/cp_async_bulk_prefetch_tensor_2d_l2.ll index 5ec6ad2d1a..7b824af059 100644 --- a/intrinsics/probes/cp_async_bulk_prefetch_tensor_2d_l2.ll +++ b/intrinsics/probes/cp_async_bulk_prefetch_tensor_2d_l2.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/cp_async_bulk_prefetch_tensor_2d_l2_cache_hint.ll b/intrinsics/probes/cp_async_bulk_prefetch_tensor_2d_l2_cache_hint.ll index 4ca8b5a33f..5ed38ff78f 100644 --- a/intrinsics/probes/cp_async_bulk_prefetch_tensor_2d_l2_cache_hint.ll +++ b/intrinsics/probes/cp_async_bulk_prefetch_tensor_2d_l2_cache_hint.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/cp_async_bulk_prefetch_tensor_3d_l2.ll b/intrinsics/probes/cp_async_bulk_prefetch_tensor_3d_l2.ll index 38fe9d7db9..218684a074 100644 --- a/intrinsics/probes/cp_async_bulk_prefetch_tensor_3d_l2.ll +++ b/intrinsics/probes/cp_async_bulk_prefetch_tensor_3d_l2.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/cp_async_bulk_prefetch_tensor_3d_l2_cache_hint.ll b/intrinsics/probes/cp_async_bulk_prefetch_tensor_3d_l2_cache_hint.ll index 8972d4a078..908c4e547f 100644 --- a/intrinsics/probes/cp_async_bulk_prefetch_tensor_3d_l2_cache_hint.ll +++ b/intrinsics/probes/cp_async_bulk_prefetch_tensor_3d_l2_cache_hint.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/cp_async_bulk_prefetch_tensor_4d_l2.ll b/intrinsics/probes/cp_async_bulk_prefetch_tensor_4d_l2.ll index 3827bf4de5..0e5e99f3a5 100644 --- a/intrinsics/probes/cp_async_bulk_prefetch_tensor_4d_l2.ll +++ b/intrinsics/probes/cp_async_bulk_prefetch_tensor_4d_l2.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/cp_async_bulk_prefetch_tensor_4d_l2_cache_hint.ll b/intrinsics/probes/cp_async_bulk_prefetch_tensor_4d_l2_cache_hint.ll index 19473dcb79..f9960f5336 100644 --- a/intrinsics/probes/cp_async_bulk_prefetch_tensor_4d_l2_cache_hint.ll +++ b/intrinsics/probes/cp_async_bulk_prefetch_tensor_4d_l2_cache_hint.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/cp_async_bulk_prefetch_tensor_5d_l2.ll b/intrinsics/probes/cp_async_bulk_prefetch_tensor_5d_l2.ll index c8c0b0bdb5..83d25ac67d 100644 --- a/intrinsics/probes/cp_async_bulk_prefetch_tensor_5d_l2.ll +++ b/intrinsics/probes/cp_async_bulk_prefetch_tensor_5d_l2.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/cp_async_bulk_prefetch_tensor_5d_l2_cache_hint.ll b/intrinsics/probes/cp_async_bulk_prefetch_tensor_5d_l2_cache_hint.ll index b2fa4bfc99..37083dd972 100644 --- a/intrinsics/probes/cp_async_bulk_prefetch_tensor_5d_l2_cache_hint.ll +++ b/intrinsics/probes/cp_async_bulk_prefetch_tensor_5d_l2_cache_hint.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/cp_async_bulk_prefetch_tensor_gather4_2d_l2.ll b/intrinsics/probes/cp_async_bulk_prefetch_tensor_gather4_2d_l2.ll index 08970bfd3f..0d7f437001 100644 --- a/intrinsics/probes/cp_async_bulk_prefetch_tensor_gather4_2d_l2.ll +++ b/intrinsics/probes/cp_async_bulk_prefetch_tensor_gather4_2d_l2.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/cp_async_bulk_prefetch_tensor_gather4_2d_l2_cache_hint.ll b/intrinsics/probes/cp_async_bulk_prefetch_tensor_gather4_2d_l2_cache_hint.ll index f92d8f5f34..6b90b68421 100644 --- a/intrinsics/probes/cp_async_bulk_prefetch_tensor_gather4_2d_l2_cache_hint.ll +++ b/intrinsics/probes/cp_async_bulk_prefetch_tensor_gather4_2d_l2_cache_hint.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/cp_async_bulk_tensor_1d_g2s.ll b/intrinsics/probes/cp_async_bulk_tensor_1d_g2s.ll index 295f56a924..b89fb283b0 100644 --- a/intrinsics/probes/cp_async_bulk_tensor_1d_g2s.ll +++ b/intrinsics/probes/cp_async_bulk_tensor_1d_g2s.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/cp_async_bulk_tensor_1d_s2g.ll b/intrinsics/probes/cp_async_bulk_tensor_1d_s2g.ll index 7d276a285e..1b4f7ae66c 100644 --- a/intrinsics/probes/cp_async_bulk_tensor_1d_s2g.ll +++ b/intrinsics/probes/cp_async_bulk_tensor_1d_s2g.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/cp_async_bulk_tensor_2d_g2s.ll b/intrinsics/probes/cp_async_bulk_tensor_2d_g2s.ll index 3b1788186d..38f83cb9e0 100644 --- a/intrinsics/probes/cp_async_bulk_tensor_2d_g2s.ll +++ b/intrinsics/probes/cp_async_bulk_tensor_2d_g2s.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/cp_async_bulk_tensor_2d_g2s_multicast.ll b/intrinsics/probes/cp_async_bulk_tensor_2d_g2s_multicast.ll index dd31c18e60..75d4e18437 100644 --- a/intrinsics/probes/cp_async_bulk_tensor_2d_g2s_multicast.ll +++ b/intrinsics/probes/cp_async_bulk_tensor_2d_g2s_multicast.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/cp_async_bulk_tensor_2d_g2s_multicast_cg2.ll b/intrinsics/probes/cp_async_bulk_tensor_2d_g2s_multicast_cg2.ll index f27db3a413..170873cddc 100644 --- a/intrinsics/probes/cp_async_bulk_tensor_2d_g2s_multicast_cg2.ll +++ b/intrinsics/probes/cp_async_bulk_tensor_2d_g2s_multicast_cg2.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/cp_async_bulk_tensor_2d_s2g.ll b/intrinsics/probes/cp_async_bulk_tensor_2d_s2g.ll index 40f828605d..a32287198d 100644 --- a/intrinsics/probes/cp_async_bulk_tensor_2d_s2g.ll +++ b/intrinsics/probes/cp_async_bulk_tensor_2d_s2g.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/cp_async_bulk_tensor_3d_g2s.ll b/intrinsics/probes/cp_async_bulk_tensor_3d_g2s.ll index 3325ee5807..dd6a1fb2a1 100644 --- a/intrinsics/probes/cp_async_bulk_tensor_3d_g2s.ll +++ b/intrinsics/probes/cp_async_bulk_tensor_3d_g2s.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/cp_async_bulk_tensor_3d_s2g.ll b/intrinsics/probes/cp_async_bulk_tensor_3d_s2g.ll index c27b9f4570..461299f917 100644 --- a/intrinsics/probes/cp_async_bulk_tensor_3d_s2g.ll +++ b/intrinsics/probes/cp_async_bulk_tensor_3d_s2g.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/cp_async_bulk_tensor_4d_g2s.ll b/intrinsics/probes/cp_async_bulk_tensor_4d_g2s.ll index bf2b820075..709aa809db 100644 --- a/intrinsics/probes/cp_async_bulk_tensor_4d_g2s.ll +++ b/intrinsics/probes/cp_async_bulk_tensor_4d_g2s.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/cp_async_bulk_tensor_4d_s2g.ll b/intrinsics/probes/cp_async_bulk_tensor_4d_s2g.ll index 595e1e1cfd..8f991cdc61 100644 --- a/intrinsics/probes/cp_async_bulk_tensor_4d_s2g.ll +++ b/intrinsics/probes/cp_async_bulk_tensor_4d_s2g.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/cp_async_bulk_tensor_5d_g2s.ll b/intrinsics/probes/cp_async_bulk_tensor_5d_g2s.ll index 469e2eddad..8aedb0a905 100644 --- a/intrinsics/probes/cp_async_bulk_tensor_5d_g2s.ll +++ b/intrinsics/probes/cp_async_bulk_tensor_5d_g2s.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/cp_async_bulk_tensor_5d_s2g.ll b/intrinsics/probes/cp_async_bulk_tensor_5d_s2g.ll index ade9980928..74cc909f53 100644 --- a/intrinsics/probes/cp_async_bulk_tensor_5d_s2g.ll +++ b/intrinsics/probes/cp_async_bulk_tensor_5d_s2g.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/cp_async_bulk_tensor_reduce_add_im2col_3d.ll b/intrinsics/probes/cp_async_bulk_tensor_reduce_add_im2col_3d.ll index 268e4da5ae..cfbdd0b78d 100644 --- a/intrinsics/probes/cp_async_bulk_tensor_reduce_add_im2col_3d.ll +++ b/intrinsics/probes/cp_async_bulk_tensor_reduce_add_im2col_3d.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/cp_async_bulk_tensor_reduce_add_im2col_4d.ll b/intrinsics/probes/cp_async_bulk_tensor_reduce_add_im2col_4d.ll index ddeb857b75..21ae551cd0 100644 --- a/intrinsics/probes/cp_async_bulk_tensor_reduce_add_im2col_4d.ll +++ b/intrinsics/probes/cp_async_bulk_tensor_reduce_add_im2col_4d.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/cp_async_bulk_tensor_reduce_add_im2col_5d.ll b/intrinsics/probes/cp_async_bulk_tensor_reduce_add_im2col_5d.ll index 10fd831cce..01179667e0 100644 --- a/intrinsics/probes/cp_async_bulk_tensor_reduce_add_im2col_5d.ll +++ b/intrinsics/probes/cp_async_bulk_tensor_reduce_add_im2col_5d.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/cp_async_bulk_tensor_reduce_add_tile_1d.ll b/intrinsics/probes/cp_async_bulk_tensor_reduce_add_tile_1d.ll index c7f7489b18..2cc45beac6 100644 --- a/intrinsics/probes/cp_async_bulk_tensor_reduce_add_tile_1d.ll +++ b/intrinsics/probes/cp_async_bulk_tensor_reduce_add_tile_1d.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/cp_async_bulk_tensor_reduce_add_tile_2d.ll b/intrinsics/probes/cp_async_bulk_tensor_reduce_add_tile_2d.ll index 2cc9ef5a73..efecb433fd 100644 --- a/intrinsics/probes/cp_async_bulk_tensor_reduce_add_tile_2d.ll +++ b/intrinsics/probes/cp_async_bulk_tensor_reduce_add_tile_2d.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/cp_async_bulk_tensor_reduce_add_tile_3d.ll b/intrinsics/probes/cp_async_bulk_tensor_reduce_add_tile_3d.ll index 51dc3adafb..ed999965db 100644 --- a/intrinsics/probes/cp_async_bulk_tensor_reduce_add_tile_3d.ll +++ b/intrinsics/probes/cp_async_bulk_tensor_reduce_add_tile_3d.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/cp_async_bulk_tensor_reduce_add_tile_4d.ll b/intrinsics/probes/cp_async_bulk_tensor_reduce_add_tile_4d.ll index 7c7343706d..ce44e1cfbd 100644 --- a/intrinsics/probes/cp_async_bulk_tensor_reduce_add_tile_4d.ll +++ b/intrinsics/probes/cp_async_bulk_tensor_reduce_add_tile_4d.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/cp_async_bulk_tensor_reduce_add_tile_5d.ll b/intrinsics/probes/cp_async_bulk_tensor_reduce_add_tile_5d.ll index 4cc332d691..e7eb88f6d5 100644 --- a/intrinsics/probes/cp_async_bulk_tensor_reduce_add_tile_5d.ll +++ b/intrinsics/probes/cp_async_bulk_tensor_reduce_add_tile_5d.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/cp_async_bulk_tensor_reduce_and_im2col_3d.ll b/intrinsics/probes/cp_async_bulk_tensor_reduce_and_im2col_3d.ll index 2d159f9361..ea49a52ac2 100644 --- a/intrinsics/probes/cp_async_bulk_tensor_reduce_and_im2col_3d.ll +++ b/intrinsics/probes/cp_async_bulk_tensor_reduce_and_im2col_3d.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/cp_async_bulk_tensor_reduce_and_im2col_4d.ll b/intrinsics/probes/cp_async_bulk_tensor_reduce_and_im2col_4d.ll index 702429fc9e..85d1d755c2 100644 --- a/intrinsics/probes/cp_async_bulk_tensor_reduce_and_im2col_4d.ll +++ b/intrinsics/probes/cp_async_bulk_tensor_reduce_and_im2col_4d.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/cp_async_bulk_tensor_reduce_and_im2col_5d.ll b/intrinsics/probes/cp_async_bulk_tensor_reduce_and_im2col_5d.ll index ce29595365..9062d5e078 100644 --- a/intrinsics/probes/cp_async_bulk_tensor_reduce_and_im2col_5d.ll +++ b/intrinsics/probes/cp_async_bulk_tensor_reduce_and_im2col_5d.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/cp_async_bulk_tensor_reduce_and_tile_1d.ll b/intrinsics/probes/cp_async_bulk_tensor_reduce_and_tile_1d.ll index 9b1b3d999b..e355b46498 100644 --- a/intrinsics/probes/cp_async_bulk_tensor_reduce_and_tile_1d.ll +++ b/intrinsics/probes/cp_async_bulk_tensor_reduce_and_tile_1d.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/cp_async_bulk_tensor_reduce_and_tile_2d.ll b/intrinsics/probes/cp_async_bulk_tensor_reduce_and_tile_2d.ll index 440d752619..ef2d3f05b1 100644 --- a/intrinsics/probes/cp_async_bulk_tensor_reduce_and_tile_2d.ll +++ b/intrinsics/probes/cp_async_bulk_tensor_reduce_and_tile_2d.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/cp_async_bulk_tensor_reduce_and_tile_3d.ll b/intrinsics/probes/cp_async_bulk_tensor_reduce_and_tile_3d.ll index 838e0b9f30..f9a68ac3b8 100644 --- a/intrinsics/probes/cp_async_bulk_tensor_reduce_and_tile_3d.ll +++ b/intrinsics/probes/cp_async_bulk_tensor_reduce_and_tile_3d.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/cp_async_bulk_tensor_reduce_and_tile_4d.ll b/intrinsics/probes/cp_async_bulk_tensor_reduce_and_tile_4d.ll index 6914d93f55..873f6c6933 100644 --- a/intrinsics/probes/cp_async_bulk_tensor_reduce_and_tile_4d.ll +++ b/intrinsics/probes/cp_async_bulk_tensor_reduce_and_tile_4d.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/cp_async_bulk_tensor_reduce_and_tile_5d.ll b/intrinsics/probes/cp_async_bulk_tensor_reduce_and_tile_5d.ll index 56c7092e58..82af7b0ce1 100644 --- a/intrinsics/probes/cp_async_bulk_tensor_reduce_and_tile_5d.ll +++ b/intrinsics/probes/cp_async_bulk_tensor_reduce_and_tile_5d.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/cp_async_bulk_tensor_reduce_dec_im2col_3d.ll b/intrinsics/probes/cp_async_bulk_tensor_reduce_dec_im2col_3d.ll index 6d22f2c51a..3a16f73969 100644 --- a/intrinsics/probes/cp_async_bulk_tensor_reduce_dec_im2col_3d.ll +++ b/intrinsics/probes/cp_async_bulk_tensor_reduce_dec_im2col_3d.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/cp_async_bulk_tensor_reduce_dec_im2col_4d.ll b/intrinsics/probes/cp_async_bulk_tensor_reduce_dec_im2col_4d.ll index 4a4838fb6b..00bc258812 100644 --- a/intrinsics/probes/cp_async_bulk_tensor_reduce_dec_im2col_4d.ll +++ b/intrinsics/probes/cp_async_bulk_tensor_reduce_dec_im2col_4d.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/cp_async_bulk_tensor_reduce_dec_im2col_5d.ll b/intrinsics/probes/cp_async_bulk_tensor_reduce_dec_im2col_5d.ll index 8c4a8845fb..e4e9bf002e 100644 --- a/intrinsics/probes/cp_async_bulk_tensor_reduce_dec_im2col_5d.ll +++ b/intrinsics/probes/cp_async_bulk_tensor_reduce_dec_im2col_5d.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/cp_async_bulk_tensor_reduce_dec_tile_1d.ll b/intrinsics/probes/cp_async_bulk_tensor_reduce_dec_tile_1d.ll index 5f6b0c77d2..fba71578f1 100644 --- a/intrinsics/probes/cp_async_bulk_tensor_reduce_dec_tile_1d.ll +++ b/intrinsics/probes/cp_async_bulk_tensor_reduce_dec_tile_1d.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/cp_async_bulk_tensor_reduce_dec_tile_2d.ll b/intrinsics/probes/cp_async_bulk_tensor_reduce_dec_tile_2d.ll index a379abd999..f620c7719d 100644 --- a/intrinsics/probes/cp_async_bulk_tensor_reduce_dec_tile_2d.ll +++ b/intrinsics/probes/cp_async_bulk_tensor_reduce_dec_tile_2d.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/cp_async_bulk_tensor_reduce_dec_tile_3d.ll b/intrinsics/probes/cp_async_bulk_tensor_reduce_dec_tile_3d.ll index 33998bee99..c65d256e6c 100644 --- a/intrinsics/probes/cp_async_bulk_tensor_reduce_dec_tile_3d.ll +++ b/intrinsics/probes/cp_async_bulk_tensor_reduce_dec_tile_3d.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/cp_async_bulk_tensor_reduce_dec_tile_4d.ll b/intrinsics/probes/cp_async_bulk_tensor_reduce_dec_tile_4d.ll index 18fc842d51..e857a62c8e 100644 --- a/intrinsics/probes/cp_async_bulk_tensor_reduce_dec_tile_4d.ll +++ b/intrinsics/probes/cp_async_bulk_tensor_reduce_dec_tile_4d.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/cp_async_bulk_tensor_reduce_dec_tile_5d.ll b/intrinsics/probes/cp_async_bulk_tensor_reduce_dec_tile_5d.ll index b21cc711d8..1a7d199d36 100644 --- a/intrinsics/probes/cp_async_bulk_tensor_reduce_dec_tile_5d.ll +++ b/intrinsics/probes/cp_async_bulk_tensor_reduce_dec_tile_5d.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/cp_async_bulk_tensor_reduce_inc_im2col_3d.ll b/intrinsics/probes/cp_async_bulk_tensor_reduce_inc_im2col_3d.ll index 6335462cb5..dc364ccc86 100644 --- a/intrinsics/probes/cp_async_bulk_tensor_reduce_inc_im2col_3d.ll +++ b/intrinsics/probes/cp_async_bulk_tensor_reduce_inc_im2col_3d.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/cp_async_bulk_tensor_reduce_inc_im2col_4d.ll b/intrinsics/probes/cp_async_bulk_tensor_reduce_inc_im2col_4d.ll index c9943b8ab2..26a7f8e213 100644 --- a/intrinsics/probes/cp_async_bulk_tensor_reduce_inc_im2col_4d.ll +++ b/intrinsics/probes/cp_async_bulk_tensor_reduce_inc_im2col_4d.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/cp_async_bulk_tensor_reduce_inc_im2col_5d.ll b/intrinsics/probes/cp_async_bulk_tensor_reduce_inc_im2col_5d.ll index 6a9230f79c..533f05960b 100644 --- a/intrinsics/probes/cp_async_bulk_tensor_reduce_inc_im2col_5d.ll +++ b/intrinsics/probes/cp_async_bulk_tensor_reduce_inc_im2col_5d.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/cp_async_bulk_tensor_reduce_inc_tile_1d.ll b/intrinsics/probes/cp_async_bulk_tensor_reduce_inc_tile_1d.ll index b0fd045edd..a6f11e09d9 100644 --- a/intrinsics/probes/cp_async_bulk_tensor_reduce_inc_tile_1d.ll +++ b/intrinsics/probes/cp_async_bulk_tensor_reduce_inc_tile_1d.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/cp_async_bulk_tensor_reduce_inc_tile_2d.ll b/intrinsics/probes/cp_async_bulk_tensor_reduce_inc_tile_2d.ll index 2ab7eff10e..e6be002a82 100644 --- a/intrinsics/probes/cp_async_bulk_tensor_reduce_inc_tile_2d.ll +++ b/intrinsics/probes/cp_async_bulk_tensor_reduce_inc_tile_2d.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/cp_async_bulk_tensor_reduce_inc_tile_3d.ll b/intrinsics/probes/cp_async_bulk_tensor_reduce_inc_tile_3d.ll index b6d006edae..7061a86379 100644 --- a/intrinsics/probes/cp_async_bulk_tensor_reduce_inc_tile_3d.ll +++ b/intrinsics/probes/cp_async_bulk_tensor_reduce_inc_tile_3d.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/cp_async_bulk_tensor_reduce_inc_tile_4d.ll b/intrinsics/probes/cp_async_bulk_tensor_reduce_inc_tile_4d.ll index ae5e414ae3..6fb03059d2 100644 --- a/intrinsics/probes/cp_async_bulk_tensor_reduce_inc_tile_4d.ll +++ b/intrinsics/probes/cp_async_bulk_tensor_reduce_inc_tile_4d.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/cp_async_bulk_tensor_reduce_inc_tile_5d.ll b/intrinsics/probes/cp_async_bulk_tensor_reduce_inc_tile_5d.ll index 2ee58152a1..e77f084536 100644 --- a/intrinsics/probes/cp_async_bulk_tensor_reduce_inc_tile_5d.ll +++ b/intrinsics/probes/cp_async_bulk_tensor_reduce_inc_tile_5d.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/cp_async_bulk_tensor_reduce_max_im2col_3d.ll b/intrinsics/probes/cp_async_bulk_tensor_reduce_max_im2col_3d.ll index d38b7cf1dc..ec89d6feb6 100644 --- a/intrinsics/probes/cp_async_bulk_tensor_reduce_max_im2col_3d.ll +++ b/intrinsics/probes/cp_async_bulk_tensor_reduce_max_im2col_3d.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/cp_async_bulk_tensor_reduce_max_im2col_4d.ll b/intrinsics/probes/cp_async_bulk_tensor_reduce_max_im2col_4d.ll index 0a9c8564a1..9162aedf63 100644 --- a/intrinsics/probes/cp_async_bulk_tensor_reduce_max_im2col_4d.ll +++ b/intrinsics/probes/cp_async_bulk_tensor_reduce_max_im2col_4d.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/cp_async_bulk_tensor_reduce_max_im2col_5d.ll b/intrinsics/probes/cp_async_bulk_tensor_reduce_max_im2col_5d.ll index 33b3e710d1..37a989c8e0 100644 --- a/intrinsics/probes/cp_async_bulk_tensor_reduce_max_im2col_5d.ll +++ b/intrinsics/probes/cp_async_bulk_tensor_reduce_max_im2col_5d.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/cp_async_bulk_tensor_reduce_max_tile_1d.ll b/intrinsics/probes/cp_async_bulk_tensor_reduce_max_tile_1d.ll index 2f3576fb5d..b62e873bf1 100644 --- a/intrinsics/probes/cp_async_bulk_tensor_reduce_max_tile_1d.ll +++ b/intrinsics/probes/cp_async_bulk_tensor_reduce_max_tile_1d.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/cp_async_bulk_tensor_reduce_max_tile_2d.ll b/intrinsics/probes/cp_async_bulk_tensor_reduce_max_tile_2d.ll index c05cd1739e..bc6dcbd9e8 100644 --- a/intrinsics/probes/cp_async_bulk_tensor_reduce_max_tile_2d.ll +++ b/intrinsics/probes/cp_async_bulk_tensor_reduce_max_tile_2d.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/cp_async_bulk_tensor_reduce_max_tile_3d.ll b/intrinsics/probes/cp_async_bulk_tensor_reduce_max_tile_3d.ll index 1b661b2ea4..9eb2207465 100644 --- a/intrinsics/probes/cp_async_bulk_tensor_reduce_max_tile_3d.ll +++ b/intrinsics/probes/cp_async_bulk_tensor_reduce_max_tile_3d.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/cp_async_bulk_tensor_reduce_max_tile_4d.ll b/intrinsics/probes/cp_async_bulk_tensor_reduce_max_tile_4d.ll index a15666d0a4..42bcce286a 100644 --- a/intrinsics/probes/cp_async_bulk_tensor_reduce_max_tile_4d.ll +++ b/intrinsics/probes/cp_async_bulk_tensor_reduce_max_tile_4d.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/cp_async_bulk_tensor_reduce_max_tile_5d.ll b/intrinsics/probes/cp_async_bulk_tensor_reduce_max_tile_5d.ll index ec55113d92..b58577c08b 100644 --- a/intrinsics/probes/cp_async_bulk_tensor_reduce_max_tile_5d.ll +++ b/intrinsics/probes/cp_async_bulk_tensor_reduce_max_tile_5d.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/cp_async_bulk_tensor_reduce_min_im2col_3d.ll b/intrinsics/probes/cp_async_bulk_tensor_reduce_min_im2col_3d.ll index 6287d08447..c42f9b24fc 100644 --- a/intrinsics/probes/cp_async_bulk_tensor_reduce_min_im2col_3d.ll +++ b/intrinsics/probes/cp_async_bulk_tensor_reduce_min_im2col_3d.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/cp_async_bulk_tensor_reduce_min_im2col_4d.ll b/intrinsics/probes/cp_async_bulk_tensor_reduce_min_im2col_4d.ll index 0f4640bb52..a047862207 100644 --- a/intrinsics/probes/cp_async_bulk_tensor_reduce_min_im2col_4d.ll +++ b/intrinsics/probes/cp_async_bulk_tensor_reduce_min_im2col_4d.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/cp_async_bulk_tensor_reduce_min_im2col_5d.ll b/intrinsics/probes/cp_async_bulk_tensor_reduce_min_im2col_5d.ll index 4bdb639a65..d6b20da10a 100644 --- a/intrinsics/probes/cp_async_bulk_tensor_reduce_min_im2col_5d.ll +++ b/intrinsics/probes/cp_async_bulk_tensor_reduce_min_im2col_5d.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/cp_async_bulk_tensor_reduce_min_tile_1d.ll b/intrinsics/probes/cp_async_bulk_tensor_reduce_min_tile_1d.ll index cddb0bb15e..3537ec7fc4 100644 --- a/intrinsics/probes/cp_async_bulk_tensor_reduce_min_tile_1d.ll +++ b/intrinsics/probes/cp_async_bulk_tensor_reduce_min_tile_1d.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/cp_async_bulk_tensor_reduce_min_tile_2d.ll b/intrinsics/probes/cp_async_bulk_tensor_reduce_min_tile_2d.ll index 3c711d04ab..7243da6ecf 100644 --- a/intrinsics/probes/cp_async_bulk_tensor_reduce_min_tile_2d.ll +++ b/intrinsics/probes/cp_async_bulk_tensor_reduce_min_tile_2d.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/cp_async_bulk_tensor_reduce_min_tile_3d.ll b/intrinsics/probes/cp_async_bulk_tensor_reduce_min_tile_3d.ll index 54f1e492a2..8f5af4c565 100644 --- a/intrinsics/probes/cp_async_bulk_tensor_reduce_min_tile_3d.ll +++ b/intrinsics/probes/cp_async_bulk_tensor_reduce_min_tile_3d.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/cp_async_bulk_tensor_reduce_min_tile_4d.ll b/intrinsics/probes/cp_async_bulk_tensor_reduce_min_tile_4d.ll index ccd2c74557..5e3a33ea78 100644 --- a/intrinsics/probes/cp_async_bulk_tensor_reduce_min_tile_4d.ll +++ b/intrinsics/probes/cp_async_bulk_tensor_reduce_min_tile_4d.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/cp_async_bulk_tensor_reduce_min_tile_5d.ll b/intrinsics/probes/cp_async_bulk_tensor_reduce_min_tile_5d.ll index b104c0f6c1..e7f0b1184c 100644 --- a/intrinsics/probes/cp_async_bulk_tensor_reduce_min_tile_5d.ll +++ b/intrinsics/probes/cp_async_bulk_tensor_reduce_min_tile_5d.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/cp_async_bulk_tensor_reduce_or_im2col_3d.ll b/intrinsics/probes/cp_async_bulk_tensor_reduce_or_im2col_3d.ll index 5d83df9abb..a90f5f2a85 100644 --- a/intrinsics/probes/cp_async_bulk_tensor_reduce_or_im2col_3d.ll +++ b/intrinsics/probes/cp_async_bulk_tensor_reduce_or_im2col_3d.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/cp_async_bulk_tensor_reduce_or_im2col_4d.ll b/intrinsics/probes/cp_async_bulk_tensor_reduce_or_im2col_4d.ll index 7670347b0e..802811a3d2 100644 --- a/intrinsics/probes/cp_async_bulk_tensor_reduce_or_im2col_4d.ll +++ b/intrinsics/probes/cp_async_bulk_tensor_reduce_or_im2col_4d.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/cp_async_bulk_tensor_reduce_or_im2col_5d.ll b/intrinsics/probes/cp_async_bulk_tensor_reduce_or_im2col_5d.ll index de1c1b78de..c27c437be2 100644 --- a/intrinsics/probes/cp_async_bulk_tensor_reduce_or_im2col_5d.ll +++ b/intrinsics/probes/cp_async_bulk_tensor_reduce_or_im2col_5d.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/cp_async_bulk_tensor_reduce_or_tile_1d.ll b/intrinsics/probes/cp_async_bulk_tensor_reduce_or_tile_1d.ll index 4d124af7f1..080ab62990 100644 --- a/intrinsics/probes/cp_async_bulk_tensor_reduce_or_tile_1d.ll +++ b/intrinsics/probes/cp_async_bulk_tensor_reduce_or_tile_1d.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/cp_async_bulk_tensor_reduce_or_tile_2d.ll b/intrinsics/probes/cp_async_bulk_tensor_reduce_or_tile_2d.ll index 3e415f190c..d99c0588b4 100644 --- a/intrinsics/probes/cp_async_bulk_tensor_reduce_or_tile_2d.ll +++ b/intrinsics/probes/cp_async_bulk_tensor_reduce_or_tile_2d.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/cp_async_bulk_tensor_reduce_or_tile_3d.ll b/intrinsics/probes/cp_async_bulk_tensor_reduce_or_tile_3d.ll index 28565ac2e8..20de43fcd5 100644 --- a/intrinsics/probes/cp_async_bulk_tensor_reduce_or_tile_3d.ll +++ b/intrinsics/probes/cp_async_bulk_tensor_reduce_or_tile_3d.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/cp_async_bulk_tensor_reduce_or_tile_4d.ll b/intrinsics/probes/cp_async_bulk_tensor_reduce_or_tile_4d.ll index d18bc049ce..22e5506705 100644 --- a/intrinsics/probes/cp_async_bulk_tensor_reduce_or_tile_4d.ll +++ b/intrinsics/probes/cp_async_bulk_tensor_reduce_or_tile_4d.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/cp_async_bulk_tensor_reduce_or_tile_5d.ll b/intrinsics/probes/cp_async_bulk_tensor_reduce_or_tile_5d.ll index 224264fe43..29fa485bdd 100644 --- a/intrinsics/probes/cp_async_bulk_tensor_reduce_or_tile_5d.ll +++ b/intrinsics/probes/cp_async_bulk_tensor_reduce_or_tile_5d.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/cp_async_bulk_tensor_reduce_xor_im2col_3d.ll b/intrinsics/probes/cp_async_bulk_tensor_reduce_xor_im2col_3d.ll index f809982860..bfe1b7cf59 100644 --- a/intrinsics/probes/cp_async_bulk_tensor_reduce_xor_im2col_3d.ll +++ b/intrinsics/probes/cp_async_bulk_tensor_reduce_xor_im2col_3d.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/cp_async_bulk_tensor_reduce_xor_im2col_4d.ll b/intrinsics/probes/cp_async_bulk_tensor_reduce_xor_im2col_4d.ll index 95c35a3dff..4030f56b77 100644 --- a/intrinsics/probes/cp_async_bulk_tensor_reduce_xor_im2col_4d.ll +++ b/intrinsics/probes/cp_async_bulk_tensor_reduce_xor_im2col_4d.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/cp_async_bulk_tensor_reduce_xor_im2col_5d.ll b/intrinsics/probes/cp_async_bulk_tensor_reduce_xor_im2col_5d.ll index 0d1120601d..6866b9f5d4 100644 --- a/intrinsics/probes/cp_async_bulk_tensor_reduce_xor_im2col_5d.ll +++ b/intrinsics/probes/cp_async_bulk_tensor_reduce_xor_im2col_5d.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/cp_async_bulk_tensor_reduce_xor_tile_1d.ll b/intrinsics/probes/cp_async_bulk_tensor_reduce_xor_tile_1d.ll index 1e616b06a2..3563d16428 100644 --- a/intrinsics/probes/cp_async_bulk_tensor_reduce_xor_tile_1d.ll +++ b/intrinsics/probes/cp_async_bulk_tensor_reduce_xor_tile_1d.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/cp_async_bulk_tensor_reduce_xor_tile_2d.ll b/intrinsics/probes/cp_async_bulk_tensor_reduce_xor_tile_2d.ll index 9153547a3e..2dc1020be2 100644 --- a/intrinsics/probes/cp_async_bulk_tensor_reduce_xor_tile_2d.ll +++ b/intrinsics/probes/cp_async_bulk_tensor_reduce_xor_tile_2d.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/cp_async_bulk_tensor_reduce_xor_tile_3d.ll b/intrinsics/probes/cp_async_bulk_tensor_reduce_xor_tile_3d.ll index e6176171e2..3dcb85d010 100644 --- a/intrinsics/probes/cp_async_bulk_tensor_reduce_xor_tile_3d.ll +++ b/intrinsics/probes/cp_async_bulk_tensor_reduce_xor_tile_3d.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/cp_async_bulk_tensor_reduce_xor_tile_4d.ll b/intrinsics/probes/cp_async_bulk_tensor_reduce_xor_tile_4d.ll index 15e96ad925..938444e606 100644 --- a/intrinsics/probes/cp_async_bulk_tensor_reduce_xor_tile_4d.ll +++ b/intrinsics/probes/cp_async_bulk_tensor_reduce_xor_tile_4d.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/cp_async_bulk_tensor_reduce_xor_tile_5d.ll b/intrinsics/probes/cp_async_bulk_tensor_reduce_xor_tile_5d.ll index e8adcf3e12..1b6a8dbd87 100644 --- a/intrinsics/probes/cp_async_bulk_tensor_reduce_xor_tile_5d.ll +++ b/intrinsics/probes/cp_async_bulk_tensor_reduce_xor_tile_5d.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/cp_async_bulk_wait_group.ll b/intrinsics/probes/cp_async_bulk_wait_group.ll index 8006304539..44678910ad 100644 --- a/intrinsics/probes/cp_async_bulk_wait_group.ll +++ b/intrinsics/probes/cp_async_bulk_wait_group.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/cp_async_bulk_wait_group_read.ll b/intrinsics/probes/cp_async_bulk_wait_group_read.ll index 326856ad05..d2ba023126 100644 --- a/intrinsics/probes/cp_async_bulk_wait_group_read.ll +++ b/intrinsics/probes/cp_async_bulk_wait_group_read.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/cp_async_ca_16.ll b/intrinsics/probes/cp_async_ca_16.ll index f9fbc8df3d..33c4277da3 100644 --- a/intrinsics/probes/cp_async_ca_16.ll +++ b/intrinsics/probes/cp_async_ca_16.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/cp_async_ca_4.ll b/intrinsics/probes/cp_async_ca_4.ll index 50a6c12190..ffb4ee84eb 100644 --- a/intrinsics/probes/cp_async_ca_4.ll +++ b/intrinsics/probes/cp_async_ca_4.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/cp_async_ca_8.ll b/intrinsics/probes/cp_async_ca_8.ll index f7eb7f71ee..eb907c33b5 100644 --- a/intrinsics/probes/cp_async_ca_8.ll +++ b/intrinsics/probes/cp_async_ca_8.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/cp_async_ca_zfill_16.ll b/intrinsics/probes/cp_async_ca_zfill_16.ll index 51f91aabad..cfbf37eb40 100644 --- a/intrinsics/probes/cp_async_ca_zfill_16.ll +++ b/intrinsics/probes/cp_async_ca_zfill_16.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/cp_async_ca_zfill_4.ll b/intrinsics/probes/cp_async_ca_zfill_4.ll index 3840088a72..6ece2ba07e 100644 --- a/intrinsics/probes/cp_async_ca_zfill_4.ll +++ b/intrinsics/probes/cp_async_ca_zfill_4.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/cp_async_ca_zfill_8.ll b/intrinsics/probes/cp_async_ca_zfill_8.ll index fab62cc2bf..ef9295c0de 100644 --- a/intrinsics/probes/cp_async_ca_zfill_8.ll +++ b/intrinsics/probes/cp_async_ca_zfill_8.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/cp_async_cg_16.ll b/intrinsics/probes/cp_async_cg_16.ll index 0c8a571adb..c573c28e21 100644 --- a/intrinsics/probes/cp_async_cg_16.ll +++ b/intrinsics/probes/cp_async_cg_16.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/cp_async_cg_zfill_16.ll b/intrinsics/probes/cp_async_cg_zfill_16.ll index a4d0a810fe..5bee2452aa 100644 --- a/intrinsics/probes/cp_async_cg_zfill_16.ll +++ b/intrinsics/probes/cp_async_cg_zfill_16.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/cp_async_commit_group.ll b/intrinsics/probes/cp_async_commit_group.ll index b3b19cbb79..a4a7c5a28a 100644 --- a/intrinsics/probes/cp_async_commit_group.ll +++ b/intrinsics/probes/cp_async_commit_group.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/cp_async_mbarrier_arrive.ll b/intrinsics/probes/cp_async_mbarrier_arrive.ll index 265b852723..cd64f7449d 100644 --- a/intrinsics/probes/cp_async_mbarrier_arrive.ll +++ b/intrinsics/probes/cp_async_mbarrier_arrive.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/cp_async_mbarrier_arrive_noinc.ll b/intrinsics/probes/cp_async_mbarrier_arrive_noinc.ll index 234c4f02bf..4570a99266 100644 --- a/intrinsics/probes/cp_async_mbarrier_arrive_noinc.ll +++ b/intrinsics/probes/cp_async_mbarrier_arrive_noinc.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/cp_async_mbarrier_arrive_noinc_shared.ll b/intrinsics/probes/cp_async_mbarrier_arrive_noinc_shared.ll index 085e6b0c82..5c4b07eec3 100644 --- a/intrinsics/probes/cp_async_mbarrier_arrive_noinc_shared.ll +++ b/intrinsics/probes/cp_async_mbarrier_arrive_noinc_shared.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/cp_async_mbarrier_arrive_shared.ll b/intrinsics/probes/cp_async_mbarrier_arrive_shared.ll index 4df9ad56fe..9c2e24e432 100644 --- a/intrinsics/probes/cp_async_mbarrier_arrive_shared.ll +++ b/intrinsics/probes/cp_async_mbarrier_arrive_shared.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/cp_async_wait_all.ll b/intrinsics/probes/cp_async_wait_all.ll index ef4a3ca299..893163b749 100644 --- a/intrinsics/probes/cp_async_wait_all.ll +++ b/intrinsics/probes/cp_async_wait_all.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/cp_async_wait_group.ll b/intrinsics/probes/cp_async_wait_group.ll index 19d7b7a6f6..4d44fa5420 100644 --- a/intrinsics/probes/cp_async_wait_group.ll +++ b/intrinsics/probes/cp_async_wait_group.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/cvt_f16x2_f32.ll b/intrinsics/probes/cvt_f16x2_f32.ll index 3ac1216a68..cb43ba80f9 100644 --- a/intrinsics/probes/cvt_f16x2_f32.ll +++ b/intrinsics/probes/cvt_f16x2_f32.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/cvt_f32x2_bf16x2.ll b/intrinsics/probes/cvt_f32x2_bf16x2.ll index d2595ebb10..d12886d612 100644 --- a/intrinsics/probes/cvt_f32x2_bf16x2.ll +++ b/intrinsics/probes/cvt_f32x2_bf16x2.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/cvt_rn_f16x2_e4m3x2.ll b/intrinsics/probes/cvt_rn_f16x2_e4m3x2.ll index 30e9cd4d5c..971480e3be 100644 --- a/intrinsics/probes/cvt_rn_f16x2_e4m3x2.ll +++ b/intrinsics/probes/cvt_rn_f16x2_e4m3x2.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/cvt_rn_f16x2_e5m2x2.ll b/intrinsics/probes/cvt_rn_f16x2_e5m2x2.ll index 85b3c267cf..3811b62c6d 100644 --- a/intrinsics/probes/cvt_rn_f16x2_e5m2x2.ll +++ b/intrinsics/probes/cvt_rn_f16x2_e5m2x2.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/cvt_rn_relu_bf16x2_f32.ll b/intrinsics/probes/cvt_rn_relu_bf16x2_f32.ll index f5fee83e19..3c30da1314 100644 --- a/intrinsics/probes/cvt_rn_relu_bf16x2_f32.ll +++ b/intrinsics/probes/cvt_rn_relu_bf16x2_f32.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/cvt_rn_relu_f16x2_e4m3x2.ll b/intrinsics/probes/cvt_rn_relu_f16x2_e4m3x2.ll index 0f77f7fd20..dbb6dfade5 100644 --- a/intrinsics/probes/cvt_rn_relu_f16x2_e4m3x2.ll +++ b/intrinsics/probes/cvt_rn_relu_f16x2_e4m3x2.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/cvt_rn_relu_f16x2_e5m2x2.ll b/intrinsics/probes/cvt_rn_relu_f16x2_e5m2x2.ll index 4ca090abc0..2b27eddb92 100644 --- a/intrinsics/probes/cvt_rn_relu_f16x2_e5m2x2.ll +++ b/intrinsics/probes/cvt_rn_relu_f16x2_e5m2x2.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/cvt_rn_relu_f16x2_f32.ll b/intrinsics/probes/cvt_rn_relu_f16x2_f32.ll index cf8e3c06e1..2551600b3f 100644 --- a/intrinsics/probes/cvt_rn_relu_f16x2_f32.ll +++ b/intrinsics/probes/cvt_rn_relu_f16x2_f32.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/cvt_rn_relu_satfinite_tf32_f32.ll b/intrinsics/probes/cvt_rn_relu_satfinite_tf32_f32.ll index 51b090ca0c..81ecb7a474 100644 --- a/intrinsics/probes/cvt_rn_relu_satfinite_tf32_f32.ll +++ b/intrinsics/probes/cvt_rn_relu_satfinite_tf32_f32.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/cvt_rn_relu_tf32_f32.ll b/intrinsics/probes/cvt_rn_relu_tf32_f32.ll index 7391f44102..916ef2dc6a 100644 --- a/intrinsics/probes/cvt_rn_relu_tf32_f32.ll +++ b/intrinsics/probes/cvt_rn_relu_tf32_f32.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/cvt_rn_satfinite_e4m3x2_f16x2.ll b/intrinsics/probes/cvt_rn_satfinite_e4m3x2_f16x2.ll index 437d265932..30a1af09d1 100644 --- a/intrinsics/probes/cvt_rn_satfinite_e4m3x2_f16x2.ll +++ b/intrinsics/probes/cvt_rn_satfinite_e4m3x2_f16x2.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/cvt_rn_satfinite_e4m3x2_f32.ll b/intrinsics/probes/cvt_rn_satfinite_e4m3x2_f32.ll index 1c2a325434..2966dc6713 100644 --- a/intrinsics/probes/cvt_rn_satfinite_e4m3x2_f32.ll +++ b/intrinsics/probes/cvt_rn_satfinite_e4m3x2_f32.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/cvt_rn_satfinite_e5m2x2_f16x2.ll b/intrinsics/probes/cvt_rn_satfinite_e5m2x2_f16x2.ll index 5f3907156b..f9a239e797 100644 --- a/intrinsics/probes/cvt_rn_satfinite_e5m2x2_f16x2.ll +++ b/intrinsics/probes/cvt_rn_satfinite_e5m2x2_f16x2.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/cvt_rn_satfinite_e5m2x2_f32.ll b/intrinsics/probes/cvt_rn_satfinite_e5m2x2_f32.ll index e1b9673638..545d1378c4 100644 --- a/intrinsics/probes/cvt_rn_satfinite_e5m2x2_f32.ll +++ b/intrinsics/probes/cvt_rn_satfinite_e5m2x2_f32.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/cvt_rn_satfinite_relu_e4m3x2_f16x2.ll b/intrinsics/probes/cvt_rn_satfinite_relu_e4m3x2_f16x2.ll index bb508cbf14..dc53435152 100644 --- a/intrinsics/probes/cvt_rn_satfinite_relu_e4m3x2_f16x2.ll +++ b/intrinsics/probes/cvt_rn_satfinite_relu_e4m3x2_f16x2.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/cvt_rn_satfinite_relu_e4m3x2_f32.ll b/intrinsics/probes/cvt_rn_satfinite_relu_e4m3x2_f32.ll index 48c48e7548..f270dea37b 100644 --- a/intrinsics/probes/cvt_rn_satfinite_relu_e4m3x2_f32.ll +++ b/intrinsics/probes/cvt_rn_satfinite_relu_e4m3x2_f32.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/cvt_rn_satfinite_relu_e5m2x2_f16x2.ll b/intrinsics/probes/cvt_rn_satfinite_relu_e5m2x2_f16x2.ll index 560bd66535..66b7d5cf2f 100644 --- a/intrinsics/probes/cvt_rn_satfinite_relu_e5m2x2_f16x2.ll +++ b/intrinsics/probes/cvt_rn_satfinite_relu_e5m2x2_f16x2.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/cvt_rn_satfinite_relu_e5m2x2_f32.ll b/intrinsics/probes/cvt_rn_satfinite_relu_e5m2x2_f32.ll index 22c346ca66..b420c6360a 100644 --- a/intrinsics/probes/cvt_rn_satfinite_relu_e5m2x2_f32.ll +++ b/intrinsics/probes/cvt_rn_satfinite_relu_e5m2x2_f32.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/cvt_rn_satfinite_tf32_f32.ll b/intrinsics/probes/cvt_rn_satfinite_tf32_f32.ll index b414df0229..13b123ffe2 100644 --- a/intrinsics/probes/cvt_rn_satfinite_tf32_f32.ll +++ b/intrinsics/probes/cvt_rn_satfinite_tf32_f32.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/cvt_rn_tf32_f32.ll b/intrinsics/probes/cvt_rn_tf32_f32.ll index 9e685ed0e8..cdc31c19d0 100644 --- a/intrinsics/probes/cvt_rn_tf32_f32.ll +++ b/intrinsics/probes/cvt_rn_tf32_f32.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/cvt_rna_satfinite_tf32_f32.ll b/intrinsics/probes/cvt_rna_satfinite_tf32_f32.ll index 227e2cc4ed..13c9d6edb3 100644 --- a/intrinsics/probes/cvt_rna_satfinite_tf32_f32.ll +++ b/intrinsics/probes/cvt_rna_satfinite_tf32_f32.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/cvt_rna_tf32_f32.ll b/intrinsics/probes/cvt_rna_tf32_f32.ll index 4d703bcf74..28ee545777 100644 --- a/intrinsics/probes/cvt_rna_tf32_f32.ll +++ b/intrinsics/probes/cvt_rna_tf32_f32.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/cvt_rz_bf16x2_f32.ll b/intrinsics/probes/cvt_rz_bf16x2_f32.ll index cb8f53e0e7..16d8318ceb 100644 --- a/intrinsics/probes/cvt_rz_bf16x2_f32.ll +++ b/intrinsics/probes/cvt_rz_bf16x2_f32.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/cvt_rz_f16x2_f32.ll b/intrinsics/probes/cvt_rz_f16x2_f32.ll index c35a6f812b..d6774f16fb 100644 --- a/intrinsics/probes/cvt_rz_f16x2_f32.ll +++ b/intrinsics/probes/cvt_rz_f16x2_f32.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/cvt_rz_relu_satfinite_tf32_f32.ll b/intrinsics/probes/cvt_rz_relu_satfinite_tf32_f32.ll index fe8c1c85c2..2053dc6901 100644 --- a/intrinsics/probes/cvt_rz_relu_satfinite_tf32_f32.ll +++ b/intrinsics/probes/cvt_rz_relu_satfinite_tf32_f32.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/cvt_rz_relu_tf32_f32.ll b/intrinsics/probes/cvt_rz_relu_tf32_f32.ll index b7467d1085..318181fce4 100644 --- a/intrinsics/probes/cvt_rz_relu_tf32_f32.ll +++ b/intrinsics/probes/cvt_rz_relu_tf32_f32.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/cvt_rz_satfinite_tf32_f32.ll b/intrinsics/probes/cvt_rz_satfinite_tf32_f32.ll index cc5418a9f6..cfb9c5af9d 100644 --- a/intrinsics/probes/cvt_rz_satfinite_tf32_f32.ll +++ b/intrinsics/probes/cvt_rz_satfinite_tf32_f32.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/cvt_rz_tf32_f32.ll b/intrinsics/probes/cvt_rz_tf32_f32.ll index 2cace93148..17cfc54170 100644 --- a/intrinsics/probes/cvt_rz_tf32_f32.ll +++ b/intrinsics/probes/cvt_rz_tf32_f32.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/div_rm_f32.ll b/intrinsics/probes/div_rm_f32.ll index 1d42f08ddc..de336bb636 100644 --- a/intrinsics/probes/div_rm_f32.ll +++ b/intrinsics/probes/div_rm_f32.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/div_rm_f64.ll b/intrinsics/probes/div_rm_f64.ll index f6d131ef92..bb60e94386 100644 --- a/intrinsics/probes/div_rm_f64.ll +++ b/intrinsics/probes/div_rm_f64.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/div_rm_ftz_f32.ll b/intrinsics/probes/div_rm_ftz_f32.ll index 9ace298339..2666ed47e2 100644 --- a/intrinsics/probes/div_rm_ftz_f32.ll +++ b/intrinsics/probes/div_rm_ftz_f32.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/div_rn_f32.ll b/intrinsics/probes/div_rn_f32.ll index 33af93744e..c20b780fef 100644 --- a/intrinsics/probes/div_rn_f32.ll +++ b/intrinsics/probes/div_rn_f32.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/div_rn_f64.ll b/intrinsics/probes/div_rn_f64.ll index fb3d16bec3..0d81c67f5a 100644 --- a/intrinsics/probes/div_rn_f64.ll +++ b/intrinsics/probes/div_rn_f64.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/div_rn_ftz_f32.ll b/intrinsics/probes/div_rn_ftz_f32.ll index 5e0ad77d95..cde9f80af5 100644 --- a/intrinsics/probes/div_rn_ftz_f32.ll +++ b/intrinsics/probes/div_rn_ftz_f32.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/div_rp_f32.ll b/intrinsics/probes/div_rp_f32.ll index 54e0904e21..cdf784f916 100644 --- a/intrinsics/probes/div_rp_f32.ll +++ b/intrinsics/probes/div_rp_f32.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/div_rp_f64.ll b/intrinsics/probes/div_rp_f64.ll index 67a3b87054..066ae5af17 100644 --- a/intrinsics/probes/div_rp_f64.ll +++ b/intrinsics/probes/div_rp_f64.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/div_rp_ftz_f32.ll b/intrinsics/probes/div_rp_ftz_f32.ll index 4e0f046c80..bc965a10ff 100644 --- a/intrinsics/probes/div_rp_ftz_f32.ll +++ b/intrinsics/probes/div_rp_ftz_f32.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/div_rz_f32.ll b/intrinsics/probes/div_rz_f32.ll index 57342f90ef..e3a1f039c7 100644 --- a/intrinsics/probes/div_rz_f32.ll +++ b/intrinsics/probes/div_rz_f32.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/div_rz_f64.ll b/intrinsics/probes/div_rz_f64.ll index 9f8173ccef..b08c19b518 100644 --- a/intrinsics/probes/div_rz_f64.ll +++ b/intrinsics/probes/div_rz_f64.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/div_rz_ftz_f32.ll b/intrinsics/probes/div_rz_ftz_f32.ll index a5e90ac9bf..9017e9be04 100644 --- a/intrinsics/probes/div_rz_ftz_f32.ll +++ b/intrinsics/probes/div_rz_ftz_f32.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/dp2a_s32.ll b/intrinsics/probes/dp2a_s32.ll index b27427efa2..7fbb6fb131 100644 --- a/intrinsics/probes/dp2a_s32.ll +++ b/intrinsics/probes/dp2a_s32.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/dp2a_u32.ll b/intrinsics/probes/dp2a_u32.ll index b0ecbb1994..cdcabffaa5 100644 --- a/intrinsics/probes/dp2a_u32.ll +++ b/intrinsics/probes/dp2a_u32.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/dp4a_s32.ll b/intrinsics/probes/dp4a_s32.ll index 7d5cc40aec..b5ec025fd6 100644 --- a/intrinsics/probes/dp4a_s32.ll +++ b/intrinsics/probes/dp4a_s32.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/dp4a_u32.ll b/intrinsics/probes/dp4a_u32.ll index ea42b1f8f1..3cdb2ee1dd 100644 --- a/intrinsics/probes/dp4a_u32.ll +++ b/intrinsics/probes/dp4a_u32.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/dsmem_read_u32.ll b/intrinsics/probes/dsmem_read_u32.ll index 4c3579a50a..d7df1fbcea 100644 --- a/intrinsics/probes/dsmem_read_u32.ll +++ b/intrinsics/probes/dsmem_read_u32.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/dynamic_smem_size.lib_nvvm.ll b/intrinsics/probes/dynamic_smem_size.lib_nvvm.ll index bdf087dd6b..e31bdd544e 100644 --- a/intrinsics/probes/dynamic_smem_size.lib_nvvm.ll +++ b/intrinsics/probes/dynamic_smem_size.lib_nvvm.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/dynamic_smem_size.llvm_nvptx.ll b/intrinsics/probes/dynamic_smem_size.llvm_nvptx.ll index 03f3f35646..a90c11791d 100644 --- a/intrinsics/probes/dynamic_smem_size.llvm_nvptx.ll +++ b/intrinsics/probes/dynamic_smem_size.llvm_nvptx.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/elect_sync.lib_nvvm.ll b/intrinsics/probes/elect_sync.lib_nvvm.ll index 8ef7e0e4d2..ed67af373a 100644 --- a/intrinsics/probes/elect_sync.lib_nvvm.ll +++ b/intrinsics/probes/elect_sync.lib_nvvm.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/elect_sync.llvm_nvptx.ll b/intrinsics/probes/elect_sync.llvm_nvptx.ll index f3df3ce5f9..3db7236cf6 100644 --- a/intrinsics/probes/elect_sync.llvm_nvptx.ll +++ b/intrinsics/probes/elect_sync.llvm_nvptx.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/envreg1.lib_nvvm.ll b/intrinsics/probes/envreg1.lib_nvvm.ll index 9563026b9e..fdf0cc0c6d 100644 --- a/intrinsics/probes/envreg1.lib_nvvm.ll +++ b/intrinsics/probes/envreg1.lib_nvvm.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/envreg1.llvm_nvptx.ll b/intrinsics/probes/envreg1.llvm_nvptx.ll index c180239116..559741de13 100644 --- a/intrinsics/probes/envreg1.llvm_nvptx.ll +++ b/intrinsics/probes/envreg1.llvm_nvptx.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/envreg2.lib_nvvm.ll b/intrinsics/probes/envreg2.lib_nvvm.ll index 0e7da6648d..838ce50367 100644 --- a/intrinsics/probes/envreg2.lib_nvvm.ll +++ b/intrinsics/probes/envreg2.lib_nvvm.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/envreg2.llvm_nvptx.ll b/intrinsics/probes/envreg2.llvm_nvptx.ll index cf96270568..7740b84046 100644 --- a/intrinsics/probes/envreg2.llvm_nvptx.ll +++ b/intrinsics/probes/envreg2.llvm_nvptx.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/ex2_approx_f32.ll b/intrinsics/probes/ex2_approx_f32.ll index ecf3de1c7b..243f5cc7b3 100644 --- a/intrinsics/probes/ex2_approx_f32.ll +++ b/intrinsics/probes/ex2_approx_f32.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/ex2_approx_ftz_f32.ll b/intrinsics/probes/ex2_approx_ftz_f32.ll index 0225163c95..625070d6c9 100644 --- a/intrinsics/probes/ex2_approx_ftz_f32.ll +++ b/intrinsics/probes/ex2_approx_ftz_f32.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/fence_mbarrier_init_release_cluster.ll b/intrinsics/probes/fence_mbarrier_init_release_cluster.ll index 3c32d777b5..3e81132156 100644 --- a/intrinsics/probes/fence_mbarrier_init_release_cluster.ll +++ b/intrinsics/probes/fence_mbarrier_init_release_cluster.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/fence_proxy_async_generic_acquire_shared_cluster_cluster.ll b/intrinsics/probes/fence_proxy_async_generic_acquire_shared_cluster_cluster.ll index 055d7652ba..8afaa3b5b7 100644 --- a/intrinsics/probes/fence_proxy_async_generic_acquire_shared_cluster_cluster.ll +++ b/intrinsics/probes/fence_proxy_async_generic_acquire_shared_cluster_cluster.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/fence_proxy_async_generic_release_shared_cta_cluster.ll b/intrinsics/probes/fence_proxy_async_generic_release_shared_cta_cluster.ll index ce867b1d08..5866fa05ba 100644 --- a/intrinsics/probes/fence_proxy_async_generic_release_shared_cta_cluster.ll +++ b/intrinsics/probes/fence_proxy_async_generic_release_shared_cta_cluster.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/fence_proxy_async_shared_cta.ll b/intrinsics/probes/fence_proxy_async_shared_cta.ll index ec1c66d330..2d14301035 100644 --- a/intrinsics/probes/fence_proxy_async_shared_cta.ll +++ b/intrinsics/probes/fence_proxy_async_shared_cta.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/fence_proxy_tensormap_generic_acquire_cluster.ll b/intrinsics/probes/fence_proxy_tensormap_generic_acquire_cluster.ll index 84a1450dc4..2a17b40ad1 100644 --- a/intrinsics/probes/fence_proxy_tensormap_generic_acquire_cluster.ll +++ b/intrinsics/probes/fence_proxy_tensormap_generic_acquire_cluster.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/fence_proxy_tensormap_generic_acquire_cta.ll b/intrinsics/probes/fence_proxy_tensormap_generic_acquire_cta.ll index bb2f01ea97..e5619604b3 100644 --- a/intrinsics/probes/fence_proxy_tensormap_generic_acquire_cta.ll +++ b/intrinsics/probes/fence_proxy_tensormap_generic_acquire_cta.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/fence_proxy_tensormap_generic_acquire_gpu.ll b/intrinsics/probes/fence_proxy_tensormap_generic_acquire_gpu.ll index d7dcf8a05d..657f66ab44 100644 --- a/intrinsics/probes/fence_proxy_tensormap_generic_acquire_gpu.ll +++ b/intrinsics/probes/fence_proxy_tensormap_generic_acquire_gpu.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/fence_proxy_tensormap_generic_acquire_system.ll b/intrinsics/probes/fence_proxy_tensormap_generic_acquire_system.ll index 88cbee1c54..6196367c9e 100644 --- a/intrinsics/probes/fence_proxy_tensormap_generic_acquire_system.ll +++ b/intrinsics/probes/fence_proxy_tensormap_generic_acquire_system.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/fence_proxy_tensormap_generic_release_cluster.ll b/intrinsics/probes/fence_proxy_tensormap_generic_release_cluster.ll index 9b03922a4e..0b26080a0a 100644 --- a/intrinsics/probes/fence_proxy_tensormap_generic_release_cluster.ll +++ b/intrinsics/probes/fence_proxy_tensormap_generic_release_cluster.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/fence_proxy_tensormap_generic_release_cta.ll b/intrinsics/probes/fence_proxy_tensormap_generic_release_cta.ll index 76baa88409..52059ad56e 100644 --- a/intrinsics/probes/fence_proxy_tensormap_generic_release_cta.ll +++ b/intrinsics/probes/fence_proxy_tensormap_generic_release_cta.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/fence_proxy_tensormap_generic_release_gpu.ll b/intrinsics/probes/fence_proxy_tensormap_generic_release_gpu.ll index 3541c85993..210ee339f6 100644 --- a/intrinsics/probes/fence_proxy_tensormap_generic_release_gpu.ll +++ b/intrinsics/probes/fence_proxy_tensormap_generic_release_gpu.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/fence_proxy_tensormap_generic_release_system.ll b/intrinsics/probes/fence_proxy_tensormap_generic_release_system.ll index 23222448f1..8c3f829365 100644 --- a/intrinsics/probes/fence_proxy_tensormap_generic_release_system.ll +++ b/intrinsics/probes/fence_proxy_tensormap_generic_release_system.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/fma_bf16x2.ll b/intrinsics/probes/fma_bf16x2.ll index 7545f860d4..38b467ca9e 100644 --- a/intrinsics/probes/fma_bf16x2.ll +++ b/intrinsics/probes/fma_bf16x2.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/fma_f16x2.ll b/intrinsics/probes/fma_f16x2.ll index e3364528e7..4b699a1c8a 100644 --- a/intrinsics/probes/fma_f16x2.ll +++ b/intrinsics/probes/fma_f16x2.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/fma_f32x2.ll b/intrinsics/probes/fma_f32x2.ll index 804ec35acd..6c295801de 100644 --- a/intrinsics/probes/fma_f32x2.ll +++ b/intrinsics/probes/fma_f32x2.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/fma_ftz_f16x2.ll b/intrinsics/probes/fma_ftz_f16x2.ll index a014bbdb3a..9a87ebf640 100644 --- a/intrinsics/probes/fma_ftz_f16x2.ll +++ b/intrinsics/probes/fma_ftz_f16x2.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/fma_ftz_f32x2.ll b/intrinsics/probes/fma_ftz_f32x2.ll index fd19e23c81..ff3824176b 100644 --- a/intrinsics/probes/fma_ftz_f32x2.ll +++ b/intrinsics/probes/fma_ftz_f32x2.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/fma_ftz_relu_f16x2.ll b/intrinsics/probes/fma_ftz_relu_f16x2.ll index af929b1867..4dc378fcf9 100644 --- a/intrinsics/probes/fma_ftz_relu_f16x2.ll +++ b/intrinsics/probes/fma_ftz_relu_f16x2.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/fma_ftz_sat_f16x2.ll b/intrinsics/probes/fma_ftz_sat_f16x2.ll index 7002e2356f..3629f07c46 100644 --- a/intrinsics/probes/fma_ftz_sat_f16x2.ll +++ b/intrinsics/probes/fma_ftz_sat_f16x2.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/fma_relu_bf16x2.ll b/intrinsics/probes/fma_relu_bf16x2.ll index ffb14a0099..4d4d23ed3a 100644 --- a/intrinsics/probes/fma_relu_bf16x2.ll +++ b/intrinsics/probes/fma_relu_bf16x2.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/fma_relu_f16x2.ll b/intrinsics/probes/fma_relu_f16x2.ll index 5ce91ebcbd..ba11b94af0 100644 --- a/intrinsics/probes/fma_relu_f16x2.ll +++ b/intrinsics/probes/fma_relu_f16x2.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/fma_rm_f32.ll b/intrinsics/probes/fma_rm_f32.ll index f0b36273a0..160cc21af4 100644 --- a/intrinsics/probes/fma_rm_f32.ll +++ b/intrinsics/probes/fma_rm_f32.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/fma_rm_f64.ll b/intrinsics/probes/fma_rm_f64.ll index 991b8dd1b1..e77ea6c954 100644 --- a/intrinsics/probes/fma_rm_f64.ll +++ b/intrinsics/probes/fma_rm_f64.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/fma_rm_ftz_f32.ll b/intrinsics/probes/fma_rm_ftz_f32.ll index 3831125b4d..edf51396a3 100644 --- a/intrinsics/probes/fma_rm_ftz_f32.ll +++ b/intrinsics/probes/fma_rm_ftz_f32.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/fma_rm_ftz_sat_f32.ll b/intrinsics/probes/fma_rm_ftz_sat_f32.ll index 787ad9ada7..0d63f6ff38 100644 --- a/intrinsics/probes/fma_rm_ftz_sat_f32.ll +++ b/intrinsics/probes/fma_rm_ftz_sat_f32.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/fma_rm_sat_f32.ll b/intrinsics/probes/fma_rm_sat_f32.ll index 2e63ba2fd0..f5dcbdbfee 100644 --- a/intrinsics/probes/fma_rm_sat_f32.ll +++ b/intrinsics/probes/fma_rm_sat_f32.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/fma_rn_f32.ll b/intrinsics/probes/fma_rn_f32.ll index 2bed415e60..c87aa8ab0a 100644 --- a/intrinsics/probes/fma_rn_f32.ll +++ b/intrinsics/probes/fma_rn_f32.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/fma_rn_f64.ll b/intrinsics/probes/fma_rn_f64.ll index 1d14f9ff1e..fcaa88df22 100644 --- a/intrinsics/probes/fma_rn_f64.ll +++ b/intrinsics/probes/fma_rn_f64.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/fma_rn_ftz_f32.ll b/intrinsics/probes/fma_rn_ftz_f32.ll index c8e93516b3..3a836db5d7 100644 --- a/intrinsics/probes/fma_rn_ftz_f32.ll +++ b/intrinsics/probes/fma_rn_ftz_f32.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/fma_rn_ftz_sat_f32.ll b/intrinsics/probes/fma_rn_ftz_sat_f32.ll index 43a144c2f3..91e43ae445 100644 --- a/intrinsics/probes/fma_rn_ftz_sat_f32.ll +++ b/intrinsics/probes/fma_rn_ftz_sat_f32.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/fma_rn_sat_f32.ll b/intrinsics/probes/fma_rn_sat_f32.ll index 93b9e7ddc2..038736a568 100644 --- a/intrinsics/probes/fma_rn_sat_f32.ll +++ b/intrinsics/probes/fma_rn_sat_f32.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/fma_rp_f32.ll b/intrinsics/probes/fma_rp_f32.ll index 2de348ff53..d42587b574 100644 --- a/intrinsics/probes/fma_rp_f32.ll +++ b/intrinsics/probes/fma_rp_f32.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/fma_rp_f64.ll b/intrinsics/probes/fma_rp_f64.ll index ce00f12bfb..7c747e5b13 100644 --- a/intrinsics/probes/fma_rp_f64.ll +++ b/intrinsics/probes/fma_rp_f64.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/fma_rp_ftz_f32.ll b/intrinsics/probes/fma_rp_ftz_f32.ll index 992773d585..b28be42552 100644 --- a/intrinsics/probes/fma_rp_ftz_f32.ll +++ b/intrinsics/probes/fma_rp_ftz_f32.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/fma_rp_ftz_sat_f32.ll b/intrinsics/probes/fma_rp_ftz_sat_f32.ll index fb5f492c9b..25257ffd10 100644 --- a/intrinsics/probes/fma_rp_ftz_sat_f32.ll +++ b/intrinsics/probes/fma_rp_ftz_sat_f32.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/fma_rp_sat_f32.ll b/intrinsics/probes/fma_rp_sat_f32.ll index 7a494e428a..5f8c8fb5b2 100644 --- a/intrinsics/probes/fma_rp_sat_f32.ll +++ b/intrinsics/probes/fma_rp_sat_f32.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/fma_rz_f32.ll b/intrinsics/probes/fma_rz_f32.ll index 345049c016..2444052ae5 100644 --- a/intrinsics/probes/fma_rz_f32.ll +++ b/intrinsics/probes/fma_rz_f32.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/fma_rz_f64.ll b/intrinsics/probes/fma_rz_f64.ll index 5a07c7accf..c714293b00 100644 --- a/intrinsics/probes/fma_rz_f64.ll +++ b/intrinsics/probes/fma_rz_f64.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/fma_rz_ftz_f32.ll b/intrinsics/probes/fma_rz_ftz_f32.ll index f4a0a63e29..195eeac054 100644 --- a/intrinsics/probes/fma_rz_ftz_f32.ll +++ b/intrinsics/probes/fma_rz_ftz_f32.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/fma_rz_ftz_sat_f32.ll b/intrinsics/probes/fma_rz_ftz_sat_f32.ll index 8e7c09282b..63244f269c 100644 --- a/intrinsics/probes/fma_rz_ftz_sat_f32.ll +++ b/intrinsics/probes/fma_rz_ftz_sat_f32.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/fma_rz_sat_f32.ll b/intrinsics/probes/fma_rz_sat_f32.ll index 1238f85947..48abf724cc 100644 --- a/intrinsics/probes/fma_rz_sat_f32.ll +++ b/intrinsics/probes/fma_rz_sat_f32.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/fma_sat_f16x2.ll b/intrinsics/probes/fma_sat_f16x2.ll index 7aa66aba7b..064a7556e8 100644 --- a/intrinsics/probes/fma_sat_f16x2.ll +++ b/intrinsics/probes/fma_sat_f16x2.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/globaltimer.lib_nvvm.ll b/intrinsics/probes/globaltimer.lib_nvvm.ll index 0bcc2ccf8e..f4f1521496 100644 --- a/intrinsics/probes/globaltimer.lib_nvvm.ll +++ b/intrinsics/probes/globaltimer.lib_nvvm.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/globaltimer.llvm_nvptx.ll b/intrinsics/probes/globaltimer.llvm_nvptx.ll index 681500c049..91252eb745 100644 --- a/intrinsics/probes/globaltimer.llvm_nvptx.ll +++ b/intrinsics/probes/globaltimer.llvm_nvptx.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/grid_dependency_launch_dependents.ll b/intrinsics/probes/grid_dependency_launch_dependents.ll index ac736be7d0..c88e8194c1 100644 --- a/intrinsics/probes/grid_dependency_launch_dependents.ll +++ b/intrinsics/probes/grid_dependency_launch_dependents.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/grid_dependency_wait.ll b/intrinsics/probes/grid_dependency_wait.ll index 4d1c49549f..cad41fc1a9 100644 --- a/intrinsics/probes/grid_dependency_wait.ll +++ b/intrinsics/probes/grid_dependency_wait.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/grid_dim_x.ll b/intrinsics/probes/grid_dim_x.ll index 0fdaeea1e5..f9219224ee 100644 --- a/intrinsics/probes/grid_dim_x.ll +++ b/intrinsics/probes/grid_dim_x.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/grid_dim_y.ll b/intrinsics/probes/grid_dim_y.ll index 8a15fd4b44..e1864d7ebf 100644 --- a/intrinsics/probes/grid_dim_y.ll +++ b/intrinsics/probes/grid_dim_y.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/grid_dim_z.ll b/intrinsics/probes/grid_dim_z.ll index 1845f3d85c..4cb6a37d99 100644 --- a/intrinsics/probes/grid_dim_z.ll +++ b/intrinsics/probes/grid_dim_z.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/gridid.lib_nvvm.ll b/intrinsics/probes/gridid.lib_nvvm.ll index 217cf30ea0..cd0e4f08a9 100644 --- a/intrinsics/probes/gridid.lib_nvvm.ll +++ b/intrinsics/probes/gridid.lib_nvvm.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/gridid.llvm_nvptx.ll b/intrinsics/probes/gridid.llvm_nvptx.ll index 7332b5d6ef..dfd3dd7f0c 100644 --- a/intrinsics/probes/gridid.llvm_nvptx.ll +++ b/intrinsics/probes/gridid.llvm_nvptx.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/lane_id.ll b/intrinsics/probes/lane_id.ll index a18555343f..bb004ced65 100644 --- a/intrinsics/probes/lane_id.ll +++ b/intrinsics/probes/lane_id.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/lanemask_eq.ll b/intrinsics/probes/lanemask_eq.ll index fcb260c73d..3fbace2d98 100644 --- a/intrinsics/probes/lanemask_eq.ll +++ b/intrinsics/probes/lanemask_eq.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/lanemask_ge.ll b/intrinsics/probes/lanemask_ge.ll index 50990258b6..77d3b40350 100644 --- a/intrinsics/probes/lanemask_ge.ll +++ b/intrinsics/probes/lanemask_ge.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/lanemask_gt.ll b/intrinsics/probes/lanemask_gt.ll index 814f8ec296..9e583b5606 100644 --- a/intrinsics/probes/lanemask_gt.ll +++ b/intrinsics/probes/lanemask_gt.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/lanemask_le.ll b/intrinsics/probes/lanemask_le.ll index 8f44dfdb45..96e5147e63 100644 --- a/intrinsics/probes/lanemask_le.ll +++ b/intrinsics/probes/lanemask_le.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/lanemask_lt.ll b/intrinsics/probes/lanemask_lt.ll index 43d95e7446..be349e15c2 100644 --- a/intrinsics/probes/lanemask_lt.ll +++ b/intrinsics/probes/lanemask_lt.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/ldmatrix_m16n16_x1_trans_b8.ll b/intrinsics/probes/ldmatrix_m16n16_x1_trans_b8.ll index a9375893f7..8ab38ee1f2 100644 --- a/intrinsics/probes/ldmatrix_m16n16_x1_trans_b8.ll +++ b/intrinsics/probes/ldmatrix_m16n16_x1_trans_b8.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/ldmatrix_m16n16_x1_trans_b8x16_b4x16_p64.ll b/intrinsics/probes/ldmatrix_m16n16_x1_trans_b8x16_b4x16_p64.ll index be4059c44c..6f3bfc1abe 100644 --- a/intrinsics/probes/ldmatrix_m16n16_x1_trans_b8x16_b4x16_p64.ll +++ b/intrinsics/probes/ldmatrix_m16n16_x1_trans_b8x16_b4x16_p64.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/ldmatrix_m16n16_x1_trans_b8x16_b6x16_p32.ll b/intrinsics/probes/ldmatrix_m16n16_x1_trans_b8x16_b6x16_p32.ll index c04712c52e..cc8c666cee 100644 --- a/intrinsics/probes/ldmatrix_m16n16_x1_trans_b8x16_b6x16_p32.ll +++ b/intrinsics/probes/ldmatrix_m16n16_x1_trans_b8x16_b6x16_p32.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/ldmatrix_m16n16_x2_trans_b8.ll b/intrinsics/probes/ldmatrix_m16n16_x2_trans_b8.ll index 065b78261c..b3dc054196 100644 --- a/intrinsics/probes/ldmatrix_m16n16_x2_trans_b8.ll +++ b/intrinsics/probes/ldmatrix_m16n16_x2_trans_b8.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/ldmatrix_m16n16_x2_trans_b8x16_b4x16_p64.ll b/intrinsics/probes/ldmatrix_m16n16_x2_trans_b8x16_b4x16_p64.ll index 3bfea7cfb4..4cdb0230bb 100644 --- a/intrinsics/probes/ldmatrix_m16n16_x2_trans_b8x16_b4x16_p64.ll +++ b/intrinsics/probes/ldmatrix_m16n16_x2_trans_b8x16_b4x16_p64.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/ldmatrix_m16n16_x2_trans_b8x16_b6x16_p32.ll b/intrinsics/probes/ldmatrix_m16n16_x2_trans_b8x16_b6x16_p32.ll index 46206beee0..6a038bfbe9 100644 --- a/intrinsics/probes/ldmatrix_m16n16_x2_trans_b8x16_b6x16_p32.ll +++ b/intrinsics/probes/ldmatrix_m16n16_x2_trans_b8x16_b6x16_p32.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/ldmatrix_m8n16_x1_b8x16_b4x16_p64.ll b/intrinsics/probes/ldmatrix_m8n16_x1_b8x16_b4x16_p64.ll index 53cd37282e..cc24f4f6b5 100644 --- a/intrinsics/probes/ldmatrix_m8n16_x1_b8x16_b4x16_p64.ll +++ b/intrinsics/probes/ldmatrix_m8n16_x1_b8x16_b4x16_p64.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/ldmatrix_m8n16_x1_b8x16_b6x16_p32.ll b/intrinsics/probes/ldmatrix_m8n16_x1_b8x16_b6x16_p32.ll index 190c79ed56..cd3136a0a0 100644 --- a/intrinsics/probes/ldmatrix_m8n16_x1_b8x16_b6x16_p32.ll +++ b/intrinsics/probes/ldmatrix_m8n16_x1_b8x16_b6x16_p32.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/ldmatrix_m8n16_x2_b8x16_b4x16_p64.ll b/intrinsics/probes/ldmatrix_m8n16_x2_b8x16_b4x16_p64.ll index 11895560fc..e5a43b7b57 100644 --- a/intrinsics/probes/ldmatrix_m8n16_x2_b8x16_b4x16_p64.ll +++ b/intrinsics/probes/ldmatrix_m8n16_x2_b8x16_b4x16_p64.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/ldmatrix_m8n16_x2_b8x16_b6x16_p32.ll b/intrinsics/probes/ldmatrix_m8n16_x2_b8x16_b6x16_p32.ll index 8916641b45..87f82a3026 100644 --- a/intrinsics/probes/ldmatrix_m8n16_x2_b8x16_b6x16_p32.ll +++ b/intrinsics/probes/ldmatrix_m8n16_x2_b8x16_b6x16_p32.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/ldmatrix_m8n16_x4_b8x16_b4x16_p64.ll b/intrinsics/probes/ldmatrix_m8n16_x4_b8x16_b4x16_p64.ll index cd62cbbfda..4b63b4cd21 100644 --- a/intrinsics/probes/ldmatrix_m8n16_x4_b8x16_b4x16_p64.ll +++ b/intrinsics/probes/ldmatrix_m8n16_x4_b8x16_b4x16_p64.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/ldmatrix_m8n16_x4_b8x16_b6x16_p32.ll b/intrinsics/probes/ldmatrix_m8n16_x4_b8x16_b6x16_p32.ll index 2ee9c3f8ae..352c75e5b0 100644 --- a/intrinsics/probes/ldmatrix_m8n16_x4_b8x16_b6x16_p32.ll +++ b/intrinsics/probes/ldmatrix_m8n16_x4_b8x16_b6x16_p32.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/ldmatrix_m8n8_x1_b16.ll b/intrinsics/probes/ldmatrix_m8n8_x1_b16.ll index 8316bcb619..0e6228f97b 100644 --- a/intrinsics/probes/ldmatrix_m8n8_x1_b16.ll +++ b/intrinsics/probes/ldmatrix_m8n8_x1_b16.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/ldmatrix_m8n8_x1_trans_b16.ll b/intrinsics/probes/ldmatrix_m8n8_x1_trans_b16.ll index ca998d2cb8..8a46acc0e6 100644 --- a/intrinsics/probes/ldmatrix_m8n8_x1_trans_b16.ll +++ b/intrinsics/probes/ldmatrix_m8n8_x1_trans_b16.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/ldmatrix_m8n8_x2_b16.ll b/intrinsics/probes/ldmatrix_m8n8_x2_b16.ll index df30011914..9b4190151a 100644 --- a/intrinsics/probes/ldmatrix_m8n8_x2_b16.ll +++ b/intrinsics/probes/ldmatrix_m8n8_x2_b16.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/ldmatrix_m8n8_x2_trans_b16.ll b/intrinsics/probes/ldmatrix_m8n8_x2_trans_b16.ll index 04207d27fb..ad92e6fa56 100644 --- a/intrinsics/probes/ldmatrix_m8n8_x2_trans_b16.ll +++ b/intrinsics/probes/ldmatrix_m8n8_x2_trans_b16.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/ldmatrix_m8n8_x4_b16.ll b/intrinsics/probes/ldmatrix_m8n8_x4_b16.ll index ee08633d40..6ca12c318b 100644 --- a/intrinsics/probes/ldmatrix_m8n8_x4_b16.ll +++ b/intrinsics/probes/ldmatrix_m8n8_x4_b16.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/ldmatrix_m8n8_x4_trans_b16.ll b/intrinsics/probes/ldmatrix_m8n8_x4_trans_b16.ll index 8e1ec009d2..0a09e54b6c 100644 --- a/intrinsics/probes/ldmatrix_m8n8_x4_trans_b16.ll +++ b/intrinsics/probes/ldmatrix_m8n8_x4_trans_b16.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/lg2_approx_f32.ll b/intrinsics/probes/lg2_approx_f32.ll index aa71a031d8..3e2a011349 100644 --- a/intrinsics/probes/lg2_approx_f32.ll +++ b/intrinsics/probes/lg2_approx_f32.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/lg2_approx_ftz_f32.ll b/intrinsics/probes/lg2_approx_ftz_f32.ll index d2029b9261..55441a7c5b 100644 --- a/intrinsics/probes/lg2_approx_ftz_f32.ll +++ b/intrinsics/probes/lg2_approx_ftz_f32.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/map_shared_rank.ll b/intrinsics/probes/map_shared_rank.ll index 67f5a410d6..8426167dde 100644 --- a/intrinsics/probes/map_shared_rank.ll +++ b/intrinsics/probes/map_shared_rank.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/match_all_i64_sync.ll b/intrinsics/probes/match_all_i64_sync.ll index 8850d6b2df..584257dbec 100644 --- a/intrinsics/probes/match_all_i64_sync.ll +++ b/intrinsics/probes/match_all_i64_sync.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/match_all_sync.ll b/intrinsics/probes/match_all_sync.ll index 578d384c4a..5b7878ef52 100644 --- a/intrinsics/probes/match_all_sync.ll +++ b/intrinsics/probes/match_all_sync.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/match_any_i64_sync.ll b/intrinsics/probes/match_any_i64_sync.ll index c31c16c871..7e54a00d10 100644 --- a/intrinsics/probes/match_any_i64_sync.ll +++ b/intrinsics/probes/match_any_i64_sync.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/match_any_sync.ll b/intrinsics/probes/match_any_sync.ll index 1a35d9a2c4..9129ba99b2 100644 --- a/intrinsics/probes/match_any_sync.ll +++ b/intrinsics/probes/match_any_sync.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/max_bf16.ll b/intrinsics/probes/max_bf16.ll index dde8dde6c3..904b0e5e13 100644 --- a/intrinsics/probes/max_bf16.ll +++ b/intrinsics/probes/max_bf16.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/max_bf16x2.ll b/intrinsics/probes/max_bf16x2.ll index 313e1672a4..320e423ed1 100644 --- a/intrinsics/probes/max_bf16x2.ll +++ b/intrinsics/probes/max_bf16x2.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/max_f16.ll b/intrinsics/probes/max_f16.ll index 1d6ad48a83..ba12b97cb8 100644 --- a/intrinsics/probes/max_f16.ll +++ b/intrinsics/probes/max_f16.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/max_f16x2.ll b/intrinsics/probes/max_f16x2.ll index 2b8a63eb8e..56f5b139d3 100644 --- a/intrinsics/probes/max_f16x2.ll +++ b/intrinsics/probes/max_f16x2.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/max_ftz_f16.ll b/intrinsics/probes/max_ftz_f16.ll index f426260193..bf29159953 100644 --- a/intrinsics/probes/max_ftz_f16.ll +++ b/intrinsics/probes/max_ftz_f16.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/max_ftz_f16x2.ll b/intrinsics/probes/max_ftz_f16x2.ll index 1153c7fef4..0a857aee36 100644 --- a/intrinsics/probes/max_ftz_f16x2.ll +++ b/intrinsics/probes/max_ftz_f16x2.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/max_ftz_nan_f16.ll b/intrinsics/probes/max_ftz_nan_f16.ll index b41ebafb17..893e42edbb 100644 --- a/intrinsics/probes/max_ftz_nan_f16.ll +++ b/intrinsics/probes/max_ftz_nan_f16.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/max_ftz_nan_f16x2.ll b/intrinsics/probes/max_ftz_nan_f16x2.ll index 2241fb6b3c..a053ef20fb 100644 --- a/intrinsics/probes/max_ftz_nan_f16x2.ll +++ b/intrinsics/probes/max_ftz_nan_f16x2.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/max_ftz_nan_xorsign_abs_f16.ll b/intrinsics/probes/max_ftz_nan_xorsign_abs_f16.ll index e6393eedd9..9b9a915389 100644 --- a/intrinsics/probes/max_ftz_nan_xorsign_abs_f16.ll +++ b/intrinsics/probes/max_ftz_nan_xorsign_abs_f16.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/max_ftz_nan_xorsign_abs_f16x2.ll b/intrinsics/probes/max_ftz_nan_xorsign_abs_f16x2.ll index ef61a6745b..b8935954e7 100644 --- a/intrinsics/probes/max_ftz_nan_xorsign_abs_f16x2.ll +++ b/intrinsics/probes/max_ftz_nan_xorsign_abs_f16x2.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/max_ftz_nan_xorsign_abs_f32.ll b/intrinsics/probes/max_ftz_nan_xorsign_abs_f32.ll index 1b1dbdff2c..26cee4df38 100644 --- a/intrinsics/probes/max_ftz_nan_xorsign_abs_f32.ll +++ b/intrinsics/probes/max_ftz_nan_xorsign_abs_f32.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/max_ftz_xorsign_abs_f16.ll b/intrinsics/probes/max_ftz_xorsign_abs_f16.ll index af0487c83b..ff1a993a27 100644 --- a/intrinsics/probes/max_ftz_xorsign_abs_f16.ll +++ b/intrinsics/probes/max_ftz_xorsign_abs_f16.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/max_ftz_xorsign_abs_f16x2.ll b/intrinsics/probes/max_ftz_xorsign_abs_f16x2.ll index 2411afcc4a..f7a8619572 100644 --- a/intrinsics/probes/max_ftz_xorsign_abs_f16x2.ll +++ b/intrinsics/probes/max_ftz_xorsign_abs_f16x2.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/max_ftz_xorsign_abs_f32.ll b/intrinsics/probes/max_ftz_xorsign_abs_f32.ll index 20357fec13..3dcc1d7676 100644 --- a/intrinsics/probes/max_ftz_xorsign_abs_f32.ll +++ b/intrinsics/probes/max_ftz_xorsign_abs_f32.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/max_nan_bf16.ll b/intrinsics/probes/max_nan_bf16.ll index ad8cd71b32..0b7b2acef2 100644 --- a/intrinsics/probes/max_nan_bf16.ll +++ b/intrinsics/probes/max_nan_bf16.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/max_nan_bf16x2.ll b/intrinsics/probes/max_nan_bf16x2.ll index b63c238470..2b15847ac9 100644 --- a/intrinsics/probes/max_nan_bf16x2.ll +++ b/intrinsics/probes/max_nan_bf16x2.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/max_nan_f16.ll b/intrinsics/probes/max_nan_f16.ll index c2cb206046..8ae00fc9a2 100644 --- a/intrinsics/probes/max_nan_f16.ll +++ b/intrinsics/probes/max_nan_f16.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/max_nan_f16x2.ll b/intrinsics/probes/max_nan_f16x2.ll index d5ebda5b4a..700c492858 100644 --- a/intrinsics/probes/max_nan_f16x2.ll +++ b/intrinsics/probes/max_nan_f16x2.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/max_nan_xorsign_abs_bf16.ll b/intrinsics/probes/max_nan_xorsign_abs_bf16.ll index 6de7e4deda..447d1764f5 100644 --- a/intrinsics/probes/max_nan_xorsign_abs_bf16.ll +++ b/intrinsics/probes/max_nan_xorsign_abs_bf16.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/max_nan_xorsign_abs_bf16x2.ll b/intrinsics/probes/max_nan_xorsign_abs_bf16x2.ll index e9015336e2..6a568e9adb 100644 --- a/intrinsics/probes/max_nan_xorsign_abs_bf16x2.ll +++ b/intrinsics/probes/max_nan_xorsign_abs_bf16x2.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/max_nan_xorsign_abs_f16.ll b/intrinsics/probes/max_nan_xorsign_abs_f16.ll index 11930691de..c9065dc02e 100644 --- a/intrinsics/probes/max_nan_xorsign_abs_f16.ll +++ b/intrinsics/probes/max_nan_xorsign_abs_f16.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/max_nan_xorsign_abs_f16x2.ll b/intrinsics/probes/max_nan_xorsign_abs_f16x2.ll index e171228b00..1a150d6b86 100644 --- a/intrinsics/probes/max_nan_xorsign_abs_f16x2.ll +++ b/intrinsics/probes/max_nan_xorsign_abs_f16x2.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/max_nan_xorsign_abs_f32.ll b/intrinsics/probes/max_nan_xorsign_abs_f32.ll index 6b776cee58..edab5de7cf 100644 --- a/intrinsics/probes/max_nan_xorsign_abs_f32.ll +++ b/intrinsics/probes/max_nan_xorsign_abs_f32.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/max_relu_s16x2.ll b/intrinsics/probes/max_relu_s16x2.ll index 6e45ddde81..ca2362be34 100644 --- a/intrinsics/probes/max_relu_s16x2.ll +++ b/intrinsics/probes/max_relu_s16x2.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/max_relu_s32.ll b/intrinsics/probes/max_relu_s32.ll index 84a5526037..fc548028b5 100644 --- a/intrinsics/probes/max_relu_s32.ll +++ b/intrinsics/probes/max_relu_s32.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/max_s16x2.ll b/intrinsics/probes/max_s16x2.ll index adf6f4145a..41d9c13eb6 100644 --- a/intrinsics/probes/max_s16x2.ll +++ b/intrinsics/probes/max_s16x2.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/max_u16x2.ll b/intrinsics/probes/max_u16x2.ll index 64dac3ccd3..f384d90df3 100644 --- a/intrinsics/probes/max_u16x2.ll +++ b/intrinsics/probes/max_u16x2.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/max_xorsign_abs_bf16.ll b/intrinsics/probes/max_xorsign_abs_bf16.ll index ae7dc896ce..4526b2ad73 100644 --- a/intrinsics/probes/max_xorsign_abs_bf16.ll +++ b/intrinsics/probes/max_xorsign_abs_bf16.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/max_xorsign_abs_bf16x2.ll b/intrinsics/probes/max_xorsign_abs_bf16x2.ll index e35741abfe..78d1bc07a3 100644 --- a/intrinsics/probes/max_xorsign_abs_bf16x2.ll +++ b/intrinsics/probes/max_xorsign_abs_bf16x2.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/max_xorsign_abs_f16.ll b/intrinsics/probes/max_xorsign_abs_f16.ll index 53281db774..faa076d5be 100644 --- a/intrinsics/probes/max_xorsign_abs_f16.ll +++ b/intrinsics/probes/max_xorsign_abs_f16.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/max_xorsign_abs_f16x2.ll b/intrinsics/probes/max_xorsign_abs_f16x2.ll index f309142c32..9e9b9bb16c 100644 --- a/intrinsics/probes/max_xorsign_abs_f16x2.ll +++ b/intrinsics/probes/max_xorsign_abs_f16x2.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/max_xorsign_abs_f32.ll b/intrinsics/probes/max_xorsign_abs_f32.ll index d57f072cb6..28174616f6 100644 --- a/intrinsics/probes/max_xorsign_abs_f32.ll +++ b/intrinsics/probes/max_xorsign_abs_f32.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mbarrier_arrive.ll b/intrinsics/probes/mbarrier_arrive.ll index a147e2b75c..86d5fae4e8 100644 --- a/intrinsics/probes/mbarrier_arrive.ll +++ b/intrinsics/probes/mbarrier_arrive.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mbarrier_arrive_cluster.ll b/intrinsics/probes/mbarrier_arrive_cluster.ll index 1f388fdbef..8f04fa4e3d 100644 --- a/intrinsics/probes/mbarrier_arrive_cluster.ll +++ b/intrinsics/probes/mbarrier_arrive_cluster.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mbarrier_arrive_expect_tx.ll b/intrinsics/probes/mbarrier_arrive_expect_tx.ll index 219820140c..b2e922911d 100644 --- a/intrinsics/probes/mbarrier_arrive_expect_tx.ll +++ b/intrinsics/probes/mbarrier_arrive_expect_tx.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mbarrier_arrive_expect_tx_cluster.ll b/intrinsics/probes/mbarrier_arrive_expect_tx_cluster.ll index ca70e57822..3e986117d6 100644 --- a/intrinsics/probes/mbarrier_arrive_expect_tx_cluster.ll +++ b/intrinsics/probes/mbarrier_arrive_expect_tx_cluster.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mbarrier_init.ll b/intrinsics/probes/mbarrier_init.ll index d6e945805c..9872490c59 100644 --- a/intrinsics/probes/mbarrier_init.ll +++ b/intrinsics/probes/mbarrier_init.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mbarrier_inval.ll b/intrinsics/probes/mbarrier_inval.ll index c31ecda80b..c1b840ba87 100644 --- a/intrinsics/probes/mbarrier_inval.ll +++ b/intrinsics/probes/mbarrier_inval.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mbarrier_test_wait.ll b/intrinsics/probes/mbarrier_test_wait.ll index ce687ebfda..e68a17e7e0 100644 --- a/intrinsics/probes/mbarrier_test_wait.ll +++ b/intrinsics/probes/mbarrier_test_wait.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mbarrier_try_wait.ll b/intrinsics/probes/mbarrier_try_wait.ll index f2483fbe5c..d87c71fec7 100644 --- a/intrinsics/probes/mbarrier_try_wait.ll +++ b/intrinsics/probes/mbarrier_try_wait.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mbarrier_try_wait_parity.ll b/intrinsics/probes/mbarrier_try_wait_parity.ll index 87b0786658..66eecb7b5c 100644 --- a/intrinsics/probes/mbarrier_try_wait_parity.ll +++ b/intrinsics/probes/mbarrier_try_wait_parity.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mbarrier_try_wait_parity_cluster.ll b/intrinsics/probes/mbarrier_try_wait_parity_cluster.ll index 4fd2d0933f..8392485a7a 100644 --- a/intrinsics/probes/mbarrier_try_wait_parity_cluster.ll +++ b/intrinsics/probes/mbarrier_try_wait_parity_cluster.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/min_bf16.ll b/intrinsics/probes/min_bf16.ll index 5361d9daf1..d7cf8abcf3 100644 --- a/intrinsics/probes/min_bf16.ll +++ b/intrinsics/probes/min_bf16.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/min_bf16x2.ll b/intrinsics/probes/min_bf16x2.ll index f86f214035..8454695351 100644 --- a/intrinsics/probes/min_bf16x2.ll +++ b/intrinsics/probes/min_bf16x2.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/min_f16.ll b/intrinsics/probes/min_f16.ll index bbe990c75b..f13fda8349 100644 --- a/intrinsics/probes/min_f16.ll +++ b/intrinsics/probes/min_f16.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/min_f16x2.ll b/intrinsics/probes/min_f16x2.ll index 597b84307d..7586d4bc3c 100644 --- a/intrinsics/probes/min_f16x2.ll +++ b/intrinsics/probes/min_f16x2.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/min_ftz_f16.ll b/intrinsics/probes/min_ftz_f16.ll index fb1c0c34dd..c3d2dd016a 100644 --- a/intrinsics/probes/min_ftz_f16.ll +++ b/intrinsics/probes/min_ftz_f16.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/min_ftz_f16x2.ll b/intrinsics/probes/min_ftz_f16x2.ll index cc9b84d788..b0e3e52bc8 100644 --- a/intrinsics/probes/min_ftz_f16x2.ll +++ b/intrinsics/probes/min_ftz_f16x2.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/min_ftz_nan_f16.ll b/intrinsics/probes/min_ftz_nan_f16.ll index 9334a47b2f..ba4c56af05 100644 --- a/intrinsics/probes/min_ftz_nan_f16.ll +++ b/intrinsics/probes/min_ftz_nan_f16.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/min_ftz_nan_f16x2.ll b/intrinsics/probes/min_ftz_nan_f16x2.ll index f86fe98ed4..d09ef1a996 100644 --- a/intrinsics/probes/min_ftz_nan_f16x2.ll +++ b/intrinsics/probes/min_ftz_nan_f16x2.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/min_ftz_nan_xorsign_abs_f16.ll b/intrinsics/probes/min_ftz_nan_xorsign_abs_f16.ll index 93e72a451f..90aafda0b9 100644 --- a/intrinsics/probes/min_ftz_nan_xorsign_abs_f16.ll +++ b/intrinsics/probes/min_ftz_nan_xorsign_abs_f16.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/min_ftz_nan_xorsign_abs_f16x2.ll b/intrinsics/probes/min_ftz_nan_xorsign_abs_f16x2.ll index f2d4cea182..7954dd6ebc 100644 --- a/intrinsics/probes/min_ftz_nan_xorsign_abs_f16x2.ll +++ b/intrinsics/probes/min_ftz_nan_xorsign_abs_f16x2.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/min_ftz_nan_xorsign_abs_f32.ll b/intrinsics/probes/min_ftz_nan_xorsign_abs_f32.ll index 3117d18609..d405e5eb82 100644 --- a/intrinsics/probes/min_ftz_nan_xorsign_abs_f32.ll +++ b/intrinsics/probes/min_ftz_nan_xorsign_abs_f32.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/min_ftz_xorsign_abs_f16.ll b/intrinsics/probes/min_ftz_xorsign_abs_f16.ll index aba3df0530..5800825885 100644 --- a/intrinsics/probes/min_ftz_xorsign_abs_f16.ll +++ b/intrinsics/probes/min_ftz_xorsign_abs_f16.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/min_ftz_xorsign_abs_f16x2.ll b/intrinsics/probes/min_ftz_xorsign_abs_f16x2.ll index f31812c413..b8bd783029 100644 --- a/intrinsics/probes/min_ftz_xorsign_abs_f16x2.ll +++ b/intrinsics/probes/min_ftz_xorsign_abs_f16x2.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/min_ftz_xorsign_abs_f32.ll b/intrinsics/probes/min_ftz_xorsign_abs_f32.ll index 8419b215dd..18f029b75e 100644 --- a/intrinsics/probes/min_ftz_xorsign_abs_f32.ll +++ b/intrinsics/probes/min_ftz_xorsign_abs_f32.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/min_nan_bf16.ll b/intrinsics/probes/min_nan_bf16.ll index dfc6858913..2c52d6a265 100644 --- a/intrinsics/probes/min_nan_bf16.ll +++ b/intrinsics/probes/min_nan_bf16.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/min_nan_bf16x2.ll b/intrinsics/probes/min_nan_bf16x2.ll index e99e3e3b11..e1260b17e9 100644 --- a/intrinsics/probes/min_nan_bf16x2.ll +++ b/intrinsics/probes/min_nan_bf16x2.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/min_nan_f16.ll b/intrinsics/probes/min_nan_f16.ll index 14c524ea0b..228f61afd0 100644 --- a/intrinsics/probes/min_nan_f16.ll +++ b/intrinsics/probes/min_nan_f16.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/min_nan_f16x2.ll b/intrinsics/probes/min_nan_f16x2.ll index 9e4500c6f5..b3563dc157 100644 --- a/intrinsics/probes/min_nan_f16x2.ll +++ b/intrinsics/probes/min_nan_f16x2.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/min_nan_xorsign_abs_bf16.ll b/intrinsics/probes/min_nan_xorsign_abs_bf16.ll index 3b7be6d2a2..6dbcbf9ed0 100644 --- a/intrinsics/probes/min_nan_xorsign_abs_bf16.ll +++ b/intrinsics/probes/min_nan_xorsign_abs_bf16.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/min_nan_xorsign_abs_bf16x2.ll b/intrinsics/probes/min_nan_xorsign_abs_bf16x2.ll index c779cd86a1..6ed42af3cb 100644 --- a/intrinsics/probes/min_nan_xorsign_abs_bf16x2.ll +++ b/intrinsics/probes/min_nan_xorsign_abs_bf16x2.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/min_nan_xorsign_abs_f16.ll b/intrinsics/probes/min_nan_xorsign_abs_f16.ll index e84b67ed67..d910136bee 100644 --- a/intrinsics/probes/min_nan_xorsign_abs_f16.ll +++ b/intrinsics/probes/min_nan_xorsign_abs_f16.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/min_nan_xorsign_abs_f16x2.ll b/intrinsics/probes/min_nan_xorsign_abs_f16x2.ll index 56d5b0a468..2a3e05dff1 100644 --- a/intrinsics/probes/min_nan_xorsign_abs_f16x2.ll +++ b/intrinsics/probes/min_nan_xorsign_abs_f16x2.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/min_nan_xorsign_abs_f32.ll b/intrinsics/probes/min_nan_xorsign_abs_f32.ll index 350eef9906..76aa684d11 100644 --- a/intrinsics/probes/min_nan_xorsign_abs_f32.ll +++ b/intrinsics/probes/min_nan_xorsign_abs_f32.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/min_relu_s16x2.ll b/intrinsics/probes/min_relu_s16x2.ll index 7dcbb131f4..54d0abb90b 100644 --- a/intrinsics/probes/min_relu_s16x2.ll +++ b/intrinsics/probes/min_relu_s16x2.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/min_relu_s32.ll b/intrinsics/probes/min_relu_s32.ll index 87485d77c5..40aeb9be66 100644 --- a/intrinsics/probes/min_relu_s32.ll +++ b/intrinsics/probes/min_relu_s32.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/min_s16x2.ll b/intrinsics/probes/min_s16x2.ll index 67071bacfc..66ed6281b7 100644 --- a/intrinsics/probes/min_s16x2.ll +++ b/intrinsics/probes/min_s16x2.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/min_u16x2.ll b/intrinsics/probes/min_u16x2.ll index 51d69206f5..58fff360a1 100644 --- a/intrinsics/probes/min_u16x2.ll +++ b/intrinsics/probes/min_u16x2.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/min_xorsign_abs_bf16.ll b/intrinsics/probes/min_xorsign_abs_bf16.ll index 3e1ee3680d..e5ad315103 100644 --- a/intrinsics/probes/min_xorsign_abs_bf16.ll +++ b/intrinsics/probes/min_xorsign_abs_bf16.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/min_xorsign_abs_bf16x2.ll b/intrinsics/probes/min_xorsign_abs_bf16x2.ll index c3337de1cc..425c618c26 100644 --- a/intrinsics/probes/min_xorsign_abs_bf16x2.ll +++ b/intrinsics/probes/min_xorsign_abs_bf16x2.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/min_xorsign_abs_f16.ll b/intrinsics/probes/min_xorsign_abs_f16.ll index fcb5837137..eac851aa89 100644 --- a/intrinsics/probes/min_xorsign_abs_f16.ll +++ b/intrinsics/probes/min_xorsign_abs_f16.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/min_xorsign_abs_f16x2.ll b/intrinsics/probes/min_xorsign_abs_f16x2.ll index bbc5aa1357..d64545d338 100644 --- a/intrinsics/probes/min_xorsign_abs_f16x2.ll +++ b/intrinsics/probes/min_xorsign_abs_f16x2.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/min_xorsign_abs_f32.ll b/intrinsics/probes/min_xorsign_abs_f32.ll index 2ba0137013..b2924785b8 100644 --- a/intrinsics/probes/min_xorsign_abs_f32.ll +++ b/intrinsics/probes/min_xorsign_abs_f32.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_m16n8k128_s32_b1_and_popc.ll b/intrinsics/probes/mma_m16n8k128_s32_b1_and_popc.ll index eeecdcbe23..2fc1b2982f 100644 --- a/intrinsics/probes/mma_m16n8k128_s32_b1_and_popc.ll +++ b/intrinsics/probes/mma_m16n8k128_s32_b1_and_popc.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_m16n8k128_s32_b1_xor_popc.ll b/intrinsics/probes/mma_m16n8k128_s32_b1_xor_popc.ll index 71271c4018..865b8e2708 100644 --- a/intrinsics/probes/mma_m16n8k128_s32_b1_xor_popc.ll +++ b/intrinsics/probes/mma_m16n8k128_s32_b1_xor_popc.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_m16n8k16_f16_f16.ll b/intrinsics/probes/mma_m16n8k16_f16_f16.ll index 4dd30f9029..98b2d78bdf 100644 --- a/intrinsics/probes/mma_m16n8k16_f16_f16.ll +++ b/intrinsics/probes/mma_m16n8k16_f16_f16.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_m16n8k16_f32_bf16.ll b/intrinsics/probes/mma_m16n8k16_f32_bf16.ll index 56b753ab59..1b2a5832be 100644 --- a/intrinsics/probes/mma_m16n8k16_f32_bf16.ll +++ b/intrinsics/probes/mma_m16n8k16_f32_bf16.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_m16n8k16_f32_f16.ll b/intrinsics/probes/mma_m16n8k16_f32_f16.ll index de69ab88fa..9adaacfb7c 100644 --- a/intrinsics/probes/mma_m16n8k16_f32_f16.ll +++ b/intrinsics/probes/mma_m16n8k16_f32_f16.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_m16n8k16_fp8_f16_e4m3_e4m3.ll b/intrinsics/probes/mma_m16n8k16_fp8_f16_e4m3_e4m3.ll index 64ed3cdad1..8e85bed89e 100644 --- a/intrinsics/probes/mma_m16n8k16_fp8_f16_e4m3_e4m3.ll +++ b/intrinsics/probes/mma_m16n8k16_fp8_f16_e4m3_e4m3.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_m16n8k16_fp8_f16_e4m3_e5m2.ll b/intrinsics/probes/mma_m16n8k16_fp8_f16_e4m3_e5m2.ll index d772032a7c..b94f03318b 100644 --- a/intrinsics/probes/mma_m16n8k16_fp8_f16_e4m3_e5m2.ll +++ b/intrinsics/probes/mma_m16n8k16_fp8_f16_e4m3_e5m2.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_m16n8k16_fp8_f16_e5m2_e4m3.ll b/intrinsics/probes/mma_m16n8k16_fp8_f16_e5m2_e4m3.ll index 69a70c7d55..c984660bd7 100644 --- a/intrinsics/probes/mma_m16n8k16_fp8_f16_e5m2_e4m3.ll +++ b/intrinsics/probes/mma_m16n8k16_fp8_f16_e5m2_e4m3.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_m16n8k16_fp8_f16_e5m2_e5m2.ll b/intrinsics/probes/mma_m16n8k16_fp8_f16_e5m2_e5m2.ll index e0faa71a6a..34e4f76162 100644 --- a/intrinsics/probes/mma_m16n8k16_fp8_f16_e5m2_e5m2.ll +++ b/intrinsics/probes/mma_m16n8k16_fp8_f16_e5m2_e5m2.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_m16n8k16_fp8_f32_e4m3_e4m3.ll b/intrinsics/probes/mma_m16n8k16_fp8_f32_e4m3_e4m3.ll index 1a69412ae0..b9e0102b21 100644 --- a/intrinsics/probes/mma_m16n8k16_fp8_f32_e4m3_e4m3.ll +++ b/intrinsics/probes/mma_m16n8k16_fp8_f32_e4m3_e4m3.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_m16n8k16_fp8_f32_e4m3_e5m2.ll b/intrinsics/probes/mma_m16n8k16_fp8_f32_e4m3_e5m2.ll index eebbd1e59e..9d7168f7f8 100644 --- a/intrinsics/probes/mma_m16n8k16_fp8_f32_e4m3_e5m2.ll +++ b/intrinsics/probes/mma_m16n8k16_fp8_f32_e4m3_e5m2.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_m16n8k16_fp8_f32_e5m2_e4m3.ll b/intrinsics/probes/mma_m16n8k16_fp8_f32_e5m2_e4m3.ll index 4f52720059..06e5efed09 100644 --- a/intrinsics/probes/mma_m16n8k16_fp8_f32_e5m2_e4m3.ll +++ b/intrinsics/probes/mma_m16n8k16_fp8_f32_e5m2_e4m3.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_m16n8k16_fp8_f32_e5m2_e5m2.ll b/intrinsics/probes/mma_m16n8k16_fp8_f32_e5m2_e5m2.ll index 9c92aa85d3..a9d7e40399 100644 --- a/intrinsics/probes/mma_m16n8k16_fp8_f32_e5m2_e5m2.ll +++ b/intrinsics/probes/mma_m16n8k16_fp8_f32_e5m2_e5m2.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_m16n8k16_s32_s8.ll b/intrinsics/probes/mma_m16n8k16_s32_s8.ll index 3eea53992f..40751f021b 100644 --- a/intrinsics/probes/mma_m16n8k16_s32_s8.ll +++ b/intrinsics/probes/mma_m16n8k16_s32_s8.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_m16n8k16_s32_s8_satfinite.ll b/intrinsics/probes/mma_m16n8k16_s32_s8_satfinite.ll index d0262af2a6..2fbcb7da54 100644 --- a/intrinsics/probes/mma_m16n8k16_s32_s8_satfinite.ll +++ b/intrinsics/probes/mma_m16n8k16_s32_s8_satfinite.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_m16n8k16_s32_s8_u8.ll b/intrinsics/probes/mma_m16n8k16_s32_s8_u8.ll index 8ed4848177..a6455ba2dd 100644 --- a/intrinsics/probes/mma_m16n8k16_s32_s8_u8.ll +++ b/intrinsics/probes/mma_m16n8k16_s32_s8_u8.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_m16n8k16_s32_s8_u8_satfinite.ll b/intrinsics/probes/mma_m16n8k16_s32_s8_u8_satfinite.ll index 9e4a9ff74b..be35f82968 100644 --- a/intrinsics/probes/mma_m16n8k16_s32_s8_u8_satfinite.ll +++ b/intrinsics/probes/mma_m16n8k16_s32_s8_u8_satfinite.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_m16n8k16_s32_u8.ll b/intrinsics/probes/mma_m16n8k16_s32_u8.ll index f3287ab529..46be49c99a 100644 --- a/intrinsics/probes/mma_m16n8k16_s32_u8.ll +++ b/intrinsics/probes/mma_m16n8k16_s32_u8.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_m16n8k16_s32_u8_s8.ll b/intrinsics/probes/mma_m16n8k16_s32_u8_s8.ll index 105c1aa2b6..b809094595 100644 --- a/intrinsics/probes/mma_m16n8k16_s32_u8_s8.ll +++ b/intrinsics/probes/mma_m16n8k16_s32_u8_s8.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_m16n8k16_s32_u8_s8_satfinite.ll b/intrinsics/probes/mma_m16n8k16_s32_u8_s8_satfinite.ll index c7e0c3a02a..4d67cf98a2 100644 --- a/intrinsics/probes/mma_m16n8k16_s32_u8_s8_satfinite.ll +++ b/intrinsics/probes/mma_m16n8k16_s32_u8_s8_satfinite.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_m16n8k16_s32_u8_satfinite.ll b/intrinsics/probes/mma_m16n8k16_s32_u8_satfinite.ll index 9a0da5e2e2..bdadc64bdf 100644 --- a/intrinsics/probes/mma_m16n8k16_s32_u8_satfinite.ll +++ b/intrinsics/probes/mma_m16n8k16_s32_u8_satfinite.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_m16n8k256_s32_b1_and_popc.ll b/intrinsics/probes/mma_m16n8k256_s32_b1_and_popc.ll index 6b5a8c5d93..89ef1db70b 100644 --- a/intrinsics/probes/mma_m16n8k256_s32_b1_and_popc.ll +++ b/intrinsics/probes/mma_m16n8k256_s32_b1_and_popc.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_m16n8k256_s32_b1_xor_popc.ll b/intrinsics/probes/mma_m16n8k256_s32_b1_xor_popc.ll index b96fc08574..48f6eb41e0 100644 --- a/intrinsics/probes/mma_m16n8k256_s32_b1_xor_popc.ll +++ b/intrinsics/probes/mma_m16n8k256_s32_b1_xor_popc.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_m16n8k32_f16_e2m1_e2m1.ll b/intrinsics/probes/mma_m16n8k32_f16_e2m1_e2m1.ll index 6a0419d3c0..884725a97a 100644 --- a/intrinsics/probes/mma_m16n8k32_f16_e2m1_e2m1.ll +++ b/intrinsics/probes/mma_m16n8k32_f16_e2m1_e2m1.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_m16n8k32_f16_e2m1_e2m3.ll b/intrinsics/probes/mma_m16n8k32_f16_e2m1_e2m3.ll index 32cc68c6c0..d31ac55b9a 100644 --- a/intrinsics/probes/mma_m16n8k32_f16_e2m1_e2m3.ll +++ b/intrinsics/probes/mma_m16n8k32_f16_e2m1_e2m3.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_m16n8k32_f16_e2m1_e3m2.ll b/intrinsics/probes/mma_m16n8k32_f16_e2m1_e3m2.ll index 50e4219ca0..71f9035598 100644 --- a/intrinsics/probes/mma_m16n8k32_f16_e2m1_e3m2.ll +++ b/intrinsics/probes/mma_m16n8k32_f16_e2m1_e3m2.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_m16n8k32_f16_e2m1_e4m3.ll b/intrinsics/probes/mma_m16n8k32_f16_e2m1_e4m3.ll index 3f4215fbb7..f294d57ae5 100644 --- a/intrinsics/probes/mma_m16n8k32_f16_e2m1_e4m3.ll +++ b/intrinsics/probes/mma_m16n8k32_f16_e2m1_e4m3.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_m16n8k32_f16_e2m1_e5m2.ll b/intrinsics/probes/mma_m16n8k32_f16_e2m1_e5m2.ll index 15c6fb41a8..efea7c4f95 100644 --- a/intrinsics/probes/mma_m16n8k32_f16_e2m1_e5m2.ll +++ b/intrinsics/probes/mma_m16n8k32_f16_e2m1_e5m2.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_m16n8k32_f16_e2m3_e2m1.ll b/intrinsics/probes/mma_m16n8k32_f16_e2m3_e2m1.ll index 0b9a012d06..d05144c210 100644 --- a/intrinsics/probes/mma_m16n8k32_f16_e2m3_e2m1.ll +++ b/intrinsics/probes/mma_m16n8k32_f16_e2m3_e2m1.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_m16n8k32_f16_e2m3_e2m3.ll b/intrinsics/probes/mma_m16n8k32_f16_e2m3_e2m3.ll index 796d671bf3..a0d7a36a2b 100644 --- a/intrinsics/probes/mma_m16n8k32_f16_e2m3_e2m3.ll +++ b/intrinsics/probes/mma_m16n8k32_f16_e2m3_e2m3.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_m16n8k32_f16_e2m3_e3m2.ll b/intrinsics/probes/mma_m16n8k32_f16_e2m3_e3m2.ll index e2044f3b74..3c9d22111f 100644 --- a/intrinsics/probes/mma_m16n8k32_f16_e2m3_e3m2.ll +++ b/intrinsics/probes/mma_m16n8k32_f16_e2m3_e3m2.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_m16n8k32_f16_e2m3_e4m3.ll b/intrinsics/probes/mma_m16n8k32_f16_e2m3_e4m3.ll index 56baa7e8fa..60b484be3c 100644 --- a/intrinsics/probes/mma_m16n8k32_f16_e2m3_e4m3.ll +++ b/intrinsics/probes/mma_m16n8k32_f16_e2m3_e4m3.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_m16n8k32_f16_e2m3_e5m2.ll b/intrinsics/probes/mma_m16n8k32_f16_e2m3_e5m2.ll index 838d6286c3..eafcd64b94 100644 --- a/intrinsics/probes/mma_m16n8k32_f16_e2m3_e5m2.ll +++ b/intrinsics/probes/mma_m16n8k32_f16_e2m3_e5m2.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_m16n8k32_f16_e3m2_e2m1.ll b/intrinsics/probes/mma_m16n8k32_f16_e3m2_e2m1.ll index db5072150a..3c5b37f47d 100644 --- a/intrinsics/probes/mma_m16n8k32_f16_e3m2_e2m1.ll +++ b/intrinsics/probes/mma_m16n8k32_f16_e3m2_e2m1.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_m16n8k32_f16_e3m2_e2m3.ll b/intrinsics/probes/mma_m16n8k32_f16_e3m2_e2m3.ll index 0896a10b05..8f25c08830 100644 --- a/intrinsics/probes/mma_m16n8k32_f16_e3m2_e2m3.ll +++ b/intrinsics/probes/mma_m16n8k32_f16_e3m2_e2m3.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_m16n8k32_f16_e3m2_e3m2.ll b/intrinsics/probes/mma_m16n8k32_f16_e3m2_e3m2.ll index 4dc377c3a2..41c48d71a8 100644 --- a/intrinsics/probes/mma_m16n8k32_f16_e3m2_e3m2.ll +++ b/intrinsics/probes/mma_m16n8k32_f16_e3m2_e3m2.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_m16n8k32_f16_e3m2_e4m3.ll b/intrinsics/probes/mma_m16n8k32_f16_e3m2_e4m3.ll index c5fc197d40..e3690583c2 100644 --- a/intrinsics/probes/mma_m16n8k32_f16_e3m2_e4m3.ll +++ b/intrinsics/probes/mma_m16n8k32_f16_e3m2_e4m3.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_m16n8k32_f16_e3m2_e5m2.ll b/intrinsics/probes/mma_m16n8k32_f16_e3m2_e5m2.ll index 44b48c49a1..15df601836 100644 --- a/intrinsics/probes/mma_m16n8k32_f16_e3m2_e5m2.ll +++ b/intrinsics/probes/mma_m16n8k32_f16_e3m2_e5m2.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_m16n8k32_f16_e4m3_e2m1.ll b/intrinsics/probes/mma_m16n8k32_f16_e4m3_e2m1.ll index db13330de3..0288dc4d42 100644 --- a/intrinsics/probes/mma_m16n8k32_f16_e4m3_e2m1.ll +++ b/intrinsics/probes/mma_m16n8k32_f16_e4m3_e2m1.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_m16n8k32_f16_e4m3_e2m3.ll b/intrinsics/probes/mma_m16n8k32_f16_e4m3_e2m3.ll index c7942f5237..122ecf61ab 100644 --- a/intrinsics/probes/mma_m16n8k32_f16_e4m3_e2m3.ll +++ b/intrinsics/probes/mma_m16n8k32_f16_e4m3_e2m3.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_m16n8k32_f16_e4m3_e3m2.ll b/intrinsics/probes/mma_m16n8k32_f16_e4m3_e3m2.ll index b02c658045..88d9f5d974 100644 --- a/intrinsics/probes/mma_m16n8k32_f16_e4m3_e3m2.ll +++ b/intrinsics/probes/mma_m16n8k32_f16_e4m3_e3m2.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_m16n8k32_f16_e4m3_e4m3.ll b/intrinsics/probes/mma_m16n8k32_f16_e4m3_e4m3.ll index 214e8ce49a..9c98aababe 100644 --- a/intrinsics/probes/mma_m16n8k32_f16_e4m3_e4m3.ll +++ b/intrinsics/probes/mma_m16n8k32_f16_e4m3_e4m3.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_m16n8k32_f16_e4m3_e5m2.ll b/intrinsics/probes/mma_m16n8k32_f16_e4m3_e5m2.ll index b2c618b81d..30ce429238 100644 --- a/intrinsics/probes/mma_m16n8k32_f16_e4m3_e5m2.ll +++ b/intrinsics/probes/mma_m16n8k32_f16_e4m3_e5m2.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_m16n8k32_f16_e5m2_e2m1.ll b/intrinsics/probes/mma_m16n8k32_f16_e5m2_e2m1.ll index aba5c1ceff..4d6316516f 100644 --- a/intrinsics/probes/mma_m16n8k32_f16_e5m2_e2m1.ll +++ b/intrinsics/probes/mma_m16n8k32_f16_e5m2_e2m1.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_m16n8k32_f16_e5m2_e2m3.ll b/intrinsics/probes/mma_m16n8k32_f16_e5m2_e2m3.ll index d69bbc42e9..17983dbfd2 100644 --- a/intrinsics/probes/mma_m16n8k32_f16_e5m2_e2m3.ll +++ b/intrinsics/probes/mma_m16n8k32_f16_e5m2_e2m3.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_m16n8k32_f16_e5m2_e3m2.ll b/intrinsics/probes/mma_m16n8k32_f16_e5m2_e3m2.ll index d76ed64f79..2f25c616d6 100644 --- a/intrinsics/probes/mma_m16n8k32_f16_e5m2_e3m2.ll +++ b/intrinsics/probes/mma_m16n8k32_f16_e5m2_e3m2.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_m16n8k32_f16_e5m2_e4m3.ll b/intrinsics/probes/mma_m16n8k32_f16_e5m2_e4m3.ll index d2b1e58418..509511a7d4 100644 --- a/intrinsics/probes/mma_m16n8k32_f16_e5m2_e4m3.ll +++ b/intrinsics/probes/mma_m16n8k32_f16_e5m2_e4m3.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_m16n8k32_f16_e5m2_e5m2.ll b/intrinsics/probes/mma_m16n8k32_f16_e5m2_e5m2.ll index 6be5786635..e685083699 100644 --- a/intrinsics/probes/mma_m16n8k32_f16_e5m2_e5m2.ll +++ b/intrinsics/probes/mma_m16n8k32_f16_e5m2_e5m2.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_m16n8k32_f32_e2m1_e2m1.ll b/intrinsics/probes/mma_m16n8k32_f32_e2m1_e2m1.ll index 534c6b5418..f558c8aa6d 100644 --- a/intrinsics/probes/mma_m16n8k32_f32_e2m1_e2m1.ll +++ b/intrinsics/probes/mma_m16n8k32_f32_e2m1_e2m1.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_m16n8k32_f32_e2m1_e2m3.ll b/intrinsics/probes/mma_m16n8k32_f32_e2m1_e2m3.ll index fc48afb440..27374c561e 100644 --- a/intrinsics/probes/mma_m16n8k32_f32_e2m1_e2m3.ll +++ b/intrinsics/probes/mma_m16n8k32_f32_e2m1_e2m3.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_m16n8k32_f32_e2m1_e3m2.ll b/intrinsics/probes/mma_m16n8k32_f32_e2m1_e3m2.ll index 921ddc4652..a231e5a818 100644 --- a/intrinsics/probes/mma_m16n8k32_f32_e2m1_e3m2.ll +++ b/intrinsics/probes/mma_m16n8k32_f32_e2m1_e3m2.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_m16n8k32_f32_e2m1_e4m3.ll b/intrinsics/probes/mma_m16n8k32_f32_e2m1_e4m3.ll index 6c6254e94a..98f85c1ba0 100644 --- a/intrinsics/probes/mma_m16n8k32_f32_e2m1_e4m3.ll +++ b/intrinsics/probes/mma_m16n8k32_f32_e2m1_e4m3.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_m16n8k32_f32_e2m1_e5m2.ll b/intrinsics/probes/mma_m16n8k32_f32_e2m1_e5m2.ll index ca84ab85fe..818152e909 100644 --- a/intrinsics/probes/mma_m16n8k32_f32_e2m1_e5m2.ll +++ b/intrinsics/probes/mma_m16n8k32_f32_e2m1_e5m2.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_m16n8k32_f32_e2m3_e2m1.ll b/intrinsics/probes/mma_m16n8k32_f32_e2m3_e2m1.ll index f62cb62051..34a5b080b1 100644 --- a/intrinsics/probes/mma_m16n8k32_f32_e2m3_e2m1.ll +++ b/intrinsics/probes/mma_m16n8k32_f32_e2m3_e2m1.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_m16n8k32_f32_e2m3_e2m3.ll b/intrinsics/probes/mma_m16n8k32_f32_e2m3_e2m3.ll index d0f1b79b50..2184908fb0 100644 --- a/intrinsics/probes/mma_m16n8k32_f32_e2m3_e2m3.ll +++ b/intrinsics/probes/mma_m16n8k32_f32_e2m3_e2m3.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_m16n8k32_f32_e2m3_e3m2.ll b/intrinsics/probes/mma_m16n8k32_f32_e2m3_e3m2.ll index 8b7400000d..54cb13decd 100644 --- a/intrinsics/probes/mma_m16n8k32_f32_e2m3_e3m2.ll +++ b/intrinsics/probes/mma_m16n8k32_f32_e2m3_e3m2.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_m16n8k32_f32_e2m3_e4m3.ll b/intrinsics/probes/mma_m16n8k32_f32_e2m3_e4m3.ll index 36d4acc82e..0c3bb1b602 100644 --- a/intrinsics/probes/mma_m16n8k32_f32_e2m3_e4m3.ll +++ b/intrinsics/probes/mma_m16n8k32_f32_e2m3_e4m3.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_m16n8k32_f32_e2m3_e5m2.ll b/intrinsics/probes/mma_m16n8k32_f32_e2m3_e5m2.ll index ff1a29d8c4..70188c00db 100644 --- a/intrinsics/probes/mma_m16n8k32_f32_e2m3_e5m2.ll +++ b/intrinsics/probes/mma_m16n8k32_f32_e2m3_e5m2.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_m16n8k32_f32_e3m2_e2m1.ll b/intrinsics/probes/mma_m16n8k32_f32_e3m2_e2m1.ll index 675559b88e..77e67dd17d 100644 --- a/intrinsics/probes/mma_m16n8k32_f32_e3m2_e2m1.ll +++ b/intrinsics/probes/mma_m16n8k32_f32_e3m2_e2m1.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_m16n8k32_f32_e3m2_e2m3.ll b/intrinsics/probes/mma_m16n8k32_f32_e3m2_e2m3.ll index 26750a2c27..19246c6c46 100644 --- a/intrinsics/probes/mma_m16n8k32_f32_e3m2_e2m3.ll +++ b/intrinsics/probes/mma_m16n8k32_f32_e3m2_e2m3.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_m16n8k32_f32_e3m2_e3m2.ll b/intrinsics/probes/mma_m16n8k32_f32_e3m2_e3m2.ll index 9066ed9835..92fc65f06d 100644 --- a/intrinsics/probes/mma_m16n8k32_f32_e3m2_e3m2.ll +++ b/intrinsics/probes/mma_m16n8k32_f32_e3m2_e3m2.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_m16n8k32_f32_e3m2_e4m3.ll b/intrinsics/probes/mma_m16n8k32_f32_e3m2_e4m3.ll index 8745a9c412..dcb592bef0 100644 --- a/intrinsics/probes/mma_m16n8k32_f32_e3m2_e4m3.ll +++ b/intrinsics/probes/mma_m16n8k32_f32_e3m2_e4m3.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_m16n8k32_f32_e3m2_e5m2.ll b/intrinsics/probes/mma_m16n8k32_f32_e3m2_e5m2.ll index 73c24fe4f0..300291a768 100644 --- a/intrinsics/probes/mma_m16n8k32_f32_e3m2_e5m2.ll +++ b/intrinsics/probes/mma_m16n8k32_f32_e3m2_e5m2.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_m16n8k32_f32_e4m3_e2m1.ll b/intrinsics/probes/mma_m16n8k32_f32_e4m3_e2m1.ll index 0aaa6bc3b3..48b896573d 100644 --- a/intrinsics/probes/mma_m16n8k32_f32_e4m3_e2m1.ll +++ b/intrinsics/probes/mma_m16n8k32_f32_e4m3_e2m1.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_m16n8k32_f32_e4m3_e2m3.ll b/intrinsics/probes/mma_m16n8k32_f32_e4m3_e2m3.ll index 4c362572ed..80638f55d0 100644 --- a/intrinsics/probes/mma_m16n8k32_f32_e4m3_e2m3.ll +++ b/intrinsics/probes/mma_m16n8k32_f32_e4m3_e2m3.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_m16n8k32_f32_e4m3_e3m2.ll b/intrinsics/probes/mma_m16n8k32_f32_e4m3_e3m2.ll index 592de581ef..ff76caae5d 100644 --- a/intrinsics/probes/mma_m16n8k32_f32_e4m3_e3m2.ll +++ b/intrinsics/probes/mma_m16n8k32_f32_e4m3_e3m2.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_m16n8k32_f32_e4m3_e4m3.ll b/intrinsics/probes/mma_m16n8k32_f32_e4m3_e4m3.ll index 46e477ed88..bd0e022344 100644 --- a/intrinsics/probes/mma_m16n8k32_f32_e4m3_e4m3.ll +++ b/intrinsics/probes/mma_m16n8k32_f32_e4m3_e4m3.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_m16n8k32_f32_e4m3_e5m2.ll b/intrinsics/probes/mma_m16n8k32_f32_e4m3_e5m2.ll index ddfe314e8a..b626b4a7f7 100644 --- a/intrinsics/probes/mma_m16n8k32_f32_e4m3_e5m2.ll +++ b/intrinsics/probes/mma_m16n8k32_f32_e4m3_e5m2.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_m16n8k32_f32_e5m2_e2m1.ll b/intrinsics/probes/mma_m16n8k32_f32_e5m2_e2m1.ll index b84a4bb973..645a9bed4c 100644 --- a/intrinsics/probes/mma_m16n8k32_f32_e5m2_e2m1.ll +++ b/intrinsics/probes/mma_m16n8k32_f32_e5m2_e2m1.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_m16n8k32_f32_e5m2_e2m3.ll b/intrinsics/probes/mma_m16n8k32_f32_e5m2_e2m3.ll index 5bce42cb65..8dbf6b5316 100644 --- a/intrinsics/probes/mma_m16n8k32_f32_e5m2_e2m3.ll +++ b/intrinsics/probes/mma_m16n8k32_f32_e5m2_e2m3.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_m16n8k32_f32_e5m2_e3m2.ll b/intrinsics/probes/mma_m16n8k32_f32_e5m2_e3m2.ll index d00fa873d0..573694480c 100644 --- a/intrinsics/probes/mma_m16n8k32_f32_e5m2_e3m2.ll +++ b/intrinsics/probes/mma_m16n8k32_f32_e5m2_e3m2.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_m16n8k32_f32_e5m2_e4m3.ll b/intrinsics/probes/mma_m16n8k32_f32_e5m2_e4m3.ll index f6e76da29e..29b717dd38 100644 --- a/intrinsics/probes/mma_m16n8k32_f32_e5m2_e4m3.ll +++ b/intrinsics/probes/mma_m16n8k32_f32_e5m2_e4m3.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_m16n8k32_f32_e5m2_e5m2.ll b/intrinsics/probes/mma_m16n8k32_f32_e5m2_e5m2.ll index 58799720c1..9eb5157034 100644 --- a/intrinsics/probes/mma_m16n8k32_f32_e5m2_e5m2.ll +++ b/intrinsics/probes/mma_m16n8k32_f32_e5m2_e5m2.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_m16n8k32_fp8_f16_e4m3_e4m3.ll b/intrinsics/probes/mma_m16n8k32_fp8_f16_e4m3_e4m3.ll index 9ffdf7a521..af1e6fea90 100644 --- a/intrinsics/probes/mma_m16n8k32_fp8_f16_e4m3_e4m3.ll +++ b/intrinsics/probes/mma_m16n8k32_fp8_f16_e4m3_e4m3.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_m16n8k32_fp8_f16_e4m3_e5m2.ll b/intrinsics/probes/mma_m16n8k32_fp8_f16_e4m3_e5m2.ll index b61b0d4266..a805059f98 100644 --- a/intrinsics/probes/mma_m16n8k32_fp8_f16_e4m3_e5m2.ll +++ b/intrinsics/probes/mma_m16n8k32_fp8_f16_e4m3_e5m2.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_m16n8k32_fp8_f16_e5m2_e4m3.ll b/intrinsics/probes/mma_m16n8k32_fp8_f16_e5m2_e4m3.ll index 979bdb5ba2..53d6fc4fea 100644 --- a/intrinsics/probes/mma_m16n8k32_fp8_f16_e5m2_e4m3.ll +++ b/intrinsics/probes/mma_m16n8k32_fp8_f16_e5m2_e4m3.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_m16n8k32_fp8_f16_e5m2_e5m2.ll b/intrinsics/probes/mma_m16n8k32_fp8_f16_e5m2_e5m2.ll index 7680b9bd2a..1f2bfa4cc8 100644 --- a/intrinsics/probes/mma_m16n8k32_fp8_f16_e5m2_e5m2.ll +++ b/intrinsics/probes/mma_m16n8k32_fp8_f16_e5m2_e5m2.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_m16n8k32_fp8_f32_e4m3_e4m3.ll b/intrinsics/probes/mma_m16n8k32_fp8_f32_e4m3_e4m3.ll index b7d2462f8c..63cd8f65bf 100644 --- a/intrinsics/probes/mma_m16n8k32_fp8_f32_e4m3_e4m3.ll +++ b/intrinsics/probes/mma_m16n8k32_fp8_f32_e4m3_e4m3.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_m16n8k32_fp8_f32_e4m3_e5m2.ll b/intrinsics/probes/mma_m16n8k32_fp8_f32_e4m3_e5m2.ll index ae1c4823ac..420e65caaf 100644 --- a/intrinsics/probes/mma_m16n8k32_fp8_f32_e4m3_e5m2.ll +++ b/intrinsics/probes/mma_m16n8k32_fp8_f32_e4m3_e5m2.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_m16n8k32_fp8_f32_e5m2_e4m3.ll b/intrinsics/probes/mma_m16n8k32_fp8_f32_e5m2_e4m3.ll index e5f0349319..6a2679c8df 100644 --- a/intrinsics/probes/mma_m16n8k32_fp8_f32_e5m2_e4m3.ll +++ b/intrinsics/probes/mma_m16n8k32_fp8_f32_e5m2_e4m3.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_m16n8k32_fp8_f32_e5m2_e5m2.ll b/intrinsics/probes/mma_m16n8k32_fp8_f32_e5m2_e5m2.ll index 582c04886f..245a90762d 100644 --- a/intrinsics/probes/mma_m16n8k32_fp8_f32_e5m2_e5m2.ll +++ b/intrinsics/probes/mma_m16n8k32_fp8_f32_e5m2_e5m2.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_m16n8k32_mxf8f6f4_f32_e2m1_e2m1.ll b/intrinsics/probes/mma_m16n8k32_mxf8f6f4_f32_e2m1_e2m1.ll index 4e1b39643a..fd6873d525 100644 --- a/intrinsics/probes/mma_m16n8k32_mxf8f6f4_f32_e2m1_e2m1.ll +++ b/intrinsics/probes/mma_m16n8k32_mxf8f6f4_f32_e2m1_e2m1.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_m16n8k32_mxf8f6f4_f32_e2m1_e2m3.ll b/intrinsics/probes/mma_m16n8k32_mxf8f6f4_f32_e2m1_e2m3.ll index 49b2b5c3c6..19e9c42f61 100644 --- a/intrinsics/probes/mma_m16n8k32_mxf8f6f4_f32_e2m1_e2m3.ll +++ b/intrinsics/probes/mma_m16n8k32_mxf8f6f4_f32_e2m1_e2m3.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_m16n8k32_mxf8f6f4_f32_e2m1_e3m2.ll b/intrinsics/probes/mma_m16n8k32_mxf8f6f4_f32_e2m1_e3m2.ll index a853bef9fa..f4f3e0b365 100644 --- a/intrinsics/probes/mma_m16n8k32_mxf8f6f4_f32_e2m1_e3m2.ll +++ b/intrinsics/probes/mma_m16n8k32_mxf8f6f4_f32_e2m1_e3m2.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_m16n8k32_mxf8f6f4_f32_e2m1_e4m3.ll b/intrinsics/probes/mma_m16n8k32_mxf8f6f4_f32_e2m1_e4m3.ll index 5d64313e00..7511e79983 100644 --- a/intrinsics/probes/mma_m16n8k32_mxf8f6f4_f32_e2m1_e4m3.ll +++ b/intrinsics/probes/mma_m16n8k32_mxf8f6f4_f32_e2m1_e4m3.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_m16n8k32_mxf8f6f4_f32_e2m1_e5m2.ll b/intrinsics/probes/mma_m16n8k32_mxf8f6f4_f32_e2m1_e5m2.ll index b64092192f..1e08ad76c9 100644 --- a/intrinsics/probes/mma_m16n8k32_mxf8f6f4_f32_e2m1_e5m2.ll +++ b/intrinsics/probes/mma_m16n8k32_mxf8f6f4_f32_e2m1_e5m2.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_m16n8k32_mxf8f6f4_f32_e2m3_e2m1.ll b/intrinsics/probes/mma_m16n8k32_mxf8f6f4_f32_e2m3_e2m1.ll index b4706b1e98..5687aef22e 100644 --- a/intrinsics/probes/mma_m16n8k32_mxf8f6f4_f32_e2m3_e2m1.ll +++ b/intrinsics/probes/mma_m16n8k32_mxf8f6f4_f32_e2m3_e2m1.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_m16n8k32_mxf8f6f4_f32_e2m3_e2m3.ll b/intrinsics/probes/mma_m16n8k32_mxf8f6f4_f32_e2m3_e2m3.ll index 604d7c6bb5..fc737ce6d9 100644 --- a/intrinsics/probes/mma_m16n8k32_mxf8f6f4_f32_e2m3_e2m3.ll +++ b/intrinsics/probes/mma_m16n8k32_mxf8f6f4_f32_e2m3_e2m3.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_m16n8k32_mxf8f6f4_f32_e2m3_e3m2.ll b/intrinsics/probes/mma_m16n8k32_mxf8f6f4_f32_e2m3_e3m2.ll index dab52abf17..bd94386f45 100644 --- a/intrinsics/probes/mma_m16n8k32_mxf8f6f4_f32_e2m3_e3m2.ll +++ b/intrinsics/probes/mma_m16n8k32_mxf8f6f4_f32_e2m3_e3m2.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_m16n8k32_mxf8f6f4_f32_e2m3_e4m3.ll b/intrinsics/probes/mma_m16n8k32_mxf8f6f4_f32_e2m3_e4m3.ll index 3af5407678..783a062938 100644 --- a/intrinsics/probes/mma_m16n8k32_mxf8f6f4_f32_e2m3_e4m3.ll +++ b/intrinsics/probes/mma_m16n8k32_mxf8f6f4_f32_e2m3_e4m3.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_m16n8k32_mxf8f6f4_f32_e2m3_e5m2.ll b/intrinsics/probes/mma_m16n8k32_mxf8f6f4_f32_e2m3_e5m2.ll index 4b3aaf2a82..ae151a2cef 100644 --- a/intrinsics/probes/mma_m16n8k32_mxf8f6f4_f32_e2m3_e5m2.ll +++ b/intrinsics/probes/mma_m16n8k32_mxf8f6f4_f32_e2m3_e5m2.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_m16n8k32_mxf8f6f4_f32_e3m2_e2m1.ll b/intrinsics/probes/mma_m16n8k32_mxf8f6f4_f32_e3m2_e2m1.ll index 17181b8ae6..2a12c79edc 100644 --- a/intrinsics/probes/mma_m16n8k32_mxf8f6f4_f32_e3m2_e2m1.ll +++ b/intrinsics/probes/mma_m16n8k32_mxf8f6f4_f32_e3m2_e2m1.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_m16n8k32_mxf8f6f4_f32_e3m2_e2m3.ll b/intrinsics/probes/mma_m16n8k32_mxf8f6f4_f32_e3m2_e2m3.ll index 7fcaac01d7..cbd3b307b6 100644 --- a/intrinsics/probes/mma_m16n8k32_mxf8f6f4_f32_e3m2_e2m3.ll +++ b/intrinsics/probes/mma_m16n8k32_mxf8f6f4_f32_e3m2_e2m3.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_m16n8k32_mxf8f6f4_f32_e3m2_e3m2.ll b/intrinsics/probes/mma_m16n8k32_mxf8f6f4_f32_e3m2_e3m2.ll index f467003f98..bfea8be55c 100644 --- a/intrinsics/probes/mma_m16n8k32_mxf8f6f4_f32_e3m2_e3m2.ll +++ b/intrinsics/probes/mma_m16n8k32_mxf8f6f4_f32_e3m2_e3m2.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_m16n8k32_mxf8f6f4_f32_e3m2_e4m3.ll b/intrinsics/probes/mma_m16n8k32_mxf8f6f4_f32_e3m2_e4m3.ll index 33ac413e9f..cd9fbadf95 100644 --- a/intrinsics/probes/mma_m16n8k32_mxf8f6f4_f32_e3m2_e4m3.ll +++ b/intrinsics/probes/mma_m16n8k32_mxf8f6f4_f32_e3m2_e4m3.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_m16n8k32_mxf8f6f4_f32_e3m2_e5m2.ll b/intrinsics/probes/mma_m16n8k32_mxf8f6f4_f32_e3m2_e5m2.ll index e1eb59ce5f..652caed1da 100644 --- a/intrinsics/probes/mma_m16n8k32_mxf8f6f4_f32_e3m2_e5m2.ll +++ b/intrinsics/probes/mma_m16n8k32_mxf8f6f4_f32_e3m2_e5m2.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_m16n8k32_mxf8f6f4_f32_e4m3_e2m1.ll b/intrinsics/probes/mma_m16n8k32_mxf8f6f4_f32_e4m3_e2m1.ll index 6d321f7cfd..ce0a83ebd0 100644 --- a/intrinsics/probes/mma_m16n8k32_mxf8f6f4_f32_e4m3_e2m1.ll +++ b/intrinsics/probes/mma_m16n8k32_mxf8f6f4_f32_e4m3_e2m1.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_m16n8k32_mxf8f6f4_f32_e4m3_e2m3.ll b/intrinsics/probes/mma_m16n8k32_mxf8f6f4_f32_e4m3_e2m3.ll index 9fb3ec0965..c800a1b4ae 100644 --- a/intrinsics/probes/mma_m16n8k32_mxf8f6f4_f32_e4m3_e2m3.ll +++ b/intrinsics/probes/mma_m16n8k32_mxf8f6f4_f32_e4m3_e2m3.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_m16n8k32_mxf8f6f4_f32_e4m3_e3m2.ll b/intrinsics/probes/mma_m16n8k32_mxf8f6f4_f32_e4m3_e3m2.ll index 38e473f0a3..783d264c13 100644 --- a/intrinsics/probes/mma_m16n8k32_mxf8f6f4_f32_e4m3_e3m2.ll +++ b/intrinsics/probes/mma_m16n8k32_mxf8f6f4_f32_e4m3_e3m2.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_m16n8k32_mxf8f6f4_f32_e4m3_e4m3.ll b/intrinsics/probes/mma_m16n8k32_mxf8f6f4_f32_e4m3_e4m3.ll index 22a18b67ea..ed83846af8 100644 --- a/intrinsics/probes/mma_m16n8k32_mxf8f6f4_f32_e4m3_e4m3.ll +++ b/intrinsics/probes/mma_m16n8k32_mxf8f6f4_f32_e4m3_e4m3.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_m16n8k32_mxf8f6f4_f32_e4m3_e5m2.ll b/intrinsics/probes/mma_m16n8k32_mxf8f6f4_f32_e4m3_e5m2.ll index 49355dadcf..880df97517 100644 --- a/intrinsics/probes/mma_m16n8k32_mxf8f6f4_f32_e4m3_e5m2.ll +++ b/intrinsics/probes/mma_m16n8k32_mxf8f6f4_f32_e4m3_e5m2.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_m16n8k32_mxf8f6f4_f32_e5m2_e2m1.ll b/intrinsics/probes/mma_m16n8k32_mxf8f6f4_f32_e5m2_e2m1.ll index 2e1b32e00b..c435b7eab3 100644 --- a/intrinsics/probes/mma_m16n8k32_mxf8f6f4_f32_e5m2_e2m1.ll +++ b/intrinsics/probes/mma_m16n8k32_mxf8f6f4_f32_e5m2_e2m1.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_m16n8k32_mxf8f6f4_f32_e5m2_e2m3.ll b/intrinsics/probes/mma_m16n8k32_mxf8f6f4_f32_e5m2_e2m3.ll index e516c2d07b..21b1bdd7d0 100644 --- a/intrinsics/probes/mma_m16n8k32_mxf8f6f4_f32_e5m2_e2m3.ll +++ b/intrinsics/probes/mma_m16n8k32_mxf8f6f4_f32_e5m2_e2m3.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_m16n8k32_mxf8f6f4_f32_e5m2_e3m2.ll b/intrinsics/probes/mma_m16n8k32_mxf8f6f4_f32_e5m2_e3m2.ll index 68318be186..f23e3bef97 100644 --- a/intrinsics/probes/mma_m16n8k32_mxf8f6f4_f32_e5m2_e3m2.ll +++ b/intrinsics/probes/mma_m16n8k32_mxf8f6f4_f32_e5m2_e3m2.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_m16n8k32_mxf8f6f4_f32_e5m2_e4m3.ll b/intrinsics/probes/mma_m16n8k32_mxf8f6f4_f32_e5m2_e4m3.ll index 8c2fa23bc7..99cf6e2c1c 100644 --- a/intrinsics/probes/mma_m16n8k32_mxf8f6f4_f32_e5m2_e4m3.ll +++ b/intrinsics/probes/mma_m16n8k32_mxf8f6f4_f32_e5m2_e4m3.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_m16n8k32_mxf8f6f4_f32_e5m2_e5m2.ll b/intrinsics/probes/mma_m16n8k32_mxf8f6f4_f32_e5m2_e5m2.ll index 6ce9a71e57..388609b60a 100644 --- a/intrinsics/probes/mma_m16n8k32_mxf8f6f4_f32_e5m2_e5m2.ll +++ b/intrinsics/probes/mma_m16n8k32_mxf8f6f4_f32_e5m2_e5m2.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_m16n8k32_s32_s4.ll b/intrinsics/probes/mma_m16n8k32_s32_s4.ll index dd00d52b90..a195abaad4 100644 --- a/intrinsics/probes/mma_m16n8k32_s32_s4.ll +++ b/intrinsics/probes/mma_m16n8k32_s32_s4.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_m16n8k32_s32_s4_satfinite.ll b/intrinsics/probes/mma_m16n8k32_s32_s4_satfinite.ll index 53aea41379..230d2c6c30 100644 --- a/intrinsics/probes/mma_m16n8k32_s32_s4_satfinite.ll +++ b/intrinsics/probes/mma_m16n8k32_s32_s4_satfinite.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_m16n8k32_s32_s4_u4.ll b/intrinsics/probes/mma_m16n8k32_s32_s4_u4.ll index 2539412aed..01e757e693 100644 --- a/intrinsics/probes/mma_m16n8k32_s32_s4_u4.ll +++ b/intrinsics/probes/mma_m16n8k32_s32_s4_u4.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_m16n8k32_s32_s4_u4_satfinite.ll b/intrinsics/probes/mma_m16n8k32_s32_s4_u4_satfinite.ll index dcf2f02e92..cbd2615cab 100644 --- a/intrinsics/probes/mma_m16n8k32_s32_s4_u4_satfinite.ll +++ b/intrinsics/probes/mma_m16n8k32_s32_s4_u4_satfinite.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_m16n8k32_s32_s8.ll b/intrinsics/probes/mma_m16n8k32_s32_s8.ll index 15c5a28ba9..2186eebcfe 100644 --- a/intrinsics/probes/mma_m16n8k32_s32_s8.ll +++ b/intrinsics/probes/mma_m16n8k32_s32_s8.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_m16n8k32_s32_s8_satfinite.ll b/intrinsics/probes/mma_m16n8k32_s32_s8_satfinite.ll index 03b46a145c..1a713ea410 100644 --- a/intrinsics/probes/mma_m16n8k32_s32_s8_satfinite.ll +++ b/intrinsics/probes/mma_m16n8k32_s32_s8_satfinite.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_m16n8k32_s32_s8_u8.ll b/intrinsics/probes/mma_m16n8k32_s32_s8_u8.ll index cbfd42c804..92ddbbb8f2 100644 --- a/intrinsics/probes/mma_m16n8k32_s32_s8_u8.ll +++ b/intrinsics/probes/mma_m16n8k32_s32_s8_u8.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_m16n8k32_s32_s8_u8_satfinite.ll b/intrinsics/probes/mma_m16n8k32_s32_s8_u8_satfinite.ll index 4e5b02e3b4..d06d01b015 100644 --- a/intrinsics/probes/mma_m16n8k32_s32_s8_u8_satfinite.ll +++ b/intrinsics/probes/mma_m16n8k32_s32_s8_u8_satfinite.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_m16n8k32_s32_u4.ll b/intrinsics/probes/mma_m16n8k32_s32_u4.ll index 05f2570e0e..ca5c3b8d4b 100644 --- a/intrinsics/probes/mma_m16n8k32_s32_u4.ll +++ b/intrinsics/probes/mma_m16n8k32_s32_u4.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_m16n8k32_s32_u4_s4.ll b/intrinsics/probes/mma_m16n8k32_s32_u4_s4.ll index 08626837b0..d6bba89da6 100644 --- a/intrinsics/probes/mma_m16n8k32_s32_u4_s4.ll +++ b/intrinsics/probes/mma_m16n8k32_s32_u4_s4.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_m16n8k32_s32_u4_s4_satfinite.ll b/intrinsics/probes/mma_m16n8k32_s32_u4_s4_satfinite.ll index 5585b9bc02..676ef2f5b7 100644 --- a/intrinsics/probes/mma_m16n8k32_s32_u4_s4_satfinite.ll +++ b/intrinsics/probes/mma_m16n8k32_s32_u4_s4_satfinite.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_m16n8k32_s32_u4_satfinite.ll b/intrinsics/probes/mma_m16n8k32_s32_u4_satfinite.ll index d09f8a5373..20c361ae33 100644 --- a/intrinsics/probes/mma_m16n8k32_s32_u4_satfinite.ll +++ b/intrinsics/probes/mma_m16n8k32_s32_u4_satfinite.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_m16n8k32_s32_u8.ll b/intrinsics/probes/mma_m16n8k32_s32_u8.ll index f5689413a3..10a7ea0b9c 100644 --- a/intrinsics/probes/mma_m16n8k32_s32_u8.ll +++ b/intrinsics/probes/mma_m16n8k32_s32_u8.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_m16n8k32_s32_u8_s8.ll b/intrinsics/probes/mma_m16n8k32_s32_u8_s8.ll index ad48c2420c..e394a6748a 100644 --- a/intrinsics/probes/mma_m16n8k32_s32_u8_s8.ll +++ b/intrinsics/probes/mma_m16n8k32_s32_u8_s8.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_m16n8k32_s32_u8_s8_satfinite.ll b/intrinsics/probes/mma_m16n8k32_s32_u8_s8_satfinite.ll index 3596d84db3..c27dd64699 100644 --- a/intrinsics/probes/mma_m16n8k32_s32_u8_s8_satfinite.ll +++ b/intrinsics/probes/mma_m16n8k32_s32_u8_s8_satfinite.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_m16n8k32_s32_u8_satfinite.ll b/intrinsics/probes/mma_m16n8k32_s32_u8_satfinite.ll index d0f92439ed..c391a20dc1 100644 --- a/intrinsics/probes/mma_m16n8k32_s32_u8_satfinite.ll +++ b/intrinsics/probes/mma_m16n8k32_s32_u8_satfinite.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_m16n8k4_f32_tf32.ll b/intrinsics/probes/mma_m16n8k4_f32_tf32.ll index 529a9d8b2c..e8854438b7 100644 --- a/intrinsics/probes/mma_m16n8k4_f32_tf32.ll +++ b/intrinsics/probes/mma_m16n8k4_f32_tf32.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_m16n8k64_s32_s4.ll b/intrinsics/probes/mma_m16n8k64_s32_s4.ll index 8112d0d6e2..40b1baeeef 100644 --- a/intrinsics/probes/mma_m16n8k64_s32_s4.ll +++ b/intrinsics/probes/mma_m16n8k64_s32_s4.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_m16n8k64_s32_s4_satfinite.ll b/intrinsics/probes/mma_m16n8k64_s32_s4_satfinite.ll index 8d4c647d24..bab816bc17 100644 --- a/intrinsics/probes/mma_m16n8k64_s32_s4_satfinite.ll +++ b/intrinsics/probes/mma_m16n8k64_s32_s4_satfinite.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_m16n8k64_s32_s4_u4.ll b/intrinsics/probes/mma_m16n8k64_s32_s4_u4.ll index b85541ddce..eaca5fd13d 100644 --- a/intrinsics/probes/mma_m16n8k64_s32_s4_u4.ll +++ b/intrinsics/probes/mma_m16n8k64_s32_s4_u4.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_m16n8k64_s32_s4_u4_satfinite.ll b/intrinsics/probes/mma_m16n8k64_s32_s4_u4_satfinite.ll index 3101a6ecfb..056fe803e1 100644 --- a/intrinsics/probes/mma_m16n8k64_s32_s4_u4_satfinite.ll +++ b/intrinsics/probes/mma_m16n8k64_s32_s4_u4_satfinite.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_m16n8k64_s32_u4.ll b/intrinsics/probes/mma_m16n8k64_s32_u4.ll index c2710460ec..fe68a56a63 100644 --- a/intrinsics/probes/mma_m16n8k64_s32_u4.ll +++ b/intrinsics/probes/mma_m16n8k64_s32_u4.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_m16n8k64_s32_u4_s4.ll b/intrinsics/probes/mma_m16n8k64_s32_u4_s4.ll index e4875059e6..0eb1a62cd1 100644 --- a/intrinsics/probes/mma_m16n8k64_s32_u4_s4.ll +++ b/intrinsics/probes/mma_m16n8k64_s32_u4_s4.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_m16n8k64_s32_u4_s4_satfinite.ll b/intrinsics/probes/mma_m16n8k64_s32_u4_s4_satfinite.ll index efd002614c..94d7442f76 100644 --- a/intrinsics/probes/mma_m16n8k64_s32_u4_s4_satfinite.ll +++ b/intrinsics/probes/mma_m16n8k64_s32_u4_s4_satfinite.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_m16n8k64_s32_u4_satfinite.ll b/intrinsics/probes/mma_m16n8k64_s32_u4_satfinite.ll index a176fe7f17..ed36c49402 100644 --- a/intrinsics/probes/mma_m16n8k64_s32_u4_satfinite.ll +++ b/intrinsics/probes/mma_m16n8k64_s32_u4_satfinite.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_m16n8k8_f16_f16.ll b/intrinsics/probes/mma_m16n8k8_f16_f16.ll index 86fcb2189b..8941b8ab15 100644 --- a/intrinsics/probes/mma_m16n8k8_f16_f16.ll +++ b/intrinsics/probes/mma_m16n8k8_f16_f16.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_m16n8k8_f32_bf16.ll b/intrinsics/probes/mma_m16n8k8_f32_bf16.ll index 48e0aaeeca..e06b39bddb 100644 --- a/intrinsics/probes/mma_m16n8k8_f32_bf16.ll +++ b/intrinsics/probes/mma_m16n8k8_f32_bf16.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_m16n8k8_f32_f16.ll b/intrinsics/probes/mma_m16n8k8_f32_f16.ll index 0894887050..51d639e2b7 100644 --- a/intrinsics/probes/mma_m16n8k8_f32_f16.ll +++ b/intrinsics/probes/mma_m16n8k8_f32_f16.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_m16n8k8_f32_tf32.ll b/intrinsics/probes/mma_m16n8k8_f32_tf32.ll index 463936d32c..4245019b4a 100644 --- a/intrinsics/probes/mma_m16n8k8_f32_tf32.ll +++ b/intrinsics/probes/mma_m16n8k8_f32_tf32.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_m8n8k128_s32_b1_and_popc.ll b/intrinsics/probes/mma_m8n8k128_s32_b1_and_popc.ll index 08aa62eaad..7bbbb15ec5 100644 --- a/intrinsics/probes/mma_m8n8k128_s32_b1_and_popc.ll +++ b/intrinsics/probes/mma_m8n8k128_s32_b1_and_popc.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_m8n8k128_s32_b1_xor_popc.ll b/intrinsics/probes/mma_m8n8k128_s32_b1_xor_popc.ll index a1365cdd8a..538e53ba81 100644 --- a/intrinsics/probes/mma_m8n8k128_s32_b1_xor_popc.ll +++ b/intrinsics/probes/mma_m8n8k128_s32_b1_xor_popc.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_m8n8k16_s32_s8.ll b/intrinsics/probes/mma_m8n8k16_s32_s8.ll index 0ed993821c..1d5003780f 100644 --- a/intrinsics/probes/mma_m8n8k16_s32_s8.ll +++ b/intrinsics/probes/mma_m8n8k16_s32_s8.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_m8n8k16_s32_s8_satfinite.ll b/intrinsics/probes/mma_m8n8k16_s32_s8_satfinite.ll index 359569eead..696c90fe49 100644 --- a/intrinsics/probes/mma_m8n8k16_s32_s8_satfinite.ll +++ b/intrinsics/probes/mma_m8n8k16_s32_s8_satfinite.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_m8n8k16_s32_s8_u8.ll b/intrinsics/probes/mma_m8n8k16_s32_s8_u8.ll index c559e781e7..89e090d34e 100644 --- a/intrinsics/probes/mma_m8n8k16_s32_s8_u8.ll +++ b/intrinsics/probes/mma_m8n8k16_s32_s8_u8.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_m8n8k16_s32_s8_u8_satfinite.ll b/intrinsics/probes/mma_m8n8k16_s32_s8_u8_satfinite.ll index eb257ac56e..bfc0df4c2e 100644 --- a/intrinsics/probes/mma_m8n8k16_s32_s8_u8_satfinite.ll +++ b/intrinsics/probes/mma_m8n8k16_s32_s8_u8_satfinite.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_m8n8k16_s32_u8.ll b/intrinsics/probes/mma_m8n8k16_s32_u8.ll index 852ec52d20..8d76050cc6 100644 --- a/intrinsics/probes/mma_m8n8k16_s32_u8.ll +++ b/intrinsics/probes/mma_m8n8k16_s32_u8.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_m8n8k16_s32_u8_s8.ll b/intrinsics/probes/mma_m8n8k16_s32_u8_s8.ll index c9a83b97d2..c69aaa64fd 100644 --- a/intrinsics/probes/mma_m8n8k16_s32_u8_s8.ll +++ b/intrinsics/probes/mma_m8n8k16_s32_u8_s8.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_m8n8k16_s32_u8_s8_satfinite.ll b/intrinsics/probes/mma_m8n8k16_s32_u8_s8_satfinite.ll index 3764b3587f..3d6595a8e8 100644 --- a/intrinsics/probes/mma_m8n8k16_s32_u8_s8_satfinite.ll +++ b/intrinsics/probes/mma_m8n8k16_s32_u8_s8_satfinite.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_m8n8k16_s32_u8_satfinite.ll b/intrinsics/probes/mma_m8n8k16_s32_u8_satfinite.ll index fb91705eeb..37762639da 100644 --- a/intrinsics/probes/mma_m8n8k16_s32_u8_satfinite.ll +++ b/intrinsics/probes/mma_m8n8k16_s32_u8_satfinite.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_m8n8k32_s32_s4.ll b/intrinsics/probes/mma_m8n8k32_s32_s4.ll index 980645a3dd..3015359d30 100644 --- a/intrinsics/probes/mma_m8n8k32_s32_s4.ll +++ b/intrinsics/probes/mma_m8n8k32_s32_s4.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_m8n8k32_s32_s4_satfinite.ll b/intrinsics/probes/mma_m8n8k32_s32_s4_satfinite.ll index fb55624cc5..e1f3ed4189 100644 --- a/intrinsics/probes/mma_m8n8k32_s32_s4_satfinite.ll +++ b/intrinsics/probes/mma_m8n8k32_s32_s4_satfinite.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_m8n8k32_s32_s4_u4.ll b/intrinsics/probes/mma_m8n8k32_s32_s4_u4.ll index e2ccf19978..4526b52d4d 100644 --- a/intrinsics/probes/mma_m8n8k32_s32_s4_u4.ll +++ b/intrinsics/probes/mma_m8n8k32_s32_s4_u4.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_m8n8k32_s32_s4_u4_satfinite.ll b/intrinsics/probes/mma_m8n8k32_s32_s4_u4_satfinite.ll index 747766d299..87e95e0ebb 100644 --- a/intrinsics/probes/mma_m8n8k32_s32_s4_u4_satfinite.ll +++ b/intrinsics/probes/mma_m8n8k32_s32_s4_u4_satfinite.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_m8n8k32_s32_u4.ll b/intrinsics/probes/mma_m8n8k32_s32_u4.ll index 11e76475dd..13e1e9c4f0 100644 --- a/intrinsics/probes/mma_m8n8k32_s32_u4.ll +++ b/intrinsics/probes/mma_m8n8k32_s32_u4.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_m8n8k32_s32_u4_s4.ll b/intrinsics/probes/mma_m8n8k32_s32_u4_s4.ll index 2d5b2abf70..8f7b2f1589 100644 --- a/intrinsics/probes/mma_m8n8k32_s32_u4_s4.ll +++ b/intrinsics/probes/mma_m8n8k32_s32_u4_s4.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_m8n8k32_s32_u4_s4_satfinite.ll b/intrinsics/probes/mma_m8n8k32_s32_u4_s4_satfinite.ll index 99ed673593..3833cc4061 100644 --- a/intrinsics/probes/mma_m8n8k32_s32_u4_s4_satfinite.ll +++ b/intrinsics/probes/mma_m8n8k32_s32_u4_s4_satfinite.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_m8n8k32_s32_u4_satfinite.ll b/intrinsics/probes/mma_m8n8k32_s32_u4_satfinite.ll index bee101de2c..894c1a0d82 100644 --- a/intrinsics/probes/mma_m8n8k32_s32_u4_satfinite.ll +++ b/intrinsics/probes/mma_m8n8k32_s32_u4_satfinite.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_m8n8k4_f64.ll b/intrinsics/probes/mma_m8n8k4_f64.ll index 17977f1a48..61818c435f 100644 --- a/intrinsics/probes/mma_m8n8k4_f64.ll +++ b/intrinsics/probes/mma_m8n8k4_f64.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_sp_m16n8k128_s32_s4.ll b/intrinsics/probes/mma_sp_m16n8k128_s32_s4.ll index dc613a2628..83373b11cf 100644 --- a/intrinsics/probes/mma_sp_m16n8k128_s32_s4.ll +++ b/intrinsics/probes/mma_sp_m16n8k128_s32_s4.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_sp_m16n8k128_s32_s4_satfinite.ll b/intrinsics/probes/mma_sp_m16n8k128_s32_s4_satfinite.ll index 7bde190a45..99239fd0d0 100644 --- a/intrinsics/probes/mma_sp_m16n8k128_s32_s4_satfinite.ll +++ b/intrinsics/probes/mma_sp_m16n8k128_s32_s4_satfinite.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_sp_m16n8k128_s32_s4_u4.ll b/intrinsics/probes/mma_sp_m16n8k128_s32_s4_u4.ll index 1a901e331d..9d56421d5c 100644 --- a/intrinsics/probes/mma_sp_m16n8k128_s32_s4_u4.ll +++ b/intrinsics/probes/mma_sp_m16n8k128_s32_s4_u4.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_sp_m16n8k128_s32_s4_u4_satfinite.ll b/intrinsics/probes/mma_sp_m16n8k128_s32_s4_u4_satfinite.ll index f6aa6ad571..ad6f01cd8d 100644 --- a/intrinsics/probes/mma_sp_m16n8k128_s32_s4_u4_satfinite.ll +++ b/intrinsics/probes/mma_sp_m16n8k128_s32_s4_u4_satfinite.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_sp_m16n8k128_s32_u4.ll b/intrinsics/probes/mma_sp_m16n8k128_s32_u4.ll index 0ee3a4a26b..7444412035 100644 --- a/intrinsics/probes/mma_sp_m16n8k128_s32_u4.ll +++ b/intrinsics/probes/mma_sp_m16n8k128_s32_u4.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_sp_m16n8k128_s32_u4_s4.ll b/intrinsics/probes/mma_sp_m16n8k128_s32_u4_s4.ll index 1213e594ca..62fb16fddc 100644 --- a/intrinsics/probes/mma_sp_m16n8k128_s32_u4_s4.ll +++ b/intrinsics/probes/mma_sp_m16n8k128_s32_u4_s4.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_sp_m16n8k128_s32_u4_s4_satfinite.ll b/intrinsics/probes/mma_sp_m16n8k128_s32_u4_s4_satfinite.ll index 81fae446cf..ace65a452e 100644 --- a/intrinsics/probes/mma_sp_m16n8k128_s32_u4_s4_satfinite.ll +++ b/intrinsics/probes/mma_sp_m16n8k128_s32_u4_s4_satfinite.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_sp_m16n8k128_s32_u4_satfinite.ll b/intrinsics/probes/mma_sp_m16n8k128_s32_u4_satfinite.ll index 2bc4eb536b..3f63ec0c57 100644 --- a/intrinsics/probes/mma_sp_m16n8k128_s32_u4_satfinite.ll +++ b/intrinsics/probes/mma_sp_m16n8k128_s32_u4_satfinite.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_sp_m16n8k32_s32_s8.ll b/intrinsics/probes/mma_sp_m16n8k32_s32_s8.ll index ce8ce84d62..c53c9096c5 100644 --- a/intrinsics/probes/mma_sp_m16n8k32_s32_s8.ll +++ b/intrinsics/probes/mma_sp_m16n8k32_s32_s8.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_sp_m16n8k32_s32_s8_satfinite.ll b/intrinsics/probes/mma_sp_m16n8k32_s32_s8_satfinite.ll index 5384a60c8d..473e9cb32a 100644 --- a/intrinsics/probes/mma_sp_m16n8k32_s32_s8_satfinite.ll +++ b/intrinsics/probes/mma_sp_m16n8k32_s32_s8_satfinite.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_sp_m16n8k32_s32_s8_u8.ll b/intrinsics/probes/mma_sp_m16n8k32_s32_s8_u8.ll index 2cbfcd83b9..047bf623c7 100644 --- a/intrinsics/probes/mma_sp_m16n8k32_s32_s8_u8.ll +++ b/intrinsics/probes/mma_sp_m16n8k32_s32_s8_u8.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_sp_m16n8k32_s32_s8_u8_satfinite.ll b/intrinsics/probes/mma_sp_m16n8k32_s32_s8_u8_satfinite.ll index d94c373ba7..040c92372f 100644 --- a/intrinsics/probes/mma_sp_m16n8k32_s32_s8_u8_satfinite.ll +++ b/intrinsics/probes/mma_sp_m16n8k32_s32_s8_u8_satfinite.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_sp_m16n8k32_s32_u8.ll b/intrinsics/probes/mma_sp_m16n8k32_s32_u8.ll index 9515a19ebd..76ccf61184 100644 --- a/intrinsics/probes/mma_sp_m16n8k32_s32_u8.ll +++ b/intrinsics/probes/mma_sp_m16n8k32_s32_u8.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_sp_m16n8k32_s32_u8_s8.ll b/intrinsics/probes/mma_sp_m16n8k32_s32_u8_s8.ll index b9bba170dc..5d1fc59259 100644 --- a/intrinsics/probes/mma_sp_m16n8k32_s32_u8_s8.ll +++ b/intrinsics/probes/mma_sp_m16n8k32_s32_u8_s8.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_sp_m16n8k32_s32_u8_s8_satfinite.ll b/intrinsics/probes/mma_sp_m16n8k32_s32_u8_s8_satfinite.ll index 1594408ba8..4f17791b6b 100644 --- a/intrinsics/probes/mma_sp_m16n8k32_s32_u8_s8_satfinite.ll +++ b/intrinsics/probes/mma_sp_m16n8k32_s32_u8_s8_satfinite.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_sp_m16n8k32_s32_u8_satfinite.ll b/intrinsics/probes/mma_sp_m16n8k32_s32_u8_satfinite.ll index 3f6bf74e26..b3a131063b 100644 --- a/intrinsics/probes/mma_sp_m16n8k32_s32_u8_satfinite.ll +++ b/intrinsics/probes/mma_sp_m16n8k32_s32_u8_satfinite.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_sp_m16n8k64_s32_s4.ll b/intrinsics/probes/mma_sp_m16n8k64_s32_s4.ll index 8e0c8e04dc..846ac7a4aa 100644 --- a/intrinsics/probes/mma_sp_m16n8k64_s32_s4.ll +++ b/intrinsics/probes/mma_sp_m16n8k64_s32_s4.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_sp_m16n8k64_s32_s4_satfinite.ll b/intrinsics/probes/mma_sp_m16n8k64_s32_s4_satfinite.ll index c437e19476..2a1cb6bb7e 100644 --- a/intrinsics/probes/mma_sp_m16n8k64_s32_s4_satfinite.ll +++ b/intrinsics/probes/mma_sp_m16n8k64_s32_s4_satfinite.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_sp_m16n8k64_s32_s4_u4.ll b/intrinsics/probes/mma_sp_m16n8k64_s32_s4_u4.ll index 5a096c327e..705a2a5394 100644 --- a/intrinsics/probes/mma_sp_m16n8k64_s32_s4_u4.ll +++ b/intrinsics/probes/mma_sp_m16n8k64_s32_s4_u4.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_sp_m16n8k64_s32_s4_u4_satfinite.ll b/intrinsics/probes/mma_sp_m16n8k64_s32_s4_u4_satfinite.ll index 2fe373523f..d5dc1b8379 100644 --- a/intrinsics/probes/mma_sp_m16n8k64_s32_s4_u4_satfinite.ll +++ b/intrinsics/probes/mma_sp_m16n8k64_s32_s4_u4_satfinite.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_sp_m16n8k64_s32_s8.ll b/intrinsics/probes/mma_sp_m16n8k64_s32_s8.ll index 90a3338445..a6a631a9f7 100644 --- a/intrinsics/probes/mma_sp_m16n8k64_s32_s8.ll +++ b/intrinsics/probes/mma_sp_m16n8k64_s32_s8.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_sp_m16n8k64_s32_s8_satfinite.ll b/intrinsics/probes/mma_sp_m16n8k64_s32_s8_satfinite.ll index 8f3372ae0b..a5d4243a39 100644 --- a/intrinsics/probes/mma_sp_m16n8k64_s32_s8_satfinite.ll +++ b/intrinsics/probes/mma_sp_m16n8k64_s32_s8_satfinite.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_sp_m16n8k64_s32_s8_u8.ll b/intrinsics/probes/mma_sp_m16n8k64_s32_s8_u8.ll index 464d253e6e..2f6aca2e8a 100644 --- a/intrinsics/probes/mma_sp_m16n8k64_s32_s8_u8.ll +++ b/intrinsics/probes/mma_sp_m16n8k64_s32_s8_u8.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_sp_m16n8k64_s32_s8_u8_satfinite.ll b/intrinsics/probes/mma_sp_m16n8k64_s32_s8_u8_satfinite.ll index 5642451f45..1cf65ef871 100644 --- a/intrinsics/probes/mma_sp_m16n8k64_s32_s8_u8_satfinite.ll +++ b/intrinsics/probes/mma_sp_m16n8k64_s32_s8_u8_satfinite.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_sp_m16n8k64_s32_u4.ll b/intrinsics/probes/mma_sp_m16n8k64_s32_u4.ll index 71d1df807f..142391c705 100644 --- a/intrinsics/probes/mma_sp_m16n8k64_s32_u4.ll +++ b/intrinsics/probes/mma_sp_m16n8k64_s32_u4.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_sp_m16n8k64_s32_u4_s4.ll b/intrinsics/probes/mma_sp_m16n8k64_s32_u4_s4.ll index 41d1c5e9ac..be60f81b12 100644 --- a/intrinsics/probes/mma_sp_m16n8k64_s32_u4_s4.ll +++ b/intrinsics/probes/mma_sp_m16n8k64_s32_u4_s4.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_sp_m16n8k64_s32_u4_s4_satfinite.ll b/intrinsics/probes/mma_sp_m16n8k64_s32_u4_s4_satfinite.ll index 82fb1de30e..23d8629090 100644 --- a/intrinsics/probes/mma_sp_m16n8k64_s32_u4_s4_satfinite.ll +++ b/intrinsics/probes/mma_sp_m16n8k64_s32_u4_s4_satfinite.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_sp_m16n8k64_s32_u4_satfinite.ll b/intrinsics/probes/mma_sp_m16n8k64_s32_u4_satfinite.ll index bfa64ae3a4..897f961f8a 100644 --- a/intrinsics/probes/mma_sp_m16n8k64_s32_u4_satfinite.ll +++ b/intrinsics/probes/mma_sp_m16n8k64_s32_u4_satfinite.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_sp_m16n8k64_s32_u8.ll b/intrinsics/probes/mma_sp_m16n8k64_s32_u8.ll index 0155766889..7a83ad34e2 100644 --- a/intrinsics/probes/mma_sp_m16n8k64_s32_u8.ll +++ b/intrinsics/probes/mma_sp_m16n8k64_s32_u8.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_sp_m16n8k64_s32_u8_s8.ll b/intrinsics/probes/mma_sp_m16n8k64_s32_u8_s8.ll index 8334cfa4e8..0c77b6858c 100644 --- a/intrinsics/probes/mma_sp_m16n8k64_s32_u8_s8.ll +++ b/intrinsics/probes/mma_sp_m16n8k64_s32_u8_s8.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_sp_m16n8k64_s32_u8_s8_satfinite.ll b/intrinsics/probes/mma_sp_m16n8k64_s32_u8_s8_satfinite.ll index 5cc299f13f..4dcca1060e 100644 --- a/intrinsics/probes/mma_sp_m16n8k64_s32_u8_s8_satfinite.ll +++ b/intrinsics/probes/mma_sp_m16n8k64_s32_u8_s8_satfinite.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_sp_m16n8k64_s32_u8_satfinite.ll b/intrinsics/probes/mma_sp_m16n8k64_s32_u8_satfinite.ll index 858caf4494..431d7b1b79 100644 --- a/intrinsics/probes/mma_sp_m16n8k64_s32_u8_satfinite.ll +++ b/intrinsics/probes/mma_sp_m16n8k64_s32_u8_satfinite.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_sp_ordered_metadata_m16n8k128_s32_s4.ll b/intrinsics/probes/mma_sp_ordered_metadata_m16n8k128_s32_s4.ll index 7a26202730..17418272de 100644 --- a/intrinsics/probes/mma_sp_ordered_metadata_m16n8k128_s32_s4.ll +++ b/intrinsics/probes/mma_sp_ordered_metadata_m16n8k128_s32_s4.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_sp_ordered_metadata_m16n8k128_s32_s4_satfinite.ll b/intrinsics/probes/mma_sp_ordered_metadata_m16n8k128_s32_s4_satfinite.ll index 382500fda5..38583f1bd2 100644 --- a/intrinsics/probes/mma_sp_ordered_metadata_m16n8k128_s32_s4_satfinite.ll +++ b/intrinsics/probes/mma_sp_ordered_metadata_m16n8k128_s32_s4_satfinite.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_sp_ordered_metadata_m16n8k128_s32_s4_u4.ll b/intrinsics/probes/mma_sp_ordered_metadata_m16n8k128_s32_s4_u4.ll index 025a59a0da..3151acd1e3 100644 --- a/intrinsics/probes/mma_sp_ordered_metadata_m16n8k128_s32_s4_u4.ll +++ b/intrinsics/probes/mma_sp_ordered_metadata_m16n8k128_s32_s4_u4.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_sp_ordered_metadata_m16n8k128_s32_s4_u4_satfinite.ll b/intrinsics/probes/mma_sp_ordered_metadata_m16n8k128_s32_s4_u4_satfinite.ll index 727cbc7ac7..095950ea6d 100644 --- a/intrinsics/probes/mma_sp_ordered_metadata_m16n8k128_s32_s4_u4_satfinite.ll +++ b/intrinsics/probes/mma_sp_ordered_metadata_m16n8k128_s32_s4_u4_satfinite.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_sp_ordered_metadata_m16n8k128_s32_u4.ll b/intrinsics/probes/mma_sp_ordered_metadata_m16n8k128_s32_u4.ll index 10d35239d9..47728ca70f 100644 --- a/intrinsics/probes/mma_sp_ordered_metadata_m16n8k128_s32_u4.ll +++ b/intrinsics/probes/mma_sp_ordered_metadata_m16n8k128_s32_u4.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_sp_ordered_metadata_m16n8k128_s32_u4_s4.ll b/intrinsics/probes/mma_sp_ordered_metadata_m16n8k128_s32_u4_s4.ll index 5a49da0c7c..d2fc8fa48d 100644 --- a/intrinsics/probes/mma_sp_ordered_metadata_m16n8k128_s32_u4_s4.ll +++ b/intrinsics/probes/mma_sp_ordered_metadata_m16n8k128_s32_u4_s4.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_sp_ordered_metadata_m16n8k128_s32_u4_s4_satfinite.ll b/intrinsics/probes/mma_sp_ordered_metadata_m16n8k128_s32_u4_s4_satfinite.ll index 8507bde9e0..4325ba0db6 100644 --- a/intrinsics/probes/mma_sp_ordered_metadata_m16n8k128_s32_u4_s4_satfinite.ll +++ b/intrinsics/probes/mma_sp_ordered_metadata_m16n8k128_s32_u4_s4_satfinite.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_sp_ordered_metadata_m16n8k128_s32_u4_satfinite.ll b/intrinsics/probes/mma_sp_ordered_metadata_m16n8k128_s32_u4_satfinite.ll index 315ef2d57b..34f75c1a9f 100644 --- a/intrinsics/probes/mma_sp_ordered_metadata_m16n8k128_s32_u4_satfinite.ll +++ b/intrinsics/probes/mma_sp_ordered_metadata_m16n8k128_s32_u4_satfinite.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_sp_ordered_metadata_m16n8k32_s32_s8.ll b/intrinsics/probes/mma_sp_ordered_metadata_m16n8k32_s32_s8.ll index 070021d432..8e45f516a0 100644 --- a/intrinsics/probes/mma_sp_ordered_metadata_m16n8k32_s32_s8.ll +++ b/intrinsics/probes/mma_sp_ordered_metadata_m16n8k32_s32_s8.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_sp_ordered_metadata_m16n8k32_s32_s8_satfinite.ll b/intrinsics/probes/mma_sp_ordered_metadata_m16n8k32_s32_s8_satfinite.ll index 4e0fe1deca..0ac8ca48be 100644 --- a/intrinsics/probes/mma_sp_ordered_metadata_m16n8k32_s32_s8_satfinite.ll +++ b/intrinsics/probes/mma_sp_ordered_metadata_m16n8k32_s32_s8_satfinite.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_sp_ordered_metadata_m16n8k32_s32_s8_u8.ll b/intrinsics/probes/mma_sp_ordered_metadata_m16n8k32_s32_s8_u8.ll index 9c2e6bde46..7d2ce4cb81 100644 --- a/intrinsics/probes/mma_sp_ordered_metadata_m16n8k32_s32_s8_u8.ll +++ b/intrinsics/probes/mma_sp_ordered_metadata_m16n8k32_s32_s8_u8.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_sp_ordered_metadata_m16n8k32_s32_s8_u8_satfinite.ll b/intrinsics/probes/mma_sp_ordered_metadata_m16n8k32_s32_s8_u8_satfinite.ll index 3a12212c63..400c975231 100644 --- a/intrinsics/probes/mma_sp_ordered_metadata_m16n8k32_s32_s8_u8_satfinite.ll +++ b/intrinsics/probes/mma_sp_ordered_metadata_m16n8k32_s32_s8_u8_satfinite.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_sp_ordered_metadata_m16n8k32_s32_u8.ll b/intrinsics/probes/mma_sp_ordered_metadata_m16n8k32_s32_u8.ll index 1880898701..9f4ce72275 100644 --- a/intrinsics/probes/mma_sp_ordered_metadata_m16n8k32_s32_u8.ll +++ b/intrinsics/probes/mma_sp_ordered_metadata_m16n8k32_s32_u8.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_sp_ordered_metadata_m16n8k32_s32_u8_s8.ll b/intrinsics/probes/mma_sp_ordered_metadata_m16n8k32_s32_u8_s8.ll index e60a130d3e..1234a3caca 100644 --- a/intrinsics/probes/mma_sp_ordered_metadata_m16n8k32_s32_u8_s8.ll +++ b/intrinsics/probes/mma_sp_ordered_metadata_m16n8k32_s32_u8_s8.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_sp_ordered_metadata_m16n8k32_s32_u8_s8_satfinite.ll b/intrinsics/probes/mma_sp_ordered_metadata_m16n8k32_s32_u8_s8_satfinite.ll index f5e7fa01cb..c80b6e9789 100644 --- a/intrinsics/probes/mma_sp_ordered_metadata_m16n8k32_s32_u8_s8_satfinite.ll +++ b/intrinsics/probes/mma_sp_ordered_metadata_m16n8k32_s32_u8_s8_satfinite.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_sp_ordered_metadata_m16n8k32_s32_u8_satfinite.ll b/intrinsics/probes/mma_sp_ordered_metadata_m16n8k32_s32_u8_satfinite.ll index 085e54b13d..2e5ebd764f 100644 --- a/intrinsics/probes/mma_sp_ordered_metadata_m16n8k32_s32_u8_satfinite.ll +++ b/intrinsics/probes/mma_sp_ordered_metadata_m16n8k32_s32_u8_satfinite.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e2m1_e2m1_f16.ll b/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e2m1_e2m1_f16.ll index 944c19d2f3..654a5ab01f 100644 --- a/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e2m1_e2m1_f16.ll +++ b/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e2m1_e2m1_f16.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e2m1_e2m3_f16.ll b/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e2m1_e2m3_f16.ll index 6df24565f9..019f11526c 100644 --- a/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e2m1_e2m3_f16.ll +++ b/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e2m1_e2m3_f16.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e2m1_e3m2_f16.ll b/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e2m1_e3m2_f16.ll index 9e69773ee3..37e28692eb 100644 --- a/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e2m1_e3m2_f16.ll +++ b/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e2m1_e3m2_f16.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e2m1_e4m3_f16.ll b/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e2m1_e4m3_f16.ll index 6a88a7a11d..eb4930f985 100644 --- a/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e2m1_e4m3_f16.ll +++ b/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e2m1_e4m3_f16.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e2m1_e5m2_f16.ll b/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e2m1_e5m2_f16.ll index e06f6d7114..bb8562473a 100644 --- a/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e2m1_e5m2_f16.ll +++ b/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e2m1_e5m2_f16.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e2m3_e2m1_f16.ll b/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e2m3_e2m1_f16.ll index 23080890a2..48433a201d 100644 --- a/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e2m3_e2m1_f16.ll +++ b/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e2m3_e2m1_f16.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e2m3_e2m3_f16.ll b/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e2m3_e2m3_f16.ll index 17c9b0cc70..664e247f5e 100644 --- a/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e2m3_e2m3_f16.ll +++ b/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e2m3_e2m3_f16.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e2m3_e3m2_f16.ll b/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e2m3_e3m2_f16.ll index 757e1689a4..0158940d1a 100644 --- a/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e2m3_e3m2_f16.ll +++ b/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e2m3_e3m2_f16.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e2m3_e4m3_f16.ll b/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e2m3_e4m3_f16.ll index 410230b278..532e6ba40c 100644 --- a/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e2m3_e4m3_f16.ll +++ b/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e2m3_e4m3_f16.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e2m3_e5m2_f16.ll b/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e2m3_e5m2_f16.ll index 98fca31f6f..93e1c13020 100644 --- a/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e2m3_e5m2_f16.ll +++ b/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e2m3_e5m2_f16.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e3m2_e2m1_f16.ll b/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e3m2_e2m1_f16.ll index fb99ad27ee..5a18acf3aa 100644 --- a/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e3m2_e2m1_f16.ll +++ b/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e3m2_e2m1_f16.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e3m2_e2m3_f16.ll b/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e3m2_e2m3_f16.ll index 98e6b4f058..c79b991871 100644 --- a/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e3m2_e2m3_f16.ll +++ b/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e3m2_e2m3_f16.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e3m2_e3m2_f16.ll b/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e3m2_e3m2_f16.ll index a74ae12411..249c38ba84 100644 --- a/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e3m2_e3m2_f16.ll +++ b/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e3m2_e3m2_f16.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e3m2_e4m3_f16.ll b/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e3m2_e4m3_f16.ll index 25ba101cfb..0ef58dfa6e 100644 --- a/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e3m2_e4m3_f16.ll +++ b/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e3m2_e4m3_f16.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e3m2_e5m2_f16.ll b/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e3m2_e5m2_f16.ll index c4a38f01e7..7a8c755caa 100644 --- a/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e3m2_e5m2_f16.ll +++ b/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e3m2_e5m2_f16.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e4m3_e2m1_f16.ll b/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e4m3_e2m1_f16.ll index bcebaca692..7e2d1b9cdb 100644 --- a/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e4m3_e2m1_f16.ll +++ b/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e4m3_e2m1_f16.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e4m3_e2m3_f16.ll b/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e4m3_e2m3_f16.ll index 7b0e8c6ce8..34e28f8b4e 100644 --- a/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e4m3_e2m3_f16.ll +++ b/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e4m3_e2m3_f16.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e4m3_e3m2_f16.ll b/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e4m3_e3m2_f16.ll index fd34020409..3d1eecc048 100644 --- a/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e4m3_e3m2_f16.ll +++ b/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e4m3_e3m2_f16.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e4m3_e4m3_f16.ll b/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e4m3_e4m3_f16.ll index ad8daa6b0a..4213d5b21d 100644 --- a/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e4m3_e4m3_f16.ll +++ b/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e4m3_e4m3_f16.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e4m3_e5m2_f16.ll b/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e4m3_e5m2_f16.ll index d9ef2fdbae..e72285b99b 100644 --- a/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e4m3_e5m2_f16.ll +++ b/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e4m3_e5m2_f16.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e5m2_e2m1_f16.ll b/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e5m2_e2m1_f16.ll index de35c14944..1677967876 100644 --- a/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e5m2_e2m1_f16.ll +++ b/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e5m2_e2m1_f16.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e5m2_e2m3_f16.ll b/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e5m2_e2m3_f16.ll index 2485071d7b..4510edec79 100644 --- a/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e5m2_e2m3_f16.ll +++ b/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e5m2_e2m3_f16.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e5m2_e3m2_f16.ll b/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e5m2_e3m2_f16.ll index c27c4a0cdd..8adfc93cfc 100644 --- a/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e5m2_e3m2_f16.ll +++ b/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e5m2_e3m2_f16.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e5m2_e4m3_f16.ll b/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e5m2_e4m3_f16.ll index ba8298fd0e..bd5ddf6c4e 100644 --- a/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e5m2_e4m3_f16.ll +++ b/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e5m2_e4m3_f16.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e5m2_e5m2_f16.ll b/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e5m2_e5m2_f16.ll index 6ebb4f0a62..e62baf5789 100644 --- a/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e5m2_e5m2_f16.ll +++ b/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f16_e5m2_e5m2_f16.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e2m1_e2m1_f32.ll b/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e2m1_e2m1_f32.ll index f5699f1bfd..b839a27f45 100644 --- a/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e2m1_e2m1_f32.ll +++ b/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e2m1_e2m1_f32.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e2m1_e2m3_f32.ll b/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e2m1_e2m3_f32.ll index 6572fc9022..52d406f638 100644 --- a/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e2m1_e2m3_f32.ll +++ b/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e2m1_e2m3_f32.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e2m1_e3m2_f32.ll b/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e2m1_e3m2_f32.ll index 469e58b233..9f7b5e5b07 100644 --- a/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e2m1_e3m2_f32.ll +++ b/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e2m1_e3m2_f32.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e2m1_e4m3_f32.ll b/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e2m1_e4m3_f32.ll index af7be97231..2d9e046169 100644 --- a/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e2m1_e4m3_f32.ll +++ b/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e2m1_e4m3_f32.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e2m1_e5m2_f32.ll b/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e2m1_e5m2_f32.ll index 788d6736b9..929e061242 100644 --- a/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e2m1_e5m2_f32.ll +++ b/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e2m1_e5m2_f32.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e2m3_e2m1_f32.ll b/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e2m3_e2m1_f32.ll index 02584d2c1a..dd71571eb7 100644 --- a/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e2m3_e2m1_f32.ll +++ b/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e2m3_e2m1_f32.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e2m3_e2m3_f32.ll b/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e2m3_e2m3_f32.ll index 79504d0c56..5bfb68e241 100644 --- a/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e2m3_e2m3_f32.ll +++ b/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e2m3_e2m3_f32.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e2m3_e3m2_f32.ll b/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e2m3_e3m2_f32.ll index de665dff88..03a79c86d1 100644 --- a/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e2m3_e3m2_f32.ll +++ b/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e2m3_e3m2_f32.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e2m3_e4m3_f32.ll b/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e2m3_e4m3_f32.ll index 357bb3b1e5..ad8b514c51 100644 --- a/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e2m3_e4m3_f32.ll +++ b/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e2m3_e4m3_f32.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e2m3_e5m2_f32.ll b/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e2m3_e5m2_f32.ll index 8e774c6f57..4ef514acf5 100644 --- a/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e2m3_e5m2_f32.ll +++ b/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e2m3_e5m2_f32.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e3m2_e2m1_f32.ll b/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e3m2_e2m1_f32.ll index 5e762d6161..c94b984ed9 100644 --- a/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e3m2_e2m1_f32.ll +++ b/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e3m2_e2m1_f32.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e3m2_e2m3_f32.ll b/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e3m2_e2m3_f32.ll index eb85454626..d1c4f1e71f 100644 --- a/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e3m2_e2m3_f32.ll +++ b/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e3m2_e2m3_f32.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e3m2_e3m2_f32.ll b/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e3m2_e3m2_f32.ll index 3b5089e32e..627fd2d594 100644 --- a/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e3m2_e3m2_f32.ll +++ b/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e3m2_e3m2_f32.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e3m2_e4m3_f32.ll b/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e3m2_e4m3_f32.ll index df3669f156..891b737cb7 100644 --- a/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e3m2_e4m3_f32.ll +++ b/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e3m2_e4m3_f32.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e3m2_e5m2_f32.ll b/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e3m2_e5m2_f32.ll index 5e5b06b772..67e1eaaecc 100644 --- a/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e3m2_e5m2_f32.ll +++ b/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e3m2_e5m2_f32.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e4m3_e2m1_f32.ll b/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e4m3_e2m1_f32.ll index c2b615aeb6..5ba2fb21fa 100644 --- a/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e4m3_e2m1_f32.ll +++ b/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e4m3_e2m1_f32.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e4m3_e2m3_f32.ll b/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e4m3_e2m3_f32.ll index 13cb1f51ef..e5f7353df7 100644 --- a/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e4m3_e2m3_f32.ll +++ b/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e4m3_e2m3_f32.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e4m3_e3m2_f32.ll b/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e4m3_e3m2_f32.ll index 9823417be4..0fbe05ef7c 100644 --- a/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e4m3_e3m2_f32.ll +++ b/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e4m3_e3m2_f32.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e4m3_e4m3_f32.ll b/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e4m3_e4m3_f32.ll index 638d81f24f..5dde5ba97f 100644 --- a/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e4m3_e4m3_f32.ll +++ b/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e4m3_e4m3_f32.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e4m3_e5m2_f32.ll b/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e4m3_e5m2_f32.ll index c126c6a753..4f09ce4c7a 100644 --- a/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e4m3_e5m2_f32.ll +++ b/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e4m3_e5m2_f32.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e5m2_e2m1_f32.ll b/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e5m2_e2m1_f32.ll index 973ee1cd5c..124af47e29 100644 --- a/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e5m2_e2m1_f32.ll +++ b/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e5m2_e2m1_f32.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e5m2_e2m3_f32.ll b/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e5m2_e2m3_f32.ll index 2bff06025c..b40c2a7647 100644 --- a/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e5m2_e2m3_f32.ll +++ b/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e5m2_e2m3_f32.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e5m2_e3m2_f32.ll b/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e5m2_e3m2_f32.ll index cec47466b0..a1581523f3 100644 --- a/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e5m2_e3m2_f32.ll +++ b/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e5m2_e3m2_f32.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e5m2_e4m3_f32.ll b/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e5m2_e4m3_f32.ll index d60010e444..dc682bdb79 100644 --- a/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e5m2_e4m3_f32.ll +++ b/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e5m2_e4m3_f32.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e5m2_e5m2_f32.ll b/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e5m2_e5m2_f32.ll index 542f649c74..da5a099e83 100644 --- a/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e5m2_e5m2_f32.ll +++ b/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_kind_f8f6f4_f32_e5m2_e5m2_f32.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_s32_s4.ll b/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_s32_s4.ll index 0e7c2c6a4e..b8cd802f2f 100644 --- a/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_s32_s4.ll +++ b/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_s32_s4.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_s32_s4_satfinite.ll b/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_s32_s4_satfinite.ll index 2080bd74ba..09f20dc325 100644 --- a/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_s32_s4_satfinite.ll +++ b/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_s32_s4_satfinite.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_s32_s4_u4.ll b/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_s32_s4_u4.ll index 2ae5d1df7e..b2eebbd3c4 100644 --- a/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_s32_s4_u4.ll +++ b/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_s32_s4_u4.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_s32_s4_u4_satfinite.ll b/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_s32_s4_u4_satfinite.ll index e7833effb4..ab7a4b880b 100644 --- a/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_s32_s4_u4_satfinite.ll +++ b/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_s32_s4_u4_satfinite.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_s32_s8.ll b/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_s32_s8.ll index 7e1fef831b..6b055b4573 100644 --- a/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_s32_s8.ll +++ b/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_s32_s8.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_s32_s8_satfinite.ll b/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_s32_s8_satfinite.ll index 24c92a5cc4..3af9dfc2f5 100644 --- a/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_s32_s8_satfinite.ll +++ b/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_s32_s8_satfinite.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_s32_s8_u8.ll b/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_s32_s8_u8.ll index 2508bee79f..bdadcfec87 100644 --- a/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_s32_s8_u8.ll +++ b/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_s32_s8_u8.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_s32_s8_u8_satfinite.ll b/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_s32_s8_u8_satfinite.ll index 4b3198e033..995d459aed 100644 --- a/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_s32_s8_u8_satfinite.ll +++ b/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_s32_s8_u8_satfinite.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_s32_u4.ll b/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_s32_u4.ll index 88eaf63ac5..11fe0ed9e8 100644 --- a/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_s32_u4.ll +++ b/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_s32_u4.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_s32_u4_s4.ll b/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_s32_u4_s4.ll index 33c2d76965..9e0c66b29f 100644 --- a/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_s32_u4_s4.ll +++ b/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_s32_u4_s4.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_s32_u4_s4_satfinite.ll b/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_s32_u4_s4_satfinite.ll index 1935e53615..ec77818b18 100644 --- a/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_s32_u4_s4_satfinite.ll +++ b/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_s32_u4_s4_satfinite.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_s32_u4_satfinite.ll b/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_s32_u4_satfinite.ll index c82fb86188..da00b831b5 100644 --- a/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_s32_u4_satfinite.ll +++ b/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_s32_u4_satfinite.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_s32_u8.ll b/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_s32_u8.ll index 3dd0f2846a..47bbd57599 100644 --- a/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_s32_u8.ll +++ b/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_s32_u8.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_s32_u8_s8.ll b/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_s32_u8_s8.ll index 7e40e9216e..b47c7a8dd1 100644 --- a/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_s32_u8_s8.ll +++ b/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_s32_u8_s8.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_s32_u8_s8_satfinite.ll b/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_s32_u8_s8_satfinite.ll index 63c6cda49d..a49ae56161 100644 --- a/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_s32_u8_s8_satfinite.ll +++ b/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_s32_u8_s8_satfinite.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_s32_u8_satfinite.ll b/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_s32_u8_satfinite.ll index cc05b4e735..5222c4e18d 100644 --- a/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_s32_u8_satfinite.ll +++ b/intrinsics/probes/mma_sp_ordered_metadata_m16n8k64_s32_u8_satfinite.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/movmatrix_trans_b16.ll b/intrinsics/probes/movmatrix_trans_b16.ll index 2f326115a8..94a2453cee 100644 --- a/intrinsics/probes/movmatrix_trans_b16.ll +++ b/intrinsics/probes/movmatrix_trans_b16.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mul_bf16x2.ll b/intrinsics/probes/mul_bf16x2.ll index a035a81781..19f1c7575a 100644 --- a/intrinsics/probes/mul_bf16x2.ll +++ b/intrinsics/probes/mul_bf16x2.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mul_f16x2.ll b/intrinsics/probes/mul_f16x2.ll index 1ae5e96445..f2ec8659bd 100644 --- a/intrinsics/probes/mul_f16x2.ll +++ b/intrinsics/probes/mul_f16x2.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mul_f32x2.ll b/intrinsics/probes/mul_f32x2.ll index f340497d65..acbbd6a45a 100644 --- a/intrinsics/probes/mul_f32x2.ll +++ b/intrinsics/probes/mul_f32x2.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mul_ftz_f32x2.ll b/intrinsics/probes/mul_ftz_f32x2.ll index 99ea8a36f1..5ba0533676 100644 --- a/intrinsics/probes/mul_ftz_f32x2.ll +++ b/intrinsics/probes/mul_ftz_f32x2.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mul_rm_f32.ll b/intrinsics/probes/mul_rm_f32.ll index 53a951fd82..4445c4a161 100644 --- a/intrinsics/probes/mul_rm_f32.ll +++ b/intrinsics/probes/mul_rm_f32.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mul_rm_f64.ll b/intrinsics/probes/mul_rm_f64.ll index 41034087dd..07e5e974fb 100644 --- a/intrinsics/probes/mul_rm_f64.ll +++ b/intrinsics/probes/mul_rm_f64.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mul_rm_ftz_f32.ll b/intrinsics/probes/mul_rm_ftz_f32.ll index c555f6f763..d6a0d9c78f 100644 --- a/intrinsics/probes/mul_rm_ftz_f32.ll +++ b/intrinsics/probes/mul_rm_ftz_f32.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mul_rn_f32.ll b/intrinsics/probes/mul_rn_f32.ll index 001ddf5d64..b0babd5836 100644 --- a/intrinsics/probes/mul_rn_f32.ll +++ b/intrinsics/probes/mul_rn_f32.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mul_rn_f64.ll b/intrinsics/probes/mul_rn_f64.ll index 6f07da6bcd..eb17f66a3c 100644 --- a/intrinsics/probes/mul_rn_f64.ll +++ b/intrinsics/probes/mul_rn_f64.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mul_rn_ftz_f32.ll b/intrinsics/probes/mul_rn_ftz_f32.ll index 93911cddc9..27cc0aaa79 100644 --- a/intrinsics/probes/mul_rn_ftz_f32.ll +++ b/intrinsics/probes/mul_rn_ftz_f32.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mul_rp_f32.ll b/intrinsics/probes/mul_rp_f32.ll index d51f89a164..25a2e1e381 100644 --- a/intrinsics/probes/mul_rp_f32.ll +++ b/intrinsics/probes/mul_rp_f32.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mul_rp_f64.ll b/intrinsics/probes/mul_rp_f64.ll index 189528bd4d..e15230b998 100644 --- a/intrinsics/probes/mul_rp_f64.ll +++ b/intrinsics/probes/mul_rp_f64.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mul_rp_ftz_f32.ll b/intrinsics/probes/mul_rp_ftz_f32.ll index 408920cccb..18abd3dc95 100644 --- a/intrinsics/probes/mul_rp_ftz_f32.ll +++ b/intrinsics/probes/mul_rp_ftz_f32.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mul_rz_f32.ll b/intrinsics/probes/mul_rz_f32.ll index 213fb732ea..e922e2b2a0 100644 --- a/intrinsics/probes/mul_rz_f32.ll +++ b/intrinsics/probes/mul_rz_f32.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mul_rz_f64.ll b/intrinsics/probes/mul_rz_f64.ll index 9760131070..0e44cabec2 100644 --- a/intrinsics/probes/mul_rz_f64.ll +++ b/intrinsics/probes/mul_rz_f64.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/mul_rz_ftz_f32.ll b/intrinsics/probes/mul_rz_ftz_f32.ll index fd4441ed57..0df089a8e7 100644 --- a/intrinsics/probes/mul_rz_ftz_f32.ll +++ b/intrinsics/probes/mul_rz_ftz_f32.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/nanosleep.ll b/intrinsics/probes/nanosleep.ll index c990d650ea..878965f82f 100644 --- a/intrinsics/probes/nanosleep.ll +++ b/intrinsics/probes/nanosleep.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/neg_bf16x2.ll b/intrinsics/probes/neg_bf16x2.ll index a837628754..80a35d5df3 100644 --- a/intrinsics/probes/neg_bf16x2.ll +++ b/intrinsics/probes/neg_bf16x2.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/neg_f16x2.ll b/intrinsics/probes/neg_f16x2.ll index b384b6d789..5ed638fcbf 100644 --- a/intrinsics/probes/neg_f16x2.ll +++ b/intrinsics/probes/neg_f16x2.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/nsmid.lib_nvvm.ll b/intrinsics/probes/nsmid.lib_nvvm.ll index fd40ec5a29..7b5c74327c 100644 --- a/intrinsics/probes/nsmid.lib_nvvm.ll +++ b/intrinsics/probes/nsmid.lib_nvvm.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/nsmid.llvm_nvptx.ll b/intrinsics/probes/nsmid.llvm_nvptx.ll index 7c56741deb..74b3f08628 100644 --- a/intrinsics/probes/nsmid.llvm_nvptx.ll +++ b/intrinsics/probes/nsmid.llvm_nvptx.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/nwarpid.lib_nvvm.ll b/intrinsics/probes/nwarpid.lib_nvvm.ll index 1ecf2c6d30..8feadb3d47 100644 --- a/intrinsics/probes/nwarpid.lib_nvvm.ll +++ b/intrinsics/probes/nwarpid.lib_nvvm.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/nwarpid.llvm_nvptx.ll b/intrinsics/probes/nwarpid.llvm_nvptx.ll index 6213c65b31..6b810c3864 100644 --- a/intrinsics/probes/nwarpid.llvm_nvptx.ll +++ b/intrinsics/probes/nwarpid.llvm_nvptx.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/packed_atomic_add_bf16x2.ll b/intrinsics/probes/packed_atomic_add_bf16x2.ll index 6372dc7c7b..a25b9c748f 100644 --- a/intrinsics/probes/packed_atomic_add_bf16x2.ll +++ b/intrinsics/probes/packed_atomic_add_bf16x2.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/packed_atomic_add_f16x2.ll b/intrinsics/probes/packed_atomic_add_f16x2.ll index a8e0655874..74b440c7da 100644 --- a/intrinsics/probes/packed_atomic_add_f16x2.ll +++ b/intrinsics/probes/packed_atomic_add_f16x2.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/pmevent.ll b/intrinsics/probes/pmevent.ll index 667091425e..292a8e9a83 100644 --- a/intrinsics/probes/pmevent.ll +++ b/intrinsics/probes/pmevent.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/prefetch_tma_descriptor.ll b/intrinsics/probes/prefetch_tma_descriptor.ll index 296a73159e..89912702c0 100644 --- a/intrinsics/probes/prefetch_tma_descriptor.ll +++ b/intrinsics/probes/prefetch_tma_descriptor.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/prmt.ll b/intrinsics/probes/prmt.ll index 93246a546f..9f50eef95a 100644 --- a/intrinsics/probes/prmt.ll +++ b/intrinsics/probes/prmt.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/prmt_b4e.ll b/intrinsics/probes/prmt_b4e.ll index d50aba5caf..ff1b678728 100644 --- a/intrinsics/probes/prmt_b4e.ll +++ b/intrinsics/probes/prmt_b4e.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/prmt_ecl.ll b/intrinsics/probes/prmt_ecl.ll index b5e723072d..e4293ea1aa 100644 --- a/intrinsics/probes/prmt_ecl.ll +++ b/intrinsics/probes/prmt_ecl.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/prmt_ecr.ll b/intrinsics/probes/prmt_ecr.ll index 119dfe7c4f..de7b3e90b4 100644 --- a/intrinsics/probes/prmt_ecr.ll +++ b/intrinsics/probes/prmt_ecr.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/prmt_f4e.ll b/intrinsics/probes/prmt_f4e.ll index 197bdf99fd..b6c570b0f1 100644 --- a/intrinsics/probes/prmt_f4e.ll +++ b/intrinsics/probes/prmt_f4e.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/prmt_rc16.ll b/intrinsics/probes/prmt_rc16.ll index dbf4df6b2b..249ad19472 100644 --- a/intrinsics/probes/prmt_rc16.ll +++ b/intrinsics/probes/prmt_rc16.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/prmt_rc8.ll b/intrinsics/probes/prmt_rc8.ll index 594271807c..5be02bb839 100644 --- a/intrinsics/probes/prmt_rc8.ll +++ b/intrinsics/probes/prmt_rc8.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/rcp_approx_ftz_f32.ll b/intrinsics/probes/rcp_approx_ftz_f32.ll index fcdd11b460..c7b155c900 100644 --- a/intrinsics/probes/rcp_approx_ftz_f32.ll +++ b/intrinsics/probes/rcp_approx_ftz_f32.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/rcp_approx_ftz_f64.ll b/intrinsics/probes/rcp_approx_ftz_f64.ll index e89d38b28d..b83366f1f9 100644 --- a/intrinsics/probes/rcp_approx_ftz_f64.ll +++ b/intrinsics/probes/rcp_approx_ftz_f64.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/rcp_rm_f32.ll b/intrinsics/probes/rcp_rm_f32.ll index 28c1e129ed..465a312442 100644 --- a/intrinsics/probes/rcp_rm_f32.ll +++ b/intrinsics/probes/rcp_rm_f32.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/rcp_rm_f64.ll b/intrinsics/probes/rcp_rm_f64.ll index 72b3686708..f299df0f29 100644 --- a/intrinsics/probes/rcp_rm_f64.ll +++ b/intrinsics/probes/rcp_rm_f64.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/rcp_rm_ftz_f32.ll b/intrinsics/probes/rcp_rm_ftz_f32.ll index 0cf346df4e..de2291cfce 100644 --- a/intrinsics/probes/rcp_rm_ftz_f32.ll +++ b/intrinsics/probes/rcp_rm_ftz_f32.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/rcp_rn_f32.ll b/intrinsics/probes/rcp_rn_f32.ll index e683e69528..8ecedfa351 100644 --- a/intrinsics/probes/rcp_rn_f32.ll +++ b/intrinsics/probes/rcp_rn_f32.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/rcp_rn_f64.ll b/intrinsics/probes/rcp_rn_f64.ll index 6666898fd6..69679b4c86 100644 --- a/intrinsics/probes/rcp_rn_f64.ll +++ b/intrinsics/probes/rcp_rn_f64.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/rcp_rn_ftz_f32.ll b/intrinsics/probes/rcp_rn_ftz_f32.ll index 6a3f5e880e..fd76bebfe3 100644 --- a/intrinsics/probes/rcp_rn_ftz_f32.ll +++ b/intrinsics/probes/rcp_rn_ftz_f32.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/rcp_rp_f32.ll b/intrinsics/probes/rcp_rp_f32.ll index fb8bc96e8f..4c8e7da5ee 100644 --- a/intrinsics/probes/rcp_rp_f32.ll +++ b/intrinsics/probes/rcp_rp_f32.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/rcp_rp_f64.ll b/intrinsics/probes/rcp_rp_f64.ll index be2746ab9b..5f288233f1 100644 --- a/intrinsics/probes/rcp_rp_f64.ll +++ b/intrinsics/probes/rcp_rp_f64.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/rcp_rp_ftz_f32.ll b/intrinsics/probes/rcp_rp_ftz_f32.ll index ab7d8a5b10..0526e8fedb 100644 --- a/intrinsics/probes/rcp_rp_ftz_f32.ll +++ b/intrinsics/probes/rcp_rp_ftz_f32.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/rcp_rz_f32.ll b/intrinsics/probes/rcp_rz_f32.ll index e8dac00c23..1270b8f397 100644 --- a/intrinsics/probes/rcp_rz_f32.ll +++ b/intrinsics/probes/rcp_rz_f32.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/rcp_rz_f64.ll b/intrinsics/probes/rcp_rz_f64.ll index 7323888c6a..974201bba0 100644 --- a/intrinsics/probes/rcp_rz_f64.ll +++ b/intrinsics/probes/rcp_rz_f64.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/rcp_rz_ftz_f32.ll b/intrinsics/probes/rcp_rz_ftz_f32.ll index 8edfb6612b..c886cb7d7d 100644 --- a/intrinsics/probes/rcp_rz_ftz_f32.ll +++ b/intrinsics/probes/rcp_rz_ftz_f32.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/redux_sync_add.ll b/intrinsics/probes/redux_sync_add.ll index dca549d2e4..5f7a285c29 100644 --- a/intrinsics/probes/redux_sync_add.ll +++ b/intrinsics/probes/redux_sync_add.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/redux_sync_and.ll b/intrinsics/probes/redux_sync_and.ll index 064808db0f..c8601fb96c 100644 --- a/intrinsics/probes/redux_sync_and.ll +++ b/intrinsics/probes/redux_sync_and.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/redux_sync_max_abs_f32.ll b/intrinsics/probes/redux_sync_max_abs_f32.ll index 2e8f684bb3..bb7380c499 100644 --- a/intrinsics/probes/redux_sync_max_abs_f32.ll +++ b/intrinsics/probes/redux_sync_max_abs_f32.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/redux_sync_max_abs_nan_f32.ll b/intrinsics/probes/redux_sync_max_abs_nan_f32.ll index 6dc86475ef..af8b0945e5 100644 --- a/intrinsics/probes/redux_sync_max_abs_nan_f32.ll +++ b/intrinsics/probes/redux_sync_max_abs_nan_f32.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/redux_sync_max_f32.ll b/intrinsics/probes/redux_sync_max_f32.ll index fb400bceb3..a2f39690c3 100644 --- a/intrinsics/probes/redux_sync_max_f32.ll +++ b/intrinsics/probes/redux_sync_max_f32.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/redux_sync_max_i32.ll b/intrinsics/probes/redux_sync_max_i32.ll index 0c64c14b05..7d6385364c 100644 --- a/intrinsics/probes/redux_sync_max_i32.ll +++ b/intrinsics/probes/redux_sync_max_i32.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/redux_sync_max_nan_f32.ll b/intrinsics/probes/redux_sync_max_nan_f32.ll index 3baf2fc810..0a47152d37 100644 --- a/intrinsics/probes/redux_sync_max_nan_f32.ll +++ b/intrinsics/probes/redux_sync_max_nan_f32.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/redux_sync_max_u32.ll b/intrinsics/probes/redux_sync_max_u32.ll index 815696d8e6..c1a4037595 100644 --- a/intrinsics/probes/redux_sync_max_u32.ll +++ b/intrinsics/probes/redux_sync_max_u32.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/redux_sync_min_abs_f32.ll b/intrinsics/probes/redux_sync_min_abs_f32.ll index 368086b420..a672fdc94b 100644 --- a/intrinsics/probes/redux_sync_min_abs_f32.ll +++ b/intrinsics/probes/redux_sync_min_abs_f32.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/redux_sync_min_abs_nan_f32.ll b/intrinsics/probes/redux_sync_min_abs_nan_f32.ll index 45e130534f..aaefb72949 100644 --- a/intrinsics/probes/redux_sync_min_abs_nan_f32.ll +++ b/intrinsics/probes/redux_sync_min_abs_nan_f32.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/redux_sync_min_f32.ll b/intrinsics/probes/redux_sync_min_f32.ll index 2890055008..6590dc75a9 100644 --- a/intrinsics/probes/redux_sync_min_f32.ll +++ b/intrinsics/probes/redux_sync_min_f32.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/redux_sync_min_i32.ll b/intrinsics/probes/redux_sync_min_i32.ll index 6675c452f8..960696257f 100644 --- a/intrinsics/probes/redux_sync_min_i32.ll +++ b/intrinsics/probes/redux_sync_min_i32.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/redux_sync_min_nan_f32.ll b/intrinsics/probes/redux_sync_min_nan_f32.ll index 7e110ceafe..3942c99bc3 100644 --- a/intrinsics/probes/redux_sync_min_nan_f32.ll +++ b/intrinsics/probes/redux_sync_min_nan_f32.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/redux_sync_min_u32.ll b/intrinsics/probes/redux_sync_min_u32.ll index 0ec77c6747..2fe2c7eaa2 100644 --- a/intrinsics/probes/redux_sync_min_u32.ll +++ b/intrinsics/probes/redux_sync_min_u32.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/redux_sync_or.ll b/intrinsics/probes/redux_sync_or.ll index d25be9ccdf..c59a1a5585 100644 --- a/intrinsics/probes/redux_sync_or.ll +++ b/intrinsics/probes/redux_sync_or.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/redux_sync_xor.ll b/intrinsics/probes/redux_sync_xor.ll index 1a338a1844..ad7df3d761 100644 --- a/intrinsics/probes/redux_sync_xor.ll +++ b/intrinsics/probes/redux_sync_xor.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/rsqrt_approx_f32.ll b/intrinsics/probes/rsqrt_approx_f32.ll index b71a37926f..639a0abbc6 100644 --- a/intrinsics/probes/rsqrt_approx_f32.ll +++ b/intrinsics/probes/rsqrt_approx_f32.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/rsqrt_approx_f64.ll b/intrinsics/probes/rsqrt_approx_f64.ll index 6805b5d0f3..39ac7eed4b 100644 --- a/intrinsics/probes/rsqrt_approx_f64.ll +++ b/intrinsics/probes/rsqrt_approx_f64.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/rsqrt_approx_ftz_f32.ll b/intrinsics/probes/rsqrt_approx_ftz_f32.ll index d443b66c6b..e9b52796ff 100644 --- a/intrinsics/probes/rsqrt_approx_ftz_f32.ll +++ b/intrinsics/probes/rsqrt_approx_ftz_f32.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/setmaxnreg_dec.ll b/intrinsics/probes/setmaxnreg_dec.ll index 769afce806..e338b64b50 100644 --- a/intrinsics/probes/setmaxnreg_dec.ll +++ b/intrinsics/probes/setmaxnreg_dec.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/setmaxnreg_inc.ll b/intrinsics/probes/setmaxnreg_inc.ll index 112cfa028a..07558039eb 100644 --- a/intrinsics/probes/setmaxnreg_inc.ll +++ b/intrinsics/probes/setmaxnreg_inc.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/shuffle_down_f32_sync.ll b/intrinsics/probes/shuffle_down_f32_sync.ll index f8a9b0547b..dfd930ebd0 100644 --- a/intrinsics/probes/shuffle_down_f32_sync.ll +++ b/intrinsics/probes/shuffle_down_f32_sync.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/shuffle_down_sync.ll b/intrinsics/probes/shuffle_down_sync.ll index 925d9bb607..506e403974 100644 --- a/intrinsics/probes/shuffle_down_sync.ll +++ b/intrinsics/probes/shuffle_down_sync.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/shuffle_down_u64_sync.ll b/intrinsics/probes/shuffle_down_u64_sync.ll index 5066e58329..41b00a9d04 100644 --- a/intrinsics/probes/shuffle_down_u64_sync.ll +++ b/intrinsics/probes/shuffle_down_u64_sync.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/shuffle_f32_sync.ll b/intrinsics/probes/shuffle_f32_sync.ll index 398df1774a..21fbefa7b7 100644 --- a/intrinsics/probes/shuffle_f32_sync.ll +++ b/intrinsics/probes/shuffle_f32_sync.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/shuffle_sync.ll b/intrinsics/probes/shuffle_sync.ll index c9804bb6e4..9054306ee5 100644 --- a/intrinsics/probes/shuffle_sync.ll +++ b/intrinsics/probes/shuffle_sync.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/shuffle_u64_sync.ll b/intrinsics/probes/shuffle_u64_sync.ll index a16ad86fe3..28b9cdd35e 100644 --- a/intrinsics/probes/shuffle_u64_sync.ll +++ b/intrinsics/probes/shuffle_u64_sync.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/shuffle_up_f32_sync.ll b/intrinsics/probes/shuffle_up_f32_sync.ll index ff7cb068ef..48d6d84403 100644 --- a/intrinsics/probes/shuffle_up_f32_sync.ll +++ b/intrinsics/probes/shuffle_up_f32_sync.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/shuffle_up_sync.ll b/intrinsics/probes/shuffle_up_sync.ll index 31a60799d9..7deb1298d2 100644 --- a/intrinsics/probes/shuffle_up_sync.ll +++ b/intrinsics/probes/shuffle_up_sync.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/shuffle_up_u64_sync.ll b/intrinsics/probes/shuffle_up_u64_sync.ll index c171635daf..c127627c7c 100644 --- a/intrinsics/probes/shuffle_up_u64_sync.ll +++ b/intrinsics/probes/shuffle_up_u64_sync.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/shuffle_xor_f32_sync.ll b/intrinsics/probes/shuffle_xor_f32_sync.ll index 91400c6af1..31c2ab047d 100644 --- a/intrinsics/probes/shuffle_xor_f32_sync.ll +++ b/intrinsics/probes/shuffle_xor_f32_sync.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/shuffle_xor_sync.ll b/intrinsics/probes/shuffle_xor_sync.ll index 7f95aa3620..b3bad4fb97 100644 --- a/intrinsics/probes/shuffle_xor_sync.ll +++ b/intrinsics/probes/shuffle_xor_sync.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/shuffle_xor_u64_sync.ll b/intrinsics/probes/shuffle_xor_u64_sync.ll index d8292d11f6..05f51c1052 100644 --- a/intrinsics/probes/shuffle_xor_u64_sync.ll +++ b/intrinsics/probes/shuffle_xor_u64_sync.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/sin_approx_f32.ll b/intrinsics/probes/sin_approx_f32.ll index 0a1a2fbd7d..4fbb1cde10 100644 --- a/intrinsics/probes/sin_approx_f32.ll +++ b/intrinsics/probes/sin_approx_f32.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/sin_approx_ftz_f32.ll b/intrinsics/probes/sin_approx_ftz_f32.ll index 2274708d78..734486aae5 100644 --- a/intrinsics/probes/sin_approx_ftz_f32.ll +++ b/intrinsics/probes/sin_approx_ftz_f32.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/smid.lib_nvvm.ll b/intrinsics/probes/smid.lib_nvvm.ll index 658f030d4a..032d31fe45 100644 --- a/intrinsics/probes/smid.lib_nvvm.ll +++ b/intrinsics/probes/smid.lib_nvvm.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/smid.llvm_nvptx.ll b/intrinsics/probes/smid.llvm_nvptx.ll index 4b1164c258..e010b28288 100644 --- a/intrinsics/probes/smid.llvm_nvptx.ll +++ b/intrinsics/probes/smid.llvm_nvptx.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/sqrt_approx_f32.ll b/intrinsics/probes/sqrt_approx_f32.ll index 6164eb4167..d5dc426383 100644 --- a/intrinsics/probes/sqrt_approx_f32.ll +++ b/intrinsics/probes/sqrt_approx_f32.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/sqrt_approx_ftz_f32.ll b/intrinsics/probes/sqrt_approx_ftz_f32.ll index abc5a561ad..8679e09930 100644 --- a/intrinsics/probes/sqrt_approx_ftz_f32.ll +++ b/intrinsics/probes/sqrt_approx_ftz_f32.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/sqrt_rm_f32.ll b/intrinsics/probes/sqrt_rm_f32.ll index 86d97ce017..45092183ed 100644 --- a/intrinsics/probes/sqrt_rm_f32.ll +++ b/intrinsics/probes/sqrt_rm_f32.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/sqrt_rm_f64.ll b/intrinsics/probes/sqrt_rm_f64.ll index 04acb2965f..f97883f114 100644 --- a/intrinsics/probes/sqrt_rm_f64.ll +++ b/intrinsics/probes/sqrt_rm_f64.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/sqrt_rm_ftz_f32.ll b/intrinsics/probes/sqrt_rm_ftz_f32.ll index 684ce6e598..ddb272cf67 100644 --- a/intrinsics/probes/sqrt_rm_ftz_f32.ll +++ b/intrinsics/probes/sqrt_rm_ftz_f32.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/sqrt_rn_f32.ll b/intrinsics/probes/sqrt_rn_f32.ll index 2a08a6bf9f..3e160d233b 100644 --- a/intrinsics/probes/sqrt_rn_f32.ll +++ b/intrinsics/probes/sqrt_rn_f32.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/sqrt_rn_f64.ll b/intrinsics/probes/sqrt_rn_f64.ll index dfbbb552d8..061b943160 100644 --- a/intrinsics/probes/sqrt_rn_f64.ll +++ b/intrinsics/probes/sqrt_rn_f64.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/sqrt_rn_ftz_f32.ll b/intrinsics/probes/sqrt_rn_ftz_f32.ll index bd24981c40..206dda14c9 100644 --- a/intrinsics/probes/sqrt_rn_ftz_f32.ll +++ b/intrinsics/probes/sqrt_rn_ftz_f32.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/sqrt_rp_f32.ll b/intrinsics/probes/sqrt_rp_f32.ll index 9ff989af92..a42ed6c407 100644 --- a/intrinsics/probes/sqrt_rp_f32.ll +++ b/intrinsics/probes/sqrt_rp_f32.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/sqrt_rp_f64.ll b/intrinsics/probes/sqrt_rp_f64.ll index 35997c4562..7aa7ffa473 100644 --- a/intrinsics/probes/sqrt_rp_f64.ll +++ b/intrinsics/probes/sqrt_rp_f64.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/sqrt_rp_ftz_f32.ll b/intrinsics/probes/sqrt_rp_ftz_f32.ll index 7fca122859..d2eb896b82 100644 --- a/intrinsics/probes/sqrt_rp_ftz_f32.ll +++ b/intrinsics/probes/sqrt_rp_ftz_f32.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/sqrt_rz_f32.ll b/intrinsics/probes/sqrt_rz_f32.ll index 902a448cbb..ff40025ab0 100644 --- a/intrinsics/probes/sqrt_rz_f32.ll +++ b/intrinsics/probes/sqrt_rz_f32.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/sqrt_rz_f64.ll b/intrinsics/probes/sqrt_rz_f64.ll index 494db1c57f..1abe69142f 100644 --- a/intrinsics/probes/sqrt_rz_f64.ll +++ b/intrinsics/probes/sqrt_rz_f64.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/sqrt_rz_ftz_f32.ll b/intrinsics/probes/sqrt_rz_ftz_f32.ll index f232124383..06b33246dd 100644 --- a/intrinsics/probes/sqrt_rz_ftz_f32.ll +++ b/intrinsics/probes/sqrt_rz_ftz_f32.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/stmatrix_m8n8_x2_b16.ll b/intrinsics/probes/stmatrix_m8n8_x2_b16.ll index 1fdafa864d..9b02ad9751 100644 --- a/intrinsics/probes/stmatrix_m8n8_x2_b16.ll +++ b/intrinsics/probes/stmatrix_m8n8_x2_b16.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/stmatrix_m8n8_x2_trans_b16.ll b/intrinsics/probes/stmatrix_m8n8_x2_trans_b16.ll index 38502f4672..f5bf5812a8 100644 --- a/intrinsics/probes/stmatrix_m8n8_x2_trans_b16.ll +++ b/intrinsics/probes/stmatrix_m8n8_x2_trans_b16.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/stmatrix_m8n8_x4_b16.ll b/intrinsics/probes/stmatrix_m8n8_x4_b16.ll index 9262105c6a..ac8a39ca32 100644 --- a/intrinsics/probes/stmatrix_m8n8_x4_b16.ll +++ b/intrinsics/probes/stmatrix_m8n8_x4_b16.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/stmatrix_m8n8_x4_trans_b16.ll b/intrinsics/probes/stmatrix_m8n8_x4_trans_b16.ll index 4b538ca913..31aff5375b 100644 --- a/intrinsics/probes/stmatrix_m8n8_x4_trans_b16.ll +++ b/intrinsics/probes/stmatrix_m8n8_x4_trans_b16.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/sub_bf16x2.ll b/intrinsics/probes/sub_bf16x2.ll index 15224ffc13..d096a47e1f 100644 --- a/intrinsics/probes/sub_bf16x2.ll +++ b/intrinsics/probes/sub_bf16x2.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/sub_f16x2.ll b/intrinsics/probes/sub_f16x2.ll index fd78abca09..9c988dce9b 100644 --- a/intrinsics/probes/sub_f16x2.ll +++ b/intrinsics/probes/sub_f16x2.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/sub_f32x2.ll b/intrinsics/probes/sub_f32x2.ll index 5402dbf31e..100bc262c7 100644 --- a/intrinsics/probes/sub_f32x2.ll +++ b/intrinsics/probes/sub_f32x2.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/sub_ftz_f32x2.ll b/intrinsics/probes/sub_ftz_f32x2.ll index 2f9cddaa30..c51433cd09 100644 --- a/intrinsics/probes/sub_ftz_f32x2.ll +++ b/intrinsics/probes/sub_ftz_f32x2.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/sync_mask.ll b/intrinsics/probes/sync_mask.ll index 81708bcc09..06a9d76b1d 100644 --- a/intrinsics/probes/sync_mask.ll +++ b/intrinsics/probes/sync_mask.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/sync_threads.ll b/intrinsics/probes/sync_threads.ll index 1766778df4..16459ae285 100644 --- a/intrinsics/probes/sync_threads.ll +++ b/intrinsics/probes/sync_threads.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tanh_approx_f32.ll b/intrinsics/probes/tanh_approx_f32.ll index 635c3b9083..3429bfd198 100644 --- a/intrinsics/probes/tanh_approx_f32.ll +++ b/intrinsics/probes/tanh_approx_f32.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_alloc.ll b/intrinsics/probes/tcgen05_alloc.ll index 7926297e11..9d93ddc843 100644 --- a/intrinsics/probes/tcgen05_alloc.ll +++ b/intrinsics/probes/tcgen05_alloc.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_alloc_cg2.ll b/intrinsics/probes/tcgen05_alloc_cg2.ll index 29c168792d..1e6c45f5d0 100644 --- a/intrinsics/probes/tcgen05_alloc_cg2.ll +++ b/intrinsics/probes/tcgen05_alloc_cg2.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_commit.ll b/intrinsics/probes/tcgen05_commit.ll index a71a927746..23703a0739 100644 --- a/intrinsics/probes/tcgen05_commit.ll +++ b/intrinsics/probes/tcgen05_commit.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_commit_cg2.ll b/intrinsics/probes/tcgen05_commit_cg2.ll index 28ff92d530..edb8009889 100644 --- a/intrinsics/probes/tcgen05_commit_cg2.ll +++ b/intrinsics/probes/tcgen05_commit_cg2.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_commit_multicast.ll b/intrinsics/probes/tcgen05_commit_multicast.ll index af91a088d3..7da256d662 100644 --- a/intrinsics/probes/tcgen05_commit_multicast.ll +++ b/intrinsics/probes/tcgen05_commit_multicast.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_commit_multicast_cg2.ll b/intrinsics/probes/tcgen05_commit_multicast_cg2.ll index 546d0ff5dd..d71893cfca 100644 --- a/intrinsics/probes/tcgen05_commit_multicast_cg2.ll +++ b/intrinsics/probes/tcgen05_commit_multicast_cg2.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_commit_shared_cluster.ll b/intrinsics/probes/tcgen05_commit_shared_cluster.ll index b00dfbee14..c55668d7b3 100644 --- a/intrinsics/probes/tcgen05_commit_shared_cluster.ll +++ b/intrinsics/probes/tcgen05_commit_shared_cluster.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_commit_shared_cluster_cg2.ll b/intrinsics/probes/tcgen05_commit_shared_cluster_cg2.ll index bab965056e..920724430a 100644 --- a/intrinsics/probes/tcgen05_commit_shared_cluster_cg2.ll +++ b/intrinsics/probes/tcgen05_commit_shared_cluster_cg2.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_cp_128x128b.ll b/intrinsics/probes/tcgen05_cp_128x128b.ll index df8e627d74..aaff190b59 100644 --- a/intrinsics/probes/tcgen05_cp_128x128b.ll +++ b/intrinsics/probes/tcgen05_cp_128x128b.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_cp_128x128b_b4x16_p64.ll b/intrinsics/probes/tcgen05_cp_128x128b_b4x16_p64.ll index 98755b8f0b..67c9b0ba6d 100644 --- a/intrinsics/probes/tcgen05_cp_128x128b_b4x16_p64.ll +++ b/intrinsics/probes/tcgen05_cp_128x128b_b4x16_p64.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_cp_128x128b_b4x16_p64_cg2.ll b/intrinsics/probes/tcgen05_cp_128x128b_b4x16_p64_cg2.ll index 1d7708ad09..37b41946bb 100644 --- a/intrinsics/probes/tcgen05_cp_128x128b_b4x16_p64_cg2.ll +++ b/intrinsics/probes/tcgen05_cp_128x128b_b4x16_p64_cg2.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_cp_128x128b_b6x16_p32.ll b/intrinsics/probes/tcgen05_cp_128x128b_b6x16_p32.ll index cdf4ae4044..394522a4e2 100644 --- a/intrinsics/probes/tcgen05_cp_128x128b_b6x16_p32.ll +++ b/intrinsics/probes/tcgen05_cp_128x128b_b6x16_p32.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_cp_128x128b_b6x16_p32_cg2.ll b/intrinsics/probes/tcgen05_cp_128x128b_b6x16_p32_cg2.ll index f24095fcd1..5e95bbb6d9 100644 --- a/intrinsics/probes/tcgen05_cp_128x128b_b6x16_p32_cg2.ll +++ b/intrinsics/probes/tcgen05_cp_128x128b_b6x16_p32_cg2.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_cp_128x128b_cg2.ll b/intrinsics/probes/tcgen05_cp_128x128b_cg2.ll index fac71862d7..938af905d9 100644 --- a/intrinsics/probes/tcgen05_cp_128x128b_cg2.ll +++ b/intrinsics/probes/tcgen05_cp_128x128b_cg2.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_cp_128x256b_b4x16_p64.ll b/intrinsics/probes/tcgen05_cp_128x256b_b4x16_p64.ll index 39b8fbcc09..2e0238b73c 100644 --- a/intrinsics/probes/tcgen05_cp_128x256b_b4x16_p64.ll +++ b/intrinsics/probes/tcgen05_cp_128x256b_b4x16_p64.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_cp_128x256b_b4x16_p64_cg2.ll b/intrinsics/probes/tcgen05_cp_128x256b_b4x16_p64_cg2.ll index 3ec9554e44..d0813a8f06 100644 --- a/intrinsics/probes/tcgen05_cp_128x256b_b4x16_p64_cg2.ll +++ b/intrinsics/probes/tcgen05_cp_128x256b_b4x16_p64_cg2.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_cp_128x256b_b6x16_p32.ll b/intrinsics/probes/tcgen05_cp_128x256b_b6x16_p32.ll index 727b511644..46c9e697c9 100644 --- a/intrinsics/probes/tcgen05_cp_128x256b_b6x16_p32.ll +++ b/intrinsics/probes/tcgen05_cp_128x256b_b6x16_p32.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_cp_128x256b_b6x16_p32_cg2.ll b/intrinsics/probes/tcgen05_cp_128x256b_b6x16_p32_cg2.ll index bb73b0014c..cf2cfc8060 100644 --- a/intrinsics/probes/tcgen05_cp_128x256b_b6x16_p32_cg2.ll +++ b/intrinsics/probes/tcgen05_cp_128x256b_b6x16_p32_cg2.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_cp_32x128b_warpx4.ll b/intrinsics/probes/tcgen05_cp_32x128b_warpx4.ll index 90e50690ba..fe1fd31d4f 100644 --- a/intrinsics/probes/tcgen05_cp_32x128b_warpx4.ll +++ b/intrinsics/probes/tcgen05_cp_32x128b_warpx4.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_cp_32x128b_warpx4_b4x16_p64.ll b/intrinsics/probes/tcgen05_cp_32x128b_warpx4_b4x16_p64.ll index 6839612170..07a105466e 100644 --- a/intrinsics/probes/tcgen05_cp_32x128b_warpx4_b4x16_p64.ll +++ b/intrinsics/probes/tcgen05_cp_32x128b_warpx4_b4x16_p64.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_cp_32x128b_warpx4_b4x16_p64_cg2.ll b/intrinsics/probes/tcgen05_cp_32x128b_warpx4_b4x16_p64_cg2.ll index e934fbb476..9b535df2f0 100644 --- a/intrinsics/probes/tcgen05_cp_32x128b_warpx4_b4x16_p64_cg2.ll +++ b/intrinsics/probes/tcgen05_cp_32x128b_warpx4_b4x16_p64_cg2.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_cp_32x128b_warpx4_b6x16_p32.ll b/intrinsics/probes/tcgen05_cp_32x128b_warpx4_b6x16_p32.ll index 861175a295..4be15a6303 100644 --- a/intrinsics/probes/tcgen05_cp_32x128b_warpx4_b6x16_p32.ll +++ b/intrinsics/probes/tcgen05_cp_32x128b_warpx4_b6x16_p32.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_cp_32x128b_warpx4_b6x16_p32_cg2.ll b/intrinsics/probes/tcgen05_cp_32x128b_warpx4_b6x16_p32_cg2.ll index 3e84b39889..7e16dc90a3 100644 --- a/intrinsics/probes/tcgen05_cp_32x128b_warpx4_b6x16_p32_cg2.ll +++ b/intrinsics/probes/tcgen05_cp_32x128b_warpx4_b6x16_p32_cg2.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_cp_32x128b_warpx4_cg2.ll b/intrinsics/probes/tcgen05_cp_32x128b_warpx4_cg2.ll index 6449b6ea12..414ad080ab 100644 --- a/intrinsics/probes/tcgen05_cp_32x128b_warpx4_cg2.ll +++ b/intrinsics/probes/tcgen05_cp_32x128b_warpx4_cg2.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_cp_4x256b.ll b/intrinsics/probes/tcgen05_cp_4x256b.ll index d03bb99bb0..fac67dc1a4 100644 --- a/intrinsics/probes/tcgen05_cp_4x256b.ll +++ b/intrinsics/probes/tcgen05_cp_4x256b.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_cp_4x256b_b4x16_p64.ll b/intrinsics/probes/tcgen05_cp_4x256b_b4x16_p64.ll index 36c4241f62..c040c1f158 100644 --- a/intrinsics/probes/tcgen05_cp_4x256b_b4x16_p64.ll +++ b/intrinsics/probes/tcgen05_cp_4x256b_b4x16_p64.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_cp_4x256b_b4x16_p64_cg2.ll b/intrinsics/probes/tcgen05_cp_4x256b_b4x16_p64_cg2.ll index a6f203fefa..6dfadca725 100644 --- a/intrinsics/probes/tcgen05_cp_4x256b_b4x16_p64_cg2.ll +++ b/intrinsics/probes/tcgen05_cp_4x256b_b4x16_p64_cg2.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_cp_4x256b_b6x16_p32.ll b/intrinsics/probes/tcgen05_cp_4x256b_b6x16_p32.ll index b69a1c2995..b8c09411c8 100644 --- a/intrinsics/probes/tcgen05_cp_4x256b_b6x16_p32.ll +++ b/intrinsics/probes/tcgen05_cp_4x256b_b6x16_p32.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_cp_4x256b_b6x16_p32_cg2.ll b/intrinsics/probes/tcgen05_cp_4x256b_b6x16_p32_cg2.ll index e131385600..aaeb9e6037 100644 --- a/intrinsics/probes/tcgen05_cp_4x256b_b6x16_p32_cg2.ll +++ b/intrinsics/probes/tcgen05_cp_4x256b_b6x16_p32_cg2.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_cp_4x256b_cg2.ll b/intrinsics/probes/tcgen05_cp_4x256b_cg2.ll index 2a961fb69d..3d6a8fb11d 100644 --- a/intrinsics/probes/tcgen05_cp_4x256b_cg2.ll +++ b/intrinsics/probes/tcgen05_cp_4x256b_cg2.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_cp_64x128b_warpx2_01_23.ll b/intrinsics/probes/tcgen05_cp_64x128b_warpx2_01_23.ll index 55713f7411..50a5879fc9 100644 --- a/intrinsics/probes/tcgen05_cp_64x128b_warpx2_01_23.ll +++ b/intrinsics/probes/tcgen05_cp_64x128b_warpx2_01_23.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_cp_64x128b_warpx2_01_23_b4x16_p64.ll b/intrinsics/probes/tcgen05_cp_64x128b_warpx2_01_23_b4x16_p64.ll index a47743d275..2c9de91b98 100644 --- a/intrinsics/probes/tcgen05_cp_64x128b_warpx2_01_23_b4x16_p64.ll +++ b/intrinsics/probes/tcgen05_cp_64x128b_warpx2_01_23_b4x16_p64.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_cp_64x128b_warpx2_01_23_b4x16_p64_cg2.ll b/intrinsics/probes/tcgen05_cp_64x128b_warpx2_01_23_b4x16_p64_cg2.ll index 9674b54aad..e42ca3d32b 100644 --- a/intrinsics/probes/tcgen05_cp_64x128b_warpx2_01_23_b4x16_p64_cg2.ll +++ b/intrinsics/probes/tcgen05_cp_64x128b_warpx2_01_23_b4x16_p64_cg2.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_cp_64x128b_warpx2_01_23_b6x16_p32.ll b/intrinsics/probes/tcgen05_cp_64x128b_warpx2_01_23_b6x16_p32.ll index 9892decd12..b2af3b697e 100644 --- a/intrinsics/probes/tcgen05_cp_64x128b_warpx2_01_23_b6x16_p32.ll +++ b/intrinsics/probes/tcgen05_cp_64x128b_warpx2_01_23_b6x16_p32.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_cp_64x128b_warpx2_01_23_b6x16_p32_cg2.ll b/intrinsics/probes/tcgen05_cp_64x128b_warpx2_01_23_b6x16_p32_cg2.ll index 4ea3a79c65..fdf80bb596 100644 --- a/intrinsics/probes/tcgen05_cp_64x128b_warpx2_01_23_b6x16_p32_cg2.ll +++ b/intrinsics/probes/tcgen05_cp_64x128b_warpx2_01_23_b6x16_p32_cg2.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_cp_64x128b_warpx2_01_23_cg2.ll b/intrinsics/probes/tcgen05_cp_64x128b_warpx2_01_23_cg2.ll index 90e213898c..cd3538bf60 100644 --- a/intrinsics/probes/tcgen05_cp_64x128b_warpx2_01_23_cg2.ll +++ b/intrinsics/probes/tcgen05_cp_64x128b_warpx2_01_23_cg2.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_cp_64x128b_warpx2_02_13.ll b/intrinsics/probes/tcgen05_cp_64x128b_warpx2_02_13.ll index 0cadaedcda..2588076a51 100644 --- a/intrinsics/probes/tcgen05_cp_64x128b_warpx2_02_13.ll +++ b/intrinsics/probes/tcgen05_cp_64x128b_warpx2_02_13.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_cp_64x128b_warpx2_02_13_b4x16_p64.ll b/intrinsics/probes/tcgen05_cp_64x128b_warpx2_02_13_b4x16_p64.ll index f85706ea5c..9bee6a3bcd 100644 --- a/intrinsics/probes/tcgen05_cp_64x128b_warpx2_02_13_b4x16_p64.ll +++ b/intrinsics/probes/tcgen05_cp_64x128b_warpx2_02_13_b4x16_p64.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_cp_64x128b_warpx2_02_13_b4x16_p64_cg2.ll b/intrinsics/probes/tcgen05_cp_64x128b_warpx2_02_13_b4x16_p64_cg2.ll index 83d075b3f5..d8e2aa07b2 100644 --- a/intrinsics/probes/tcgen05_cp_64x128b_warpx2_02_13_b4x16_p64_cg2.ll +++ b/intrinsics/probes/tcgen05_cp_64x128b_warpx2_02_13_b4x16_p64_cg2.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_cp_64x128b_warpx2_02_13_b6x16_p32.ll b/intrinsics/probes/tcgen05_cp_64x128b_warpx2_02_13_b6x16_p32.ll index e046155673..e36b4af67d 100644 --- a/intrinsics/probes/tcgen05_cp_64x128b_warpx2_02_13_b6x16_p32.ll +++ b/intrinsics/probes/tcgen05_cp_64x128b_warpx2_02_13_b6x16_p32.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_cp_64x128b_warpx2_02_13_b6x16_p32_cg2.ll b/intrinsics/probes/tcgen05_cp_64x128b_warpx2_02_13_b6x16_p32_cg2.ll index 31a45dd82e..f8a30e5f47 100644 --- a/intrinsics/probes/tcgen05_cp_64x128b_warpx2_02_13_b6x16_p32_cg2.ll +++ b/intrinsics/probes/tcgen05_cp_64x128b_warpx2_02_13_b6x16_p32_cg2.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_cp_64x128b_warpx2_02_13_cg2.ll b/intrinsics/probes/tcgen05_cp_64x128b_warpx2_02_13_cg2.ll index 9f796edda5..ef9e710cb5 100644 --- a/intrinsics/probes/tcgen05_cp_64x128b_warpx2_02_13_cg2.ll +++ b/intrinsics/probes/tcgen05_cp_64x128b_warpx2_02_13_cg2.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_cp_smem_to_tmem.ll b/intrinsics/probes/tcgen05_cp_smem_to_tmem.ll index e2f537b12b..ba9baeeb46 100644 --- a/intrinsics/probes/tcgen05_cp_smem_to_tmem.ll +++ b/intrinsics/probes/tcgen05_cp_smem_to_tmem.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_cp_smem_to_tmem_cg2.ll b/intrinsics/probes/tcgen05_cp_smem_to_tmem_cg2.ll index 4ab19ba203..626de64029 100644 --- a/intrinsics/probes/tcgen05_cp_smem_to_tmem_cg2.ll +++ b/intrinsics/probes/tcgen05_cp_smem_to_tmem_cg2.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_dealloc.ll b/intrinsics/probes/tcgen05_dealloc.ll index 724a158a39..ed3a0d282f 100644 --- a/intrinsics/probes/tcgen05_dealloc.ll +++ b/intrinsics/probes/tcgen05_dealloc.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_dealloc_cg2.ll b/intrinsics/probes/tcgen05_dealloc_cg2.ll index e31fce6905..4d05f52b8d 100644 --- a/intrinsics/probes/tcgen05_dealloc_cg2.ll +++ b/intrinsics/probes/tcgen05_dealloc_cg2.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_fence_after_thread_sync.ll b/intrinsics/probes/tcgen05_fence_after_thread_sync.ll index bcf288ee5d..ed8195f0f5 100644 --- a/intrinsics/probes/tcgen05_fence_after_thread_sync.ll +++ b/intrinsics/probes/tcgen05_fence_after_thread_sync.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_fence_before_thread_sync.ll b/intrinsics/probes/tcgen05_fence_before_thread_sync.ll index c51255f13d..7cf5aeeaaa 100644 --- a/intrinsics/probes/tcgen05_fence_before_thread_sync.ll +++ b/intrinsics/probes/tcgen05_fence_before_thread_sync.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_ld_16x128b_x16_pack16.ll b/intrinsics/probes/tcgen05_ld_16x128b_x16_pack16.ll index 806b23c038..ee79d0f654 100644 --- a/intrinsics/probes/tcgen05_ld_16x128b_x16_pack16.ll +++ b/intrinsics/probes/tcgen05_ld_16x128b_x16_pack16.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_ld_16x128b_x16_raw.ll b/intrinsics/probes/tcgen05_ld_16x128b_x16_raw.ll index 9ab57bc9fe..4df11af768 100644 --- a/intrinsics/probes/tcgen05_ld_16x128b_x16_raw.ll +++ b/intrinsics/probes/tcgen05_ld_16x128b_x16_raw.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_ld_16x128b_x1_pack16.ll b/intrinsics/probes/tcgen05_ld_16x128b_x1_pack16.ll index 5c9d4e99d6..4542e164f3 100644 --- a/intrinsics/probes/tcgen05_ld_16x128b_x1_pack16.ll +++ b/intrinsics/probes/tcgen05_ld_16x128b_x1_pack16.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_ld_16x128b_x1_raw.ll b/intrinsics/probes/tcgen05_ld_16x128b_x1_raw.ll index 989de29014..0e4e9ea546 100644 --- a/intrinsics/probes/tcgen05_ld_16x128b_x1_raw.ll +++ b/intrinsics/probes/tcgen05_ld_16x128b_x1_raw.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_ld_16x128b_x2_pack16.ll b/intrinsics/probes/tcgen05_ld_16x128b_x2_pack16.ll index 5f3695f189..078de58870 100644 --- a/intrinsics/probes/tcgen05_ld_16x128b_x2_pack16.ll +++ b/intrinsics/probes/tcgen05_ld_16x128b_x2_pack16.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_ld_16x128b_x2_raw.ll b/intrinsics/probes/tcgen05_ld_16x128b_x2_raw.ll index debe4bf19a..e79500371e 100644 --- a/intrinsics/probes/tcgen05_ld_16x128b_x2_raw.ll +++ b/intrinsics/probes/tcgen05_ld_16x128b_x2_raw.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_ld_16x128b_x32_pack16.ll b/intrinsics/probes/tcgen05_ld_16x128b_x32_pack16.ll index 723fc8e3d7..a745dfe154 100644 --- a/intrinsics/probes/tcgen05_ld_16x128b_x32_pack16.ll +++ b/intrinsics/probes/tcgen05_ld_16x128b_x32_pack16.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_ld_16x128b_x32_raw.ll b/intrinsics/probes/tcgen05_ld_16x128b_x32_raw.ll index 75dfa2273d..be1fbd4983 100644 --- a/intrinsics/probes/tcgen05_ld_16x128b_x32_raw.ll +++ b/intrinsics/probes/tcgen05_ld_16x128b_x32_raw.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_ld_16x128b_x4_pack16.ll b/intrinsics/probes/tcgen05_ld_16x128b_x4_pack16.ll index b2a7d3ded5..ef0af532a1 100644 --- a/intrinsics/probes/tcgen05_ld_16x128b_x4_pack16.ll +++ b/intrinsics/probes/tcgen05_ld_16x128b_x4_pack16.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_ld_16x128b_x4_raw.ll b/intrinsics/probes/tcgen05_ld_16x128b_x4_raw.ll index 1d1ea63ef0..c82ebab4b3 100644 --- a/intrinsics/probes/tcgen05_ld_16x128b_x4_raw.ll +++ b/intrinsics/probes/tcgen05_ld_16x128b_x4_raw.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_ld_16x128b_x64_pack16.ll b/intrinsics/probes/tcgen05_ld_16x128b_x64_pack16.ll index 6e1dd9d3ad..2e382189ec 100644 --- a/intrinsics/probes/tcgen05_ld_16x128b_x64_pack16.ll +++ b/intrinsics/probes/tcgen05_ld_16x128b_x64_pack16.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_ld_16x128b_x64_raw.ll b/intrinsics/probes/tcgen05_ld_16x128b_x64_raw.ll index 36672d6543..6e84c957dc 100644 --- a/intrinsics/probes/tcgen05_ld_16x128b_x64_raw.ll +++ b/intrinsics/probes/tcgen05_ld_16x128b_x64_raw.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_ld_16x128b_x8_pack16.ll b/intrinsics/probes/tcgen05_ld_16x128b_x8_pack16.ll index b75f2da964..08416ef172 100644 --- a/intrinsics/probes/tcgen05_ld_16x128b_x8_pack16.ll +++ b/intrinsics/probes/tcgen05_ld_16x128b_x8_pack16.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_ld_16x128b_x8_raw.ll b/intrinsics/probes/tcgen05_ld_16x128b_x8_raw.ll index bcb999ea64..5a6a3a788f 100644 --- a/intrinsics/probes/tcgen05_ld_16x128b_x8_raw.ll +++ b/intrinsics/probes/tcgen05_ld_16x128b_x8_raw.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_ld_16x256b_pure.ll b/intrinsics/probes/tcgen05_ld_16x256b_pure.ll index 6a5bb19061..ba56c52d23 100644 --- a/intrinsics/probes/tcgen05_ld_16x256b_pure.ll +++ b/intrinsics/probes/tcgen05_ld_16x256b_pure.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_ld_16x256b_x16_pack16.ll b/intrinsics/probes/tcgen05_ld_16x256b_x16_pack16.ll index 5bb9393a83..6f997b961d 100644 --- a/intrinsics/probes/tcgen05_ld_16x256b_x16_pack16.ll +++ b/intrinsics/probes/tcgen05_ld_16x256b_x16_pack16.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_ld_16x256b_x16_raw.ll b/intrinsics/probes/tcgen05_ld_16x256b_x16_raw.ll index 69954160ef..b1ba3b9ebc 100644 --- a/intrinsics/probes/tcgen05_ld_16x256b_x16_raw.ll +++ b/intrinsics/probes/tcgen05_ld_16x256b_x16_raw.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_ld_16x256b_x1_pack16.ll b/intrinsics/probes/tcgen05_ld_16x256b_x1_pack16.ll index 84434e6513..087fd615d3 100644 --- a/intrinsics/probes/tcgen05_ld_16x256b_x1_pack16.ll +++ b/intrinsics/probes/tcgen05_ld_16x256b_x1_pack16.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_ld_16x256b_x1_raw.ll b/intrinsics/probes/tcgen05_ld_16x256b_x1_raw.ll index 38fb9e9825..bfbdccdaa9 100644 --- a/intrinsics/probes/tcgen05_ld_16x256b_x1_raw.ll +++ b/intrinsics/probes/tcgen05_ld_16x256b_x1_raw.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_ld_16x256b_x2_pack16.ll b/intrinsics/probes/tcgen05_ld_16x256b_x2_pack16.ll index 925ab0afc9..6efae85f4d 100644 --- a/intrinsics/probes/tcgen05_ld_16x256b_x2_pack16.ll +++ b/intrinsics/probes/tcgen05_ld_16x256b_x2_pack16.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_ld_16x256b_x2_raw.ll b/intrinsics/probes/tcgen05_ld_16x256b_x2_raw.ll index 466fdc540b..2c4a53aecc 100644 --- a/intrinsics/probes/tcgen05_ld_16x256b_x2_raw.ll +++ b/intrinsics/probes/tcgen05_ld_16x256b_x2_raw.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_ld_16x256b_x32_pack16.ll b/intrinsics/probes/tcgen05_ld_16x256b_x32_pack16.ll index 98e32682c0..e66ca3a193 100644 --- a/intrinsics/probes/tcgen05_ld_16x256b_x32_pack16.ll +++ b/intrinsics/probes/tcgen05_ld_16x256b_x32_pack16.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_ld_16x256b_x32_raw.ll b/intrinsics/probes/tcgen05_ld_16x256b_x32_raw.ll index 1a8bbfd20c..11c2fee3c6 100644 --- a/intrinsics/probes/tcgen05_ld_16x256b_x32_raw.ll +++ b/intrinsics/probes/tcgen05_ld_16x256b_x32_raw.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_ld_16x256b_x4_pack16.ll b/intrinsics/probes/tcgen05_ld_16x256b_x4_pack16.ll index 2550679a73..ad3fbe50ee 100644 --- a/intrinsics/probes/tcgen05_ld_16x256b_x4_pack16.ll +++ b/intrinsics/probes/tcgen05_ld_16x256b_x4_pack16.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_ld_16x256b_x4_raw.ll b/intrinsics/probes/tcgen05_ld_16x256b_x4_raw.ll index e8ae23b374..cfc8bbd707 100644 --- a/intrinsics/probes/tcgen05_ld_16x256b_x4_raw.ll +++ b/intrinsics/probes/tcgen05_ld_16x256b_x4_raw.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_ld_16x256b_x8_pack16.ll b/intrinsics/probes/tcgen05_ld_16x256b_x8_pack16.ll index 328ef7325f..8787723a14 100644 --- a/intrinsics/probes/tcgen05_ld_16x256b_x8_pack16.ll +++ b/intrinsics/probes/tcgen05_ld_16x256b_x8_pack16.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_ld_16x256b_x8_pure.ll b/intrinsics/probes/tcgen05_ld_16x256b_x8_pure.ll index d5c49f8b25..67d26b256b 100644 --- a/intrinsics/probes/tcgen05_ld_16x256b_x8_pure.ll +++ b/intrinsics/probes/tcgen05_ld_16x256b_x8_pure.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_ld_16x256b_x8_raw.ll b/intrinsics/probes/tcgen05_ld_16x256b_x8_raw.ll index b1f572fb42..75be667be5 100644 --- a/intrinsics/probes/tcgen05_ld_16x256b_x8_raw.ll +++ b/intrinsics/probes/tcgen05_ld_16x256b_x8_raw.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_ld_16x32bx2_x128_pack16.ll b/intrinsics/probes/tcgen05_ld_16x32bx2_x128_pack16.ll index 1d72c19276..8e8c77214e 100644 --- a/intrinsics/probes/tcgen05_ld_16x32bx2_x128_pack16.ll +++ b/intrinsics/probes/tcgen05_ld_16x32bx2_x128_pack16.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_ld_16x32bx2_x128_raw.ll b/intrinsics/probes/tcgen05_ld_16x32bx2_x128_raw.ll index 407112d09c..cf454f440d 100644 --- a/intrinsics/probes/tcgen05_ld_16x32bx2_x128_raw.ll +++ b/intrinsics/probes/tcgen05_ld_16x32bx2_x128_raw.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_ld_16x32bx2_x16_pack16.ll b/intrinsics/probes/tcgen05_ld_16x32bx2_x16_pack16.ll index 0e2f7be418..87e905ffc7 100644 --- a/intrinsics/probes/tcgen05_ld_16x32bx2_x16_pack16.ll +++ b/intrinsics/probes/tcgen05_ld_16x32bx2_x16_pack16.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_ld_16x32bx2_x16_raw.ll b/intrinsics/probes/tcgen05_ld_16x32bx2_x16_raw.ll index 7e172dac3e..f48799dd72 100644 --- a/intrinsics/probes/tcgen05_ld_16x32bx2_x16_raw.ll +++ b/intrinsics/probes/tcgen05_ld_16x32bx2_x16_raw.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_ld_16x32bx2_x1_pack16.ll b/intrinsics/probes/tcgen05_ld_16x32bx2_x1_pack16.ll index 3ce18fd596..8dcfd2c51e 100644 --- a/intrinsics/probes/tcgen05_ld_16x32bx2_x1_pack16.ll +++ b/intrinsics/probes/tcgen05_ld_16x32bx2_x1_pack16.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_ld_16x32bx2_x1_raw.ll b/intrinsics/probes/tcgen05_ld_16x32bx2_x1_raw.ll index 767d5d0501..034588c346 100644 --- a/intrinsics/probes/tcgen05_ld_16x32bx2_x1_raw.ll +++ b/intrinsics/probes/tcgen05_ld_16x32bx2_x1_raw.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_ld_16x32bx2_x2_pack16.ll b/intrinsics/probes/tcgen05_ld_16x32bx2_x2_pack16.ll index d2d11b60ed..9722aafe63 100644 --- a/intrinsics/probes/tcgen05_ld_16x32bx2_x2_pack16.ll +++ b/intrinsics/probes/tcgen05_ld_16x32bx2_x2_pack16.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_ld_16x32bx2_x2_raw.ll b/intrinsics/probes/tcgen05_ld_16x32bx2_x2_raw.ll index 9cf184467d..8f7e2c1f40 100644 --- a/intrinsics/probes/tcgen05_ld_16x32bx2_x2_raw.ll +++ b/intrinsics/probes/tcgen05_ld_16x32bx2_x2_raw.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_ld_16x32bx2_x32_pack16.ll b/intrinsics/probes/tcgen05_ld_16x32bx2_x32_pack16.ll index 66d6df815a..1e552b4407 100644 --- a/intrinsics/probes/tcgen05_ld_16x32bx2_x32_pack16.ll +++ b/intrinsics/probes/tcgen05_ld_16x32bx2_x32_pack16.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_ld_16x32bx2_x32_raw.ll b/intrinsics/probes/tcgen05_ld_16x32bx2_x32_raw.ll index 77ac790f2d..c3dd546931 100644 --- a/intrinsics/probes/tcgen05_ld_16x32bx2_x32_raw.ll +++ b/intrinsics/probes/tcgen05_ld_16x32bx2_x32_raw.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_ld_16x32bx2_x4_pack16.ll b/intrinsics/probes/tcgen05_ld_16x32bx2_x4_pack16.ll index 37aef78deb..4c988fc957 100644 --- a/intrinsics/probes/tcgen05_ld_16x32bx2_x4_pack16.ll +++ b/intrinsics/probes/tcgen05_ld_16x32bx2_x4_pack16.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_ld_16x32bx2_x4_raw.ll b/intrinsics/probes/tcgen05_ld_16x32bx2_x4_raw.ll index 2752a08b19..44a9e42218 100644 --- a/intrinsics/probes/tcgen05_ld_16x32bx2_x4_raw.ll +++ b/intrinsics/probes/tcgen05_ld_16x32bx2_x4_raw.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_ld_16x32bx2_x64_pack16.ll b/intrinsics/probes/tcgen05_ld_16x32bx2_x64_pack16.ll index 1561187927..10d512753e 100644 --- a/intrinsics/probes/tcgen05_ld_16x32bx2_x64_pack16.ll +++ b/intrinsics/probes/tcgen05_ld_16x32bx2_x64_pack16.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_ld_16x32bx2_x64_raw.ll b/intrinsics/probes/tcgen05_ld_16x32bx2_x64_raw.ll index e1574adef6..7fe44940a3 100644 --- a/intrinsics/probes/tcgen05_ld_16x32bx2_x64_raw.ll +++ b/intrinsics/probes/tcgen05_ld_16x32bx2_x64_raw.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_ld_16x32bx2_x8_pack16.ll b/intrinsics/probes/tcgen05_ld_16x32bx2_x8_pack16.ll index a8a65c40df..69fb65264c 100644 --- a/intrinsics/probes/tcgen05_ld_16x32bx2_x8_pack16.ll +++ b/intrinsics/probes/tcgen05_ld_16x32bx2_x8_pack16.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_ld_16x32bx2_x8_raw.ll b/intrinsics/probes/tcgen05_ld_16x32bx2_x8_raw.ll index 315b2d588e..75ee225cf3 100644 --- a/intrinsics/probes/tcgen05_ld_16x32bx2_x8_raw.ll +++ b/intrinsics/probes/tcgen05_ld_16x32bx2_x8_raw.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_ld_16x64b_x128_pack16.ll b/intrinsics/probes/tcgen05_ld_16x64b_x128_pack16.ll index 26bcc53f16..554cfb3a0e 100644 --- a/intrinsics/probes/tcgen05_ld_16x64b_x128_pack16.ll +++ b/intrinsics/probes/tcgen05_ld_16x64b_x128_pack16.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_ld_16x64b_x128_raw.ll b/intrinsics/probes/tcgen05_ld_16x64b_x128_raw.ll index e46dd5c6d0..393b76b785 100644 --- a/intrinsics/probes/tcgen05_ld_16x64b_x128_raw.ll +++ b/intrinsics/probes/tcgen05_ld_16x64b_x128_raw.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_ld_16x64b_x16_pack16.ll b/intrinsics/probes/tcgen05_ld_16x64b_x16_pack16.ll index c24693aaad..3d1838419b 100644 --- a/intrinsics/probes/tcgen05_ld_16x64b_x16_pack16.ll +++ b/intrinsics/probes/tcgen05_ld_16x64b_x16_pack16.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_ld_16x64b_x16_raw.ll b/intrinsics/probes/tcgen05_ld_16x64b_x16_raw.ll index 64e8086afc..72ca9fcee0 100644 --- a/intrinsics/probes/tcgen05_ld_16x64b_x16_raw.ll +++ b/intrinsics/probes/tcgen05_ld_16x64b_x16_raw.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_ld_16x64b_x1_pack16.ll b/intrinsics/probes/tcgen05_ld_16x64b_x1_pack16.ll index 450673bc59..c88ec1a474 100644 --- a/intrinsics/probes/tcgen05_ld_16x64b_x1_pack16.ll +++ b/intrinsics/probes/tcgen05_ld_16x64b_x1_pack16.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_ld_16x64b_x1_raw.ll b/intrinsics/probes/tcgen05_ld_16x64b_x1_raw.ll index a9548a83d3..ba1aee7dd6 100644 --- a/intrinsics/probes/tcgen05_ld_16x64b_x1_raw.ll +++ b/intrinsics/probes/tcgen05_ld_16x64b_x1_raw.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_ld_16x64b_x2_pack16.ll b/intrinsics/probes/tcgen05_ld_16x64b_x2_pack16.ll index 217a54c19f..4ffd35b1d6 100644 --- a/intrinsics/probes/tcgen05_ld_16x64b_x2_pack16.ll +++ b/intrinsics/probes/tcgen05_ld_16x64b_x2_pack16.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_ld_16x64b_x2_raw.ll b/intrinsics/probes/tcgen05_ld_16x64b_x2_raw.ll index f50530e114..43e7a5e8ee 100644 --- a/intrinsics/probes/tcgen05_ld_16x64b_x2_raw.ll +++ b/intrinsics/probes/tcgen05_ld_16x64b_x2_raw.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_ld_16x64b_x32_pack16.ll b/intrinsics/probes/tcgen05_ld_16x64b_x32_pack16.ll index 38c260ccd4..409fc00a58 100644 --- a/intrinsics/probes/tcgen05_ld_16x64b_x32_pack16.ll +++ b/intrinsics/probes/tcgen05_ld_16x64b_x32_pack16.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_ld_16x64b_x32_raw.ll b/intrinsics/probes/tcgen05_ld_16x64b_x32_raw.ll index ac17e535f0..ffde216bd3 100644 --- a/intrinsics/probes/tcgen05_ld_16x64b_x32_raw.ll +++ b/intrinsics/probes/tcgen05_ld_16x64b_x32_raw.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_ld_16x64b_x4_pack16.ll b/intrinsics/probes/tcgen05_ld_16x64b_x4_pack16.ll index dd5ad53623..28b0bd0842 100644 --- a/intrinsics/probes/tcgen05_ld_16x64b_x4_pack16.ll +++ b/intrinsics/probes/tcgen05_ld_16x64b_x4_pack16.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_ld_16x64b_x4_raw.ll b/intrinsics/probes/tcgen05_ld_16x64b_x4_raw.ll index 95c466eb73..7ce8400a21 100644 --- a/intrinsics/probes/tcgen05_ld_16x64b_x4_raw.ll +++ b/intrinsics/probes/tcgen05_ld_16x64b_x4_raw.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_ld_16x64b_x64_pack16.ll b/intrinsics/probes/tcgen05_ld_16x64b_x64_pack16.ll index 0f202bb398..9f6c640f02 100644 --- a/intrinsics/probes/tcgen05_ld_16x64b_x64_pack16.ll +++ b/intrinsics/probes/tcgen05_ld_16x64b_x64_pack16.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_ld_16x64b_x64_raw.ll b/intrinsics/probes/tcgen05_ld_16x64b_x64_raw.ll index 1d51b2b0af..b62e7287ba 100644 --- a/intrinsics/probes/tcgen05_ld_16x64b_x64_raw.ll +++ b/intrinsics/probes/tcgen05_ld_16x64b_x64_raw.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_ld_16x64b_x8_pack16.ll b/intrinsics/probes/tcgen05_ld_16x64b_x8_pack16.ll index b2f5f611e7..6493526ab4 100644 --- a/intrinsics/probes/tcgen05_ld_16x64b_x8_pack16.ll +++ b/intrinsics/probes/tcgen05_ld_16x64b_x8_pack16.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_ld_16x64b_x8_raw.ll b/intrinsics/probes/tcgen05_ld_16x64b_x8_raw.ll index f6aafab23d..5e27e3cd9a 100644 --- a/intrinsics/probes/tcgen05_ld_16x64b_x8_raw.ll +++ b/intrinsics/probes/tcgen05_ld_16x64b_x8_raw.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_ld_32x32b_x128_pack16.ll b/intrinsics/probes/tcgen05_ld_32x32b_x128_pack16.ll index bf2816b921..53063e7b86 100644 --- a/intrinsics/probes/tcgen05_ld_32x32b_x128_pack16.ll +++ b/intrinsics/probes/tcgen05_ld_32x32b_x128_pack16.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_ld_32x32b_x128_raw.ll b/intrinsics/probes/tcgen05_ld_32x32b_x128_raw.ll index 7080de6ea8..4d0cf9935d 100644 --- a/intrinsics/probes/tcgen05_ld_32x32b_x128_raw.ll +++ b/intrinsics/probes/tcgen05_ld_32x32b_x128_raw.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_ld_32x32b_x16_pack16.ll b/intrinsics/probes/tcgen05_ld_32x32b_x16_pack16.ll index 1570bb47c3..4f606b52de 100644 --- a/intrinsics/probes/tcgen05_ld_32x32b_x16_pack16.ll +++ b/intrinsics/probes/tcgen05_ld_32x32b_x16_pack16.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_ld_32x32b_x16_raw.ll b/intrinsics/probes/tcgen05_ld_32x32b_x16_raw.ll index e79e98cc41..b1448185ca 100644 --- a/intrinsics/probes/tcgen05_ld_32x32b_x16_raw.ll +++ b/intrinsics/probes/tcgen05_ld_32x32b_x16_raw.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_ld_32x32b_x1_pack16.ll b/intrinsics/probes/tcgen05_ld_32x32b_x1_pack16.ll index 781bb015bc..7ce8be86de 100644 --- a/intrinsics/probes/tcgen05_ld_32x32b_x1_pack16.ll +++ b/intrinsics/probes/tcgen05_ld_32x32b_x1_pack16.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_ld_32x32b_x1_raw.ll b/intrinsics/probes/tcgen05_ld_32x32b_x1_raw.ll index 56bd3eb924..dc69608896 100644 --- a/intrinsics/probes/tcgen05_ld_32x32b_x1_raw.ll +++ b/intrinsics/probes/tcgen05_ld_32x32b_x1_raw.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_ld_32x32b_x2_pack16.ll b/intrinsics/probes/tcgen05_ld_32x32b_x2_pack16.ll index 440a9a12c5..dc695f0998 100644 --- a/intrinsics/probes/tcgen05_ld_32x32b_x2_pack16.ll +++ b/intrinsics/probes/tcgen05_ld_32x32b_x2_pack16.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_ld_32x32b_x2_raw.ll b/intrinsics/probes/tcgen05_ld_32x32b_x2_raw.ll index e8d2e7c22b..cb519a7444 100644 --- a/intrinsics/probes/tcgen05_ld_32x32b_x2_raw.ll +++ b/intrinsics/probes/tcgen05_ld_32x32b_x2_raw.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_ld_32x32b_x32_pack16.ll b/intrinsics/probes/tcgen05_ld_32x32b_x32_pack16.ll index 3d7b7f0057..0158e8ecbf 100644 --- a/intrinsics/probes/tcgen05_ld_32x32b_x32_pack16.ll +++ b/intrinsics/probes/tcgen05_ld_32x32b_x32_pack16.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_ld_32x32b_x32_raw.ll b/intrinsics/probes/tcgen05_ld_32x32b_x32_raw.ll index 5ce4d67abe..85cfefc3da 100644 --- a/intrinsics/probes/tcgen05_ld_32x32b_x32_raw.ll +++ b/intrinsics/probes/tcgen05_ld_32x32b_x32_raw.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_ld_32x32b_x4_pack16.ll b/intrinsics/probes/tcgen05_ld_32x32b_x4_pack16.ll index 2f7d7c8959..c0841323c0 100644 --- a/intrinsics/probes/tcgen05_ld_32x32b_x4_pack16.ll +++ b/intrinsics/probes/tcgen05_ld_32x32b_x4_pack16.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_ld_32x32b_x4_raw.ll b/intrinsics/probes/tcgen05_ld_32x32b_x4_raw.ll index 08241b1b3a..2ea9f2087b 100644 --- a/intrinsics/probes/tcgen05_ld_32x32b_x4_raw.ll +++ b/intrinsics/probes/tcgen05_ld_32x32b_x4_raw.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_ld_32x32b_x64_pack16.ll b/intrinsics/probes/tcgen05_ld_32x32b_x64_pack16.ll index b64b5c6d58..c5cc80d087 100644 --- a/intrinsics/probes/tcgen05_ld_32x32b_x64_pack16.ll +++ b/intrinsics/probes/tcgen05_ld_32x32b_x64_pack16.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_ld_32x32b_x64_raw.ll b/intrinsics/probes/tcgen05_ld_32x32b_x64_raw.ll index eecbcadcca..ae77f3ab07 100644 --- a/intrinsics/probes/tcgen05_ld_32x32b_x64_raw.ll +++ b/intrinsics/probes/tcgen05_ld_32x32b_x64_raw.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_ld_32x32b_x8_pack16.ll b/intrinsics/probes/tcgen05_ld_32x32b_x8_pack16.ll index 6f8cb4dd2a..2c7240b481 100644 --- a/intrinsics/probes/tcgen05_ld_32x32b_x8_pack16.ll +++ b/intrinsics/probes/tcgen05_ld_32x32b_x8_pack16.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_ld_32x32b_x8_raw.ll b/intrinsics/probes/tcgen05_ld_32x32b_x8_raw.ll index 88a1a669fb..204b35971d 100644 --- a/intrinsics/probes/tcgen05_ld_32x32b_x8_raw.ll +++ b/intrinsics/probes/tcgen05_ld_32x32b_x8_raw.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_load_wait.ll b/intrinsics/probes/tcgen05_load_wait.ll index df921358fb..3355f4bf49 100644 --- a/intrinsics/probes/tcgen05_load_wait.ll +++ b/intrinsics/probes/tcgen05_load_wait.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_mma_e2m1.ll b/intrinsics/probes/tcgen05_mma_e2m1.ll index b557400102..ba7a20cec9 100644 --- a/intrinsics/probes/tcgen05_mma_e2m1.ll +++ b/intrinsics/probes/tcgen05_mma_e2m1.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_mma_e2m3.ll b/intrinsics/probes/tcgen05_mma_e2m3.ll index 2747a5ae56..2ddc579d3d 100644 --- a/intrinsics/probes/tcgen05_mma_e2m3.ll +++ b/intrinsics/probes/tcgen05_mma_e2m3.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_mma_e3m2.ll b/intrinsics/probes/tcgen05_mma_e3m2.ll index 88379a2887..1369195698 100644 --- a/intrinsics/probes/tcgen05_mma_e3m2.ll +++ b/intrinsics/probes/tcgen05_mma_e3m2.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_mma_e4m3.ll b/intrinsics/probes/tcgen05_mma_e4m3.ll index 18753e8c5b..b17e44169e 100644 --- a/intrinsics/probes/tcgen05_mma_e4m3.ll +++ b/intrinsics/probes/tcgen05_mma_e4m3.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_mma_e5m2.ll b/intrinsics/probes/tcgen05_mma_e5m2.ll index 1b5f3c113e..a3e3152347 100644 --- a/intrinsics/probes/tcgen05_mma_e5m2.ll +++ b/intrinsics/probes/tcgen05_mma_e5m2.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_mma_f16.ll b/intrinsics/probes/tcgen05_mma_f16.ll index 502fafcc25..2f6e702dc1 100644 --- a/intrinsics/probes/tcgen05_mma_f16.ll +++ b/intrinsics/probes/tcgen05_mma_f16.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_mma_f16_cg2.ll b/intrinsics/probes/tcgen05_mma_f16_cg2.ll index 32c8bd4aeb..2900de7665 100644 --- a/intrinsics/probes/tcgen05_mma_f16_cg2.ll +++ b/intrinsics/probes/tcgen05_mma_f16_cg2.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_mma_shared.ll b/intrinsics/probes/tcgen05_mma_shared.ll index 39589bd1a9..2ebe2e7de8 100644 --- a/intrinsics/probes/tcgen05_mma_shared.ll +++ b/intrinsics/probes/tcgen05_mma_shared.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_mma_sp_shared.ll b/intrinsics/probes/tcgen05_mma_sp_shared.ll index 1297699240..b2b0e3f935 100644 --- a/intrinsics/probes/tcgen05_mma_sp_shared.ll +++ b/intrinsics/probes/tcgen05_mma_sp_shared.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_mma_sp_tensor.ll b/intrinsics/probes/tcgen05_mma_sp_tensor.ll index 181cb78f42..8ec6df0c41 100644 --- a/intrinsics/probes/tcgen05_mma_sp_tensor.ll +++ b/intrinsics/probes/tcgen05_mma_sp_tensor.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_mma_sp_tensor_ashift.ll b/intrinsics/probes/tcgen05_mma_sp_tensor_ashift.ll index d038f01072..a8972cedf4 100644 --- a/intrinsics/probes/tcgen05_mma_sp_tensor_ashift.ll +++ b/intrinsics/probes/tcgen05_mma_sp_tensor_ashift.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_mma_tensor.ll b/intrinsics/probes/tcgen05_mma_tensor.ll index 035a27b1e5..5781bcd54f 100644 --- a/intrinsics/probes/tcgen05_mma_tensor.ll +++ b/intrinsics/probes/tcgen05_mma_tensor.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_mma_tensor_ashift.ll b/intrinsics/probes/tcgen05_mma_tensor_ashift.ll index 40561c5dca..7d52532d3b 100644 --- a/intrinsics/probes/tcgen05_mma_tensor_ashift.ll +++ b/intrinsics/probes/tcgen05_mma_tensor_ashift.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_mma_ws_bf16.ll b/intrinsics/probes/tcgen05_mma_ws_bf16.ll index 819ddfc8b5..608dfccbcc 100644 --- a/intrinsics/probes/tcgen05_mma_ws_bf16.ll +++ b/intrinsics/probes/tcgen05_mma_ws_bf16.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_mma_ws_e2m1.ll b/intrinsics/probes/tcgen05_mma_ws_e2m1.ll index 89cd61aeb8..5f065970d8 100644 --- a/intrinsics/probes/tcgen05_mma_ws_e2m1.ll +++ b/intrinsics/probes/tcgen05_mma_ws_e2m1.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_mma_ws_e2m3.ll b/intrinsics/probes/tcgen05_mma_ws_e2m3.ll index 18aed6e6a8..4246b0e196 100644 --- a/intrinsics/probes/tcgen05_mma_ws_e2m3.ll +++ b/intrinsics/probes/tcgen05_mma_ws_e2m3.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_mma_ws_e3m2.ll b/intrinsics/probes/tcgen05_mma_ws_e3m2.ll index 5deba1c051..61028e34ee 100644 --- a/intrinsics/probes/tcgen05_mma_ws_e3m2.ll +++ b/intrinsics/probes/tcgen05_mma_ws_e3m2.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_mma_ws_e4m3.ll b/intrinsics/probes/tcgen05_mma_ws_e4m3.ll index 295545b6ad..4e7ff51e91 100644 --- a/intrinsics/probes/tcgen05_mma_ws_e4m3.ll +++ b/intrinsics/probes/tcgen05_mma_ws_e4m3.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_mma_ws_e5m2.ll b/intrinsics/probes/tcgen05_mma_ws_e5m2.ll index 6187524523..d3215ffb83 100644 --- a/intrinsics/probes/tcgen05_mma_ws_e5m2.ll +++ b/intrinsics/probes/tcgen05_mma_ws_e5m2.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_mma_ws_f16.ll b/intrinsics/probes/tcgen05_mma_ws_f16.ll index f84cea68e5..5bbe73e01f 100644 --- a/intrinsics/probes/tcgen05_mma_ws_f16.ll +++ b/intrinsics/probes/tcgen05_mma_ws_f16.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_mma_ws_shared.ll b/intrinsics/probes/tcgen05_mma_ws_shared.ll index ee8abf38b7..a7ad98fca4 100644 --- a/intrinsics/probes/tcgen05_mma_ws_shared.ll +++ b/intrinsics/probes/tcgen05_mma_ws_shared.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_mma_ws_shared_zero_col_mask.ll b/intrinsics/probes/tcgen05_mma_ws_shared_zero_col_mask.ll index 897ecb73df..b6978de797 100644 --- a/intrinsics/probes/tcgen05_mma_ws_shared_zero_col_mask.ll +++ b/intrinsics/probes/tcgen05_mma_ws_shared_zero_col_mask.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_mma_ws_sp_shared.ll b/intrinsics/probes/tcgen05_mma_ws_sp_shared.ll index 64068028a3..68de190460 100644 --- a/intrinsics/probes/tcgen05_mma_ws_sp_shared.ll +++ b/intrinsics/probes/tcgen05_mma_ws_sp_shared.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_mma_ws_sp_shared_zero_col_mask.ll b/intrinsics/probes/tcgen05_mma_ws_sp_shared_zero_col_mask.ll index 219e31fb07..9afe4d7e62 100644 --- a/intrinsics/probes/tcgen05_mma_ws_sp_shared_zero_col_mask.ll +++ b/intrinsics/probes/tcgen05_mma_ws_sp_shared_zero_col_mask.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_mma_ws_sp_tensor.ll b/intrinsics/probes/tcgen05_mma_ws_sp_tensor.ll index a539c643d1..84c013b7cb 100644 --- a/intrinsics/probes/tcgen05_mma_ws_sp_tensor.ll +++ b/intrinsics/probes/tcgen05_mma_ws_sp_tensor.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_mma_ws_sp_tensor_zero_col_mask.ll b/intrinsics/probes/tcgen05_mma_ws_sp_tensor_zero_col_mask.ll index d9c7511670..1a1cffbe51 100644 --- a/intrinsics/probes/tcgen05_mma_ws_sp_tensor_zero_col_mask.ll +++ b/intrinsics/probes/tcgen05_mma_ws_sp_tensor_zero_col_mask.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_mma_ws_tensor.ll b/intrinsics/probes/tcgen05_mma_ws_tensor.ll index fa08ceac73..4df46b4f30 100644 --- a/intrinsics/probes/tcgen05_mma_ws_tensor.ll +++ b/intrinsics/probes/tcgen05_mma_ws_tensor.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_mma_ws_tensor_zero_col_mask.ll b/intrinsics/probes/tcgen05_mma_ws_tensor_zero_col_mask.ll index a542493fc0..4844ccb466 100644 --- a/intrinsics/probes/tcgen05_mma_ws_tensor_zero_col_mask.ll +++ b/intrinsics/probes/tcgen05_mma_ws_tensor_zero_col_mask.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_mma_ws_tf32.ll b/intrinsics/probes/tcgen05_mma_ws_tf32.ll index 73153f5d3d..98f83c4f70 100644 --- a/intrinsics/probes/tcgen05_mma_ws_tf32.ll +++ b/intrinsics/probes/tcgen05_mma_ws_tf32.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_relinquish_alloc_permit.ll b/intrinsics/probes/tcgen05_relinquish_alloc_permit.ll index b3a6d6ac61..2ded66252f 100644 --- a/intrinsics/probes/tcgen05_relinquish_alloc_permit.ll +++ b/intrinsics/probes/tcgen05_relinquish_alloc_permit.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_relinquish_alloc_permit_cg2.ll b/intrinsics/probes/tcgen05_relinquish_alloc_permit_cg2.ll index 39d32dbabd..e23deefd80 100644 --- a/intrinsics/probes/tcgen05_relinquish_alloc_permit_cg2.ll +++ b/intrinsics/probes/tcgen05_relinquish_alloc_permit_cg2.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_shift_down.ll b/intrinsics/probes/tcgen05_shift_down.ll index 4d61888ce4..6bc24244fb 100644 --- a/intrinsics/probes/tcgen05_shift_down.ll +++ b/intrinsics/probes/tcgen05_shift_down.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_shift_down_cg2.ll b/intrinsics/probes/tcgen05_shift_down_cg2.ll index 5a56c2b2e7..db7ba2797f 100644 --- a/intrinsics/probes/tcgen05_shift_down_cg2.ll +++ b/intrinsics/probes/tcgen05_shift_down_cg2.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_st_16x128b_x16_raw.ll b/intrinsics/probes/tcgen05_st_16x128b_x16_raw.ll index f8c74a7c7c..2342a9b409 100644 --- a/intrinsics/probes/tcgen05_st_16x128b_x16_raw.ll +++ b/intrinsics/probes/tcgen05_st_16x128b_x16_raw.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_st_16x128b_x16_unpack16.ll b/intrinsics/probes/tcgen05_st_16x128b_x16_unpack16.ll index 9bae5cc267..5f47e59b2d 100644 --- a/intrinsics/probes/tcgen05_st_16x128b_x16_unpack16.ll +++ b/intrinsics/probes/tcgen05_st_16x128b_x16_unpack16.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_st_16x128b_x1_raw.ll b/intrinsics/probes/tcgen05_st_16x128b_x1_raw.ll index 4326cf577a..e59dd99dfd 100644 --- a/intrinsics/probes/tcgen05_st_16x128b_x1_raw.ll +++ b/intrinsics/probes/tcgen05_st_16x128b_x1_raw.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_st_16x128b_x1_unpack16.ll b/intrinsics/probes/tcgen05_st_16x128b_x1_unpack16.ll index f395e3afd4..e81ffc4f82 100644 --- a/intrinsics/probes/tcgen05_st_16x128b_x1_unpack16.ll +++ b/intrinsics/probes/tcgen05_st_16x128b_x1_unpack16.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_st_16x128b_x2_raw.ll b/intrinsics/probes/tcgen05_st_16x128b_x2_raw.ll index d4665bc8bc..d5d00d4336 100644 --- a/intrinsics/probes/tcgen05_st_16x128b_x2_raw.ll +++ b/intrinsics/probes/tcgen05_st_16x128b_x2_raw.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_st_16x128b_x2_unpack16.ll b/intrinsics/probes/tcgen05_st_16x128b_x2_unpack16.ll index 36e7bd7135..55493d5ffa 100644 --- a/intrinsics/probes/tcgen05_st_16x128b_x2_unpack16.ll +++ b/intrinsics/probes/tcgen05_st_16x128b_x2_unpack16.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_st_16x128b_x32_raw.ll b/intrinsics/probes/tcgen05_st_16x128b_x32_raw.ll index 167ad9c9bf..03978500c6 100644 --- a/intrinsics/probes/tcgen05_st_16x128b_x32_raw.ll +++ b/intrinsics/probes/tcgen05_st_16x128b_x32_raw.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_st_16x128b_x32_unpack16.ll b/intrinsics/probes/tcgen05_st_16x128b_x32_unpack16.ll index 4a4cb1459c..2a36a7dcb4 100644 --- a/intrinsics/probes/tcgen05_st_16x128b_x32_unpack16.ll +++ b/intrinsics/probes/tcgen05_st_16x128b_x32_unpack16.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_st_16x128b_x4_raw.ll b/intrinsics/probes/tcgen05_st_16x128b_x4_raw.ll index 7610bae9d9..83852a7973 100644 --- a/intrinsics/probes/tcgen05_st_16x128b_x4_raw.ll +++ b/intrinsics/probes/tcgen05_st_16x128b_x4_raw.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_st_16x128b_x4_unpack16.ll b/intrinsics/probes/tcgen05_st_16x128b_x4_unpack16.ll index f3deeca916..ca52b25992 100644 --- a/intrinsics/probes/tcgen05_st_16x128b_x4_unpack16.ll +++ b/intrinsics/probes/tcgen05_st_16x128b_x4_unpack16.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_st_16x128b_x64_raw.ll b/intrinsics/probes/tcgen05_st_16x128b_x64_raw.ll index ad1ee011f0..f2aba61e89 100644 --- a/intrinsics/probes/tcgen05_st_16x128b_x64_raw.ll +++ b/intrinsics/probes/tcgen05_st_16x128b_x64_raw.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_st_16x128b_x64_unpack16.ll b/intrinsics/probes/tcgen05_st_16x128b_x64_unpack16.ll index f62b252856..ebee5307ab 100644 --- a/intrinsics/probes/tcgen05_st_16x128b_x64_unpack16.ll +++ b/intrinsics/probes/tcgen05_st_16x128b_x64_unpack16.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_st_16x128b_x8_raw.ll b/intrinsics/probes/tcgen05_st_16x128b_x8_raw.ll index 917bb24f25..1ae4b748d6 100644 --- a/intrinsics/probes/tcgen05_st_16x128b_x8_raw.ll +++ b/intrinsics/probes/tcgen05_st_16x128b_x8_raw.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_st_16x128b_x8_unpack16.ll b/intrinsics/probes/tcgen05_st_16x128b_x8_unpack16.ll index 55840a7b42..44a8f39f85 100644 --- a/intrinsics/probes/tcgen05_st_16x128b_x8_unpack16.ll +++ b/intrinsics/probes/tcgen05_st_16x128b_x8_unpack16.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_st_16x256b_x16_raw.ll b/intrinsics/probes/tcgen05_st_16x256b_x16_raw.ll index 951c062951..c35cb16aa6 100644 --- a/intrinsics/probes/tcgen05_st_16x256b_x16_raw.ll +++ b/intrinsics/probes/tcgen05_st_16x256b_x16_raw.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_st_16x256b_x16_unpack16.ll b/intrinsics/probes/tcgen05_st_16x256b_x16_unpack16.ll index 06563f031a..b4ed001a26 100644 --- a/intrinsics/probes/tcgen05_st_16x256b_x16_unpack16.ll +++ b/intrinsics/probes/tcgen05_st_16x256b_x16_unpack16.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_st_16x256b_x1_raw.ll b/intrinsics/probes/tcgen05_st_16x256b_x1_raw.ll index cb688e8562..7479ccb541 100644 --- a/intrinsics/probes/tcgen05_st_16x256b_x1_raw.ll +++ b/intrinsics/probes/tcgen05_st_16x256b_x1_raw.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_st_16x256b_x1_unpack16.ll b/intrinsics/probes/tcgen05_st_16x256b_x1_unpack16.ll index 79d5e8d87a..9fc38623a6 100644 --- a/intrinsics/probes/tcgen05_st_16x256b_x1_unpack16.ll +++ b/intrinsics/probes/tcgen05_st_16x256b_x1_unpack16.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_st_16x256b_x2_raw.ll b/intrinsics/probes/tcgen05_st_16x256b_x2_raw.ll index f53acbfadd..79068baaa1 100644 --- a/intrinsics/probes/tcgen05_st_16x256b_x2_raw.ll +++ b/intrinsics/probes/tcgen05_st_16x256b_x2_raw.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_st_16x256b_x2_unpack16.ll b/intrinsics/probes/tcgen05_st_16x256b_x2_unpack16.ll index 88d026c992..89c3cf9408 100644 --- a/intrinsics/probes/tcgen05_st_16x256b_x2_unpack16.ll +++ b/intrinsics/probes/tcgen05_st_16x256b_x2_unpack16.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_st_16x256b_x32_raw.ll b/intrinsics/probes/tcgen05_st_16x256b_x32_raw.ll index 0b87a887c7..c6fa26bb2a 100644 --- a/intrinsics/probes/tcgen05_st_16x256b_x32_raw.ll +++ b/intrinsics/probes/tcgen05_st_16x256b_x32_raw.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_st_16x256b_x32_unpack16.ll b/intrinsics/probes/tcgen05_st_16x256b_x32_unpack16.ll index 14d0b7ee28..497c87f771 100644 --- a/intrinsics/probes/tcgen05_st_16x256b_x32_unpack16.ll +++ b/intrinsics/probes/tcgen05_st_16x256b_x32_unpack16.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_st_16x256b_x4_raw.ll b/intrinsics/probes/tcgen05_st_16x256b_x4_raw.ll index 51ac8c8ff8..da0aaaeef6 100644 --- a/intrinsics/probes/tcgen05_st_16x256b_x4_raw.ll +++ b/intrinsics/probes/tcgen05_st_16x256b_x4_raw.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_st_16x256b_x4_unpack16.ll b/intrinsics/probes/tcgen05_st_16x256b_x4_unpack16.ll index 0b4d78d43e..7275d8590c 100644 --- a/intrinsics/probes/tcgen05_st_16x256b_x4_unpack16.ll +++ b/intrinsics/probes/tcgen05_st_16x256b_x4_unpack16.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_st_16x256b_x8_raw.ll b/intrinsics/probes/tcgen05_st_16x256b_x8_raw.ll index e3a72e70c4..95f30d2afb 100644 --- a/intrinsics/probes/tcgen05_st_16x256b_x8_raw.ll +++ b/intrinsics/probes/tcgen05_st_16x256b_x8_raw.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_st_16x256b_x8_unpack16.ll b/intrinsics/probes/tcgen05_st_16x256b_x8_unpack16.ll index f02db7141d..c2c8a784e0 100644 --- a/intrinsics/probes/tcgen05_st_16x256b_x8_unpack16.ll +++ b/intrinsics/probes/tcgen05_st_16x256b_x8_unpack16.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_st_16x32bx2_x128_raw.ll b/intrinsics/probes/tcgen05_st_16x32bx2_x128_raw.ll index b7075e2719..e68aac6fcf 100644 --- a/intrinsics/probes/tcgen05_st_16x32bx2_x128_raw.ll +++ b/intrinsics/probes/tcgen05_st_16x32bx2_x128_raw.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_st_16x32bx2_x128_unpack16.ll b/intrinsics/probes/tcgen05_st_16x32bx2_x128_unpack16.ll index df4e5fd009..a4b852aef6 100644 --- a/intrinsics/probes/tcgen05_st_16x32bx2_x128_unpack16.ll +++ b/intrinsics/probes/tcgen05_st_16x32bx2_x128_unpack16.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_st_16x32bx2_x16_raw.ll b/intrinsics/probes/tcgen05_st_16x32bx2_x16_raw.ll index 4375518aeb..08c2efceb1 100644 --- a/intrinsics/probes/tcgen05_st_16x32bx2_x16_raw.ll +++ b/intrinsics/probes/tcgen05_st_16x32bx2_x16_raw.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_st_16x32bx2_x16_unpack16.ll b/intrinsics/probes/tcgen05_st_16x32bx2_x16_unpack16.ll index 23c4a65c98..dce6e71390 100644 --- a/intrinsics/probes/tcgen05_st_16x32bx2_x16_unpack16.ll +++ b/intrinsics/probes/tcgen05_st_16x32bx2_x16_unpack16.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_st_16x32bx2_x1_raw.ll b/intrinsics/probes/tcgen05_st_16x32bx2_x1_raw.ll index b347964f57..cbbb77a7ec 100644 --- a/intrinsics/probes/tcgen05_st_16x32bx2_x1_raw.ll +++ b/intrinsics/probes/tcgen05_st_16x32bx2_x1_raw.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_st_16x32bx2_x1_unpack16.ll b/intrinsics/probes/tcgen05_st_16x32bx2_x1_unpack16.ll index 9ce47ff089..c8c8e4c5e3 100644 --- a/intrinsics/probes/tcgen05_st_16x32bx2_x1_unpack16.ll +++ b/intrinsics/probes/tcgen05_st_16x32bx2_x1_unpack16.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_st_16x32bx2_x2_raw.ll b/intrinsics/probes/tcgen05_st_16x32bx2_x2_raw.ll index 7955d5b478..86d96ed94d 100644 --- a/intrinsics/probes/tcgen05_st_16x32bx2_x2_raw.ll +++ b/intrinsics/probes/tcgen05_st_16x32bx2_x2_raw.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_st_16x32bx2_x2_unpack16.ll b/intrinsics/probes/tcgen05_st_16x32bx2_x2_unpack16.ll index f67f8aea52..4fcbdef5d2 100644 --- a/intrinsics/probes/tcgen05_st_16x32bx2_x2_unpack16.ll +++ b/intrinsics/probes/tcgen05_st_16x32bx2_x2_unpack16.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_st_16x32bx2_x32_raw.ll b/intrinsics/probes/tcgen05_st_16x32bx2_x32_raw.ll index 4d12d628be..223ee0702d 100644 --- a/intrinsics/probes/tcgen05_st_16x32bx2_x32_raw.ll +++ b/intrinsics/probes/tcgen05_st_16x32bx2_x32_raw.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_st_16x32bx2_x32_unpack16.ll b/intrinsics/probes/tcgen05_st_16x32bx2_x32_unpack16.ll index c2fbbdd7e0..7bc1b2c703 100644 --- a/intrinsics/probes/tcgen05_st_16x32bx2_x32_unpack16.ll +++ b/intrinsics/probes/tcgen05_st_16x32bx2_x32_unpack16.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_st_16x32bx2_x4_raw.ll b/intrinsics/probes/tcgen05_st_16x32bx2_x4_raw.ll index 89cf5accc8..9096d529e0 100644 --- a/intrinsics/probes/tcgen05_st_16x32bx2_x4_raw.ll +++ b/intrinsics/probes/tcgen05_st_16x32bx2_x4_raw.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_st_16x32bx2_x4_unpack16.ll b/intrinsics/probes/tcgen05_st_16x32bx2_x4_unpack16.ll index df59c81717..f479156ee6 100644 --- a/intrinsics/probes/tcgen05_st_16x32bx2_x4_unpack16.ll +++ b/intrinsics/probes/tcgen05_st_16x32bx2_x4_unpack16.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_st_16x32bx2_x64_raw.ll b/intrinsics/probes/tcgen05_st_16x32bx2_x64_raw.ll index efc06d2187..e4a8a48e8b 100644 --- a/intrinsics/probes/tcgen05_st_16x32bx2_x64_raw.ll +++ b/intrinsics/probes/tcgen05_st_16x32bx2_x64_raw.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_st_16x32bx2_x64_unpack16.ll b/intrinsics/probes/tcgen05_st_16x32bx2_x64_unpack16.ll index 3326169928..7120056b6c 100644 --- a/intrinsics/probes/tcgen05_st_16x32bx2_x64_unpack16.ll +++ b/intrinsics/probes/tcgen05_st_16x32bx2_x64_unpack16.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_st_16x32bx2_x8_raw.ll b/intrinsics/probes/tcgen05_st_16x32bx2_x8_raw.ll index cdf9a4b5bb..a5eabe993e 100644 --- a/intrinsics/probes/tcgen05_st_16x32bx2_x8_raw.ll +++ b/intrinsics/probes/tcgen05_st_16x32bx2_x8_raw.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_st_16x32bx2_x8_unpack16.ll b/intrinsics/probes/tcgen05_st_16x32bx2_x8_unpack16.ll index 98e0c578d2..70155aadb1 100644 --- a/intrinsics/probes/tcgen05_st_16x32bx2_x8_unpack16.ll +++ b/intrinsics/probes/tcgen05_st_16x32bx2_x8_unpack16.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_st_16x64b_x128_raw.ll b/intrinsics/probes/tcgen05_st_16x64b_x128_raw.ll index e301adf7e2..ebfd86dea5 100644 --- a/intrinsics/probes/tcgen05_st_16x64b_x128_raw.ll +++ b/intrinsics/probes/tcgen05_st_16x64b_x128_raw.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_st_16x64b_x128_unpack16.ll b/intrinsics/probes/tcgen05_st_16x64b_x128_unpack16.ll index ea39548135..8d5ea40fe4 100644 --- a/intrinsics/probes/tcgen05_st_16x64b_x128_unpack16.ll +++ b/intrinsics/probes/tcgen05_st_16x64b_x128_unpack16.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_st_16x64b_x16_raw.ll b/intrinsics/probes/tcgen05_st_16x64b_x16_raw.ll index 4c8d940a5f..62e1c895f7 100644 --- a/intrinsics/probes/tcgen05_st_16x64b_x16_raw.ll +++ b/intrinsics/probes/tcgen05_st_16x64b_x16_raw.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_st_16x64b_x16_unpack16.ll b/intrinsics/probes/tcgen05_st_16x64b_x16_unpack16.ll index 931e54c6b7..2156e62166 100644 --- a/intrinsics/probes/tcgen05_st_16x64b_x16_unpack16.ll +++ b/intrinsics/probes/tcgen05_st_16x64b_x16_unpack16.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_st_16x64b_x1_raw.ll b/intrinsics/probes/tcgen05_st_16x64b_x1_raw.ll index 31696ed0d6..a08d107edd 100644 --- a/intrinsics/probes/tcgen05_st_16x64b_x1_raw.ll +++ b/intrinsics/probes/tcgen05_st_16x64b_x1_raw.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_st_16x64b_x1_unpack16.ll b/intrinsics/probes/tcgen05_st_16x64b_x1_unpack16.ll index 835cd9c17b..9a3222ca8b 100644 --- a/intrinsics/probes/tcgen05_st_16x64b_x1_unpack16.ll +++ b/intrinsics/probes/tcgen05_st_16x64b_x1_unpack16.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_st_16x64b_x2_raw.ll b/intrinsics/probes/tcgen05_st_16x64b_x2_raw.ll index 8196771a79..3b2bcd0de9 100644 --- a/intrinsics/probes/tcgen05_st_16x64b_x2_raw.ll +++ b/intrinsics/probes/tcgen05_st_16x64b_x2_raw.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_st_16x64b_x2_unpack16.ll b/intrinsics/probes/tcgen05_st_16x64b_x2_unpack16.ll index a41d22b088..9f3111488e 100644 --- a/intrinsics/probes/tcgen05_st_16x64b_x2_unpack16.ll +++ b/intrinsics/probes/tcgen05_st_16x64b_x2_unpack16.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_st_16x64b_x32_raw.ll b/intrinsics/probes/tcgen05_st_16x64b_x32_raw.ll index 7b27dc6b53..1d506d80da 100644 --- a/intrinsics/probes/tcgen05_st_16x64b_x32_raw.ll +++ b/intrinsics/probes/tcgen05_st_16x64b_x32_raw.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_st_16x64b_x32_unpack16.ll b/intrinsics/probes/tcgen05_st_16x64b_x32_unpack16.ll index 9b7182bc0e..ce90018725 100644 --- a/intrinsics/probes/tcgen05_st_16x64b_x32_unpack16.ll +++ b/intrinsics/probes/tcgen05_st_16x64b_x32_unpack16.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_st_16x64b_x4_raw.ll b/intrinsics/probes/tcgen05_st_16x64b_x4_raw.ll index 6e82e9cf23..a7d9022898 100644 --- a/intrinsics/probes/tcgen05_st_16x64b_x4_raw.ll +++ b/intrinsics/probes/tcgen05_st_16x64b_x4_raw.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_st_16x64b_x4_unpack16.ll b/intrinsics/probes/tcgen05_st_16x64b_x4_unpack16.ll index 8604dbd1f7..de4e524f07 100644 --- a/intrinsics/probes/tcgen05_st_16x64b_x4_unpack16.ll +++ b/intrinsics/probes/tcgen05_st_16x64b_x4_unpack16.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_st_16x64b_x64_raw.ll b/intrinsics/probes/tcgen05_st_16x64b_x64_raw.ll index 577a670b75..d52e902eda 100644 --- a/intrinsics/probes/tcgen05_st_16x64b_x64_raw.ll +++ b/intrinsics/probes/tcgen05_st_16x64b_x64_raw.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_st_16x64b_x64_unpack16.ll b/intrinsics/probes/tcgen05_st_16x64b_x64_unpack16.ll index 33606e270d..1c49c9b86c 100644 --- a/intrinsics/probes/tcgen05_st_16x64b_x64_unpack16.ll +++ b/intrinsics/probes/tcgen05_st_16x64b_x64_unpack16.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_st_16x64b_x8_raw.ll b/intrinsics/probes/tcgen05_st_16x64b_x8_raw.ll index ec687a0ad0..c05072a99d 100644 --- a/intrinsics/probes/tcgen05_st_16x64b_x8_raw.ll +++ b/intrinsics/probes/tcgen05_st_16x64b_x8_raw.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_st_16x64b_x8_unpack16.ll b/intrinsics/probes/tcgen05_st_16x64b_x8_unpack16.ll index c7166cc52f..7175fab183 100644 --- a/intrinsics/probes/tcgen05_st_16x64b_x8_unpack16.ll +++ b/intrinsics/probes/tcgen05_st_16x64b_x8_unpack16.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_st_32x32b_x128_raw.ll b/intrinsics/probes/tcgen05_st_32x32b_x128_raw.ll index d406f726dd..e9d736486f 100644 --- a/intrinsics/probes/tcgen05_st_32x32b_x128_raw.ll +++ b/intrinsics/probes/tcgen05_st_32x32b_x128_raw.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_st_32x32b_x128_unpack16.ll b/intrinsics/probes/tcgen05_st_32x32b_x128_unpack16.ll index e4706508fd..3964c7291c 100644 --- a/intrinsics/probes/tcgen05_st_32x32b_x128_unpack16.ll +++ b/intrinsics/probes/tcgen05_st_32x32b_x128_unpack16.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_st_32x32b_x16_raw.ll b/intrinsics/probes/tcgen05_st_32x32b_x16_raw.ll index 2873bcea6a..e2eda07a6f 100644 --- a/intrinsics/probes/tcgen05_st_32x32b_x16_raw.ll +++ b/intrinsics/probes/tcgen05_st_32x32b_x16_raw.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_st_32x32b_x16_unpack16.ll b/intrinsics/probes/tcgen05_st_32x32b_x16_unpack16.ll index 58aeb58f16..145ad0d0de 100644 --- a/intrinsics/probes/tcgen05_st_32x32b_x16_unpack16.ll +++ b/intrinsics/probes/tcgen05_st_32x32b_x16_unpack16.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_st_32x32b_x1_raw.ll b/intrinsics/probes/tcgen05_st_32x32b_x1_raw.ll index 20050b6f07..4ffcdf8376 100644 --- a/intrinsics/probes/tcgen05_st_32x32b_x1_raw.ll +++ b/intrinsics/probes/tcgen05_st_32x32b_x1_raw.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_st_32x32b_x1_unpack16.ll b/intrinsics/probes/tcgen05_st_32x32b_x1_unpack16.ll index e2d29cc103..0042486455 100644 --- a/intrinsics/probes/tcgen05_st_32x32b_x1_unpack16.ll +++ b/intrinsics/probes/tcgen05_st_32x32b_x1_unpack16.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_st_32x32b_x2_raw.ll b/intrinsics/probes/tcgen05_st_32x32b_x2_raw.ll index 8310ad68bb..8b2d1d6559 100644 --- a/intrinsics/probes/tcgen05_st_32x32b_x2_raw.ll +++ b/intrinsics/probes/tcgen05_st_32x32b_x2_raw.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_st_32x32b_x2_unpack16.ll b/intrinsics/probes/tcgen05_st_32x32b_x2_unpack16.ll index eca830d1bf..e1a52ff247 100644 --- a/intrinsics/probes/tcgen05_st_32x32b_x2_unpack16.ll +++ b/intrinsics/probes/tcgen05_st_32x32b_x2_unpack16.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_st_32x32b_x32_raw.ll b/intrinsics/probes/tcgen05_st_32x32b_x32_raw.ll index 0e3d4bc7af..9afd49129c 100644 --- a/intrinsics/probes/tcgen05_st_32x32b_x32_raw.ll +++ b/intrinsics/probes/tcgen05_st_32x32b_x32_raw.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_st_32x32b_x32_unpack16.ll b/intrinsics/probes/tcgen05_st_32x32b_x32_unpack16.ll index 63902824b2..70ba95ad7f 100644 --- a/intrinsics/probes/tcgen05_st_32x32b_x32_unpack16.ll +++ b/intrinsics/probes/tcgen05_st_32x32b_x32_unpack16.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_st_32x32b_x4_raw.ll b/intrinsics/probes/tcgen05_st_32x32b_x4_raw.ll index a58aa18d9c..4c07cbf2cc 100644 --- a/intrinsics/probes/tcgen05_st_32x32b_x4_raw.ll +++ b/intrinsics/probes/tcgen05_st_32x32b_x4_raw.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_st_32x32b_x4_unpack16.ll b/intrinsics/probes/tcgen05_st_32x32b_x4_unpack16.ll index 829fc5b5e0..baa8dae74b 100644 --- a/intrinsics/probes/tcgen05_st_32x32b_x4_unpack16.ll +++ b/intrinsics/probes/tcgen05_st_32x32b_x4_unpack16.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_st_32x32b_x64_raw.ll b/intrinsics/probes/tcgen05_st_32x32b_x64_raw.ll index d8efc443d7..c1aba2fe2a 100644 --- a/intrinsics/probes/tcgen05_st_32x32b_x64_raw.ll +++ b/intrinsics/probes/tcgen05_st_32x32b_x64_raw.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_st_32x32b_x64_unpack16.ll b/intrinsics/probes/tcgen05_st_32x32b_x64_unpack16.ll index 6989868259..db1cd37544 100644 --- a/intrinsics/probes/tcgen05_st_32x32b_x64_unpack16.ll +++ b/intrinsics/probes/tcgen05_st_32x32b_x64_unpack16.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_st_32x32b_x8_raw.ll b/intrinsics/probes/tcgen05_st_32x32b_x8_raw.ll index 80d60acd95..6fb22b83b4 100644 --- a/intrinsics/probes/tcgen05_st_32x32b_x8_raw.ll +++ b/intrinsics/probes/tcgen05_st_32x32b_x8_raw.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_st_32x32b_x8_unpack16.ll b/intrinsics/probes/tcgen05_st_32x32b_x8_unpack16.ll index e3d03b2e62..b2c0e50e21 100644 --- a/intrinsics/probes/tcgen05_st_32x32b_x8_unpack16.ll +++ b/intrinsics/probes/tcgen05_st_32x32b_x8_unpack16.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tcgen05_store_wait.ll b/intrinsics/probes/tcgen05_store_wait.ll index d9abe4f692..1284942789 100644 --- a/intrinsics/probes/tcgen05_store_wait.ll +++ b/intrinsics/probes/tcgen05_store_wait.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tensormap_replace_box_dim.ll b/intrinsics/probes/tensormap_replace_box_dim.ll index 38718b70a2..abb7b0f6aa 100644 --- a/intrinsics/probes/tensormap_replace_box_dim.ll +++ b/intrinsics/probes/tensormap_replace_box_dim.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tensormap_replace_element_stride.ll b/intrinsics/probes/tensormap_replace_element_stride.ll index a05632cf93..037db5007b 100644 --- a/intrinsics/probes/tensormap_replace_element_stride.ll +++ b/intrinsics/probes/tensormap_replace_element_stride.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tensormap_replace_element_type.ll b/intrinsics/probes/tensormap_replace_element_type.ll index b15d2df26d..6cf6adf8f2 100644 --- a/intrinsics/probes/tensormap_replace_element_type.ll +++ b/intrinsics/probes/tensormap_replace_element_type.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tensormap_replace_fill_mode.ll b/intrinsics/probes/tensormap_replace_fill_mode.ll index 2696fbc2a1..8a4d2f4768 100644 --- a/intrinsics/probes/tensormap_replace_fill_mode.ll +++ b/intrinsics/probes/tensormap_replace_fill_mode.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tensormap_replace_global_address.ll b/intrinsics/probes/tensormap_replace_global_address.ll index 6ac728dab4..d00ee7f347 100644 --- a/intrinsics/probes/tensormap_replace_global_address.ll +++ b/intrinsics/probes/tensormap_replace_global_address.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tensormap_replace_global_dim.ll b/intrinsics/probes/tensormap_replace_global_dim.ll index 8e340579a1..0a241acdfd 100644 --- a/intrinsics/probes/tensormap_replace_global_dim.ll +++ b/intrinsics/probes/tensormap_replace_global_dim.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tensormap_replace_global_stride.ll b/intrinsics/probes/tensormap_replace_global_stride.ll index 95630a7647..a51f76a2fb 100644 --- a/intrinsics/probes/tensormap_replace_global_stride.ll +++ b/intrinsics/probes/tensormap_replace_global_stride.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tensormap_replace_interleave_layout.ll b/intrinsics/probes/tensormap_replace_interleave_layout.ll index 5c5d6dde4c..1ac28cd0ec 100644 --- a/intrinsics/probes/tensormap_replace_interleave_layout.ll +++ b/intrinsics/probes/tensormap_replace_interleave_layout.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tensormap_replace_rank.ll b/intrinsics/probes/tensormap_replace_rank.ll index 079c6025c0..ec2e08d558 100644 --- a/intrinsics/probes/tensormap_replace_rank.ll +++ b/intrinsics/probes/tensormap_replace_rank.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tensormap_replace_swizzle_atomicity.ll b/intrinsics/probes/tensormap_replace_swizzle_atomicity.ll index 7b1db4dbeb..cc2d5a78fd 100644 --- a/intrinsics/probes/tensormap_replace_swizzle_atomicity.ll +++ b/intrinsics/probes/tensormap_replace_swizzle_atomicity.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/tensormap_replace_swizzle_mode.ll b/intrinsics/probes/tensormap_replace_swizzle_mode.ll index 9886893230..1aefdb91f0 100644 --- a/intrinsics/probes/tensormap_replace_swizzle_mode.ll +++ b/intrinsics/probes/tensormap_replace_swizzle_mode.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/thread_idx_x.ll b/intrinsics/probes/thread_idx_x.ll index 434ff2942c..382731ca04 100644 --- a/intrinsics/probes/thread_idx_x.ll +++ b/intrinsics/probes/thread_idx_x.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/thread_idx_y.ll b/intrinsics/probes/thread_idx_y.ll index ea417c2dc8..79044e805d 100644 --- a/intrinsics/probes/thread_idx_y.ll +++ b/intrinsics/probes/thread_idx_y.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/thread_idx_z.ll b/intrinsics/probes/thread_idx_z.ll index aae0d2c695..30baebf69a 100644 --- a/intrinsics/probes/thread_idx_z.ll +++ b/intrinsics/probes/thread_idx_z.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/threadfence.ll b/intrinsics/probes/threadfence.ll index 8be4858d06..6dd8bf00aa 100644 --- a/intrinsics/probes/threadfence.ll +++ b/intrinsics/probes/threadfence.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/threadfence_block.ll b/intrinsics/probes/threadfence_block.ll index 6c516fdcd0..90aea76b18 100644 --- a/intrinsics/probes/threadfence_block.ll +++ b/intrinsics/probes/threadfence_block.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/threadfence_system.ll b/intrinsics/probes/threadfence_system.ll index d48267fc5b..4175c414cc 100644 --- a/intrinsics/probes/threadfence_system.ll +++ b/intrinsics/probes/threadfence_system.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/total_smem_size.lib_nvvm.ll b/intrinsics/probes/total_smem_size.lib_nvvm.ll index 4fb31d549e..0f6309649e 100644 --- a/intrinsics/probes/total_smem_size.lib_nvvm.ll +++ b/intrinsics/probes/total_smem_size.lib_nvvm.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/total_smem_size.llvm_nvptx.ll b/intrinsics/probes/total_smem_size.llvm_nvptx.ll index 3f5cc50925..52ff5296f6 100644 --- a/intrinsics/probes/total_smem_size.llvm_nvptx.ll +++ b/intrinsics/probes/total_smem_size.llvm_nvptx.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/trap.ll b/intrinsics/probes/trap.ll index 26bf29220a..eda9cd7c2b 100644 --- a/intrinsics/probes/trap.ll +++ b/intrinsics/probes/trap.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/uni_sync.ll b/intrinsics/probes/uni_sync.ll index d67c79bf71..088ec7d304 100644 --- a/intrinsics/probes/uni_sync.ll +++ b/intrinsics/probes/uni_sync.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/warpid.lib_nvvm.ll b/intrinsics/probes/warpid.lib_nvvm.ll index 6f26f86303..bf3fbb29e2 100644 --- a/intrinsics/probes/warpid.lib_nvvm.ll +++ b/intrinsics/probes/warpid.lib_nvvm.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/warpid.llvm_nvptx.ll b/intrinsics/probes/warpid.llvm_nvptx.ll index 39cf482763..627d82c99c 100644 --- a/intrinsics/probes/warpid.llvm_nvptx.ll +++ b/intrinsics/probes/warpid.llvm_nvptx.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/wgmma_commit_group.ll b/intrinsics/probes/wgmma_commit_group.ll index 442124f685..78d3d00d7e 100644 --- a/intrinsics/probes/wgmma_commit_group.ll +++ b/intrinsics/probes/wgmma_commit_group.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/wgmma_fence.ll b/intrinsics/probes/wgmma_fence.ll index f684b50ede..8a28e6b348 100644 --- a/intrinsics/probes/wgmma_fence.ll +++ b/intrinsics/probes/wgmma_fence.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" diff --git a/intrinsics/probes/wgmma_wait_group.ll b/intrinsics/probes/wgmma_wait_group.ll index a099232df6..9dd05e6959 100644 --- a/intrinsics/probes/wgmma_wait_group.ll +++ b/intrinsics/probes/wgmma_wait_group.ll @@ -1,7 +1,7 @@ ; SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. ; SPDX-License-Identifier: Apache-2.0 ; @generated by cuda-intrinsics-gen 0.1.0. DO NOT EDIT. -; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 00372dfe2e27296fcd2a4505eff6e547153693b60a4fcc0d1599a4d589193226. +; Catalog schema/version: 46/0.1.0; intrinsic ABI: v1; catalog SHA-256: 9b5ce71ce97b9a58e53bc98541d3449020497dbf7b46b91c1da19faf5b68619f. ; LLVM source: 1cb4e3833c1919c2e6fb579a23ac0e2b22587b7e. target triple = "nvptx64-nvidia-cuda" From 459dd93ffd1b0e6026d5f16aad093acb133a7c4e Mon Sep 17 00:00:00 2001 From: "Sam, Joochul Chang" Date: Sat, 22 Aug 2026 18:47:58 +0900 Subject: [PATCH 2/3] test(examples): compile CTA barrier reductions Signed-off-by: Sam, Joochul Chang --- .../examples/counted_barrier/src/main.rs | 44 ++++++++++++++++++- 1 file changed, 43 insertions(+), 1 deletion(-) diff --git a/crates/rustc-codegen-cuda/examples/counted_barrier/src/main.rs b/crates/rustc-codegen-cuda/examples/counted_barrier/src/main.rs index a7510c5f70..befd809a10 100644 --- a/crates/rustc-codegen-cuda/examples/counted_barrier/src/main.rs +++ b/crates/rustc-codegen-cuda/examples/counted_barrier/src/main.rs @@ -22,12 +22,21 @@ //! //! Both kernels verify the data actually crossed the barrier (values, //! not just completion) and that the bystander warps were unaffected. +//! `barrier_reduction_compile_coverage` additionally keeps every CTA barrier +//! reduction spelling and `barrier.sync id` in the compile-only smoke lane. It +//! is intentionally not launched because local runtime validation is unavailable. //! //! Build and run with: //! cargo oxide run counted_barrier use cuda_core::{CudaContext, DeviceBuffer, LaunchConfig}; -use cuda_device::barrier::{barrier_cta_arrive, barrier_cta_sync}; +use cuda_device::barrier::{ + barrier_cta_arrive, barrier_cta_red_and_aligned_all, barrier_cta_red_and_aligned_count, + barrier_cta_red_and_all, barrier_cta_red_and_count, barrier_cta_red_or_aligned_all, + barrier_cta_red_or_aligned_count, barrier_cta_red_or_all, barrier_cta_red_or_count, + barrier_cta_red_popc_aligned_all, barrier_cta_red_popc_aligned_count, barrier_cta_red_popc_all, + barrier_cta_red_popc_count, barrier_cta_sync, barrier_cta_sync_all, +}; use cuda_device::{DisjointSlice, SharedArray, cuda_module, kernel, thread}; const SENTINEL: u32 = 0xFACE; @@ -99,6 +108,39 @@ mod kernels { *slot = SENTINEL; } } + + /// Compile-only coverage for the twelve reduction forms and numbered + /// all-thread sync. The host deliberately never launches this kernel. + #[kernel] + pub fn barrier_reduction_compile_coverage(mut out: DisjointSlice) { + let tid = thread::threadIdx_x(); + let gid = thread::index_1d(); + let predicate = tid & 1 == 0; + + // SAFETY: this kernel is compile-only evidence. If launched, every + // non-exited CTA thread must execute these calls in the same order and + // the count forms require a 128-thread block. + unsafe { + let _ = barrier_cta_red_and_all(1, predicate); + let _ = barrier_cta_red_and_count(2, 128, predicate); + let _ = barrier_cta_red_and_aligned_all(3, predicate); + let _ = barrier_cta_red_and_aligned_count(4, 128, predicate); + let _ = barrier_cta_red_or_all(5, predicate); + let _ = barrier_cta_red_or_count(6, 128, predicate); + let _ = barrier_cta_red_or_aligned_all(7, predicate); + let _ = barrier_cta_red_or_aligned_count(8, 128, predicate); + let _ = barrier_cta_red_popc_all(9, predicate); + let _ = barrier_cta_red_popc_count(10, 128, predicate); + let _ = barrier_cta_red_popc_aligned_all(11, predicate); + let _ = barrier_cta_red_popc_aligned_count(12, 128, predicate); + } + // SAFETY: same all-thread participation contract as the reductions. + unsafe { barrier_cta_sync_all(13) }; + + if let Some(slot) = out.get_mut(gid) { + *slot = 1; + } + } } fn main() { From fc18327ab9e78c0618354e1ffc735aca1c507c7a Mon Sep 17 00:00:00 2001 From: "Sam, Joochul Chang" Date: Sat, 22 Aug 2026 18:49:30 +0900 Subject: [PATCH 3/3] docs(book): document CTA barrier reductions Signed-off-by: Sam, Joochul Chang --- .../shared-memory-and-synchronization.md | 22 +++++++++++++++++++ .../appendix/api-quick-reference.md | 12 ++++++++++ cuda-oxide-book/appendix/glossary.md | 8 +++++++ .../appendix/supported-features.md | 1 + cuda-oxide-book/compiler/mlir-dialects.md | 12 +++++----- 5 files changed, 49 insertions(+), 6 deletions(-) diff --git a/cuda-oxide-book/advanced/shared-memory-and-synchronization.md b/cuda-oxide-book/advanced/shared-memory-and-synchronization.md index 94a9b88a55..6b16f6fb66 100644 --- a/cuda-oxide-book/advanced/shared-memory-and-synchronization.md +++ b/cuda-oxide-book/advanced/shared-memory-and-synchronization.md @@ -272,6 +272,28 @@ that not all threads take. Every thread in the block must reach the same control flow, restructure so the barrier is outside the branch. ::: +### Numbered CTA barrier reductions + +The unsafe functions in `cuda_device::barrier` expose numbered CTA barriers +that synchronize and reduce a predicate in one operation: + +- `barrier_cta_red_popc_{all,count}` returns the number of participating + threads whose predicate is true. +- `barrier_cta_red_and_{all,count}` returns whether every participating + thread supplied true. +- `barrier_cta_red_or_{all,count}` returns whether any participating thread + supplied true. +- The corresponding `_aligned_` forms select PTX `bar.red`; the other forms + select PTX `barrier.red`. `barrier_cta_sync_all(id)` is the one-operand + numbered-barrier synchronization form. + +The first argument is the barrier ID. A `_count` form also takes the expected +thread count. These are not zero-argument `__syncthreads_*` aliases: every +non-exited thread covered by the barrier protocol must execute a compatible +call, with the same barrier ID and (for `_count`) count. Violating that +participation contract can deadlock the CTA, which is why the APIs are +`unsafe`. + --- ## Shared memory vs. other approaches diff --git a/cuda-oxide-book/appendix/api-quick-reference.md b/cuda-oxide-book/appendix/api-quick-reference.md index e8b726037c..b533bde09e 100644 --- a/cuda-oxide-book/appendix/api-quick-reference.md +++ b/cuda-oxide-book/appendix/api-quick-reference.md @@ -324,6 +324,18 @@ Both are `!Sync` — concurrent access requires explicit barriers. thread::sync_threads(); // __syncthreads() equivalent ``` +Numbered CTA barriers are raw unsafe APIs under `cuda_device::barrier`: + +| API family | Result | PTX spelling | Minimum typed-NVPTX target | +|:-----------|:-------|:-------------|:----------------------------| +| `barrier_cta_red_{and,or,popc}_{all,count}` | `bool`, `bool`, or `u32` | `barrier.red` | PTX 6.0 / sm_30 | +| `barrier_cta_red_{and,or,popc}_aligned_{all,count}` | `bool`, `bool`, or `u32` | `bar.red` | PTX 3.2 / sm_20 | +| `barrier_cta_sync_all(id)` | `()` | `barrier.sync` | PTX 6.0 / sm_30 | + +The CUDA 12.9 libNVVM inline-PTX route is recorded and validated at sm_75. +All participating non-exited CTA threads must use a compatible barrier ID and +count. + ### Managed Barriers (Hopper+) ```rust diff --git a/cuda-oxide-book/appendix/glossary.md b/cuda-oxide-book/appendix/glossary.md index 9675437574..8523dd41d1 100644 --- a/cuda-oxide-book/appendix/glossary.md +++ b/cuda-oxide-book/appendix/glossary.md @@ -151,6 +151,14 @@ The block-level barrier: all threads in the thread block must reach this point before any thread proceeds past it. Equivalent to `__syncthreads()` in CUDA C++. Lowers to `llvm.nvvm.barrier0()`. +## CTA barrier reduction + +A numbered block-level barrier that combines synchronization with a predicate +reduction. `popc` counts participating threads whose predicate is true, `and` +requires every participating predicate to be true, and `or` requires at least +one. Every non-exited thread covered by the barrier protocol must reach a +compatible call; count forms additionally name the expected thread count. + ## Tensor Cores Specialized matrix multiply-accumulate hardware units. WGMMA (Hopper, sm_90) diff --git a/cuda-oxide-book/appendix/supported-features.md b/cuda-oxide-book/appendix/supported-features.md index 9506a531d0..9b2ec828db 100644 --- a/cuda-oxide-book/appendix/supported-features.md +++ b/cuda-oxide-book/appendix/supported-features.md @@ -211,6 +211,7 @@ Anonymous promoted allocations remain unsupported. |:--------|:-------|:------------| | Thread/Block/Grid Intrinsics | **Full** | `threadIdx`, `blockIdx`, `blockDim`, `gridDim`. Index witnesses are layout-typed; their uniqueness also depends on matching launch dimensionality. `index_2d_runtime(&slice)` resolves against the slice's own row width, bound once by the host. See [The Safety Model](../gpu-safety/the-safety-model.md). | | Block Synchronization | **Full** | `sync_threads()` — thread block barrier. | +| Numbered CTA Barrier Reductions | **Full** | Unsafe `barrier_cta_red_{and,or,popc}_{all,count}` APIs (plus aligned forms) and `barrier_cta_sync_all`; typed NVPTX and evidenced CUDA 12.9 libNVVM routes. | | Async Barriers (mbarrier) | **Full** | Hardware async barriers for Hopper+: init, arrive, test_wait, try_wait, inval. | | Cluster Synchronization | **Full** | `cluster_sync()` for all blocks in a cluster. sm_90+. | | Fence Operations | **Full** | `fence_proxy_async_shared_cta()` for TMA visibility, `nanosleep(ns)`. | diff --git a/cuda-oxide-book/compiler/mlir-dialects.md b/cuda-oxide-book/compiler/mlir-dialects.md index 02cdc46832..267bc121cd 100644 --- a/cuda-oxide-book/compiler/mlir-dialects.md +++ b/cuda-oxide-book/compiler/mlir-dialects.md @@ -296,11 +296,11 @@ they become `call` instructions to `@llvm.nvvm.*` intrinsics. ### Architecture Coverage -At catalog SHA-256 `00372dfe` (the stamp in every `ops/generated/` file -header), the dialect holds 575 operations across 42 modules, and they come +At catalog SHA-256 `9b5ce71c` (the stamp in every `ops/generated/` file +header), the dialect holds 588 operations across 43 modules, and they come from two different places. The split is the first thing to know about it, because it decides where -- and whether -- you would add one. If the header -stamp no longer starts with `00372dfe`, the counts on this page predate the +stamp no longer starts with `9b5ce71c`, the counts on this page predate the catalog you are reading. **Hand-written**, directly under `crates/dialect-nvvm/src/ops/`. These are the @@ -320,7 +320,7 @@ describe. There are seven modules and 26 operations: **Generated**, under `ops/generated/`, from `intrinsics/catalog.json` by `cuda-intrinsics-gen`. Every file there opens with `// @generated ... DO NOT EDIT.`, and editing one by hand is undone by the next generator run. This is -the large majority -- 35 modules and 549 operations, resolved from 1015 catalog +the large majority -- 36 modules and 562 operations, resolved from 1028 catalog entries, since several intrinsics can share one structural op: | Area | Modules | Ops | @@ -329,10 +329,10 @@ entries, since several intrinsics can share one structural op: | Tensor Memory Accelerator | `tma` | 111 | | Special registers | `sreg` | 44 | | Packed (SIMD-in-register) | `packed_alu`, `packed_conversion`, `packed_atomic` | 51 | -| Async copy and barriers | `cp_async`, `mbarrier_extended`, `mbarrier_basic`, `sync` | 34 | +| Async copy and barriers | `cp_async`, `mbarrier_extended`, `mbarrier_basic`, `sync`, `barrier_reduction` | 46 | | Warp-level | `warp_shuffle`, `redux`, `vote`, `warp_match`, `warp_barrier`, `active_mask`, `elect` | 39 | | Matrix fragment movement | `ldmatrix`, `register_mma`, `stmatrix`, `wgmma_control`, `movmatrix`, `sparse_mma` | 22 | -| Execution and debug control | `execution_control`, `debug_control` | 11 | +| Execution and debug control | `execution_control`, `debug_control` | 12 | | Cluster | `clc`, `cluster_barrier`, `cluster_memory` | 10 | | Scalar math | `dotprod`, `scalar_arithmetic`, `scalar_conversion`, `scalar_math`, `extended_minmax`, `prmt` | 9 | | Integer min/max (DPX) | `integer_minmax` | 8 |