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Update Memory.scala
1 parent 6b77840 commit d27654c

1 file changed

Lines changed: 2 additions & 2 deletions

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src/main/scala/RISCV/Memory.scala

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -70,9 +70,9 @@ class Memory() extends Module {
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)
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val is_btns = RegInit(false.B)
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is_bts := io.address_1 === 0x12c00000.U // 0x4B000000
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is_btns := io.read_1 && io.address_1 === 0x12c00000.U // 0x4B000000
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when(is_btns && io.read_1) {
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when(is_btns) {
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io.read_value_1 := io.btns
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}
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}

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