diff --git a/rtl/cpu/core/decode.sv b/rtl/cpu/core/decode.sv
index 4841eb1..536df00 100644
--- a/rtl/cpu/core/decode.sv
+++ b/rtl/cpu/core/decode.sv
@@ -1,6 +1,7 @@
 import rv32_pkg::*;
 
 // Decode Module
+// EDAplayground testbench: https://edaplayground.com/x/u26L
 module decode (
 
   // Clock 
@@ -355,7 +356,7 @@ module decode (
                 5'b00000: begin amo_op_n = AMO_ADD; end // AMOADD.W
                 5'b00100: begin amo_op_n = AMO_XOR; end // AMOXOR.W
                 5'b01100: begin amo_op_n = AMO_AND; end // AMOAND.W
-                5'b01010: begin amo_op_n = AMO_OR; end  // AMOOR.W 
+                5'b01000: begin amo_op_n = AMO_OR; end  // AMOOR.W 
                 5'b10000: begin amo_op_n = AMO_MIN; end // AMOMIN.W
                 5'b10100: begin amo_op_n = AMO_MAX; end // AMOMAX.W
                 5'b11000: begin amo_op_n = AMO_MINU; end // AMOMINU.W
@@ -395,7 +396,10 @@ module decode (
     
 endmodule
 
+//------------------------------------------------------------------------------------------------------------------------
+
 // Register File
+// EDAplayground testbench: https://edaplayground.com/x/dqch
 module register_file (
 
   // Clock 
diff --git a/sim/sv/example.sv b/sim/sv/example.sv
new file mode 100644
index 0000000..8b13789
--- /dev/null
+++ b/sim/sv/example.sv
@@ -0,0 +1 @@
+