From fb57bf7c45c25ae34c8ae6350d282fe28dc31130 Mon Sep 17 00:00:00 2001 From: FoniksFox Date: Mon, 4 May 2026 11:02:23 +0200 Subject: [PATCH 1/6] feat(LinkerScript): Implemente changes to make new Linker Script work --- CMakeLists.txt | 28 ++- Core/Src/main.cpp | 6 +- Core/Src/system_stm32h7xx.c | 464 ------------------------------------ deps/ST-LIB | 2 +- 4 files changed, 32 insertions(+), 468 deletions(-) delete mode 100644 Core/Src/system_stm32h7xx.c diff --git a/CMakeLists.txt b/CMakeLists.txt index 00c73cbc..68f2d908 100644 --- a/CMakeLists.txt +++ b/CMakeLists.txt @@ -10,7 +10,8 @@ if(BOARD_NAME STREQUAL "") message(FATAL_ERROR "BOARD_NAME cannot be empty") endif() set(STLIB_DIR ${CMAKE_CURRENT_LIST_DIR}/deps/ST-LIB) -set(LD_SCRIPT ${STLIB_DIR}/STM32H723ZGTX_FLASH.ld) +set(LD_SCRIPT_INPUT ${STLIB_DIR}/LinkerScript.ld) +set(LD_SCRIPT ${CMAKE_BINARY_DIR}/LinkerScript.ld) find_package(Python3 COMPONENTS Interpreter REQUIRED) @@ -30,6 +31,8 @@ endif() option(USE_ETHERNET "Enable ethernet peripheral" OFF) option(TARGET_NUCLEO "Targets the STM32H723 Nucleo development board" OFF) option(BUILD_EXAMPLES "Build Core/Src/Examples sources" OFF) +option(ITCM_BUILD "Build code in ITCM (fast execution, no wait states)" ON) +set(ITCM_SIZE "256K" CACHE STRING "ITCM size: 64K, 128K, 192K, or 256K") option(USE_CCACHE "Use ccache if available" ON) if(NOT DEFINED ENABLE_LTO) if(CMAKE_CROSSCOMPILING) @@ -49,9 +52,26 @@ if(USE_CCACHE) endif() endif() +# Preprocess linker script through C preprocessor +add_custom_command( + OUTPUT ${LD_SCRIPT} + COMMAND ${CMAKE_C_COMPILER} -E -P -x c + -D__ITCM_BUILD=$,1,0> + -D__ITCM_SIZE=${ITCM_SIZE} + -o ${LD_SCRIPT} ${LD_SCRIPT_INPUT} + DEPENDS ${LD_SCRIPT_INPUT} + COMMENT "Preprocessing linker script (ITCM_BUILD=${ITCM_BUILD}, ITCM_SIZE=${ITCM_SIZE})" +) + +add_custom_target(preprocess_linker_script + DEPENDS ${LD_SCRIPT} +) + message(STATUS "Template project: CMAKE_CROSSCOMPILING = ${CMAKE_CROSSCOMPILING}") message(STATUS "Template project: USE_ETHERNET = ${USE_ETHERNET}") message(STATUS "Template project: TARGET_NUCLEO = ${TARGET_NUCLEO}") +message(STATUS "Template project: ITCM_BUILD = ${ITCM_BUILD}") +message(STATUS "Template project: ITCM_SIZE = ${ITCM_SIZE}") message(STATUS "Template project: BOARD_NAME = ${BOARD_NAME}") add_subdirectory(${STLIB_DIR}) @@ -142,9 +162,11 @@ if(CMAKE_CROSSCOMPILING) ${SOURCE_H} ${SOURCE_HPP} - $<$:${STLIB_DIR}/startup_stm32h723zgtx.s> + $<$:${STLIB_DIR}/StartupCode.s> ) + add_dependencies(${EXECUTABLE} preprocess_linker_script) + target_link_libraries(${EXECUTABLE} PRIVATE ${STLIB_LIBRARY} ) @@ -161,6 +183,8 @@ if(CMAKE_CROSSCOMPILING) $<$:STLIB_ETH> $,NUCLEO,BOARD> $,HSE_VALUE=8000000,HSE_VALUE=25000000> + __ITCM_BUILD=$,1,0> + __ITCM_SIZE=${ITCM_SIZE} ) target_compile_options(${EXECUTABLE} PRIVATE diff --git a/Core/Src/main.cpp b/Core/Src/main.cpp index a5c64aab..86a9f5c0 100644 --- a/Core/Src/main.cpp +++ b/Core/Src/main.cpp @@ -9,8 +9,12 @@ constexpr auto led = ST_LIB::DigitalOutputDomain::DigitalOutput(ST_LIB::PF13); using MainBoard = ST_LIB::Board; #ifndef EXAMPLE_SELECTED -int main(void) { + +void BoardInit() { MainBoard::init(); +} + +int main(void) { auto& led_instance = MainBoard::instance_of(); diff --git a/Core/Src/system_stm32h7xx.c b/Core/Src/system_stm32h7xx.c deleted file mode 100644 index c4799400..00000000 --- a/Core/Src/system_stm32h7xx.c +++ /dev/null @@ -1,464 +0,0 @@ -/** - ****************************************************************************** - * @file system_stm32h7xx.c - * @author MCD Application Team - * @brief CMSIS Cortex-Mx Device Peripheral Access Layer System Source File. - * - * This file provides two functions and one global variable to be called from - * user application: - * - SystemInit(): This function is called at startup just after reset and - * before branch to main program. This call is made inside - * the "startup_stm32h7xx.s" file. - * - * - SystemCoreClock variable: Contains the core clock, it can be used - * by the user application to setup the SysTick - * timer or configure other parameters. - * - * - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must - * be called whenever the core clock is changed - * during program execution. - * - * - ****************************************************************************** - * @attention - * - * Copyright (c) 2017 STMicroelectronics. - * All rights reserved. - * - * This software is licensed under terms that can be found in the LICENSE file - * in the root directory of this software component. - * If no LICENSE file comes with this software, it is provided AS-IS. - * - ****************************************************************************** - */ - -/** @addtogroup CMSIS - * @{ - */ - -/** @addtogroup stm32h7xx_system - * @{ - */ - -/** @addtogroup STM32H7xx_System_Private_Includes - * @{ - */ - -#include "stm32h7xx.h" -#include - -#if !defined(HSE_VALUE) -#define HSE_VALUE ((uint32_t)25000000) /*!< Value of the External oscillator in Hz */ -#endif /* HSE_VALUE */ - -#if !defined(CSI_VALUE) -#define CSI_VALUE ((uint32_t)4000000) /*!< Value of the Internal oscillator in Hz*/ -#endif /* CSI_VALUE */ - -#if !defined(HSI_VALUE) -#define HSI_VALUE ((uint32_t)64000000) /*!< Value of the Internal oscillator in Hz*/ -#endif /* HSI_VALUE */ - -/** - * @} - */ - -/** @addtogroup STM32H7xx_System_Private_TypesDefinitions - * @{ - */ - -/** - * @} - */ - -/** @addtogroup STM32H7xx_System_Private_Defines - * @{ - */ - -/************************* Miscellaneous Configuration ************************/ -/*!< Uncomment the following line if you need to use initialized data in D2 domain SRAM (AHB SRAM) - */ -/* #define DATA_IN_D2_SRAM */ - -/* Note: Following vector table addresses must be defined in line with linker - configuration. */ -/*!< Uncomment the following line if you need to relocate the vector table - anywhere in FLASH BANK1 or AXI SRAM, else the vector table is kept at the automatic - remap of boot address selected */ -/* #define USER_VECT_TAB_ADDRESS */ - -#if defined(USER_VECT_TAB_ADDRESS) -#if defined(DUAL_CORE) && defined(CORE_CM4) -/*!< Uncomment the following line if you need to relocate your vector Table - in D2 AXI SRAM else user remap will be done in FLASH BANK2. */ -/* #define VECT_TAB_SRAM */ -#if defined(VECT_TAB_SRAM) -#define VECT_TAB_BASE_ADDRESS \ - D2_AXISRAM_BASE /*!< Vector Table base address field. \ - This value must be a multiple of 0x300. */ -#define VECT_TAB_OFFSET \ - 0x00000000U /*!< Vector Table base offset field. \ - This value must be a multiple of 0x300. */ -#else -#define VECT_TAB_BASE_ADDRESS \ - FLASH_BANK2_BASE /*!< Vector Table base address field. \ - This value must be a multiple of 0x300. */ -#define VECT_TAB_OFFSET \ - 0x00000000U /*!< Vector Table base offset field. \ - This value must be a multiple of 0x300. */ -#endif /* VECT_TAB_SRAM */ -#else -/*!< Uncomment the following line if you need to relocate your vector Table - in D1 AXI SRAM else user remap will be done in FLASH BANK1. */ -/* #define VECT_TAB_SRAM */ -#if defined(VECT_TAB_SRAM) -#define VECT_TAB_BASE_ADDRESS \ - D1_AXISRAM_BASE /*!< Vector Table base address field. \ - This value must be a multiple of 0x300. */ -#define VECT_TAB_OFFSET \ - 0x00000000U /*!< Vector Table base offset field. \ - This value must be a multiple of 0x300. */ -#else -#define VECT_TAB_BASE_ADDRESS \ - FLASH_BANK1_BASE /*!< Vector Table base address field. \ - This value must be a multiple of 0x300. */ -#define VECT_TAB_OFFSET \ - 0x00000000U /*!< Vector Table base offset field. \ - This value must be a multiple of 0x300. */ -#endif /* VECT_TAB_SRAM */ -#endif /* DUAL_CORE && CORE_CM4 */ -#endif /* USER_VECT_TAB_ADDRESS */ - /******************************************************************************/ - -/** - * @} - */ - -/** @addtogroup STM32H7xx_System_Private_Macros - * @{ - */ - -/** - * @} - */ - -/** @addtogroup STM32H7xx_System_Private_Variables - * @{ - */ -/* This variable is updated in three ways: - 1) by calling CMSIS function SystemCoreClockUpdate() - 2) by calling HAL API function HAL_RCC_GetHCLKFreq() - 3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency - Note: If you use this function to configure the system clock; then there - is no need to call the 2 first functions listed above, since SystemCoreClock - variable is updated automatically. -*/ -uint32_t SystemCoreClock = 64000000; -uint32_t SystemD2Clock = 64000000; -const uint8_t D1CorePrescTable[16] = {0, 0, 0, 0, 1, 2, 3, 4, 1, 2, 3, 4, 6, 7, 8, 9}; - -/** - * @} - */ - -/** @addtogroup STM32H7xx_System_Private_FunctionPrototypes - * @{ - */ - -/** - * @} - */ - -/** @addtogroup STM32H7xx_System_Private_Functions - * @{ - */ - -/** - * @brief Setup the microcontroller system - * Initialize the FPU setting and vector table location - * configuration. - * @param None - * @retval None - */ -void SystemInit(void) { -#if defined(DATA_IN_D2_SRAM) - __IO uint32_t tmpreg; -#endif /* DATA_IN_D2_SRAM */ - -/* FPU settings ------------------------------------------------------------*/ -#if (__FPU_PRESENT == 1) && (__FPU_USED == 1) - SCB->CPACR |= ((3UL << (10 * 2)) | (3UL << (11 * 2))); /* set CP10 and CP11 Full Access */ -#endif - /* Reset the RCC clock configuration to the default reset state ------------*/ - - /* Increasing the CPU frequency */ - if (FLASH_LATENCY_DEFAULT > (READ_BIT((FLASH->ACR), FLASH_ACR_LATENCY))) { - /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */ - MODIFY_REG(FLASH->ACR, FLASH_ACR_LATENCY, (uint32_t)(FLASH_LATENCY_DEFAULT)); - } - - /* Set HSION bit */ - RCC->CR |= RCC_CR_HSION; - - /* Reset CFGR register */ - RCC->CFGR = 0x00000000; - - /* Reset HSEON, HSECSSON, CSION, HSI48ON, CSIKERON, PLL1ON, PLL2ON and PLL3ON bits */ - RCC->CR &= 0xEAF6ED7FU; - - /* Decreasing the number of wait states because of lower CPU frequency */ - if (FLASH_LATENCY_DEFAULT < (READ_BIT((FLASH->ACR), FLASH_ACR_LATENCY))) { - /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */ - MODIFY_REG(FLASH->ACR, FLASH_ACR_LATENCY, (uint32_t)(FLASH_LATENCY_DEFAULT)); - } - -#if defined(D3_SRAM_BASE) - /* Reset D1CFGR register */ - RCC->D1CFGR = 0x00000000; - - /* Reset D2CFGR register */ - RCC->D2CFGR = 0x00000000; - - /* Reset D3CFGR register */ - RCC->D3CFGR = 0x00000000; -#else - /* Reset CDCFGR1 register */ - RCC->CDCFGR1 = 0x00000000; - - /* Reset CDCFGR2 register */ - RCC->CDCFGR2 = 0x00000000; - - /* Reset SRDCFGR register */ - RCC->SRDCFGR = 0x00000000; -#endif - /* Reset PLLCKSELR register */ - RCC->PLLCKSELR = 0x02020200; - - /* Reset PLLCFGR register */ - RCC->PLLCFGR = 0x01FF0000; - /* Reset PLL1DIVR register */ - RCC->PLL1DIVR = 0x01010280; - /* Reset PLL1FRACR register */ - RCC->PLL1FRACR = 0x00000000; - - /* Reset PLL2DIVR register */ - RCC->PLL2DIVR = 0x01010280; - - /* Reset PLL2FRACR register */ - - RCC->PLL2FRACR = 0x00000000; - /* Reset PLL3DIVR register */ - RCC->PLL3DIVR = 0x01010280; - - /* Reset PLL3FRACR register */ - RCC->PLL3FRACR = 0x00000000; - - /* Reset HSEBYP bit */ - RCC->CR &= 0xFFFBFFFFU; - - /* Disable all interrupts */ - RCC->CIER = 0x00000000; - -#if (STM32H7_DEV_ID == 0x450UL) - /* dual core CM7 or single core line */ - if ((DBGMCU->IDCODE & 0xFFFF0000U) < 0x20000000U) { - /* if stm32h7 revY*/ - /* Change the switch matrix read issuing capability to 1 for the AXI SRAM target (Target 7) - */ - *((__IO uint32_t*)0x51008108) = 0x000000001U; - } -#endif /* STM32H7_DEV_ID */ - -#if defined(DATA_IN_D2_SRAM) - /* in case of initialized data in D2 SRAM (AHB SRAM), enable the D2 SRAM clock (AHB SRAM clock) - */ -#if defined(RCC_AHB2ENR_D2SRAM3EN) - RCC->AHB2ENR |= (RCC_AHB2ENR_D2SRAM1EN | RCC_AHB2ENR_D2SRAM2EN | RCC_AHB2ENR_D2SRAM3EN); -#elif defined(RCC_AHB2ENR_D2SRAM2EN) - RCC->AHB2ENR |= (RCC_AHB2ENR_D2SRAM1EN | RCC_AHB2ENR_D2SRAM2EN); -#else - RCC->AHB2ENR |= (RCC_AHB2ENR_AHBSRAM1EN | RCC_AHB2ENR_AHBSRAM2EN); -#endif /* RCC_AHB2ENR_D2SRAM3EN */ - - tmpreg = RCC->AHB2ENR; - (void)tmpreg; -#endif /* DATA_IN_D2_SRAM */ - -#if defined(DUAL_CORE) && defined(CORE_CM4) - /* Configure the Vector Table location add offset address for cortex-M4 ------------------*/ -#if defined(USER_VECT_TAB_ADDRESS) - SCB->VTOR = - VECT_TAB_BASE_ADDRESS | - VECT_TAB_OFFSET; /* Vector Table Relocation in Internal D2 AXI-RAM or in Internal FLASH */ -#endif /* USER_VECT_TAB_ADDRESS */ - -#else - /* - * Disable the FMC bank1 (enabled after reset). - * This, prevents CPU speculation access on this bank which blocks the use of FMC during - * 24us. During this time the others FMC master (such as LTDC) cannot use it! - */ - FMC_Bank1_R->BTCR[0] = 0x000030D2; - - /* Configure the Vector Table location -------------------------------------*/ -#if defined(USER_VECT_TAB_ADDRESS) - SCB->VTOR = - VECT_TAB_BASE_ADDRESS | - VECT_TAB_OFFSET; /* Vector Table Relocation in Internal D1 AXI-RAM or in Internal FLASH */ -#endif /* USER_VECT_TAB_ADDRESS */ - -#endif /*DUAL_CORE && CORE_CM4*/ -} - -/** - * @brief Update SystemCoreClock variable according to Clock Register Values. - * The SystemCoreClock variable contains the core clock , it can - * be used by the user application to setup the SysTick timer or configure - * other parameters. - * - * @note Each time the core clock changes, this function must be called - * to update SystemCoreClock variable value. Otherwise, any configuration - * based on this variable will be incorrect. - * - * @note - The system frequency computed by this function is not the real - * frequency in the chip. It is calculated based on the predefined - * constant and the selected clock source: - * - * - If SYSCLK source is CSI, SystemCoreClock will contain the CSI_VALUE(*) - * - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(**) - * - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(***) - * - If SYSCLK source is PLL, SystemCoreClock will contain the CSI_VALUE(*), - * HSI_VALUE(**) or HSE_VALUE(***) multiplied/divided by the PLL factors. - * - * (*) CSI_VALUE is a constant defined in stm32h7xx_hal.h file (default value - * 4 MHz) but the real value may vary depending on the variations - * in voltage and temperature. - * (**) HSI_VALUE is a constant defined in stm32h7xx_hal.h file (default value - * 64 MHz) but the real value may vary depending on the variations - * in voltage and temperature. - * - * (***)HSE_VALUE is a constant defined in stm32h7xx_hal.h file (default value - * 25 MHz), user has to ensure that HSE_VALUE is same as the real - * frequency of the crystal used. Otherwise, this function may - * have wrong result. - * - * - The result of this function could be not correct when using fractional - * value for HSE crystal. - * @param None - * @retval None - */ -void SystemCoreClockUpdate(void) { - uint32_t pllp, pllsource, pllm, pllfracen, hsivalue, tmp; - uint32_t common_system_clock; - float_t fracn1, pllvco; - - /* Get SYSCLK source -------------------------------------------------------*/ - - switch (RCC->CFGR & RCC_CFGR_SWS) { - case RCC_CFGR_SWS_HSI: /* HSI used as system clock source */ - common_system_clock = (uint32_t)(HSI_VALUE >> ((RCC->CR & RCC_CR_HSIDIV) >> 3)); - break; - - case RCC_CFGR_SWS_CSI: /* CSI used as system clock source */ - common_system_clock = CSI_VALUE; - break; - - case RCC_CFGR_SWS_HSE: /* HSE used as system clock source */ - common_system_clock = HSE_VALUE; - break; - - case RCC_CFGR_SWS_PLL1: /* PLL1 used as system clock source */ - - /* PLL_VCO = (HSE_VALUE or HSI_VALUE or CSI_VALUE/ PLLM) * PLLN - SYSCLK = PLL_VCO / PLLR - */ - pllsource = (RCC->PLLCKSELR & RCC_PLLCKSELR_PLLSRC); - pllm = ((RCC->PLLCKSELR & RCC_PLLCKSELR_DIVM1) >> 4); - pllfracen = ((RCC->PLLCFGR & RCC_PLLCFGR_PLL1FRACEN) >> RCC_PLLCFGR_PLL1FRACEN_Pos); - fracn1 = (float_t)(uint32_t)(pllfracen * ((RCC->PLL1FRACR & RCC_PLL1FRACR_FRACN1) >> 3)); - - if (pllm != 0U) { - switch (pllsource) { - case RCC_PLLCKSELR_PLLSRC_HSI: /* HSI used as PLL clock source */ - - hsivalue = (HSI_VALUE >> ((RCC->CR & RCC_CR_HSIDIV) >> 3)); - pllvco = ((float_t)hsivalue / (float_t)pllm) * - ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + - (fracn1 / (float_t)0x2000) + (float_t)1); - - break; - - case RCC_PLLCKSELR_PLLSRC_CSI: /* CSI used as PLL clock source */ - pllvco = ((float_t)CSI_VALUE / (float_t)pllm) * - ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + - (fracn1 / (float_t)0x2000) + (float_t)1); - break; - - case RCC_PLLCKSELR_PLLSRC_HSE: /* HSE used as PLL clock source */ - pllvco = ((float_t)HSE_VALUE / (float_t)pllm) * - ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + - (fracn1 / (float_t)0x2000) + (float_t)1); - break; - - default: - hsivalue = (HSI_VALUE >> ((RCC->CR & RCC_CR_HSIDIV) >> 3)); - pllvco = ((float_t)hsivalue / (float_t)pllm) * - ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + - (fracn1 / (float_t)0x2000) + (float_t)1); - break; - } - pllp = (((RCC->PLL1DIVR & RCC_PLL1DIVR_P1) >> 9) + 1U); - common_system_clock = (uint32_t)(float_t)(pllvco / (float_t)pllp); - } else { - common_system_clock = 0U; - } - break; - - default: - common_system_clock = (uint32_t)(HSI_VALUE >> ((RCC->CR & RCC_CR_HSIDIV) >> 3)); - break; - } - - /* Compute SystemClock frequency --------------------------------------------------*/ -#if defined(RCC_D1CFGR_D1CPRE) - tmp = D1CorePrescTable[(RCC->D1CFGR & RCC_D1CFGR_D1CPRE) >> RCC_D1CFGR_D1CPRE_Pos]; - - /* common_system_clock frequency : CM7 CPU frequency */ - common_system_clock >>= tmp; - - /* SystemD2Clock frequency : CM4 CPU, AXI and AHBs Clock frequency */ - SystemD2Clock = - (common_system_clock >> - ((D1CorePrescTable[(RCC->D1CFGR & RCC_D1CFGR_HPRE) >> RCC_D1CFGR_HPRE_Pos]) & 0x1FU)); - -#else - tmp = D1CorePrescTable[(RCC->CDCFGR1 & RCC_CDCFGR1_CDCPRE) >> RCC_CDCFGR1_CDCPRE_Pos]; - - /* common_system_clock frequency : CM7 CPU frequency */ - common_system_clock >>= tmp; - - /* SystemD2Clock frequency : AXI and AHBs Clock frequency */ - SystemD2Clock = - (common_system_clock >> - ((D1CorePrescTable[(RCC->CDCFGR1 & RCC_CDCFGR1_HPRE) >> RCC_CDCFGR1_HPRE_Pos]) & 0x1FU)); - -#endif - -#if defined(DUAL_CORE) && defined(CORE_CM4) - SystemCoreClock = SystemD2Clock; -#else - SystemCoreClock = common_system_clock; -#endif /* DUAL_CORE && CORE_CM4 */ -} - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ diff --git a/deps/ST-LIB b/deps/ST-LIB index b49fb9d5..8cedb99b 160000 --- a/deps/ST-LIB +++ b/deps/ST-LIB @@ -1 +1 @@ -Subproject commit b49fb9d55e970333c7c10febc4aae20e74e251bd +Subproject commit 8cedb99b48645d32932ea1a34ac5f5124378aa47 From 040a6d3861581f4727d651499c1b6cf15cc68961 Mon Sep 17 00:00:00 2001 From: FoniksFox Date: Mon, 4 May 2026 11:04:12 +0200 Subject: [PATCH 2/6] fix: Normal defaults --- CMakeLists.txt | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/CMakeLists.txt b/CMakeLists.txt index 68f2d908..2b4d1c04 100644 --- a/CMakeLists.txt +++ b/CMakeLists.txt @@ -31,8 +31,8 @@ endif() option(USE_ETHERNET "Enable ethernet peripheral" OFF) option(TARGET_NUCLEO "Targets the STM32H723 Nucleo development board" OFF) option(BUILD_EXAMPLES "Build Core/Src/Examples sources" OFF) -option(ITCM_BUILD "Build code in ITCM (fast execution, no wait states)" ON) -set(ITCM_SIZE "256K" CACHE STRING "ITCM size: 64K, 128K, 192K, or 256K") +option(ITCM_BUILD "Build code in ITCM (fast execution, no wait states)" OFF) +set(ITCM_SIZE "64K" CACHE STRING "ITCM size: 64K, 128K, 192K, or 256K") option(USE_CCACHE "Use ccache if available" ON) if(NOT DEFINED ENABLE_LTO) if(CMAKE_CROSSCOMPILING) From 65210fa62825d1a07d279e832140e503ddcc2d66 Mon Sep 17 00:00:00 2001 From: FoniksFox Date: Mon, 1 Jun 2026 23:42:59 +0200 Subject: [PATCH 3/6] chore: Add linker script as a dependency to the executable target --- CMakeLists.txt | 1 + 1 file changed, 1 insertion(+) diff --git a/CMakeLists.txt b/CMakeLists.txt index 2b4d1c04..aca40057 100644 --- a/CMakeLists.txt +++ b/CMakeLists.txt @@ -176,6 +176,7 @@ if(CMAKE_CROSSCOMPILING) CXX_STANDARD_REQUIRED YES C_STANDARD 17 C_STANDARD_REQUIRED YES + LINK_DEPENDS ${LD_SCRIPT} ) target_compile_definitions(${EXECUTABLE} PRIVATE From c42bd7c6614ae70ce539088881fbe126dcfe76a3 Mon Sep 17 00:00:00 2001 From: FoniksFox Date: Mon, 1 Jun 2026 23:43:37 +0200 Subject: [PATCH 4/6] feat(Examples): Fix examples, implement them with new BoardInit and better MPU tests --- Core/Src/Examples/ExampleADC.cpp | 26 +- Core/Src/Examples/ExampleEXTI.cpp | 25 +- Core/Src/Examples/ExampleMPU.cpp | 492 +++++++++++------- .../Examples/LinearSensorCharacterization.cpp | 4 +- Core/Src/main.cpp | 15 +- deps/ST-LIB | 2 +- 6 files changed, 355 insertions(+), 209 deletions(-) diff --git a/Core/Src/Examples/ExampleADC.cpp b/Core/Src/Examples/ExampleADC.cpp index eedf5608..7c5c2a1d 100644 --- a/Core/Src/Examples/ExampleADC.cpp +++ b/Core/Src/Examples/ExampleADC.cpp @@ -26,7 +26,7 @@ constexpr const char* kDualChannelWiringHint = "Connect PA0 and PC0 to two analo void start_terminal() { #ifdef HAL_UART_MODULE_ENABLED if (!UART::set_up_printf(UART::uart3)) { - ErrorHandler("Unable to set up UART printf for ADC example"); + FAULT("Unable to set up UART printf for ADC example"); } UART::start(); #endif @@ -51,13 +51,16 @@ constexpr auto adc = ADCDomain::ADC( ADCDomain::Resolution::BITS_12, ADCDomain::SampleTime::CYCLES_8_5 ); +using ExampleADCBoard = ST_LIB::Board; -int main(void) { - using ExampleADCBoard = ST_LIB::Board; +auto& adc_instance = ExampleADCBoard::instance_of(); + +extern "C" void BoardInit() { ExampleADCBoard::init(); - start_terminal(); +} - auto& adc_instance = ExampleADCBoard::instance_of(); +int main(void) { + start_terminal(); print_banner("ADC single-channel example", kSingleChannelWiringHint, "t_ms raw voltage[V]"); printf("Reading input: %s\n\r\n\r", adc_input.label); @@ -103,14 +106,19 @@ constexpr auto adc_input_1 = ADCDomain::ADC( ADCDomain::SampleTime::CYCLES_8_5 ); +using ExampleADCBoard = ST_LIB::Board; + +extern "C" void BoardInit() { + ExampleADCBoard::init(); +} + +auto& adc_input_0_instance = ExampleADCBoard::instance_of(); +auto& adc_input_1_instance = ExampleADCBoard::instance_of(); + int main(void) { - using ExampleADCBoard = ST_LIB::Board; ExampleADCBoard::init(); start_terminal(); - auto& adc_input_0_instance = ExampleADCBoard::instance_of(); - auto& adc_input_1_instance = ExampleADCBoard::instance_of(); - print_banner( "ADC dual-channel example", kDualChannelWiringHint, diff --git a/Core/Src/Examples/ExampleEXTI.cpp b/Core/Src/Examples/ExampleEXTI.cpp index 0c695806..cedfa9f8 100644 --- a/Core/Src/Examples/ExampleEXTI.cpp +++ b/Core/Src/Examples/ExampleEXTI.cpp @@ -7,25 +7,26 @@ // Press the nucleo user button (PC13) to toggle the LED (PB0) using namespace ST_LIB; -constexpr auto led = ST_LIB::DigitalOutputDomain::DigitalOutput(ST_LIB::PB0); -ST_LIB::DigitalOutputDomain::Instance* g_led; +constexpr auto led_req = ST_LIB::DigitalOutputDomain::DigitalOutput(ST_LIB::PB0); -void toggle_led() { g_led->toggle(); } +void toggle_led(); constexpr auto exti_req = ST_LIB::EXTIDomain::Device(ST_LIB::PC13, ST_LIB::EXTIDomain::Trigger::BOTH_EDGES, toggle_led); -using MainBoard = ST_LIB::Board; +using MainBoard = ST_LIB::Board; -int main(void) { - MainBoard::init(); +auto led_instance = MainBoard::instance_of(); - static auto& led_instance = MainBoard::instance_of(); - g_led = &led_instance; +void toggle_led() { + led_instance.toggle(); +} - while (1) { - // led_instance.toggle(); - // HAL_Delay(200); - } +extern "C" void BoardInit() { + MainBoard::init(); +} + +int main(void) { + while (1); } #endif diff --git a/Core/Src/Examples/ExampleMPU.cpp b/Core/Src/Examples/ExampleMPU.cpp index f85a8a66..d10369bf 100644 --- a/Core/Src/Examples/ExampleMPU.cpp +++ b/Core/Src/Examples/ExampleMPU.cpp @@ -3,151 +3,338 @@ #include "main.h" #include "ST-LIB.hpp" +using namespace ST_LIB; + +inline void mpu_assert(bool condition) { + if (!condition) { + __BKPT(0); + while (1) {} + } +} + +template +bool in_range(const T& var, const char& start, const char& end) { + auto addr = reinterpret_cast(&var); + return addr >= reinterpret_cast(&start) && addr < reinterpret_cast(&end); +} + +template +bool in_range_cached(const T& var, const char& nc_end, const char& base, const char& size) { + auto addr = reinterpret_cast(&var); + return addr >= reinterpret_cast(&nc_end) + && addr < reinterpret_cast(&base) + reinterpret_cast(&size); +} + +template +bool in_range_from(const T& var, const char& base, const char& size) { + auto addr = reinterpret_cast(&var); + return addr >= reinterpret_cast(&base) + && addr < reinterpret_cast(&base) + reinterpret_cast(&size); +} + +inline bool ptr_in_range(const volatile void* ptr, const char& start, const char& end) { + auto addr = reinterpret_cast(ptr); + return addr >= reinterpret_cast(&start) && addr < reinterpret_cast(&end); +} + +inline bool ptr_in_range_cached(const volatile void* ptr, const char& nc_end, const char& base, const char& size) { + auto addr = reinterpret_cast(ptr); + return addr >= reinterpret_cast(&nc_end) + && addr < reinterpret_cast(&base) + reinterpret_cast(&size); +} + +inline bool ptr_in_range_from(const volatile void* ptr, const char& base, const char& size) { + auto addr = reinterpret_cast(ptr); + return addr >= reinterpret_cast(&base) + && addr < reinterpret_cast(&base) + reinterpret_cast(&size); +} + #ifdef TEST_0 // No Buffers requested -int main(void) { - STLIB::start(); - - using myBoard = ST_LIB::Board<>; +using myBoard = ST_LIB::Board; +extern "C" void BoardInit() { myBoard::init(); - +} +int main(void) { while (1) { - STLIB::update(); } } #endif #ifdef TEST_1 -// Basic test with a buffer in D2 -constexpr auto my_uint32_t = MPUDomain::Buffer(); - -int main(void) { - STLIB::start(); +// Basic test with buffers in all domains +D1_NC_BSS uint32_t my_d1_nc_bss_1; +D1_NC_BSS uint8_t my_d1_nc_bss_2; +D1_C_BSS uint32_t my_d1_c_bss_1; +D1_C_BSS uint8_t my_d1_c_bss_2; +D2_NC_BSS uint32_t my_d2_nc_bss_1; +D2_NC_BSS uint8_t my_d2_nc_bss_2; +D2_C_BSS uint32_t my_d2_c_bss_1; +D2_C_BSS uint8_t my_d2_c_bss_2; +D3_NC_BSS uint32_t my_d3_nc_bss_1; +D3_NC_BSS uint8_t my_d3_nc_bss_2; +D3_C_BSS uint32_t my_d3_c_bss_1; +D3_C_BSS uint8_t my_d3_c_bss_2; + +D1_NC_DATA uint32_t my_d1_nc_data_1{40}; +D1_NC_DATA uint8_t my_d1_nc_data_2{41}; +D1_C_DATA uint32_t my_d1_c_data_1{42}; +D1_C_DATA uint8_t my_d1_c_data_2{43}; +D2_NC_DATA uint32_t my_d2_nc_data_1{44}; +D2_NC_DATA uint8_t my_d2_nc_data_2{45}; +D2_C_DATA uint32_t my_d2_c_data_1{46}; +D2_C_DATA uint8_t my_d2_c_data_2{47}; +D3_NC_DATA uint32_t my_d3_nc_data_1{48}; +D3_NC_DATA uint8_t my_d3_nc_data_2{49}; +D3_C_DATA uint32_t my_d3_c_data_1{50}; +D3_C_DATA uint8_t my_d3_c_data_2{51}; + +D1_NC_RODATA uint32_t my_d1_nc_rodata_1{100}; +D1_NC_RODATA uint8_t my_d1_nc_rodata_2{101}; +D1_C_RODATA uint32_t my_d1_c_rodata_1{102}; +D1_C_RODATA uint8_t my_d1_c_rodata_2{103}; +D2_NC_RODATA uint32_t my_d2_nc_rodata_1{104}; +D2_NC_RODATA uint8_t my_d2_nc_rodata_2{105}; +D2_C_RODATA uint32_t my_d2_c_rodata_1{106}; +D2_C_RODATA uint8_t my_d2_c_rodata_2{107}; +D3_NC_RODATA uint32_t my_d3_nc_rodata_1{108}; +D3_NC_RODATA uint8_t my_d3_nc_rodata_2{109}; +D3_C_RODATA uint32_t my_d3_c_rodata_1{110}; +D3_C_RODATA uint8_t my_d3_c_rodata_2{111}; + +DTCM_RODATA uint32_t my_dtcm_rodata_1{112}; +DTCM_RODATA uint8_t my_dtcm_rodata_2{113}; + +// INLINE variants +D1_NC_DATA_INLINE(my_inline_d1_nc_data_1) uint32_t my_inline_d1_nc_data_1{200}; +D1_NC_BSS_INLINE(my_inline_d1_nc_bss_1) uint32_t my_inline_d1_nc_bss_1; +D1_NC_RODATA_INLINE(my_inline_d1_nc_rodata_1) uint32_t my_inline_d1_nc_rodata_1{201}; +D1_C_DATA_INLINE(my_inline_d1_c_data_1) uint32_t my_inline_d1_c_data_1{202}; +D1_C_BSS_INLINE(my_inline_d1_c_bss_1) uint32_t my_inline_d1_c_bss_1; +D1_C_RODATA_INLINE(my_inline_d1_c_rodata_1) uint32_t my_inline_d1_c_rodata_1{203}; +D2_NC_DATA_INLINE(my_inline_d2_nc_data_1) uint32_t my_inline_d2_nc_data_1{204}; +D2_NC_BSS_INLINE(my_inline_d2_nc_bss_1) uint32_t my_inline_d2_nc_bss_1; +D2_NC_RODATA_INLINE(my_inline_d2_nc_rodata_1) uint32_t my_inline_d2_nc_rodata_1{205}; +D2_C_DATA_INLINE(my_inline_d2_c_data_1) uint32_t my_inline_d2_c_data_1{206}; +D2_C_BSS_INLINE(my_inline_d2_c_bss_1) uint32_t my_inline_d2_c_bss_1; +D2_C_RODATA_INLINE(my_inline_d2_c_rodata_1) uint32_t my_inline_d2_c_rodata_1{207}; +D3_NC_DATA_INLINE(my_inline_d3_nc_data_1) uint32_t my_inline_d3_nc_data_1{208}; +D3_NC_BSS_INLINE(my_inline_d3_nc_bss_1) uint32_t my_inline_d3_nc_bss_1; +D3_NC_RODATA_INLINE(my_inline_d3_nc_rodata_1) uint32_t my_inline_d3_nc_rodata_1{209}; +D3_C_DATA_INLINE(my_inline_d3_c_data_1) uint32_t my_inline_d3_c_data_1{210}; +D3_C_BSS_INLINE(my_inline_d3_c_bss_1) uint32_t my_inline_d3_c_bss_1; +D3_C_RODATA_INLINE(my_inline_d3_c_rodata_1) uint32_t my_inline_d3_c_rodata_1{211}; +DTCM_RODATA_INLINE(my_inline_dtcm_rodata_1) uint32_t my_inline_dtcm_rodata_1{212}; + +RAM_CODE void ram_code_func() { + __NOP(); +} +RAM_CODE_INLINE(my_inline_ram_code_func) void my_inline_ram_code_func() { + __NOP(); +} - using myBoard = ST_LIB::Board; +using myBoard = ST_LIB::Board; +extern "C" void BoardInit() { myBoard::init(); +} - [[maybe_unused]] auto my_buffer = - myBoard::instance_of().template as(); +const uint32_t my_rodata{301}; - while (1) { - STLIB::update(); - } +int main(void) { + mpu_assert(in_range(my_d1_nc_bss_1, _ram_d1_nc_start, _ram_d1_nc_end)); + mpu_assert(in_range(my_d1_nc_bss_2, _ram_d1_nc_start, _ram_d1_nc_end)); + mpu_assert(in_range_cached(my_d1_c_bss_1, _ram_d1_nc_end, _ram_d1_base, _ram_d1_size)); + mpu_assert(in_range_cached(my_d1_c_bss_2, _ram_d1_nc_end, _ram_d1_base, _ram_d1_size)); + mpu_assert(in_range(my_d2_nc_bss_1, _ram_d2_nc_start, _ram_d2_nc_end)); + mpu_assert(in_range(my_d2_nc_bss_2, _ram_d2_nc_start, _ram_d2_nc_end)); + mpu_assert(in_range_cached(my_d2_c_bss_1, _ram_d2_nc_end, _ram_d2_base, _ram_d2_size)); + mpu_assert(in_range_cached(my_d2_c_bss_2, _ram_d2_nc_end, _ram_d2_base, _ram_d2_size)); + mpu_assert(in_range(my_d3_nc_bss_1, _ram_d3_nc_start, _ram_d3_nc_end)); + mpu_assert(in_range(my_d3_nc_bss_2, _ram_d3_nc_start, _ram_d3_nc_end)); + mpu_assert(in_range_cached(my_d3_c_bss_1, _ram_d3_nc_end, _ram_d3_base, _ram_d3_size)); + mpu_assert(in_range_cached(my_d3_c_bss_2, _ram_d3_nc_end, _ram_d3_base, _ram_d3_size)); + + mpu_assert(in_range(my_d1_nc_data_1, _ram_d1_nc_start, _ram_d1_nc_end)); + mpu_assert(in_range(my_d1_nc_data_2, _ram_d1_nc_start, _ram_d1_nc_end)); + mpu_assert(in_range_cached(my_d1_c_data_1, _ram_d1_nc_end, _ram_d1_base, _ram_d1_size)); + mpu_assert(in_range_cached(my_d1_c_data_2, _ram_d1_nc_end, _ram_d1_base, _ram_d1_size)); + mpu_assert(in_range(my_d2_nc_data_1, _ram_d2_nc_start, _ram_d2_nc_end)); + mpu_assert(in_range(my_d2_nc_data_2, _ram_d2_nc_start, _ram_d2_nc_end)); + mpu_assert(in_range_cached(my_d2_c_data_1, _ram_d2_nc_end, _ram_d2_base, _ram_d2_size)); + mpu_assert(in_range_cached(my_d2_c_data_2, _ram_d2_nc_end, _ram_d2_base, _ram_d2_size)); + mpu_assert(in_range(my_d3_nc_data_1, _ram_d3_nc_start, _ram_d3_nc_end)); + mpu_assert(in_range(my_d3_nc_data_2, _ram_d3_nc_start, _ram_d3_nc_end)); + mpu_assert(in_range_cached(my_d3_c_data_1, _ram_d3_nc_end, _ram_d3_base, _ram_d3_size)); + mpu_assert(in_range_cached(my_d3_c_data_2, _ram_d3_nc_end, _ram_d3_base, _ram_d3_size)); + + mpu_assert(in_range(my_d1_nc_rodata_1, _ram_d1_nc_start, _ram_d1_nc_end)); + mpu_assert(in_range(my_d1_nc_rodata_2, _ram_d1_nc_start, _ram_d1_nc_end)); + mpu_assert(in_range_cached(my_d1_c_rodata_1, _ram_d1_nc_end, _ram_d1_base, _ram_d1_size)); + mpu_assert(in_range_cached(my_d1_c_rodata_2, _ram_d1_nc_end, _ram_d1_base, _ram_d1_size)); + mpu_assert(in_range(my_d2_nc_rodata_1, _ram_d2_nc_start, _ram_d2_nc_end)); + mpu_assert(in_range(my_d2_nc_rodata_2, _ram_d2_nc_start, _ram_d2_nc_end)); + mpu_assert(in_range_cached(my_d2_c_rodata_1, _ram_d2_nc_end, _ram_d2_base, _ram_d2_size)); + mpu_assert(in_range_cached(my_d2_c_rodata_2, _ram_d2_nc_end, _ram_d2_base, _ram_d2_size)); + mpu_assert(in_range(my_d3_nc_rodata_1, _ram_d3_nc_start, _ram_d3_nc_end)); + mpu_assert(in_range(my_d3_nc_rodata_2, _ram_d3_nc_start, _ram_d3_nc_end)); + mpu_assert(in_range_cached(my_d3_c_rodata_1, _ram_d3_nc_end, _ram_d3_base, _ram_d3_size)); + mpu_assert(in_range_cached(my_d3_c_rodata_2, _ram_d3_nc_end, _ram_d3_base, _ram_d3_size)); + + mpu_assert(in_range_from(my_dtcm_rodata_1, _dtcm_base, _dtcm_size)); + mpu_assert(in_range_from(my_dtcm_rodata_2, _dtcm_base, _dtcm_size)); + + // INLINE variants + mpu_assert(in_range(my_inline_d1_nc_data_1, _ram_d1_nc_start, _ram_d1_nc_end)); + mpu_assert(in_range(my_inline_d1_nc_bss_1, _ram_d1_nc_start, _ram_d1_nc_end)); + mpu_assert(in_range(my_inline_d1_nc_rodata_1, _ram_d1_nc_start, _ram_d1_nc_end)); + mpu_assert(in_range_cached(my_inline_d1_c_data_1, _ram_d1_nc_end, _ram_d1_base, _ram_d1_size)); + mpu_assert(in_range_cached(my_inline_d1_c_bss_1, _ram_d1_nc_end, _ram_d1_base, _ram_d1_size)); + mpu_assert(in_range_cached(my_inline_d1_c_rodata_1, _ram_d1_nc_end, _ram_d1_base, _ram_d1_size)); + mpu_assert(in_range(my_inline_d2_nc_data_1, _ram_d2_nc_start, _ram_d2_nc_end)); + mpu_assert(in_range(my_inline_d2_nc_bss_1, _ram_d2_nc_start, _ram_d2_nc_end)); + mpu_assert(in_range(my_inline_d2_nc_rodata_1, _ram_d2_nc_start, _ram_d2_nc_end)); + mpu_assert(in_range_cached(my_inline_d2_c_data_1, _ram_d2_nc_end, _ram_d2_base, _ram_d2_size)); + mpu_assert(in_range_cached(my_inline_d2_c_bss_1, _ram_d2_nc_end, _ram_d2_base, _ram_d2_size)); + mpu_assert(in_range_cached(my_inline_d2_c_rodata_1, _ram_d2_nc_end, _ram_d2_base, _ram_d2_size)); + mpu_assert(in_range(my_inline_d3_nc_data_1, _ram_d3_nc_start, _ram_d3_nc_end)); + mpu_assert(in_range(my_inline_d3_nc_bss_1, _ram_d3_nc_start, _ram_d3_nc_end)); + mpu_assert(in_range(my_inline_d3_nc_rodata_1, _ram_d3_nc_start, _ram_d3_nc_end)); + mpu_assert(in_range_cached(my_inline_d3_c_data_1, _ram_d3_nc_end, _ram_d3_base, _ram_d3_size)); + mpu_assert(in_range_cached(my_inline_d3_c_bss_1, _ram_d3_nc_end, _ram_d3_base, _ram_d3_size)); + mpu_assert(in_range_cached(my_inline_d3_c_rodata_1, _ram_d3_nc_end, _ram_d3_base, _ram_d3_size)); + mpu_assert(in_range_from(my_inline_dtcm_rodata_1, _dtcm_base, _dtcm_size)); + + // RAM_CODE functions in ITCM + mpu_assert(reinterpret_cast(&ram_code_func) >= reinterpret_cast(&_itcm_base) + && reinterpret_cast(&ram_code_func) < reinterpret_cast(&_itcm_base) + reinterpret_cast(&_itcm_size)); + mpu_assert(reinterpret_cast(&my_inline_ram_code_func) >= reinterpret_cast(&_itcm_base) + && reinterpret_cast(&my_inline_ram_code_func) < reinterpret_cast(&_itcm_base) + reinterpret_cast(&_itcm_size)); + + // .data in DTCM + uint32_t my_data{300}; + mpu_assert(in_range_from(my_data, _dtcm_base, _dtcm_size)); + + // .bss in DTCM + static uint32_t my_bss; + mpu_assert(in_range_from(my_bss, _dtcm_base, _dtcm_size)); + + // stack in DTCM + uint32_t my_stack; + mpu_assert(in_range_from(my_stack, _dtcm_base, _dtcm_size)); + + // .rodata in FLASH + mpu_assert(in_range_from(my_rodata, _flash_base, _flash_size)); + + while (1); } #endif #ifdef TEST_2 -// Basic test with a buffer in D1 -constexpr auto my_uint32_t = - MPUDomain::Buffer(MPUDomain::MemoryType::NonCached, MPUDomain::MemoryDomain::D1); +// MPUDomain buffers in D1 and D3 non-cached +constexpr auto my_d1 = MPUDomain::Buffer(MPUDomain::MemoryType::NonCached, MPUDomain::MemoryDomain::D1); +constexpr auto my_d3 = MPUDomain::Buffer(MPUDomain::MemoryType::NonCached, MPUDomain::MemoryDomain::D3); int main(void) { - STLIB::start(); - using myBoard = ST_LIB::Board; + using myBoard = ST_LIB::Board; myBoard::init(); - [[maybe_unused]] auto my_buffer = MPUDomain::as(); + auto* d1 = MPUDomain::as(); + auto* d3 = MPUDomain::as(); - while (1) { - STLIB::update(); - } + mpu_assert(ptr_in_range(d1, _ram_d1_nc_start, _ram_d1_nc_end)); + mpu_assert(ptr_in_range(d3, _ram_d3_nc_start, _ram_d3_nc_end)); + + while (1); } #endif #ifdef TEST_3 -// Basic test with a buffer in D3 -constexpr auto my_buff = - MPUDomain::Buffer(MPUDomain::MemoryType::NonCached, MPUDomain::MemoryDomain::D3); +// POD struct type buffer +struct MPUStruct { uint8_t a; float b; char c[10]; }; +constexpr auto my_struct = MPUDomain::Buffer(); int main(void) { - STLIB::start(); - using myBoard = ST_LIB::Board; + using myBoard = ST_LIB::Board; myBoard::init(); - [[maybe_unused]] auto my_buffer = myBoard::instance_of().template as(); - while (1) { - STLIB::update(); - } + auto* s = MPUDomain::as(); + mpu_assert(ptr_in_range(s, _ram_d1_nc_start, _ram_d1_nc_end)); + + while (1); } #endif #ifdef TEST_4 // Fail test (too much memory requested) -constexpr auto my_buff = MPUDomain::Buffer( +constexpr auto my_buff = MPUDomain::Buffer( MPUDomain::MemoryType::NonCached, MPUDomain::MemoryDomain::D3 ); int main(void) { - using myBoard = ST_LIB::Board; + using myBoard = ST_LIB::Board; myBoard::init(); [[maybe_unused]] auto my_buffer = myBoard::instance_of().template as(); - STLIB::start(); - while (1) { - STLIB::update(); - } + while (1); } #endif #ifdef TEST_5 // Cannot request any type of buffer other than the one defined -constexpr auto my_buff = MPUDomain::Buffer(); +constexpr auto my_buff = MPUDomain::Buffer(); int main(void) { - STLIB::start(); - using myBoard = ST_LIB::Board; + using myBoard = ST_LIB::Board; myBoard::init(); - [[maybe_unused]] auto my_buffer = myBoard::instance_of().template as(); + [[maybe_unused]] auto my_buffer = myBoard::instance_of().template as(); // Wrong type, should be as() - while (1) { - STLIB::update(); - } + while (1); } #endif #ifdef TEST_6 -// Ask for non-cached and cached memory on the same domain -constexpr auto my_buff = MPUDomain::Buffer(); -constexpr auto my_buff2 = MPUDomain::Buffer(MPUDomain::MemoryType::Cached); +// Non-cached and cached memory on the same domain +// TODO (doesn't work) +constexpr auto my_nc = MPUDomain::Buffer(); +constexpr auto my_c = MPUDomain::Buffer(MPUDomain::MemoryType::Cached); int main(void) { - STLIB::start(); - - using myBoard = ST_LIB::Board; + using myBoard = ST_LIB::Board; myBoard::init(); - [[maybe_unused]] auto my_buffer = myBoard::instance_of().template as(); - [[maybe_unused]] auto my_buffer2 = myBoard::instance_of().template as(); + auto* nc = MPUDomain::as(); + auto* c = MPUDomain::as(); - while (1) { - STLIB::update(); - } + mpu_assert(ptr_in_range(nc, _ram_d1_nc_start, _ram_d1_nc_end)); + mpu_assert(ptr_in_range_cached(c, _ram_d1_nc_end, _ram_d1_base, _ram_d1_size)); + + while (1); } #endif #ifdef TEST_7 -// Ask for different alignment buffers -constexpr auto my_buff = MPUDomain::Buffer(); -constexpr auto my_buff2 = MPUDomain::Buffer(); +// Different alignment buffers +constexpr auto my_8 = MPUDomain::Buffer(); +constexpr auto my_32 = MPUDomain::Buffer(); int main(void) { - STLIB::start(); - - using myBoard = ST_LIB::Board; + using myBoard = ST_LIB::Board; myBoard::init(); - [[maybe_unused]] auto my_buffer = myBoard::instance_of().template as(); - [[maybe_unused]] auto my_buffer2 = myBoard::instance_of().template as(); - while (1) { - STLIB::update(); - } + auto* a8 = MPUDomain::as(); + auto* a32 = MPUDomain::as(); + + mpu_assert(ptr_in_range(a8, _ram_d1_nc_start, _ram_d1_nc_end)); + mpu_assert(ptr_in_range(a32, _ram_d1_nc_start, _ram_d1_nc_end)); + + while (1); } #endif @@ -156,16 +343,12 @@ int main(void) { constexpr auto my_buff = MPUDomain::Buffer>(); int main(void) { - STLIB::start(); - - using myBoard = ST_LIB::Board; + using myBoard = ST_LIB::Board; myBoard::init(); [[maybe_unused]] auto my_buffer = myBoard::instance_of().template as(); - while (1) { - STLIB::update(); - } + while (1); } #endif @@ -273,9 +456,9 @@ constexpr auto my_buff99 = MPUDomain::Buffer(); constexpr auto my_buff100 = MPUDomain::Buffer(); constexpr auto my_buff101 = MPUDomain::Buffer(); int main(void) { - STLIB::start(); using myBoard = ST_LIB::Board< + ST_LIB::DefaultFaultPolicy, my_buff, my_buff2, my_buff3, @@ -381,41 +564,16 @@ int main(void) { [[maybe_unused]] auto my_buffer = myBoard::instance_of().template as(); - while (1) { - STLIB::update(); - } + while (1); } #endif #ifdef TEST_10 -// Request a struct type (also works with objects and such, as long as they are POD) -struct MyStruct { - uint8_t a; - float b; - char c[10]; -}; -constexpr auto my_buff = MPUDomain::Buffer(); - -int main(void) { - STLIB::start(); - - using myBoard = ST_LIB::Board; - myBoard::init(); - - [[maybe_unused]] auto my_buffer = myBoard::instance_of().template as(); - - while (1) { - STLIB::update(); - } -} -#endif - -#ifdef TEST_11 // Mix types of different alignments and sizes (stress test) -constexpr auto my_buff = MPUDomain::Buffer(); -constexpr auto my_buff2 = MPUDomain::Buffer(); -constexpr auto my_buff3 = MPUDomain::Buffer(); -constexpr auto my_buff4 = MPUDomain::Buffer(); +constexpr auto my_buff = MPUDomain::Buffer(); +constexpr auto my_buff2 = MPUDomain::Buffer(); +constexpr auto my_buff3 = MPUDomain::Buffer(); +constexpr auto my_buff4 = MPUDomain::Buffer(); constexpr auto my_buff5 = MPUDomain::Buffer(MPUDomain::MemoryType::Cached); constexpr auto my_buff6 = MPUDomain::Buffer(MPUDomain::MemoryType::Cached); constexpr auto my_buff7 = MPUDomain::Buffer(MPUDomain::MemoryType::Cached); @@ -430,37 +588,44 @@ D3_NC uint32_t my_global_var3; D3_NC uint8_t my_global_array[50]; int main(void) { - STLIB::start(); using myBoard = ST_LIB:: - Board; + Board; myBoard::init(); - [[maybe_unused]] auto my_buffer = myBoard::instance_of().template as(); - [[maybe_unused]] auto my_buffer2 = myBoard::instance_of().template as(); - [[maybe_unused]] auto my_buffer3 = myBoard::instance_of().template as(); - [[maybe_unused]] auto my_buffer4 = myBoard::instance_of().template as(); - [[maybe_unused]] auto my_buffer5 = myBoard::instance_of().template as(); - [[maybe_unused]] auto my_buffer6 = myBoard::instance_of().template as(); - [[maybe_unused]] auto my_buffer7 = myBoard::instance_of().template as(); - [[maybe_unused]] auto my_buffer8 = myBoard::instance_of().template as(); - [[maybe_unused]] auto* global_var1 = &my_global_var; - [[maybe_unused]] auto* global_var2 = &my_global_var2; - [[maybe_unused]] auto* global_var3 = &my_global_var3; - [[maybe_unused]] auto* global_array = &my_global_array; - - while (1) { - STLIB::update(); - } + auto* my_buffer = MPUDomain::as(); + auto* my_buffer2 = MPUDomain::as(); + auto* my_buffer3 = MPUDomain::as(); + auto* my_buffer4 = MPUDomain::as(); + auto* my_buffer5 = MPUDomain::as(); + auto* my_buffer6 = MPUDomain::as(); + auto* my_buffer7 = MPUDomain::as(); + auto* my_buffer8 = MPUDomain::as(); + + // Buffer placement checks + mpu_assert(ptr_in_range(my_buffer, _ram_d1_nc_start, _ram_d1_nc_end)); + mpu_assert(ptr_in_range(my_buffer2, _ram_d1_nc_start, _ram_d1_nc_end)); + mpu_assert(ptr_in_range(my_buffer3, _ram_d1_nc_start, _ram_d1_nc_end)); + mpu_assert(ptr_in_range(my_buffer4, _ram_d1_nc_start, _ram_d1_nc_end)); + mpu_assert(ptr_in_range_cached(my_buffer5, _ram_d1_nc_end, _ram_d1_base, _ram_d1_size)); + mpu_assert(ptr_in_range_cached(my_buffer6, _ram_d1_nc_end, _ram_d1_base, _ram_d1_size)); + mpu_assert(ptr_in_range_cached(my_buffer7, _ram_d1_nc_end, _ram_d1_base, _ram_d1_size)); + mpu_assert(ptr_in_range_cached(my_buffer8, _ram_d1_nc_end, _ram_d1_base, _ram_d1_size)); + + // Manual macro variable placement + mpu_assert(in_range(my_global_var, _ram_d1_nc_start, _ram_d1_nc_end)); + mpu_assert(in_range_cached(my_global_var2, _ram_d2_nc_end, _ram_d2_base, _ram_d2_size)); + mpu_assert(in_range(my_global_var3, _ram_d3_nc_start, _ram_d3_nc_end)); + mpu_assert(in_range(my_global_array, _ram_d3_nc_start, _ram_d3_nc_end)); + + while (1); } #endif -#ifdef TEST_12 -// Dereference a pointer to a non-accessible memory region (should compile fine, runtime error) +#ifdef TEST_11 +// Dereference a pointer to a non-accessible memory region (should compile fine, hardfault at runtime) int main(void) { - STLIB::start(); - - using myBoard = ST_LIB::Board<>; + using myBoard = ST_LIB::Board; myBoard::init(); volatile uint32_t* invalid_ptr = @@ -468,85 +633,58 @@ int main(void) { [[maybe_unused]] uint32_t value = *invalid_ptr; // Dereference - while (1) { - STLIB::update(); - } + while (1); } #endif -#ifdef TEST_13 +#ifdef TEST_12 // Try construct method struct MyStruct { - uint8_t a; - float b; - char c[10]; + uint8_t a; float b; char c[10]; MyStruct(uint8_t aa, float bb) : a(aa), b(bb) { - for (int i = 0; i < 10; ++i) - c[i] = 'A' + i; + for (int i = 0; i < 10; ++i) c[i] = 'A' + i; } }; -constexpr auto my_buff = MPUDomain::Buffer(); +constexpr auto my_buff = MPUDomain::Buffer(); int main(void) { - STLIB::start(); - using myBoard = ST_LIB::Board; + using myBoard = ST_LIB::Board; myBoard::init(); - [[maybe_unused]] auto my_buffer = - myBoard::instance_of().template construct(42, 3.14f); - while (1) { - STLIB::update(); - } + auto& s = MPUDomain::construct(42, 3.14f); + mpu_assert(ptr_in_range(&s, _ram_d1_nc_start, _ram_d1_nc_end)); + + while (1); } #endif -#ifdef TEST_14 +#ifdef TEST_13 // Test legacy MPUManager compatibility D3_NC uint8_t my_legacy_buffer[256]; int main(void) { - STLIB::start(); - - using myBoard = ST_LIB::Board<>; + using myBoard = ST_LIB::Board; myBoard::init(); - [[maybe_unused]] auto my_buff = MPUManager::allocate_non_cached_memory(256); - [[maybe_unused]] auto legacy_buffer_ptr = my_legacy_buffer; + auto* legacy = MPUManager::allocate_non_cached_memory(256); + mpu_assert(ptr_in_range(legacy, _ram_d3_nc_start, _ram_d3_nc_end)); + mpu_assert(in_range(my_legacy_buffer, _ram_d3_nc_start, _ram_d3_nc_end)); - while (1) { - STLIB::update(); - } + while (1); } #endif -#ifdef TEST_15 -// Dereference a nullptr for read/write (should compile fine, runtime error) +#ifdef TEST_14 +// Dereference a nullptr for read/write (should compile fine, hardfault at runtime) int main(void) { - STLIB::start(); - - using myBoard = ST_LIB::Board<>; + using myBoard = ST_LIB::Board; myBoard::init(); volatile uint32_t* invalid_ptr = nullptr; // Null pointer [[maybe_unused]] uint32_t value = *invalid_ptr; // Dereference - while (1) { - STLIB::update(); - } + while (1); } #endif -void Error_Handler(void) { - ErrorHandler("HAL error handler triggered"); - while (1) { - } -} - -extern "C" { -void assert_failed(uint8_t* file, uint32_t line) { - while (1) { - } -} -} - #endif diff --git a/Core/Src/Examples/LinearSensorCharacterization.cpp b/Core/Src/Examples/LinearSensorCharacterization.cpp index eb312383..2ea82321 100644 --- a/Core/Src/Examples/LinearSensorCharacterization.cpp +++ b/Core/Src/Examples/LinearSensorCharacterization.cpp @@ -47,10 +47,10 @@ constexpr auto eth = EthernetDomain::Ethernet( #else #error "No PHY selected for Ethernet pinset selection" #endif -using ExampleEthernetBoard = ST_LIB::Board; +using ExampleEthernetBoard = ST_LIB::Board; extern "C" void Error_Handler(void) { - ErrorHandler("HAL error handler triggered"); + PANIC("HAL error handler triggered"); while (1) { } } diff --git a/Core/Src/main.cpp b/Core/Src/main.cpp index 86a9f5c0..de139d91 100644 --- a/Core/Src/main.cpp +++ b/Core/Src/main.cpp @@ -4,20 +4,19 @@ using namespace ST_LIB; -constexpr auto led = ST_LIB::DigitalOutputDomain::DigitalOutput(ST_LIB::PF13); +#ifndef EXAMPLE_SELECTED -using MainBoard = ST_LIB::Board; +constexpr auto led_req = ST_LIB::DigitalOutputDomain::DigitalOutput(ST_LIB::PB0); + +using MainBoard = ST_LIB::Board; +auto& led_instance = MainBoard::instance_of(); -#ifndef EXAMPLE_SELECTED -void BoardInit() { +extern "C" void BoardInit() { MainBoard::init(); } int main(void) { - - auto& led_instance = MainBoard::instance_of(); - while (1) { led_instance.toggle(); HAL_Delay(200); @@ -26,7 +25,7 @@ int main(void) { #endif extern "C" void Error_Handler(void) { - ErrorHandler("HAL error handler triggered"); + PANIC("HAL error handler triggered"); while (1) { } } diff --git a/deps/ST-LIB b/deps/ST-LIB index 8cedb99b..ce980f3b 160000 --- a/deps/ST-LIB +++ b/deps/ST-LIB @@ -1 +1 @@ -Subproject commit 8cedb99b48645d32932ea1a34ac5f5124378aa47 +Subproject commit ce980f3b0f35ae5333c0e4d0b1308eeea9f34ade From 55173a8a35b6fb8a47697a203fdbf4e76c9fc5f6 Mon Sep 17 00:00:00 2001 From: FoniksFox Date: Mon, 1 Jun 2026 23:58:26 +0200 Subject: [PATCH 5/6] style: pre-commit --- CMakeLists.txt | 2 +- Core/Src/Examples/ExampleADC.cpp | 8 +- Core/Src/Examples/ExampleEXTI.cpp | 11 +-- Core/Src/Examples/ExampleMPU.cpp | 158 +++++++++++++++++++----------- Core/Src/main.cpp | 5 +- deps/ST-LIB | 2 +- 6 files changed, 109 insertions(+), 77 deletions(-) diff --git a/CMakeLists.txt b/CMakeLists.txt index aca40057..7dcd5b91 100644 --- a/CMakeLists.txt +++ b/CMakeLists.txt @@ -55,7 +55,7 @@ endif() # Preprocess linker script through C preprocessor add_custom_command( OUTPUT ${LD_SCRIPT} - COMMAND ${CMAKE_C_COMPILER} -E -P -x c + COMMAND ${CMAKE_C_COMPILER} -E -P -x c -D__ITCM_BUILD=$,1,0> -D__ITCM_SIZE=${ITCM_SIZE} -o ${LD_SCRIPT} ${LD_SCRIPT_INPUT} diff --git a/Core/Src/Examples/ExampleADC.cpp b/Core/Src/Examples/ExampleADC.cpp index 7c5c2a1d..78785c7f 100644 --- a/Core/Src/Examples/ExampleADC.cpp +++ b/Core/Src/Examples/ExampleADC.cpp @@ -55,9 +55,7 @@ using ExampleADCBoard = ST_LIB::Board; auto& adc_instance = ExampleADCBoard::instance_of(); -extern "C" void BoardInit() { - ExampleADCBoard::init(); -} +extern "C" void BoardInit() { ExampleADCBoard::init(); } int main(void) { start_terminal(); @@ -108,9 +106,7 @@ constexpr auto adc_input_1 = ADCDomain::ADC( using ExampleADCBoard = ST_LIB::Board; -extern "C" void BoardInit() { - ExampleADCBoard::init(); -} +extern "C" void BoardInit() { ExampleADCBoard::init(); } auto& adc_input_0_instance = ExampleADCBoard::instance_of(); auto& adc_input_1_instance = ExampleADCBoard::instance_of(); diff --git a/Core/Src/Examples/ExampleEXTI.cpp b/Core/Src/Examples/ExampleEXTI.cpp index cedfa9f8..e2905a3b 100644 --- a/Core/Src/Examples/ExampleEXTI.cpp +++ b/Core/Src/Examples/ExampleEXTI.cpp @@ -17,16 +17,13 @@ using MainBoard = ST_LIB::Board; auto led_instance = MainBoard::instance_of(); -void toggle_led() { - led_instance.toggle(); -} +void toggle_led() { led_instance.toggle(); } -extern "C" void BoardInit() { - MainBoard::init(); -} +extern "C" void BoardInit() { MainBoard::init(); } int main(void) { - while (1); + while (1) + ; } #endif diff --git a/Core/Src/Examples/ExampleMPU.cpp b/Core/Src/Examples/ExampleMPU.cpp index d10369bf..c57d4359 100644 --- a/Core/Src/Examples/ExampleMPU.cpp +++ b/Core/Src/Examples/ExampleMPU.cpp @@ -8,28 +8,27 @@ using namespace ST_LIB; inline void mpu_assert(bool condition) { if (!condition) { __BKPT(0); - while (1) {} + while (1) { + } } } -template -bool in_range(const T& var, const char& start, const char& end) { +template bool in_range(const T& var, const char& start, const char& end) { auto addr = reinterpret_cast(&var); return addr >= reinterpret_cast(&start) && addr < reinterpret_cast(&end); } -template +template bool in_range_cached(const T& var, const char& nc_end, const char& base, const char& size) { auto addr = reinterpret_cast(&var); - return addr >= reinterpret_cast(&nc_end) - && addr < reinterpret_cast(&base) + reinterpret_cast(&size); + return addr >= reinterpret_cast(&nc_end) && + addr < reinterpret_cast(&base) + reinterpret_cast(&size); } -template -bool in_range_from(const T& var, const char& base, const char& size) { +template bool in_range_from(const T& var, const char& base, const char& size) { auto addr = reinterpret_cast(&var); - return addr >= reinterpret_cast(&base) - && addr < reinterpret_cast(&base) + reinterpret_cast(&size); + return addr >= reinterpret_cast(&base) && + addr < reinterpret_cast(&base) + reinterpret_cast(&size); } inline bool ptr_in_range(const volatile void* ptr, const char& start, const char& end) { @@ -37,24 +36,27 @@ inline bool ptr_in_range(const volatile void* ptr, const char& start, const char return addr >= reinterpret_cast(&start) && addr < reinterpret_cast(&end); } -inline bool ptr_in_range_cached(const volatile void* ptr, const char& nc_end, const char& base, const char& size) { +inline bool ptr_in_range_cached( + const volatile void* ptr, + const char& nc_end, + const char& base, + const char& size +) { auto addr = reinterpret_cast(ptr); - return addr >= reinterpret_cast(&nc_end) - && addr < reinterpret_cast(&base) + reinterpret_cast(&size); + return addr >= reinterpret_cast(&nc_end) && + addr < reinterpret_cast(&base) + reinterpret_cast(&size); } inline bool ptr_in_range_from(const volatile void* ptr, const char& base, const char& size) { auto addr = reinterpret_cast(ptr); - return addr >= reinterpret_cast(&base) - && addr < reinterpret_cast(&base) + reinterpret_cast(&size); + return addr >= reinterpret_cast(&base) && + addr < reinterpret_cast(&base) + reinterpret_cast(&size); } #ifdef TEST_0 // No Buffers requested using myBoard = ST_LIB::Board; -extern "C" void BoardInit() { - myBoard::init(); -} +extern "C" void BoardInit() { myBoard::init(); } int main(void) { while (1) { } @@ -126,17 +128,11 @@ D3_C_BSS_INLINE(my_inline_d3_c_bss_1) uint32_t my_inline_d3_c_bss_1; D3_C_RODATA_INLINE(my_inline_d3_c_rodata_1) uint32_t my_inline_d3_c_rodata_1{211}; DTCM_RODATA_INLINE(my_inline_dtcm_rodata_1) uint32_t my_inline_dtcm_rodata_1{212}; -RAM_CODE void ram_code_func() { - __NOP(); -} -RAM_CODE_INLINE(my_inline_ram_code_func) void my_inline_ram_code_func() { - __NOP(); -} +RAM_CODE void ram_code_func() { __NOP(); } +RAM_CODE_INLINE(my_inline_ram_code_func) void my_inline_ram_code_func() { __NOP(); } using myBoard = ST_LIB::Board; -extern "C" void BoardInit() { - myBoard::init(); -} +extern "C" void BoardInit() { myBoard::init(); } const uint32_t my_rodata{301}; @@ -189,26 +185,36 @@ int main(void) { mpu_assert(in_range(my_inline_d1_nc_rodata_1, _ram_d1_nc_start, _ram_d1_nc_end)); mpu_assert(in_range_cached(my_inline_d1_c_data_1, _ram_d1_nc_end, _ram_d1_base, _ram_d1_size)); mpu_assert(in_range_cached(my_inline_d1_c_bss_1, _ram_d1_nc_end, _ram_d1_base, _ram_d1_size)); - mpu_assert(in_range_cached(my_inline_d1_c_rodata_1, _ram_d1_nc_end, _ram_d1_base, _ram_d1_size)); + mpu_assert(in_range_cached(my_inline_d1_c_rodata_1, _ram_d1_nc_end, _ram_d1_base, _ram_d1_size) + ); mpu_assert(in_range(my_inline_d2_nc_data_1, _ram_d2_nc_start, _ram_d2_nc_end)); mpu_assert(in_range(my_inline_d2_nc_bss_1, _ram_d2_nc_start, _ram_d2_nc_end)); mpu_assert(in_range(my_inline_d2_nc_rodata_1, _ram_d2_nc_start, _ram_d2_nc_end)); mpu_assert(in_range_cached(my_inline_d2_c_data_1, _ram_d2_nc_end, _ram_d2_base, _ram_d2_size)); mpu_assert(in_range_cached(my_inline_d2_c_bss_1, _ram_d2_nc_end, _ram_d2_base, _ram_d2_size)); - mpu_assert(in_range_cached(my_inline_d2_c_rodata_1, _ram_d2_nc_end, _ram_d2_base, _ram_d2_size)); + mpu_assert(in_range_cached(my_inline_d2_c_rodata_1, _ram_d2_nc_end, _ram_d2_base, _ram_d2_size) + ); mpu_assert(in_range(my_inline_d3_nc_data_1, _ram_d3_nc_start, _ram_d3_nc_end)); mpu_assert(in_range(my_inline_d3_nc_bss_1, _ram_d3_nc_start, _ram_d3_nc_end)); mpu_assert(in_range(my_inline_d3_nc_rodata_1, _ram_d3_nc_start, _ram_d3_nc_end)); mpu_assert(in_range_cached(my_inline_d3_c_data_1, _ram_d3_nc_end, _ram_d3_base, _ram_d3_size)); mpu_assert(in_range_cached(my_inline_d3_c_bss_1, _ram_d3_nc_end, _ram_d3_base, _ram_d3_size)); - mpu_assert(in_range_cached(my_inline_d3_c_rodata_1, _ram_d3_nc_end, _ram_d3_base, _ram_d3_size)); + mpu_assert(in_range_cached(my_inline_d3_c_rodata_1, _ram_d3_nc_end, _ram_d3_base, _ram_d3_size) + ); mpu_assert(in_range_from(my_inline_dtcm_rodata_1, _dtcm_base, _dtcm_size)); // RAM_CODE functions in ITCM - mpu_assert(reinterpret_cast(&ram_code_func) >= reinterpret_cast(&_itcm_base) - && reinterpret_cast(&ram_code_func) < reinterpret_cast(&_itcm_base) + reinterpret_cast(&_itcm_size)); - mpu_assert(reinterpret_cast(&my_inline_ram_code_func) >= reinterpret_cast(&_itcm_base) - && reinterpret_cast(&my_inline_ram_code_func) < reinterpret_cast(&_itcm_base) + reinterpret_cast(&_itcm_size)); + mpu_assert( + reinterpret_cast(&ram_code_func) >= reinterpret_cast(&_itcm_base) && + reinterpret_cast(&ram_code_func) < + reinterpret_cast(&_itcm_base) + reinterpret_cast(&_itcm_size) + ); + mpu_assert( + reinterpret_cast(&my_inline_ram_code_func) >= + reinterpret_cast(&_itcm_base) && + reinterpret_cast(&my_inline_ram_code_func) < + reinterpret_cast(&_itcm_base) + reinterpret_cast(&_itcm_size) + ); // .data in DTCM uint32_t my_data{300}; @@ -225,14 +231,21 @@ int main(void) { // .rodata in FLASH mpu_assert(in_range_from(my_rodata, _flash_base, _flash_size)); - while (1); + while (1) + ; } #endif #ifdef TEST_2 // MPUDomain buffers in D1 and D3 non-cached -constexpr auto my_d1 = MPUDomain::Buffer(MPUDomain::MemoryType::NonCached, MPUDomain::MemoryDomain::D1); -constexpr auto my_d3 = MPUDomain::Buffer(MPUDomain::MemoryType::NonCached, MPUDomain::MemoryDomain::D3); +constexpr auto my_d1 = MPUDomain::Buffer( + MPUDomain::MemoryType::NonCached, + MPUDomain::MemoryDomain::D1 +); +constexpr auto my_d3 = MPUDomain::Buffer( + MPUDomain::MemoryType::NonCached, + MPUDomain::MemoryDomain::D3 +); int main(void) { @@ -245,13 +258,18 @@ int main(void) { mpu_assert(ptr_in_range(d1, _ram_d1_nc_start, _ram_d1_nc_end)); mpu_assert(ptr_in_range(d3, _ram_d3_nc_start, _ram_d3_nc_end)); - while (1); + while (1) + ; } #endif #ifdef TEST_3 // POD struct type buffer -struct MPUStruct { uint8_t a; float b; char c[10]; }; +struct MPUStruct { + uint8_t a; + float b; + char c[10]; +}; constexpr auto my_struct = MPUDomain::Buffer(); int main(void) { @@ -262,7 +280,8 @@ int main(void) { auto* s = MPUDomain::as(); mpu_assert(ptr_in_range(s, _ram_d1_nc_start, _ram_d1_nc_end)); - while (1); + while (1) + ; } #endif @@ -279,8 +298,8 @@ int main(void) { [[maybe_unused]] auto my_buffer = myBoard::instance_of().template as(); - - while (1); + while (1) + ; } #endif @@ -293,9 +312,11 @@ int main(void) { using myBoard = ST_LIB::Board; myBoard::init(); - [[maybe_unused]] auto my_buffer = myBoard::instance_of().template as(); // Wrong type, should be as() + [[maybe_unused]] auto my_buffer = myBoard::instance_of().template as( + ); // Wrong type, should be as() - while (1); + while (1) + ; } #endif @@ -315,7 +336,8 @@ int main(void) { mpu_assert(ptr_in_range(nc, _ram_d1_nc_start, _ram_d1_nc_end)); mpu_assert(ptr_in_range_cached(c, _ram_d1_nc_end, _ram_d1_base, _ram_d1_size)); - while (1); + while (1) + ; } #endif @@ -334,7 +356,8 @@ int main(void) { mpu_assert(ptr_in_range(a8, _ram_d1_nc_start, _ram_d1_nc_end)); mpu_assert(ptr_in_range(a32, _ram_d1_nc_start, _ram_d1_nc_end)); - while (1); + while (1) + ; } #endif @@ -348,7 +371,8 @@ int main(void) { [[maybe_unused]] auto my_buffer = myBoard::instance_of().template as(); - while (1); + while (1) + ; } #endif @@ -564,7 +588,8 @@ int main(void) { [[maybe_unused]] auto my_buffer = myBoard::instance_of().template as(); - while (1); + while (1) + ; } #endif @@ -589,8 +614,16 @@ D3_NC uint8_t my_global_array[50]; int main(void) { - using myBoard = ST_LIB:: - Board; + using myBoard = ST_LIB::Board< + ST_LIB::DefaultFaultPolicy, + my_buff, + my_buff2, + my_buff3, + my_buff4, + my_buff5, + my_buff6, + my_buff7, + my_buff8>; myBoard::init(); auto* my_buffer = MPUDomain::as(); @@ -618,12 +651,14 @@ int main(void) { mpu_assert(in_range(my_global_var3, _ram_d3_nc_start, _ram_d3_nc_end)); mpu_assert(in_range(my_global_array, _ram_d3_nc_start, _ram_d3_nc_end)); - while (1); + while (1) + ; } #endif #ifdef TEST_11 -// Dereference a pointer to a non-accessible memory region (should compile fine, hardfault at runtime) +// Dereference a pointer to a non-accessible memory region (should compile fine, hardfault at +// runtime) int main(void) { using myBoard = ST_LIB::Board; myBoard::init(); @@ -633,16 +668,20 @@ int main(void) { [[maybe_unused]] uint32_t value = *invalid_ptr; // Dereference - while (1); + while (1) + ; } #endif #ifdef TEST_12 // Try construct method struct MyStruct { - uint8_t a; float b; char c[10]; + uint8_t a; + float b; + char c[10]; MyStruct(uint8_t aa, float bb) : a(aa), b(bb) { - for (int i = 0; i < 10; ++i) c[i] = 'A' + i; + for (int i = 0; i < 10; ++i) + c[i] = 'A' + i; } }; constexpr auto my_buff = MPUDomain::Buffer(); @@ -655,7 +694,8 @@ int main(void) { auto& s = MPUDomain::construct(42, 3.14f); mpu_assert(ptr_in_range(&s, _ram_d1_nc_start, _ram_d1_nc_end)); - while (1); + while (1) + ; } #endif @@ -670,7 +710,8 @@ int main(void) { mpu_assert(ptr_in_range(legacy, _ram_d3_nc_start, _ram_d3_nc_end)); mpu_assert(in_range(my_legacy_buffer, _ram_d3_nc_start, _ram_d3_nc_end)); - while (1); + while (1) + ; } #endif @@ -683,7 +724,8 @@ int main(void) { [[maybe_unused]] uint32_t value = *invalid_ptr; // Dereference - while (1); + while (1) + ; } #endif diff --git a/Core/Src/main.cpp b/Core/Src/main.cpp index de139d91..abb379da 100644 --- a/Core/Src/main.cpp +++ b/Core/Src/main.cpp @@ -11,10 +11,7 @@ constexpr auto led_req = ST_LIB::DigitalOutputDomain::DigitalOutput(ST_LIB::PB0) using MainBoard = ST_LIB::Board; auto& led_instance = MainBoard::instance_of(); - -extern "C" void BoardInit() { - MainBoard::init(); -} +extern "C" void BoardInit() { MainBoard::init(); } int main(void) { while (1) { diff --git a/deps/ST-LIB b/deps/ST-LIB index ce980f3b..02c1cc96 160000 --- a/deps/ST-LIB +++ b/deps/ST-LIB @@ -1 +1 @@ -Subproject commit ce980f3b0f35ae5333c0e4d0b1308eeea9f34ade +Subproject commit 02c1cc96fc6bb67eab02d16dea44de3e525e85c5 From 9c17ac7291a206a785241b6af17854cd65c36a13 Mon Sep 17 00:00:00 2001 From: FoniksFox Date: Tue, 2 Jun 2026 00:33:35 +0200 Subject: [PATCH 6/6] chore: Update st-lib --- deps/ST-LIB | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/deps/ST-LIB b/deps/ST-LIB index 02c1cc96..307ceee7 160000 --- a/deps/ST-LIB +++ b/deps/ST-LIB @@ -1 +1 @@ -Subproject commit 02c1cc96fc6bb67eab02d16dea44de3e525e85c5 +Subproject commit 307ceee75fb485358160cb7f428a3cdcf75e5c28