diff --git a/library/SubcircuitLibrary/74F182/3_and-cache.lib b/library/SubcircuitLibrary/74F182/3_and-cache.lib
new file mode 100644
index 000000000..af0586415
--- /dev/null
+++ b/library/SubcircuitLibrary/74F182/3_and-cache.lib
@@ -0,0 +1,61 @@
+EESchema-LIBRARY Version 2.3
+#encoding utf-8
+#
+# PORT
+#
+DEF PORT U 0 40 Y Y 26 F N
+F0 "U" 50 100 30 H V C CNN
+F1 "PORT" 0 0 30 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0
+A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50
+S -100 50 100 -50 0 1 0 N
+X ~ 1 250 0 100 L 30 30 1 1 B
+X ~ 2 250 0 100 L 30 30 2 1 B
+X ~ 3 250 0 100 L 30 30 3 1 B
+X ~ 4 250 0 100 L 30 30 4 1 B
+X ~ 5 250 0 100 L 30 30 5 1 B
+X ~ 6 250 0 100 L 30 30 6 1 B
+X ~ 7 250 0 100 L 30 30 7 1 B
+X ~ 8 250 0 100 L 30 30 8 1 B
+X ~ 9 250 0 100 L 30 30 9 1 B
+X ~ 10 250 0 100 L 30 30 10 1 B
+X ~ 11 250 0 100 L 30 30 11 1 B
+X ~ 12 250 0 100 L 30 30 12 1 B
+X ~ 13 250 0 100 L 30 30 13 1 B
+X ~ 14 250 0 100 L 30 30 14 1 B
+X ~ 15 250 0 100 L 30 30 15 1 B
+X ~ 16 250 0 100 L 30 30 16 1 B
+X ~ 17 250 0 100 L 30 30 17 1 B
+X ~ 18 250 0 100 L 30 30 18 1 B
+X ~ 19 250 0 100 L 30 30 19 1 B
+X ~ 20 250 0 100 L 30 30 20 1 B
+X ~ 21 250 0 100 L 30 30 21 1 B
+X ~ 22 250 0 100 L 30 30 22 1 B
+X ~ 23 250 0 100 L 30 30 23 1 B
+X ~ 24 250 0 100 L 30 30 24 1 B
+X ~ 25 250 0 100 L 30 30 25 1 B
+X ~ 26 250 0 100 L 30 30 26 1 B
+ENDDRAW
+ENDDEF
+#
+# d_and
+#
+DEF d_and U 0 40 Y Y 1 F N
+F0 "U" 0 0 60 H V C CNN
+F1 "d_and" 50 100 60 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A 149 50 100 -894 0 0 1 0 N 150 -50 250 50
+A 150 49 100 6 900 0 1 0 N 250 50 150 150
+P 4 0 1 0 150 -50 -250 -50 -250 150 150 150 N
+X IN1 1 -450 100 200 R 50 50 1 1 I
+X IN2 2 -450 0 200 R 50 50 1 1 I
+X OUT 3 450 50 200 L 50 50 1 1 O
+ENDDRAW
+ENDDEF
+#
+#End Library
diff --git a/library/SubcircuitLibrary/74F182/3_and.cir b/library/SubcircuitLibrary/74F182/3_and.cir
new file mode 100644
index 000000000..ba296cf01
--- /dev/null
+++ b/library/SubcircuitLibrary/74F182/3_and.cir
@@ -0,0 +1,13 @@
+* C:\Users\malli\eSim\src\SubcircuitLibrary\3_and\3_and.cir
+
+* EESchema Netlist Version 1.1 (Spice format) creation date: 03/26/19 18:42:57
+
+* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N
+* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0
+
+* Sheet Name: /
+U2 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U2-Pad3_ d_and
+U3 Net-_U2-Pad3_ Net-_U1-Pad3_ Net-_U1-Pad4_ d_and
+U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ PORT
+
+.end
diff --git a/library/SubcircuitLibrary/74F182/3_and.cir.out b/library/SubcircuitLibrary/74F182/3_and.cir.out
new file mode 100644
index 000000000..d7cf79a07
--- /dev/null
+++ b/library/SubcircuitLibrary/74F182/3_and.cir.out
@@ -0,0 +1,20 @@
+* c:\users\malli\esim\src\subcircuitlibrary\3_and\3_and.cir
+
+* u2 net-_u1-pad1_ net-_u1-pad2_ net-_u2-pad3_ d_and
+* u3 net-_u2-pad3_ net-_u1-pad3_ net-_u1-pad4_ d_and
+* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ port
+a1 [net-_u1-pad1_ net-_u1-pad2_ ] net-_u2-pad3_ u2
+a2 [net-_u2-pad3_ net-_u1-pad3_ ] net-_u1-pad4_ u3
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u3 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+.tran 0e-00 0e-00 0e-00
+
+* Control Statements
+.control
+run
+print allv > plot_data_v.txt
+print alli > plot_data_i.txt
+.endc
+.end
diff --git a/library/SubcircuitLibrary/74F182/3_and.pro b/library/SubcircuitLibrary/74F182/3_and.pro
new file mode 100644
index 000000000..06813ca78
--- /dev/null
+++ b/library/SubcircuitLibrary/74F182/3_and.pro
@@ -0,0 +1,43 @@
+update=Wed Mar 18 19:54:53 2020
+version=1
+last_client=eeschema
+[general]
+version=1
+RootSch=
+BoardNm=
+[pcbnew]
+version=1
+LastNetListRead=
+UseCmpFile=1
+PadDrill=0.600000000000
+PadDrillOvalY=0.600000000000
+PadSizeH=1.500000000000
+PadSizeV=1.500000000000
+PcbTextSizeV=1.500000000000
+PcbTextSizeH=1.500000000000
+PcbTextThickness=0.300000000000
+ModuleTextSizeV=1.000000000000
+ModuleTextSizeH=1.000000000000
+ModuleTextSizeThickness=0.150000000000
+SolderMaskClearance=0.000000000000
+SolderMaskMinWidth=0.000000000000
+DrawSegmentWidth=0.200000000000
+BoardOutlineThickness=0.100000000000
+ModuleOutlineThickness=0.150000000000
+[cvpcb]
+version=1
+NetIExt=net
+[eeschema]
+version=1
+LibDir=../../../kicadSchematicLibrary
+[eeschema/libraries]
+LibName1=eSim_Analog
+LibName2=eSim_Devices
+LibName3=eSim_Digital
+LibName4=eSim_Hybrid
+LibName5=eSim_Miscellaneous
+LibName6=eSim_Plot
+LibName7=eSim_Power
+LibName8=eSim_Sources
+LibName9=eSim_Subckt
+LibName10=eSim_User
diff --git a/library/SubcircuitLibrary/74F182/3_and.sch b/library/SubcircuitLibrary/74F182/3_and.sch
new file mode 100644
index 000000000..d6ac89f95
--- /dev/null
+++ b/library/SubcircuitLibrary/74F182/3_and.sch
@@ -0,0 +1,130 @@
+EESchema Schematic File Version 2
+LIBS:power
+LIBS:texas
+LIBS:intel
+LIBS:audio
+LIBS:interface
+LIBS:digital-audio
+LIBS:philips
+LIBS:display
+LIBS:cypress
+LIBS:siliconi
+LIBS:opto
+LIBS:atmel
+LIBS:contrib
+LIBS:valves
+LIBS:eSim_Analog
+LIBS:eSim_Devices
+LIBS:eSim_Digital
+LIBS:eSim_Hybrid
+LIBS:eSim_Miscellaneous
+LIBS:eSim_Plot
+LIBS:eSim_Power
+LIBS:eSim_PSpice
+LIBS:eSim_Sources
+LIBS:eSim_Subckt
+LIBS:eSim_User
+LIBS:3_and-cache
+EELAYER 25 0
+EELAYER END
+$Descr A4 11693 8268
+encoding utf-8
+Sheet 1 1
+Title ""
+Date ""
+Rev ""
+Comp ""
+Comment1 ""
+Comment2 ""
+Comment3 ""
+Comment4 ""
+$EndDescr
+$Comp
+L d_and U2
+U 1 1 5C9A24D8
+P 4250 2700
+F 0 "U2" H 4250 2700 60 0000 C CNN
+F 1 "d_and" H 4300 2800 60 0000 C CNN
+F 2 "" H 4250 2700 60 0000 C CNN
+F 3 "" H 4250 2700 60 0000 C CNN
+ 1 4250 2700
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_and U3
+U 1 1 5C9A2538
+P 5150 2900
+F 0 "U3" H 5150 2900 60 0000 C CNN
+F 1 "d_and" H 5200 3000 60 0000 C CNN
+F 2 "" H 5150 2900 60 0000 C CNN
+F 3 "" H 5150 2900 60 0000 C CNN
+ 1 5150 2900
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 1 1 5C9A259A
+P 3050 2600
+F 0 "U1" H 3100 2700 30 0000 C CNN
+F 1 "PORT" H 3050 2600 30 0000 C CNN
+F 2 "" H 3050 2600 60 0000 C CNN
+F 3 "" H 3050 2600 60 0000 C CNN
+ 1 3050 2600
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 2 1 5C9A25D9
+P 3050 2800
+F 0 "U1" H 3100 2900 30 0000 C CNN
+F 1 "PORT" H 3050 2800 30 0000 C CNN
+F 2 "" H 3050 2800 60 0000 C CNN
+F 3 "" H 3050 2800 60 0000 C CNN
+ 2 3050 2800
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 3 1 5C9A260A
+P 3050 3100
+F 0 "U1" H 3100 3200 30 0000 C CNN
+F 1 "PORT" H 3050 3100 30 0000 C CNN
+F 2 "" H 3050 3100 60 0000 C CNN
+F 3 "" H 3050 3100 60 0000 C CNN
+ 3 3050 3100
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 4 1 5C9A2637
+P 6900 2850
+F 0 "U1" H 6950 2950 30 0000 C CNN
+F 1 "PORT" H 6900 2850 30 0000 C CNN
+F 2 "" H 6900 2850 60 0000 C CNN
+F 3 "" H 6900 2850 60 0000 C CNN
+ 4 6900 2850
+ -1 0 0 1
+$EndComp
+Wire Wire Line
+ 4700 2650 4700 2800
+Wire Wire Line
+ 5600 2850 6650 2850
+Wire Wire Line
+ 3800 2600 3300 2600
+Wire Wire Line
+ 3800 2700 3300 2700
+Wire Wire Line
+ 3300 2700 3300 2800
+Wire Wire Line
+ 3300 3100 4700 3100
+Wire Wire Line
+ 4700 3100 4700 2900
+Text Notes 3500 2600 0 60 ~ 12
+in1
+Text Notes 3450 2800 0 60 ~ 12
+in2\n
+Text Notes 3500 3100 0 60 ~ 12
+in3
+Text Notes 6100 2850 0 60 ~ 12
+out
+$EndSCHEMATC
diff --git a/library/SubcircuitLibrary/74F182/3_and.sub b/library/SubcircuitLibrary/74F182/3_and.sub
new file mode 100644
index 000000000..3d9120bb6
--- /dev/null
+++ b/library/SubcircuitLibrary/74F182/3_and.sub
@@ -0,0 +1,14 @@
+* Subcircuit 3_and
+.subckt 3_and net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_
+* c:\users\malli\esim\src\subcircuitlibrary\3_and\3_and.cir
+* u2 net-_u1-pad1_ net-_u1-pad2_ net-_u2-pad3_ d_and
+* u3 net-_u2-pad3_ net-_u1-pad3_ net-_u1-pad4_ d_and
+a1 [net-_u1-pad1_ net-_u1-pad2_ ] net-_u2-pad3_ u2
+a2 [net-_u2-pad3_ net-_u1-pad3_ ] net-_u1-pad4_ u3
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u3 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+* Control Statements
+
+.ends 3_and
\ No newline at end of file
diff --git a/library/SubcircuitLibrary/74F182/3_and_Previous_Values.xml b/library/SubcircuitLibrary/74F182/3_and_Previous_Values.xml
new file mode 100644
index 000000000..abc5faaae
--- /dev/null
+++ b/library/SubcircuitLibrary/74F182/3_and_Previous_Values.xml
@@ -0,0 +1 @@
+d_andd_andtruefalsefalseHzHz0Volts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesSecSecSec
\ No newline at end of file
diff --git a/library/SubcircuitLibrary/74F182/4_OR-cache.lib b/library/SubcircuitLibrary/74F182/4_OR-cache.lib
new file mode 100644
index 000000000..155f5e601
--- /dev/null
+++ b/library/SubcircuitLibrary/74F182/4_OR-cache.lib
@@ -0,0 +1,63 @@
+EESchema-LIBRARY Version 2.3
+#encoding utf-8
+#
+# PORT
+#
+DEF PORT U 0 40 Y Y 26 F N
+F0 "U" 50 100 30 H V C CNN
+F1 "PORT" 0 0 30 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0
+A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50
+S -100 50 100 -50 0 1 0 N
+X ~ 1 250 0 100 L 30 30 1 1 B
+X ~ 2 250 0 100 L 30 30 2 1 B
+X ~ 3 250 0 100 L 30 30 3 1 B
+X ~ 4 250 0 100 L 30 30 4 1 B
+X ~ 5 250 0 100 L 30 30 5 1 B
+X ~ 6 250 0 100 L 30 30 6 1 B
+X ~ 7 250 0 100 L 30 30 7 1 B
+X ~ 8 250 0 100 L 30 30 8 1 B
+X ~ 9 250 0 100 L 30 30 9 1 B
+X ~ 10 250 0 100 L 30 30 10 1 B
+X ~ 11 250 0 100 L 30 30 11 1 B
+X ~ 12 250 0 100 L 30 30 12 1 B
+X ~ 13 250 0 100 L 30 30 13 1 B
+X ~ 14 250 0 100 L 30 30 14 1 B
+X ~ 15 250 0 100 L 30 30 15 1 B
+X ~ 16 250 0 100 L 30 30 16 1 B
+X ~ 17 250 0 100 L 30 30 17 1 B
+X ~ 18 250 0 100 L 30 30 18 1 B
+X ~ 19 250 0 100 L 30 30 19 1 B
+X ~ 20 250 0 100 L 30 30 20 1 B
+X ~ 21 250 0 100 L 30 30 21 1 B
+X ~ 22 250 0 100 L 30 30 22 1 B
+X ~ 23 250 0 100 L 30 30 23 1 B
+X ~ 24 250 0 100 L 30 30 24 1 B
+X ~ 25 250 0 100 L 30 30 25 1 B
+X ~ 26 250 0 100 L 30 30 26 1 B
+ENDDRAW
+ENDDEF
+#
+# d_or
+#
+DEF d_or U 0 40 Y Y 1 F N
+F0 "U" 0 0 60 H V C CNN
+F1 "d_or" 0 100 60 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A -450 50 224 266 -266 0 1 0 N -250 150 -250 -50
+A -25 -124 325 574 323 0 1 0 N 150 150 250 50
+A 74 125 191 -665 -231 0 1 0 N 150 -50 250 50
+P 2 0 1 0 -250 -50 150 -50 N
+P 2 0 1 0 -250 150 150 150 N
+X IN1 1 -450 100 215 R 50 50 1 1 I
+X IN2 2 -450 0 215 R 50 50 1 1 I
+X OUT 3 450 50 200 L 50 50 1 1 O
+ENDDRAW
+ENDDEF
+#
+#End Library
diff --git a/library/SubcircuitLibrary/74F182/4_OR.cir b/library/SubcircuitLibrary/74F182/4_OR.cir
new file mode 100644
index 000000000..b338b7b5f
--- /dev/null
+++ b/library/SubcircuitLibrary/74F182/4_OR.cir
@@ -0,0 +1,14 @@
+* C:\Users\malli\eSim\src\SubcircuitLibrary\4_OR\4_OR.cir
+
+* EESchema Netlist Version 1.1 (Spice format) creation date: 03/28/19 22:47:12
+
+* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N
+* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0
+
+* Sheet Name: /
+U2 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U2-Pad3_ d_or
+U3 Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U3-Pad3_ d_or
+U4 Net-_U2-Pad3_ Net-_U3-Pad3_ Net-_U1-Pad5_ d_or
+U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ PORT
+
+.end
diff --git a/library/SubcircuitLibrary/74F182/4_OR.cir.out b/library/SubcircuitLibrary/74F182/4_OR.cir.out
new file mode 100644
index 000000000..adb6b01be
--- /dev/null
+++ b/library/SubcircuitLibrary/74F182/4_OR.cir.out
@@ -0,0 +1,24 @@
+* c:\users\malli\esim\src\subcircuitlibrary\4_or\4_or.cir
+
+* u2 net-_u1-pad1_ net-_u1-pad2_ net-_u2-pad3_ d_or
+* u3 net-_u1-pad3_ net-_u1-pad4_ net-_u3-pad3_ d_or
+* u4 net-_u2-pad3_ net-_u3-pad3_ net-_u1-pad5_ d_or
+* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ port
+a1 [net-_u1-pad1_ net-_u1-pad2_ ] net-_u2-pad3_ u2
+a2 [net-_u1-pad3_ net-_u1-pad4_ ] net-_u3-pad3_ u3
+a3 [net-_u2-pad3_ net-_u3-pad3_ ] net-_u1-pad5_ u4
+* Schematic Name: d_or, NgSpice Name: d_or
+.model u2 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+* Schematic Name: d_or, NgSpice Name: d_or
+.model u3 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+* Schematic Name: d_or, NgSpice Name: d_or
+.model u4 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+.tran 0e-00 0e-00 0e-00
+
+* Control Statements
+.control
+run
+print allv > plot_data_v.txt
+print alli > plot_data_i.txt
+.endc
+.end
diff --git a/library/SubcircuitLibrary/74F182/4_OR.pro b/library/SubcircuitLibrary/74F182/4_OR.pro
new file mode 100644
index 000000000..881563ebd
--- /dev/null
+++ b/library/SubcircuitLibrary/74F182/4_OR.pro
@@ -0,0 +1,44 @@
+update=06/01/19 12:36:09
+version=1
+last_client=eeschema
+[general]
+version=1
+RootSch=
+BoardNm=
+[pcbnew]
+version=1
+LastNetListRead=
+UseCmpFile=1
+PadDrill=0.600000000000
+PadDrillOvalY=0.600000000000
+PadSizeH=1.500000000000
+PadSizeV=1.500000000000
+PcbTextSizeV=1.500000000000
+PcbTextSizeH=1.500000000000
+PcbTextThickness=0.300000000000
+ModuleTextSizeV=1.000000000000
+ModuleTextSizeH=1.000000000000
+ModuleTextSizeThickness=0.150000000000
+SolderMaskClearance=0.000000000000
+SolderMaskMinWidth=0.000000000000
+DrawSegmentWidth=0.200000000000
+BoardOutlineThickness=0.100000000000
+ModuleOutlineThickness=0.150000000000
+[cvpcb]
+version=1
+NetIExt=net
+[eeschema]
+version=1
+LibDir=../../../kicadSchematicLibrary
+[eeschema/libraries]
+LibName1=power
+LibName2=eSim_Analog
+LibName3=eSim_Devices
+LibName4=eSim_Digital
+LibName5=eSim_Hybrid
+LibName6=eSim_Miscellaneous
+LibName7=eSim_Plot
+LibName8=eSim_Power
+LibName9=eSim_User
+LibName10=eSim_Sources
+LibName11=eSim_Subckt
diff --git a/library/SubcircuitLibrary/74F182/4_OR.sch b/library/SubcircuitLibrary/74F182/4_OR.sch
new file mode 100644
index 000000000..118968656
--- /dev/null
+++ b/library/SubcircuitLibrary/74F182/4_OR.sch
@@ -0,0 +1,150 @@
+EESchema Schematic File Version 2
+LIBS:power
+LIBS:eSim_Analog
+LIBS:eSim_Devices
+LIBS:eSim_Digital
+LIBS:eSim_Hybrid
+LIBS:eSim_Miscellaneous
+LIBS:eSim_Plot
+LIBS:eSim_Power
+LIBS:eSim_PSpice
+LIBS:eSim_Sources
+LIBS:eSim_Subckt
+LIBS:eSim_User
+EELAYER 25 0
+EELAYER END
+$Descr A4 11693 8268
+encoding utf-8
+Sheet 1 1
+Title ""
+Date ""
+Rev ""
+Comp ""
+Comment1 ""
+Comment2 ""
+Comment3 ""
+Comment4 ""
+$EndDescr
+$Comp
+L d_or U2
+U 1 1 5C9D00E1
+P 4300 2950
+F 0 "U2" H 4300 2950 60 0000 C CNN
+F 1 "d_or" H 4300 3050 60 0000 C CNN
+F 2 "" H 4300 2950 60 0000 C CNN
+F 3 "" H 4300 2950 60 0000 C CNN
+ 1 4300 2950
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_or U3
+U 1 1 5C9D011F
+P 4300 3350
+F 0 "U3" H 4300 3350 60 0000 C CNN
+F 1 "d_or" H 4300 3450 60 0000 C CNN
+F 2 "" H 4300 3350 60 0000 C CNN
+F 3 "" H 4300 3350 60 0000 C CNN
+ 1 4300 3350
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_or U4
+U 1 1 5C9D0141
+P 5250 3150
+F 0 "U4" H 5250 3150 60 0000 C CNN
+F 1 "d_or" H 5250 3250 60 0000 C CNN
+F 2 "" H 5250 3150 60 0000 C CNN
+F 3 "" H 5250 3150 60 0000 C CNN
+ 1 5250 3150
+ 1 0 0 -1
+$EndComp
+Wire Wire Line
+ 4800 3050 4800 2900
+Wire Wire Line
+ 4800 2900 4750 2900
+Wire Wire Line
+ 4800 3150 4800 3300
+Wire Wire Line
+ 4800 3300 4750 3300
+Wire Wire Line
+ 3350 2850 3850 2850
+Wire Wire Line
+ 3850 2950 3600 2950
+Wire Wire Line
+ 3850 3250 3350 3250
+Wire Wire Line
+ 3600 2950 3600 3000
+Wire Wire Line
+ 3600 3000 3350 3000
+Wire Wire Line
+ 3850 3350 3850 3400
+Wire Wire Line
+ 3850 3400 3350 3400
+Wire Wire Line
+ 5700 3100 6200 3100
+$Comp
+L PORT U1
+U 1 1 5C9D01F4
+P 3100 2850
+F 0 "U1" H 3150 2950 30 0000 C CNN
+F 1 "PORT" H 3100 2850 30 0000 C CNN
+F 2 "" H 3100 2850 60 0000 C CNN
+F 3 "" H 3100 2850 60 0000 C CNN
+ 1 3100 2850
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 2 1 5C9D022F
+P 3100 3000
+F 0 "U1" H 3150 3100 30 0000 C CNN
+F 1 "PORT" H 3100 3000 30 0000 C CNN
+F 2 "" H 3100 3000 60 0000 C CNN
+F 3 "" H 3100 3000 60 0000 C CNN
+ 2 3100 3000
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 3 1 5C9D0271
+P 3100 3250
+F 0 "U1" H 3150 3350 30 0000 C CNN
+F 1 "PORT" H 3100 3250 30 0000 C CNN
+F 2 "" H 3100 3250 60 0000 C CNN
+F 3 "" H 3100 3250 60 0000 C CNN
+ 3 3100 3250
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 4 1 5C9D0299
+P 3100 3400
+F 0 "U1" H 3150 3500 30 0000 C CNN
+F 1 "PORT" H 3100 3400 30 0000 C CNN
+F 2 "" H 3100 3400 60 0000 C CNN
+F 3 "" H 3100 3400 60 0000 C CNN
+ 4 3100 3400
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 5 1 5C9D02C2
+P 6450 3100
+F 0 "U1" H 6500 3200 30 0000 C CNN
+F 1 "PORT" H 6450 3100 30 0000 C CNN
+F 2 "" H 6450 3100 60 0000 C CNN
+F 3 "" H 6450 3100 60 0000 C CNN
+ 5 6450 3100
+ -1 0 0 1
+$EndComp
+Text Notes 3450 2850 0 60 ~ 12
+in1
+Text Notes 3450 3000 0 60 ~ 12
+in2
+Text Notes 3450 3250 0 60 ~ 12
+in3
+Text Notes 3450 3400 0 60 ~ 12
+in4
+Text Notes 5800 3100 0 60 ~ 12
+out
+$EndSCHEMATC
diff --git a/library/SubcircuitLibrary/74F182/4_OR.sub b/library/SubcircuitLibrary/74F182/4_OR.sub
new file mode 100644
index 000000000..d1fd3a241
--- /dev/null
+++ b/library/SubcircuitLibrary/74F182/4_OR.sub
@@ -0,0 +1,18 @@
+* Subcircuit 4_OR
+.subckt 4_OR net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_
+* c:\users\malli\esim\src\subcircuitlibrary\4_or\4_or.cir
+* u2 net-_u1-pad1_ net-_u1-pad2_ net-_u2-pad3_ d_or
+* u3 net-_u1-pad3_ net-_u1-pad4_ net-_u3-pad3_ d_or
+* u4 net-_u2-pad3_ net-_u3-pad3_ net-_u1-pad5_ d_or
+a1 [net-_u1-pad1_ net-_u1-pad2_ ] net-_u2-pad3_ u2
+a2 [net-_u1-pad3_ net-_u1-pad4_ ] net-_u3-pad3_ u3
+a3 [net-_u2-pad3_ net-_u3-pad3_ ] net-_u1-pad5_ u4
+* Schematic Name: d_or, NgSpice Name: d_or
+.model u2 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+* Schematic Name: d_or, NgSpice Name: d_or
+.model u3 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+* Schematic Name: d_or, NgSpice Name: d_or
+.model u4 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+* Control Statements
+
+.ends 4_OR
\ No newline at end of file
diff --git a/library/SubcircuitLibrary/74F182/4_OR_Previous_Values.xml b/library/SubcircuitLibrary/74F182/4_OR_Previous_Values.xml
new file mode 100644
index 000000000..0683d9eb6
--- /dev/null
+++ b/library/SubcircuitLibrary/74F182/4_OR_Previous_Values.xml
@@ -0,0 +1 @@
+d_ord_ord_ortruefalsefalseHzHz0Volts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesSecSecSec
\ No newline at end of file
diff --git a/library/SubcircuitLibrary/74F182/4_and-cache.lib b/library/SubcircuitLibrary/74F182/4_and-cache.lib
new file mode 100644
index 000000000..60f1a83d4
--- /dev/null
+++ b/library/SubcircuitLibrary/74F182/4_and-cache.lib
@@ -0,0 +1,79 @@
+EESchema-LIBRARY Version 2.3
+#encoding utf-8
+#
+# 3_and-RESCUE-4_and
+#
+DEF 3_and-RESCUE-4_and X 0 40 Y Y 1 F N
+F0 "X" 900 300 60 H V C CNN
+F1 "3_and-RESCUE-4_and" 950 500 60 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A 950 400 158 716 -716 0 1 0 N 1000 550 1000 250
+P 2 0 1 0 650 550 1000 550 N
+P 3 0 1 0 650 550 650 250 1000 250 N
+X in1 1 450 500 200 R 50 50 1 1 I
+X in2 2 450 400 200 R 50 50 1 1 I
+X in3 3 450 300 200 R 50 50 1 1 I
+X out 4 1300 400 200 L 50 50 1 1 O
+ENDDRAW
+ENDDEF
+#
+# PORT
+#
+DEF PORT U 0 40 Y Y 26 F N
+F0 "U" 50 100 30 H V C CNN
+F1 "PORT" 0 0 30 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0
+A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50
+S -100 50 100 -50 0 1 0 N
+X ~ 1 250 0 100 L 30 30 1 1 B
+X ~ 2 250 0 100 L 30 30 2 1 B
+X ~ 3 250 0 100 L 30 30 3 1 B
+X ~ 4 250 0 100 L 30 30 4 1 B
+X ~ 5 250 0 100 L 30 30 5 1 B
+X ~ 6 250 0 100 L 30 30 6 1 B
+X ~ 7 250 0 100 L 30 30 7 1 B
+X ~ 8 250 0 100 L 30 30 8 1 B
+X ~ 9 250 0 100 L 30 30 9 1 B
+X ~ 10 250 0 100 L 30 30 10 1 B
+X ~ 11 250 0 100 L 30 30 11 1 B
+X ~ 12 250 0 100 L 30 30 12 1 B
+X ~ 13 250 0 100 L 30 30 13 1 B
+X ~ 14 250 0 100 L 30 30 14 1 B
+X ~ 15 250 0 100 L 30 30 15 1 B
+X ~ 16 250 0 100 L 30 30 16 1 B
+X ~ 17 250 0 100 L 30 30 17 1 B
+X ~ 18 250 0 100 L 30 30 18 1 B
+X ~ 19 250 0 100 L 30 30 19 1 B
+X ~ 20 250 0 100 L 30 30 20 1 B
+X ~ 21 250 0 100 L 30 30 21 1 B
+X ~ 22 250 0 100 L 30 30 22 1 B
+X ~ 23 250 0 100 L 30 30 23 1 B
+X ~ 24 250 0 100 L 30 30 24 1 B
+X ~ 25 250 0 100 L 30 30 25 1 B
+X ~ 26 250 0 100 L 30 30 26 1 B
+ENDDRAW
+ENDDEF
+#
+# d_and
+#
+DEF d_and U 0 40 Y Y 1 F N
+F0 "U" 0 0 60 H V C CNN
+F1 "d_and" 50 100 60 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A 149 50 100 -894 0 0 1 0 N 150 -50 250 50
+A 150 49 100 6 900 0 1 0 N 250 50 150 150
+P 4 0 1 0 150 -50 -250 -50 -250 150 150 150 N
+X IN1 1 -450 100 200 R 50 50 1 1 I
+X IN2 2 -450 0 200 R 50 50 1 1 I
+X OUT 3 450 50 200 L 50 50 1 1 O
+ENDDRAW
+ENDDEF
+#
+#End Library
diff --git a/library/SubcircuitLibrary/74F182/4_and-rescue.lib b/library/SubcircuitLibrary/74F182/4_and-rescue.lib
new file mode 100644
index 000000000..e38330518
--- /dev/null
+++ b/library/SubcircuitLibrary/74F182/4_and-rescue.lib
@@ -0,0 +1,22 @@
+EESchema-LIBRARY Version 2.3
+#encoding utf-8
+#
+# 3_and-RESCUE-4_and
+#
+DEF 3_and-RESCUE-4_and X 0 40 Y Y 1 F N
+F0 "X" 900 300 60 H V C CNN
+F1 "3_and-RESCUE-4_and" 950 500 60 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A 950 400 158 716 -716 0 1 0 N 1000 550 1000 250
+P 2 0 1 0 650 550 1000 550 N
+P 3 0 1 0 650 550 650 250 1000 250 N
+X in1 1 450 500 200 R 50 50 1 1 I
+X in2 2 450 400 200 R 50 50 1 1 I
+X in3 3 450 300 200 R 50 50 1 1 I
+X out 4 1300 400 200 L 50 50 1 1 O
+ENDDRAW
+ENDDEF
+#
+#End Library
diff --git a/library/SubcircuitLibrary/74F182/4_and.cir b/library/SubcircuitLibrary/74F182/4_and.cir
new file mode 100644
index 000000000..fdf2e1074
--- /dev/null
+++ b/library/SubcircuitLibrary/74F182/4_and.cir
@@ -0,0 +1,13 @@
+* C:\Users\malli\eSim\src\SubcircuitLibrary\4_and\4_and.cir
+
+* EESchema Netlist Version 1.1 (Spice format) creation date: 06/01/19 13:09:58
+
+* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N
+* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0
+
+* Sheet Name: /
+X1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U2-Pad1_ 3_and
+U2 Net-_U2-Pad1_ Net-_U1-Pad4_ Net-_U1-Pad5_ d_and
+U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ PORT
+
+.end
diff --git a/library/SubcircuitLibrary/74F182/4_and.cir.out b/library/SubcircuitLibrary/74F182/4_and.cir.out
new file mode 100644
index 000000000..f40e5bc62
--- /dev/null
+++ b/library/SubcircuitLibrary/74F182/4_and.cir.out
@@ -0,0 +1,18 @@
+* c:\users\malli\esim\src\subcircuitlibrary\4_and\4_and.cir
+
+.include 3_and.sub
+x1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u2-pad1_ 3_and
+* u2 net-_u2-pad1_ net-_u1-pad4_ net-_u1-pad5_ d_and
+* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ port
+a1 [net-_u2-pad1_ net-_u1-pad4_ ] net-_u1-pad5_ u2
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+.tran 0e-00 0e-00 0e-00
+
+* Control Statements
+.control
+run
+print allv > plot_data_v.txt
+print alli > plot_data_i.txt
+.endc
+.end
diff --git a/library/SubcircuitLibrary/74F182/4_and.pro b/library/SubcircuitLibrary/74F182/4_and.pro
new file mode 100644
index 000000000..b13a0a825
--- /dev/null
+++ b/library/SubcircuitLibrary/74F182/4_and.pro
@@ -0,0 +1,57 @@
+update=Wed Mar 18 19:54:24 2020
+version=1
+last_client=eeschema
+[general]
+version=1
+RootSch=
+BoardNm=
+[pcbnew]
+version=1
+LastNetListRead=
+UseCmpFile=1
+PadDrill=0.600000000000
+PadDrillOvalY=0.600000000000
+PadSizeH=1.500000000000
+PadSizeV=1.500000000000
+PcbTextSizeV=1.500000000000
+PcbTextSizeH=1.500000000000
+PcbTextThickness=0.300000000000
+ModuleTextSizeV=1.000000000000
+ModuleTextSizeH=1.000000000000
+ModuleTextSizeThickness=0.150000000000
+SolderMaskClearance=0.000000000000
+SolderMaskMinWidth=0.000000000000
+DrawSegmentWidth=0.200000000000
+BoardOutlineThickness=0.100000000000
+ModuleOutlineThickness=0.150000000000
+[cvpcb]
+version=1
+NetIExt=net
+[eeschema]
+version=1
+LibDir=../../../kicadSchematicLibrary
+[eeschema/libraries]
+LibName1=4_and-rescue
+LibName2=texas
+LibName3=intel
+LibName4=audio
+LibName5=interface
+LibName6=digital-audio
+LibName7=philips
+LibName8=display
+LibName9=cypress
+LibName10=siliconi
+LibName11=opto
+LibName12=atmel
+LibName13=contrib
+LibName14=valves
+LibName15=eSim_Analog
+LibName16=eSim_Devices
+LibName17=eSim_Digital
+LibName18=eSim_Hybrid
+LibName19=eSim_Miscellaneous
+LibName20=eSim_Plot
+LibName21=eSim_Power
+LibName22=eSim_Sources
+LibName23=eSim_Subckt
+LibName24=eSim_User
diff --git a/library/SubcircuitLibrary/74F182/4_and.sch b/library/SubcircuitLibrary/74F182/4_and.sch
new file mode 100644
index 000000000..f5e8febdc
--- /dev/null
+++ b/library/SubcircuitLibrary/74F182/4_and.sch
@@ -0,0 +1,151 @@
+EESchema Schematic File Version 2
+LIBS:4_and-rescue
+LIBS:texas
+LIBS:intel
+LIBS:audio
+LIBS:interface
+LIBS:digital-audio
+LIBS:philips
+LIBS:display
+LIBS:cypress
+LIBS:siliconi
+LIBS:opto
+LIBS:atmel
+LIBS:contrib
+LIBS:valves
+LIBS:eSim_Analog
+LIBS:eSim_Devices
+LIBS:eSim_Digital
+LIBS:eSim_Hybrid
+LIBS:eSim_Miscellaneous
+LIBS:eSim_Plot
+LIBS:eSim_Power
+LIBS:eSim_PSpice
+LIBS:eSim_Sources
+LIBS:eSim_Subckt
+LIBS:eSim_User
+LIBS:4_and-cache
+EELAYER 25 0
+EELAYER END
+$Descr A4 11693 8268
+encoding utf-8
+Sheet 1 1
+Title ""
+Date ""
+Rev ""
+Comp ""
+Comment1 ""
+Comment2 ""
+Comment3 ""
+Comment4 ""
+$EndDescr
+$Comp
+L 3_and-RESCUE-4_and X1
+U 1 1 5C9A2915
+P 3700 3500
+F 0 "X1" H 4600 3800 60 0000 C CNN
+F 1 "3_and" H 4650 4000 60 0000 C CNN
+F 2 "" H 3700 3500 60 0000 C CNN
+F 3 "" H 3700 3500 60 0000 C CNN
+ 1 3700 3500
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_and U2
+U 1 1 5C9A2940
+P 5450 3400
+F 0 "U2" H 5450 3400 60 0000 C CNN
+F 1 "d_and" H 5500 3500 60 0000 C CNN
+F 2 "" H 5450 3400 60 0000 C CNN
+F 3 "" H 5450 3400 60 0000 C CNN
+ 1 5450 3400
+ 1 0 0 -1
+$EndComp
+Wire Wire Line
+ 5000 3100 5000 3300
+Wire Wire Line
+ 4150 3000 4150 2700
+Wire Wire Line
+ 4150 2700 3200 2700
+Wire Wire Line
+ 4150 3100 4000 3100
+Wire Wire Line
+ 4000 3100 4000 3000
+Wire Wire Line
+ 4000 3000 3200 3000
+Wire Wire Line
+ 4150 3200 4150 3300
+Wire Wire Line
+ 4150 3300 3250 3300
+Wire Wire Line
+ 5000 3400 5000 3550
+Wire Wire Line
+ 5000 3550 3250 3550
+Wire Wire Line
+ 5900 3350 6500 3350
+$Comp
+L PORT U1
+U 1 1 5C9A29B1
+P 2950 2700
+F 0 "U1" H 3000 2800 30 0000 C CNN
+F 1 "PORT" H 2950 2700 30 0000 C CNN
+F 2 "" H 2950 2700 60 0000 C CNN
+F 3 "" H 2950 2700 60 0000 C CNN
+ 1 2950 2700
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 2 1 5C9A29E9
+P 2950 3000
+F 0 "U1" H 3000 3100 30 0000 C CNN
+F 1 "PORT" H 2950 3000 30 0000 C CNN
+F 2 "" H 2950 3000 60 0000 C CNN
+F 3 "" H 2950 3000 60 0000 C CNN
+ 2 2950 3000
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 3 1 5C9A2A0D
+P 3000 3300
+F 0 "U1" H 3050 3400 30 0000 C CNN
+F 1 "PORT" H 3000 3300 30 0000 C CNN
+F 2 "" H 3000 3300 60 0000 C CNN
+F 3 "" H 3000 3300 60 0000 C CNN
+ 3 3000 3300
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 4 1 5C9A2A3C
+P 3000 3550
+F 0 "U1" H 3050 3650 30 0000 C CNN
+F 1 "PORT" H 3000 3550 30 0000 C CNN
+F 2 "" H 3000 3550 60 0000 C CNN
+F 3 "" H 3000 3550 60 0000 C CNN
+ 4 3000 3550
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 5 1 5C9A2A68
+P 6750 3350
+F 0 "U1" H 6800 3450 30 0000 C CNN
+F 1 "PORT" H 6750 3350 30 0000 C CNN
+F 2 "" H 6750 3350 60 0000 C CNN
+F 3 "" H 6750 3350 60 0000 C CNN
+ 5 6750 3350
+ -1 0 0 1
+$EndComp
+Text Notes 3450 2650 0 60 ~ 12
+in1
+Text Notes 3450 2950 0 60 ~ 12
+in2
+Text Notes 3500 3300 0 60 ~ 12
+in3
+Text Notes 3500 3550 0 60 ~ 12
+in4
+Text Notes 6150 3350 0 60 ~ 12
+out
+$EndSCHEMATC
diff --git a/library/SubcircuitLibrary/74F182/4_and.sub b/library/SubcircuitLibrary/74F182/4_and.sub
new file mode 100644
index 000000000..8663f37e6
--- /dev/null
+++ b/library/SubcircuitLibrary/74F182/4_and.sub
@@ -0,0 +1,12 @@
+* Subcircuit 4_and
+.subckt 4_and net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_
+* c:\users\malli\esim\src\subcircuitlibrary\4_and\4_and.cir
+.include 3_and.sub
+x1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u2-pad1_ 3_and
+* u2 net-_u2-pad1_ net-_u1-pad4_ net-_u1-pad5_ d_and
+a1 [net-_u2-pad1_ net-_u1-pad4_ ] net-_u1-pad5_ u2
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+* Control Statements
+
+.ends 4_and
\ No newline at end of file
diff --git a/library/SubcircuitLibrary/74F182/4_and_Previous_Values.xml b/library/SubcircuitLibrary/74F182/4_and_Previous_Values.xml
new file mode 100644
index 000000000..f2ba0130e
--- /dev/null
+++ b/library/SubcircuitLibrary/74F182/4_and_Previous_Values.xml
@@ -0,0 +1 @@
+d_andC:\Users\malli\eSim\src\SubcircuitLibrary\3_andtruefalsefalseHzHz0Volts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesSecSecSec
\ No newline at end of file
diff --git a/library/SubcircuitLibrary/74F182/74F182.cir b/library/SubcircuitLibrary/74F182/74F182.cir
new file mode 100644
index 000000000..864a726c7
--- /dev/null
+++ b/library/SubcircuitLibrary/74F182/74F182.cir
@@ -0,0 +1,24 @@
+.title KiCad schematic
+X5 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad14_ Net-_U1-Pad5_ Net-_X10-Pad3_ 4_and
+X8 Net-_U1-Pad3_ Net-_U1-Pad1_ Net-_U1-Pad14_ Net-_U1-Pad5_ Net-_X10-Pad4_ 4_and
+X4 Net-_U1-Pad14_ Net-_U1-Pad15_ Net-_U1-Pad5_ Net-_X10-Pad2_ 3_and
+U19 Net-_U1-Pad5_ Net-_U1-Pad6_ Net-_U19-Pad3_ d_and
+X7 Net-_U14-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad1_ Net-_U1-Pad14_ Net-_X12-Pad4_ 4_and
+X12 Net-_U18-Pad3_ Net-_X12-Pad2_ Net-_X12-Pad3_ Net-_X12-Pad4_ Net-_U22-Pad1_ 4_OR
+U22 Net-_U22-Pad1_ Net-_U1-Pad9_ d_inverter
+U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ Net-_U1-Pad6_ Net-_U1-Pad7_ unconnected-_U1-Pad8_ Net-_U1-Pad9_ Net-_U1-Pad10_ Net-_U1-Pad11_ Net-_U1-Pad12_ Net-_U1-Pad13_ Net-_U1-Pad14_ Net-_U1-Pad15_ unconnected-_U1-Pad16_ PORT
+X10 Net-_U19-Pad3_ Net-_X10-Pad2_ Net-_X10-Pad3_ Net-_X10-Pad4_ Net-_U1-Pad10_ 4_OR
+X11 Net-_U1-Pad4_ Net-_U1-Pad2_ Net-_U1-Pad15_ Net-_U1-Pad6_ Net-_U1-Pad7_ 4_OR
+U15 Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U15-Pad3_ d_and
+U16 Net-_U1-Pad3_ Net-_U14-Pad2_ Net-_U16-Pad3_ d_and
+U17 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U17-Pad3_ d_and
+U20 Net-_U15-Pad3_ Net-_U16-Pad3_ Net-_U1-Pad12_ d_nor
+X9 Net-_U17-Pad3_ Net-_X1-Pad4_ Net-_X2-Pad4_ unconnected-_X9-Pad4_ Net-_U21-Pad1_ 4_OR
+U21 Net-_U21-Pad1_ Net-_U1-Pad11_ d_inverter
+X1 Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad1_ Net-_X1-Pad4_ 3_and
+X2 Net-_U14-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad1_ Net-_X2-Pad4_ 3_and
+X3 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad14_ Net-_X12-Pad2_ 3_and
+U18 Net-_U1-Pad14_ Net-_U1-Pad15_ Net-_U18-Pad3_ d_and
+X6 Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad1_ Net-_U1-Pad14_ Net-_X12-Pad3_ 4_and
+U14 Net-_U1-Pad13_ Net-_U14-Pad2_ d_inverter
+.end
diff --git a/library/SubcircuitLibrary/74F182/74F182.cir.out b/library/SubcircuitLibrary/74F182/74F182.cir.out
new file mode 100644
index 000000000..4cf0f04e5
--- /dev/null
+++ b/library/SubcircuitLibrary/74F182/74F182.cir.out
@@ -0,0 +1,99 @@
+.title kicad schematic
+
+.include 4_OR.sub
+.include 4_and.sub
+.include 3_and.sub
+* u18 net-_u1-pad14_ net-_u1-pad15_ net-_u18-pad3_ d_and
+x3 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad14_ net-_x12-pad2_ 3_and
+x2 net-_u14-pad2_ net-_u1-pad3_ net-_u1-pad1_ net-_x2-pad4_ 3_and
+x1 net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad1_ net-_x1-pad4_ 3_and
+x7 net-_u14-pad2_ net-_u1-pad3_ net-_u1-pad1_ net-_u1-pad14_ net-_x12-pad4_ 4_and
+* u9 net-_u1-pad6_ d_pullup
+* u8 net-_u1-pad5_ d_pullup
+x8 net-_u1-pad3_ net-_u1-pad1_ net-_u1-pad14_ net-_u1-pad5_ net-_x10-pad4_ 4_and
+* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ unconnected-_u1-pad8_ net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad13_ net-_u1-pad14_ net-_u1-pad15_ unconnected-_u1-pad16_ port
+* u19 net-_u1-pad5_ net-_u1-pad6_ net-_u19-pad3_ d_and
+x5 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad14_ net-_u1-pad5_ net-_x10-pad3_ 4_and
+x4 net-_u1-pad14_ net-_u1-pad15_ net-_u1-pad5_ net-_x10-pad2_ 3_and
+x9 net-_u17-pad3_ net-_x1-pad4_ net-_x2-pad4_ unconnected-_x9-pad4_ net-_u21-pad1_ 4_OR
+* u17 net-_u1-pad1_ net-_u1-pad2_ net-_u17-pad3_ d_and
+* u16 net-_u1-pad3_ net-_u14-pad2_ net-_u16-pad3_ d_and
+* u15 net-_u1-pad3_ net-_u1-pad4_ net-_u15-pad3_ d_and
+* u21 net-_u21-pad1_ net-_u1-pad11_ d_inverter
+* u20 net-_u15-pad3_ net-_u16-pad3_ net-_u1-pad12_ d_nor
+x11 net-_u1-pad4_ net-_u1-pad2_ net-_u1-pad15_ net-_u1-pad6_ net-_u1-pad7_ 4_OR
+x10 net-_u19-pad3_ net-_x10-pad2_ net-_x10-pad3_ net-_x10-pad4_ net-_u1-pad10_ 4_OR
+x6 net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad1_ net-_u1-pad14_ net-_x12-pad3_ 4_and
+* u22 net-_u22-pad1_ net-_u1-pad9_ d_inverter
+x12 net-_u18-pad3_ net-_x12-pad2_ net-_x12-pad3_ net-_x12-pad4_ net-_u22-pad1_ 4_OR
+* u2 net-_u1-pad3_ d_pullup
+* u14 net-_u1-pad13_ net-_u14-pad2_ d_inverter
+* u3 net-_u1-pad4_ d_pullup
+* u4 net-_u1-pad13_ d_pullup
+* u5 net-_u1-pad1_ d_pullup
+* u6 net-_u1-pad2_ d_pullup
+* u7 net-_u1-pad14_ d_pullup
+* u10 net-_u1-pad15_ d_pullup
+a1 [net-_u1-pad14_ net-_u1-pad15_ ] net-_u18-pad3_ u18
+a2 net-_u1-pad6_ u9
+a3 net-_u1-pad5_ u8
+a4 [net-_u1-pad5_ net-_u1-pad6_ ] net-_u19-pad3_ u19
+a5 [net-_u1-pad1_ net-_u1-pad2_ ] net-_u17-pad3_ u17
+a6 [net-_u1-pad3_ net-_u14-pad2_ ] net-_u16-pad3_ u16
+a7 [net-_u1-pad3_ net-_u1-pad4_ ] net-_u15-pad3_ u15
+a8 net-_u21-pad1_ net-_u1-pad11_ u21
+a9 [net-_u15-pad3_ net-_u16-pad3_ ] net-_u1-pad12_ u20
+a10 net-_u22-pad1_ net-_u1-pad9_ u22
+a11 net-_u1-pad3_ u2
+a12 net-_u1-pad13_ net-_u14-pad2_ u14
+a13 net-_u1-pad4_ u3
+a14 net-_u1-pad13_ u4
+a15 net-_u1-pad1_ u5
+a16 net-_u1-pad2_ u6
+a17 net-_u1-pad14_ u7
+a18 net-_u1-pad15_ u10
+* Schematic Name: d_and, Ngspice Name: d_and
+.model u18 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_pullup, Ngspice Name: d_pullup
+.model u9 d_pullup(load=1.0e-12 )
+* Schematic Name: d_pullup, Ngspice Name: d_pullup
+.model u8 d_pullup(load=1.0e-12 )
+* Schematic Name: d_and, Ngspice Name: d_and
+.model u19 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, Ngspice Name: d_and
+.model u17 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, Ngspice Name: d_and
+.model u16 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, Ngspice Name: d_and
+.model u15 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, Ngspice Name: d_inverter
+.model u21 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_nor, Ngspice Name: d_nor
+.model u20 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, Ngspice Name: d_inverter
+.model u22 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_pullup, Ngspice Name: d_pullup
+.model u2 d_pullup(load=1.0e-12 )
+* Schematic Name: d_inverter, Ngspice Name: d_inverter
+.model u14 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_pullup, Ngspice Name: d_pullup
+.model u3 d_pullup(load=1.0e-12 )
+* Schematic Name: d_pullup, Ngspice Name: d_pullup
+.model u4 d_pullup(load=1.0e-12 )
+* Schematic Name: d_pullup, Ngspice Name: d_pullup
+.model u5 d_pullup(load=1.0e-12 )
+* Schematic Name: d_pullup, Ngspice Name: d_pullup
+.model u6 d_pullup(load=1.0e-12 )
+* Schematic Name: d_pullup, Ngspice Name: d_pullup
+.model u7 d_pullup(load=1.0e-12 )
+* Schematic Name: d_pullup, Ngspice Name: d_pullup
+.model u10 d_pullup(load=1.0e-12 )
+.tran 0e-00 0e-00 0e-00
+
+* Control Statements
+.control
+run
+print allv > plot_data_v.txt
+print alli > plot_data_i.txt
+.endc
+.end
diff --git a/library/SubcircuitLibrary/74F182/74F182.kicad_sch b/library/SubcircuitLibrary/74F182/74F182.kicad_sch
new file mode 100644
index 000000000..e4663253c
--- /dev/null
+++ b/library/SubcircuitLibrary/74F182/74F182.kicad_sch
@@ -0,0 +1,2348 @@
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+ (path "/9bebe23c-605d-470d-810f-245c646d420c"
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+ )
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+ )
+ (path "/09fc65f9-c4d0-43fc-807b-1ef8bd7de889"
+ (reference "U21") (unit 1) (value "d_inverter") (footprint "")
+ )
+ (path "/bdeff28c-6f9d-4719-a6d8-6ea713314e53"
+ (reference "U22") (unit 1) (value "d_inverter") (footprint "")
+ )
+ (path "/300ca69a-1938-4a60-bb4f-4c87e2f532aa"
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+ )
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+ (reference "X8") (unit 1) (value "4_and") (footprint "")
+ )
+ (path "/a94f2f83-595a-4b39-9228-af01041bd56e"
+ (reference "X9") (unit 1) (value "4_OR") (footprint "")
+ )
+ (path "/b4589445-9493-4d13-bb89-8fdca901acd1"
+ (reference "X10") (unit 1) (value "4_OR") (footprint "")
+ )
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+ (reference "X11") (unit 1) (value "4_OR") (footprint "")
+ )
+ (path "/88ba4906-718d-46a8-9997-ba1e0d08b8ef"
+ (reference "X12") (unit 1) (value "4_OR") (footprint "")
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+ )
+)
diff --git a/library/SubcircuitLibrary/74F182/74F182.sub b/library/SubcircuitLibrary/74F182/74F182.sub
new file mode 100644
index 000000000..1dfa458e9
--- /dev/null
+++ b/library/SubcircuitLibrary/74F182/74F182.sub
@@ -0,0 +1,93 @@
+* Subcircuit 74F182
+.subckt 74F182 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ unconnected-_u1-pad8_ net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad13_ net-_u1-pad14_ net-_u1-pad15_ unconnected-_u1-pad16_
+.title kicad schematic
+.include 4_OR.sub
+.include 4_and.sub
+.include 3_and.sub
+* u18 net-_u1-pad14_ net-_u1-pad15_ net-_u18-pad3_ d_and
+x3 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad14_ net-_x12-pad2_ 3_and
+x2 net-_u14-pad2_ net-_u1-pad3_ net-_u1-pad1_ net-_x2-pad4_ 3_and
+x1 net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad1_ net-_x1-pad4_ 3_and
+x7 net-_u14-pad2_ net-_u1-pad3_ net-_u1-pad1_ net-_u1-pad14_ net-_x12-pad4_ 4_and
+* u9 net-_u1-pad6_ d_pullup
+* u8 net-_u1-pad5_ d_pullup
+x8 net-_u1-pad3_ net-_u1-pad1_ net-_u1-pad14_ net-_u1-pad5_ net-_x10-pad4_ 4_and
+* u19 net-_u1-pad5_ net-_u1-pad6_ net-_u19-pad3_ d_and
+x5 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad14_ net-_u1-pad5_ net-_x10-pad3_ 4_and
+x4 net-_u1-pad14_ net-_u1-pad15_ net-_u1-pad5_ net-_x10-pad2_ 3_and
+x9 net-_u17-pad3_ net-_x1-pad4_ net-_x2-pad4_ unconnected-_x9-pad4_ net-_u21-pad1_ 4_OR
+* u17 net-_u1-pad1_ net-_u1-pad2_ net-_u17-pad3_ d_and
+* u16 net-_u1-pad3_ net-_u14-pad2_ net-_u16-pad3_ d_and
+* u15 net-_u1-pad3_ net-_u1-pad4_ net-_u15-pad3_ d_and
+* u21 net-_u21-pad1_ net-_u1-pad11_ d_inverter
+* u20 net-_u15-pad3_ net-_u16-pad3_ net-_u1-pad12_ d_nor
+x11 net-_u1-pad4_ net-_u1-pad2_ net-_u1-pad15_ net-_u1-pad6_ net-_u1-pad7_ 4_OR
+x10 net-_u19-pad3_ net-_x10-pad2_ net-_x10-pad3_ net-_x10-pad4_ net-_u1-pad10_ 4_OR
+x6 net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad1_ net-_u1-pad14_ net-_x12-pad3_ 4_and
+* u22 net-_u22-pad1_ net-_u1-pad9_ d_inverter
+x12 net-_u18-pad3_ net-_x12-pad2_ net-_x12-pad3_ net-_x12-pad4_ net-_u22-pad1_ 4_OR
+* u2 net-_u1-pad3_ d_pullup
+* u14 net-_u1-pad13_ net-_u14-pad2_ d_inverter
+* u3 net-_u1-pad4_ d_pullup
+* u4 net-_u1-pad13_ d_pullup
+* u5 net-_u1-pad1_ d_pullup
+* u6 net-_u1-pad2_ d_pullup
+* u7 net-_u1-pad14_ d_pullup
+* u10 net-_u1-pad15_ d_pullup
+a1 [net-_u1-pad14_ net-_u1-pad15_ ] net-_u18-pad3_ u18
+a2 net-_u1-pad6_ u9
+a3 net-_u1-pad5_ u8
+a4 [net-_u1-pad5_ net-_u1-pad6_ ] net-_u19-pad3_ u19
+a5 [net-_u1-pad1_ net-_u1-pad2_ ] net-_u17-pad3_ u17
+a6 [net-_u1-pad3_ net-_u14-pad2_ ] net-_u16-pad3_ u16
+a7 [net-_u1-pad3_ net-_u1-pad4_ ] net-_u15-pad3_ u15
+a8 net-_u21-pad1_ net-_u1-pad11_ u21
+a9 [net-_u15-pad3_ net-_u16-pad3_ ] net-_u1-pad12_ u20
+a10 net-_u22-pad1_ net-_u1-pad9_ u22
+a11 net-_u1-pad3_ u2
+a12 net-_u1-pad13_ net-_u14-pad2_ u14
+a13 net-_u1-pad4_ u3
+a14 net-_u1-pad13_ u4
+a15 net-_u1-pad1_ u5
+a16 net-_u1-pad2_ u6
+a17 net-_u1-pad14_ u7
+a18 net-_u1-pad15_ u10
+* Schematic Name: d_and, Ngspice Name: d_and
+.model u18 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_pullup, Ngspice Name: d_pullup
+.model u9 d_pullup(load=1.0e-12 )
+* Schematic Name: d_pullup, Ngspice Name: d_pullup
+.model u8 d_pullup(load=1.0e-12 )
+* Schematic Name: d_and, Ngspice Name: d_and
+.model u19 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, Ngspice Name: d_and
+.model u17 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, Ngspice Name: d_and
+.model u16 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, Ngspice Name: d_and
+.model u15 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, Ngspice Name: d_inverter
+.model u21 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_nor, Ngspice Name: d_nor
+.model u20 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, Ngspice Name: d_inverter
+.model u22 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_pullup, Ngspice Name: d_pullup
+.model u2 d_pullup(load=1.0e-12 )
+* Schematic Name: d_inverter, Ngspice Name: d_inverter
+.model u14 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_pullup, Ngspice Name: d_pullup
+.model u3 d_pullup(load=1.0e-12 )
+* Schematic Name: d_pullup, Ngspice Name: d_pullup
+.model u4 d_pullup(load=1.0e-12 )
+* Schematic Name: d_pullup, Ngspice Name: d_pullup
+.model u5 d_pullup(load=1.0e-12 )
+* Schematic Name: d_pullup, Ngspice Name: d_pullup
+.model u6 d_pullup(load=1.0e-12 )
+* Schematic Name: d_pullup, Ngspice Name: d_pullup
+.model u7 d_pullup(load=1.0e-12 )
+* Schematic Name: d_pullup, Ngspice Name: d_pullup
+.model u10 d_pullup(load=1.0e-12 )
+* Control Statements
+
+.ends 74F182
\ No newline at end of file
diff --git a/library/SubcircuitLibrary/74F182/74F182_Previous_Values.xml b/library/SubcircuitLibrary/74F182/74F182_Previous_Values.xml
new file mode 100644
index 000000000..8630e4a87
--- /dev/null
+++ b/library/SubcircuitLibrary/74F182/74F182_Previous_Values.xml
@@ -0,0 +1 @@
+d_inverterd_andd_andd_inverterd_andd_andd_andd_nord_inverterd_pullupd_pullupd_pullupd_pullupd_pullupd_pullupd_pullupd_pullupd_pullupC:\Users\Sakhi\FOSSEE\eSim\library\SubcircuitLibrary\3_andC:\Users\Sakhi\FOSSEE\eSim\library\SubcircuitLibrary\3_andC:\Users\Sakhi\FOSSEE\eSim\library\SubcircuitLibrary\3_andC:\Users\Sakhi\FOSSEE\eSim\library\SubcircuitLibrary\4_andC:\Users\Sakhi\FOSSEE\eSim\library\SubcircuitLibrary\4_andC:\Users\Sakhi\FOSSEE\eSim\library\SubcircuitLibrary\4_andC:\Users\Sakhi\FOSSEE\eSim\library\SubcircuitLibrary\3_andC:\Users\Sakhi\FOSSEE\eSim\library\SubcircuitLibrary\4_ORC:\Users\Sakhi\FOSSEE\eSim\library\SubcircuitLibrary\4_ORC:\Users\Sakhi\FOSSEE\eSim\library\SubcircuitLibrary\4_ORC:\Users\Sakhi\FOSSEE\eSim\library\SubcircuitLibrary\4_andC:\Users\Sakhi\FOSSEE\eSim\library\SubcircuitLibrary\4_ORtruefalsefalseHzHz0Volts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or Amperessecsecsec
\ No newline at end of file
diff --git a/library/SubcircuitLibrary/74F182/_autosave-74F182.sch b/library/SubcircuitLibrary/74F182/_autosave-74F182.sch
new file mode 100644
index 000000000..c42ccd52e
--- /dev/null
+++ b/library/SubcircuitLibrary/74F182/_autosave-74F182.sch
@@ -0,0 +1,706 @@
+EESchema Schematic File Version 5
+EELAYER 36 0
+EELAYER END
+$Descr A2 23386 16535
+encoding utf-8
+Sheet 1 1
+Title ""
+Date ""
+Rev ""
+Comp ""
+Comment1 ""
+Comment2 ""
+Comment3 ""
+Comment4 ""
+Comment5 ""
+Comment6 ""
+Comment7 ""
+Comment8 ""
+Comment9 ""
+$EndDescr
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+ 13650 13300 10900 13300
+Wire Wire Line
+ 13650 13400 10600 13400
+Wire Wire Line
+ 13650 13500 10300 13500
+Wire Wire Line
+ 13700 7300 13700 7850
+Wire Wire Line
+ 13700 8050 13600 8050
+Wire Wire Line
+ 13700 8850 13700 8150
+Wire Wire Line
+ 14550 2700 16300 2700
+Wire Wire Line
+ 14550 10950 16250 10950
+Wire Wire Line
+ 15150 5350 16250 5350
+Wire Wire Line
+ 15200 8000 16250 8000
+Wire Wire Line
+ 16100 13350 14550 13350
+$Comp
+L eSim_Miscellaneous:PORT U?
+U 3 1 00000000
+P 6750 2350
+F 0 "U?" H 6775 2550 30 0000 C CNN
+F 1 "PORT" H 6775 2450 30 0000 C CNN
+F 2 "" H 6750 2350 60 0000 C CNN
+F 3 "" H 6750 2350 60 0000 C CNN
+ 3 6750 2350
+ 1 0 0 -1
+$EndComp
+$Comp
+L eSim_Miscellaneous:PORT U?
+U 4 1 00000000
+P 6750 2450
+F 0 "U?" H 6775 2650 30 0000 C CNN
+F 1 "PORT" H 6775 2550 30 0000 C CNN
+F 2 "" H 6750 2450 60 0000 C CNN
+F 3 "" H 6750 2450 60 0000 C CNN
+ 4 6750 2450
+ 1 0 0 -1
+$EndComp
+$Comp
+L eSim_Miscellaneous:PORT U?
+U 13 1 00000000
+P 6750 3100
+F 0 "U?" H 6775 3300 30 0000 C CNN
+F 1 "PORT" H 6775 3200 30 0000 C CNN
+F 2 "" H 6750 3100 60 0000 C CNN
+F 3 "" H 6750 3100 60 0000 C CNN
+ 13 6750 3100
+ 1 0 0 -1
+$EndComp
+$Comp
+L eSim_Miscellaneous:PORT U?
+U 1 1 00000000
+P 6750 4800
+F 0 "U?" H 6775 5000 30 0000 C CNN
+F 1 "PORT" H 6775 4900 30 0000 C CNN
+F 2 "" H 6750 4800 60 0000 C CNN
+F 3 "" H 6750 4800 60 0000 C CNN
+ 1 6750 4800
+ 1 0 0 -1
+$EndComp
+$Comp
+L eSim_Miscellaneous:PORT U?
+U 2 1 00000000
+P 6750 4900
+F 0 "U?" H 6750 4700 30 0000 C CNN
+F 1 "PORT" H 6750 4800 30 0000 C CNN
+F 2 "" H 6750 4900 60 0000 C CNN
+F 3 "" H 6750 4900 60 0000 C CNN
+ 2 6750 4900
+ 1 0 0 -1
+$EndComp
+$Comp
+L eSim_Miscellaneous:PORT U?
+U 14 1 00000000
+P 6750 7250
+F 0 "U?" H 6775 7450 30 0000 C CNN
+F 1 "PORT" H 6775 7350 30 0000 C CNN
+F 2 "" H 6750 7250 60 0000 C CNN
+F 3 "" H 6750 7250 60 0000 C CNN
+ 14 6750 7250
+ 1 0 0 -1
+$EndComp
+$Comp
+L eSim_Miscellaneous:PORT U?
+U 15 1 00000000
+P 6750 7350
+F 0 "U?" H 6775 7550 30 0000 C CNN
+F 1 "PORT" H 6775 7450 30 0000 C CNN
+F 2 "" H 6750 7350 60 0000 C CNN
+F 3 "" H 6750 7350 60 0000 C CNN
+ 15 6750 7350
+ 1 0 0 -1
+$EndComp
+$Comp
+L eSim_Miscellaneous:PORT U?
+U 5 1 00000000
+P 6750 10200
+F 0 "U?" H 6775 10400 30 0000 C CNN
+F 1 "PORT" H 6775 10300 30 0000 C CNN
+F 2 "" H 6750 10200 60 0000 C CNN
+F 3 "" H 6750 10200 60 0000 C CNN
+ 5 6750 10200
+ 1 0 0 -1
+$EndComp
+$Comp
+L eSim_Miscellaneous:PORT U?
+U 6 1 00000000
+P 6750 10300
+F 0 "U?" H 6775 10500 30 0000 C CNN
+F 1 "PORT" H 6775 10400 30 0000 C CNN
+F 2 "" H 6750 10300 60 0000 C CNN
+F 3 "" H 6750 10300 60 0000 C CNN
+ 6 6750 10300
+ 1 0 0 -1
+$EndComp
+$Comp
+L eSim_Miscellaneous:PORT U?
+U 16 1 00000000
+P 6750 12750
+F 0 "U?" H 6775 12950 30 0000 C CNN
+F 1 "PORT" H 6775 12850 30 0000 C CNN
+F 2 "" H 6750 12750 60 0000 C CNN
+F 3 "" H 6750 12750 60 0000 C CNN
+ 16 6750 12750
+ 1 0 0 -1
+$EndComp
+$Comp
+L eSim_Miscellaneous:PORT U?
+U 8 1 00000000
+P 6750 13200
+F 0 "U?" H 6775 13400 30 0000 C CNN
+F 1 "PORT" H 6775 13300 30 0000 C CNN
+F 2 "" H 6750 13200 60 0000 C CNN
+F 3 "" H 6750 13200 60 0000 C CNN
+ 8 6750 13200
+ 1 0 0 -1
+$EndComp
+$Comp
+L eSim_Miscellaneous:PORT U?
+U 7 1 00000000
+P 16350 13350
+F 0 "U?" H 16200 13325 30 0000 R CNN
+F 1 "PORT" H 16200 13425 30 0000 R CNN
+F 2 "" H 16350 13350 60 0000 C CNN
+F 3 "" H 16350 13350 60 0000 C CNN
+ 7 16350 13350
+ -1 0 0 1
+$EndComp
+$Comp
+L eSim_Miscellaneous:PORT U?
+U 11 1 00000000
+P 16500 5350
+F 0 "U?" H 16350 5325 30 0000 R CNN
+F 1 "PORT" H 16350 5425 30 0000 R CNN
+F 2 "" H 16500 5350 60 0000 C CNN
+F 3 "" H 16500 5350 60 0000 C CNN
+ 11 16500 5350
+ -1 0 0 1
+$EndComp
+$Comp
+L eSim_Miscellaneous:PORT U?
+U 9 1 00000000
+P 16500 8000
+F 0 "U?" H 16350 7975 30 0000 R CNN
+F 1 "PORT" H 16350 8075 30 0000 R CNN
+F 2 "" H 16500 8000 60 0000 C CNN
+F 3 "" H 16500 8000 60 0000 C CNN
+ 9 16500 8000
+ -1 0 0 1
+$EndComp
+$Comp
+L eSim_Miscellaneous:PORT U?
+U 10 1 00000000
+P 16500 10950
+F 0 "U?" H 16350 10925 30 0000 R CNN
+F 1 "PORT" H 16350 11025 30 0000 R CNN
+F 2 "" H 16500 10950 60 0000 C CNN
+F 3 "" H 16500 10950 60 0000 C CNN
+ 10 16500 10950
+ -1 0 0 1
+$EndComp
+$Comp
+L eSim_Miscellaneous:PORT U?
+U 12 1 00000000
+P 16550 2700
+F 0 "U?" H 16400 2675 30 0000 R CNN
+F 1 "PORT" H 16400 2775 30 0000 R CNN
+F 2 "" H 16550 2700 60 0000 C CNN
+F 3 "" H 16550 2700 60 0000 C CNN
+ 12 16550 2700
+ -1 0 0 1
+$EndComp
+$Comp
+L eSim_Digital:d_inverter U14
+U 1 1 00000000
+P 8950 3100
+F 0 "U14" H 8950 3350 60 0000 C CNN
+F 1 "d_inverter" H 8950 3200 60 0000 C CNN
+F 2 "" H 9000 3050 60 0000 C CNN
+F 3 "" H 9000 3050 60 0000 C CNN
+ 1 8950 3100
+ 1 0 0 -1
+$EndComp
+$Comp
+L eSim_Digital:d_inverter U21
+U 1 1 00000000
+P 14850 5350
+F 0 "U21" H 14850 5600 60 0000 C CNN
+F 1 "d_inverter" H 14850 5450 60 0000 C CNN
+F 2 "" H 14900 5300 60 0000 C CNN
+F 3 "" H 14900 5300 60 0000 C CNN
+ 1 14850 5350
+ 1 0 0 -1
+$EndComp
+$Comp
+L eSim_Digital:d_inverter U22
+U 1 1 00000000
+P 14900 8000
+F 0 "U22" H 14900 8250 60 0000 C CNN
+F 1 "d_inverter" H 14900 8100 60 0000 C CNN
+F 2 "" H 14950 7950 60 0000 C CNN
+F 3 "" H 14950 7950 60 0000 C CNN
+ 1 14900 8000
+ 1 0 0 -1
+$EndComp
+$Comp
+L eSim_Digital:d_and U15
+U 1 1 00000000
+P 12400 2450
+F 0 "U15" H 12400 2800 60 0000 C CNN
+F 1 "d_and" H 12400 2650 60 0000 C CNN
+F 2 "" H 12400 2450 60 0000 C CNN
+F 3 "" H 12400 2450 60 0000 C CNN
+ 1 12400 2450
+ 1 0 0 -1
+$EndComp
+$Comp
+L eSim_Digital:d_and U16
+U 1 1 00000000
+P 12400 3100
+F 0 "U16" H 12400 3450 60 0000 C CNN
+F 1 "d_and" H 12400 3300 60 0000 C CNN
+F 2 "" H 12400 3100 60 0000 C CNN
+F 3 "" H 12400 3100 60 0000 C CNN
+ 1 12400 3100
+ 1 0 0 -1
+$EndComp
+$Comp
+L eSim_Digital:d_and U17
+U 1 1 00000000
+P 12400 4900
+F 0 "U17" H 12400 5250 60 0000 C CNN
+F 1 "d_and" H 12400 5100 60 0000 C CNN
+F 2 "" H 12400 4900 60 0000 C CNN
+F 3 "" H 12400 4900 60 0000 C CNN
+ 1 12400 4900
+ 1 0 0 -1
+$EndComp
+$Comp
+L eSim_Digital:d_and U18
+U 1 1 00000000
+P 12400 7350
+F 0 "U18" H 12400 7700 60 0000 C CNN
+F 1 "d_and" H 12400 7550 60 0000 C CNN
+F 2 "" H 12400 7350 60 0000 C CNN
+F 3 "" H 12400 7350 60 0000 C CNN
+ 1 12400 7350
+ 1 0 0 -1
+$EndComp
+$Comp
+L eSim_Digital:d_and U19
+U 1 1 00000000
+P 12400 10300
+F 0 "U19" H 12400 10650 60 0000 C CNN
+F 1 "d_and" H 12400 10500 60 0000 C CNN
+F 2 "" H 12400 10300 60 0000 C CNN
+F 3 "" H 12400 10300 60 0000 C CNN
+ 1 12400 10300
+ 1 0 0 -1
+$EndComp
+$Comp
+L eSim_Digital:d_nor U20
+U 1 1 00000000
+P 14100 2750
+F 0 "U20" H 14100 3100 60 0000 C CNN
+F 1 "d_nor" H 14100 2950 60 0000 C CNN
+F 2 "" H 14100 2750 60 0000 C CNN
+F 3 "" H 14100 2750 60 0000 C CNN
+ 1 14100 2750
+ 1 0 0 -1
+$EndComp
+$Comp
+L eSim_Subckt:3_and X1
+U 1 1 00000000
+P 12300 5450
+F 0 "X1" H 12379 5850 60 0000 C CNN
+F 1 "3_and" H 12379 5700 60 0000 C CNN
+F 2 "" H 12300 5450 60 0000 C CNN
+F 3 "" H 12300 5450 60 0000 C CNN
+ 1 12300 5450
+ 1 0 0 -1
+$EndComp
+$Comp
+L eSim_Subckt:3_and X2
+U 1 1 00000000
+P 12300 5950
+F 0 "X2" H 12379 6350 60 0000 C CNN
+F 1 "3_and" H 12379 6200 60 0000 C CNN
+F 2 "" H 12300 5950 60 0000 C CNN
+F 3 "" H 12300 5950 60 0000 C CNN
+ 1 12300 5950
+ 1 0 0 -1
+$EndComp
+$Comp
+L eSim_Subckt:3_and X3
+U 1 1 00000000
+P 12300 7800
+F 0 "X3" H 12379 8200 60 0000 C CNN
+F 1 "3_and" H 12379 8050 60 0000 C CNN
+F 2 "" H 12300 7800 60 0000 C CNN
+F 3 "" H 12300 7800 60 0000 C CNN
+ 1 12300 7800
+ 1 0 0 -1
+$EndComp
+$Comp
+L eSim_Subckt:3_and X4
+U 1 1 00000000
+P 12300 10750
+F 0 "X4" H 12379 11150 60 0000 C CNN
+F 1 "3_and" H 12379 11000 60 0000 C CNN
+F 2 "" H 12300 10750 60 0000 C CNN
+F 3 "" H 12300 10750 60 0000 C CNN
+ 1 12300 10750
+ 1 0 0 -1
+$EndComp
+$Comp
+L eSim_Subckt:4_and X5
+U 1 1 00000000
+P 12300 11200
+F 0 "X5" H 12353 11600 60 0000 C CNN
+F 1 "4_and" H 12353 11450 60 0000 C CNN
+F 2 "" H 12300 11200 60 0000 C CNN
+F 3 "" H 12300 11200 60 0000 C CNN
+ 1 12300 11200
+ 1 0 0 -1
+$EndComp
+$Comp
+L eSim_Subckt:4_and X6
+U 1 1 00000000
+P 12350 8250
+F 0 "X6" H 12403 8650 60 0000 C CNN
+F 1 "4_and" H 12403 8500 60 0000 C CNN
+F 2 "" H 12350 8250 60 0000 C CNN
+F 3 "" H 12350 8250 60 0000 C CNN
+ 1 12350 8250
+ 1 0 0 -1
+$EndComp
+$Comp
+L eSim_Subckt:4_and X7
+U 1 1 00000000
+P 12350 8850
+F 0 "X7" H 12403 9250 60 0000 C CNN
+F 1 "4_and" H 12403 9100 60 0000 C CNN
+F 2 "" H 12350 8850 60 0000 C CNN
+F 3 "" H 12350 8850 60 0000 C CNN
+ 1 12350 8850
+ 1 0 0 -1
+$EndComp
+$Comp
+L eSim_Subckt:4_and X8
+U 1 1 00000000
+P 12350 11800
+F 0 "X8" H 12403 12200 60 0000 C CNN
+F 1 "4_and" H 12403 12050 60 0000 C CNN
+F 2 "" H 12350 11800 60 0000 C CNN
+F 3 "" H 12350 11800 60 0000 C CNN
+ 1 12350 11800
+ 1 0 0 -1
+$EndComp
+$Comp
+L eSim_Subckt:4_OR X9
+U 1 1 00000000
+P 14000 5350
+F 0 "X9" H 14075 5800 60 0000 C CNN
+F 1 "4_OR" H 14075 5650 60 0000 C CNN
+F 2 "" H 14000 5350 60 0000 C CNN
+F 3 "" H 14000 5350 60 0000 C CNN
+ 1 14000 5350
+ 1 0 0 -1
+$EndComp
+$Comp
+L eSim_Subckt:4_OR X10
+U 1 1 00000000
+P 14000 10950
+F 0 "X10" H 14075 11400 60 0000 C CNN
+F 1 "4_OR" H 14075 11250 60 0000 C CNN
+F 2 "" H 14000 10950 60 0000 C CNN
+F 3 "" H 14000 10950 60 0000 C CNN
+ 1 14000 10950
+ 1 0 0 -1
+$EndComp
+$Comp
+L eSim_Subckt:4_OR X11
+U 1 1 00000000
+P 14000 13350
+F 0 "X11" H 14075 13800 60 0000 C CNN
+F 1 "4_OR" H 14075 13650 60 0000 C CNN
+F 2 "" H 14000 13350 60 0000 C CNN
+F 3 "" H 14000 13350 60 0000 C CNN
+ 1 14000 13350
+ 1 0 0 -1
+$EndComp
+$Comp
+L eSim_Subckt:4_OR X12
+U 1 1 00000000
+P 14050 8000
+F 0 "X12" H 14125 8450 60 0000 C CNN
+F 1 "4_OR" H 14125 8300 60 0000 C CNN
+F 2 "" H 14050 8000 60 0000 C CNN
+F 3 "" H 14050 8000 60 0000 C CNN
+ 1 14050 8000
+ 1 0 0 -1
+$EndComp
+$EndSCHEMATC
diff --git a/library/SubcircuitLibrary/74F182/analysis b/library/SubcircuitLibrary/74F182/analysis
new file mode 100644
index 000000000..ebd5c0a94
--- /dev/null
+++ b/library/SubcircuitLibrary/74F182/analysis
@@ -0,0 +1 @@
+.tran 0e-00 0e-00 0e-00
\ No newline at end of file
diff --git a/library/SubcircuitLibrary/74HC157/74HC157.cir b/library/SubcircuitLibrary/74HC157/74HC157.cir
index e693accc7..2534f67f1 100644
--- a/library/SubcircuitLibrary/74HC157/74HC157.cir
+++ b/library/SubcircuitLibrary/74HC157/74HC157.cir
@@ -1,20 +1,22 @@
-* C:\FOSSEE\eSim\library\SubcircuitLibrary\74HC157\74HC157.cir
-
-* EESchema Netlist Version 1.1 (Spice format) creation date: 5/10/2025 5:51:02 PM
-
-* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N
-* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0
-
-* Sheet Name: /
-X1 Net-_U1-Pad9_ Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U3-Pad1_ mux
-X2 Net-_U1-Pad9_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U4-Pad1_ mux
-X3 Net-_U1-Pad9_ Net-_U1-Pad5_ Net-_U1-Pad6_ Net-_U5-Pad1_ mux
-X4 Net-_U1-Pad9_ Net-_U1-Pad7_ Net-_U1-Pad8_ Net-_U6-Pad1_ mux
-U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ Net-_U1-Pad6_ Net-_U1-Pad7_ Net-_U1-Pad8_ Net-_U1-Pad9_ Net-_U1-Pad10_ Net-_U1-Pad11_ Net-_U1-Pad12_ Net-_U1-Pad13_ Net-_U1-Pad14_ PORT
-U3 Net-_U3-Pad1_ Net-_U2-Pad2_ Net-_U1-Pad11_ d_and
-U4 Net-_U4-Pad1_ Net-_U2-Pad2_ Net-_U1-Pad12_ d_and
-U5 Net-_U5-Pad1_ Net-_U2-Pad2_ Net-_U1-Pad13_ d_and
-U6 Net-_U6-Pad1_ Net-_U2-Pad2_ Net-_U1-Pad14_ d_and
-U2 Net-_U1-Pad10_ Net-_U2-Pad2_ d_inverter
-
+.title KiCad schematic
+U1 /1 /2 /3 /4 /5 /6 /7 unconnected-_U1-Pad8_ /9 /10 /11 /12 /13 /14 /15 unconnected-_U1-Pad16_ PORT
+U16 /15 Net-_U16-Pad2_ d_inverter
+U17 Net-_U13-Pad2_ Net-_U17-Pad2_ d_inverter
+U15 /1 Net-_U15-Pad2_ d_inverter
+U14 /15 Net-_U14-Pad2_ d_inverter
+U19 Net-_U16-Pad2_ Net-_U17-Pad2_ Net-_U19-Pad3_ d_and
+U18 Net-_U14-Pad2_ Net-_U15-Pad2_ Net-_U18-Pad3_ d_and
+U13 /1 Net-_U13-Pad2_ d_inverter
+U22 /5 Net-_U18-Pad3_ Net-_U22-Pad3_ d_and
+U23 /6 Net-_U19-Pad3_ Net-_U23-Pad3_ d_and
+U24 /11 Net-_U18-Pad3_ Net-_U24-Pad3_ d_and
+U25 /10 Net-_U19-Pad3_ Net-_U25-Pad3_ d_and
+U29 Net-_U22-Pad3_ Net-_U23-Pad3_ /7 d_or
+U21 /3 Net-_U19-Pad3_ Net-_U21-Pad3_ d_and
+U28 Net-_U20-Pad3_ Net-_U21-Pad3_ /4 d_or
+U20 /2 Net-_U18-Pad3_ Net-_U20-Pad3_ d_and
+U31 Net-_U26-Pad3_ Net-_U27-Pad3_ /12 d_or
+U26 /14 Net-_U18-Pad3_ Net-_U26-Pad3_ d_and
+U27 /13 Net-_U19-Pad3_ Net-_U27-Pad3_ d_and
+U30 Net-_U24-Pad3_ Net-_U25-Pad3_ /9 d_or
.end
diff --git a/library/SubcircuitLibrary/74HC157/74HC157.cir.out b/library/SubcircuitLibrary/74HC157/74HC157.cir.out
index ead8d4382..0b016cefa 100644
--- a/library/SubcircuitLibrary/74HC157/74HC157.cir.out
+++ b/library/SubcircuitLibrary/74HC157/74HC157.cir.out
@@ -1,31 +1,82 @@
-* c:\fossee\esim\library\subcircuitlibrary\74hc157\74hc157.cir
+.title kicad schematic
-.include mux.sub
-x1 net-_u1-pad9_ net-_u1-pad1_ net-_u1-pad2_ net-_u3-pad1_ mux
-x2 net-_u1-pad9_ net-_u1-pad3_ net-_u1-pad4_ net-_u4-pad1_ mux
-x3 net-_u1-pad9_ net-_u1-pad5_ net-_u1-pad6_ net-_u5-pad1_ mux
-x4 net-_u1-pad9_ net-_u1-pad7_ net-_u1-pad8_ net-_u6-pad1_ mux
-* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ net-_u1-pad8_ net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad13_ net-_u1-pad14_ port
-* u3 net-_u3-pad1_ net-_u2-pad2_ net-_u1-pad11_ d_and
-* u4 net-_u4-pad1_ net-_u2-pad2_ net-_u1-pad12_ d_and
-* u5 net-_u5-pad1_ net-_u2-pad2_ net-_u1-pad13_ d_and
-* u6 net-_u6-pad1_ net-_u2-pad2_ net-_u1-pad14_ d_and
-* u2 net-_u1-pad10_ net-_u2-pad2_ d_inverter
-a1 [net-_u3-pad1_ net-_u2-pad2_ ] net-_u1-pad11_ u3
-a2 [net-_u4-pad1_ net-_u2-pad2_ ] net-_u1-pad12_ u4
-a3 [net-_u5-pad1_ net-_u2-pad2_ ] net-_u1-pad13_ u5
-a4 [net-_u6-pad1_ net-_u2-pad2_ ] net-_u1-pad14_ u6
-a5 net-_u1-pad10_ net-_u2-pad2_ u2
-* Schematic Name: d_and, NgSpice Name: d_and
-.model u3 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
-* Schematic Name: d_and, NgSpice Name: d_and
-.model u4 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
-* Schematic Name: d_and, NgSpice Name: d_and
-.model u5 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
-* Schematic Name: d_and, NgSpice Name: d_and
-.model u6 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
-* Schematic Name: d_inverter, NgSpice Name: d_inverter
-.model u2 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* u1 /1 /2 /3 /4 /5 /6 /7 unconnected-_u1-pad8_ /9 /10 /11 /12 /13 /14 /15 unconnected-_u1-pad16_ port
+* u16 /15 net-_u16-pad2_ d_inverter
+* u17 net-_u13-pad2_ net-_u17-pad2_ d_inverter
+* u15 /1 net-_u15-pad2_ d_inverter
+* u14 /15 net-_u14-pad2_ d_inverter
+* u19 net-_u16-pad2_ net-_u17-pad2_ net-_u19-pad3_ d_and
+* u18 net-_u14-pad2_ net-_u15-pad2_ net-_u18-pad3_ d_and
+* u13 /1 net-_u13-pad2_ d_inverter
+* u22 /5 net-_u18-pad3_ net-_u22-pad3_ d_and
+* u23 /6 net-_u19-pad3_ net-_u23-pad3_ d_and
+* u24 /11 net-_u18-pad3_ net-_u24-pad3_ d_and
+* u25 /10 net-_u19-pad3_ net-_u25-pad3_ d_and
+* u29 net-_u22-pad3_ net-_u23-pad3_ /7 d_or
+* u21 /3 net-_u19-pad3_ net-_u21-pad3_ d_and
+* u28 net-_u20-pad3_ net-_u21-pad3_ /4 d_or
+* u20 /2 net-_u18-pad3_ net-_u20-pad3_ d_and
+* u31 net-_u26-pad3_ net-_u27-pad3_ /12 d_or
+* u26 /14 net-_u18-pad3_ net-_u26-pad3_ d_and
+* u27 /13 net-_u19-pad3_ net-_u27-pad3_ d_and
+* u30 net-_u24-pad3_ net-_u25-pad3_ /9 d_or
+a1 /15 net-_u16-pad2_ u16
+a2 net-_u13-pad2_ net-_u17-pad2_ u17
+a3 /1 net-_u15-pad2_ u15
+a4 /15 net-_u14-pad2_ u14
+a5 [net-_u16-pad2_ net-_u17-pad2_ ] net-_u19-pad3_ u19
+a6 [net-_u14-pad2_ net-_u15-pad2_ ] net-_u18-pad3_ u18
+a7 /1 net-_u13-pad2_ u13
+a8 [/5 net-_u18-pad3_ ] net-_u22-pad3_ u22
+a9 [/6 net-_u19-pad3_ ] net-_u23-pad3_ u23
+a10 [/11 net-_u18-pad3_ ] net-_u24-pad3_ u24
+a11 [/10 net-_u19-pad3_ ] net-_u25-pad3_ u25
+a12 [net-_u22-pad3_ net-_u23-pad3_ ] /7 u29
+a13 [/3 net-_u19-pad3_ ] net-_u21-pad3_ u21
+a14 [net-_u20-pad3_ net-_u21-pad3_ ] /4 u28
+a15 [/2 net-_u18-pad3_ ] net-_u20-pad3_ u20
+a16 [net-_u26-pad3_ net-_u27-pad3_ ] /12 u31
+a17 [/14 net-_u18-pad3_ ] net-_u26-pad3_ u26
+a18 [/13 net-_u19-pad3_ ] net-_u27-pad3_ u27
+a19 [net-_u24-pad3_ net-_u25-pad3_ ] /9 u30
+* Schematic Name: d_inverter, Ngspice Name: d_inverter
+.model u16 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, Ngspice Name: d_inverter
+.model u17 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, Ngspice Name: d_inverter
+.model u15 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, Ngspice Name: d_inverter
+.model u14 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, Ngspice Name: d_and
+.model u19 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, Ngspice Name: d_and
+.model u18 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, Ngspice Name: d_inverter
+.model u13 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, Ngspice Name: d_and
+.model u22 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, Ngspice Name: d_and
+.model u23 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, Ngspice Name: d_and
+.model u24 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, Ngspice Name: d_and
+.model u25 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_or, Ngspice Name: d_or
+.model u29 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, Ngspice Name: d_and
+.model u21 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_or, Ngspice Name: d_or
+.model u28 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, Ngspice Name: d_and
+.model u20 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_or, Ngspice Name: d_or
+.model u31 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, Ngspice Name: d_and
+.model u26 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, Ngspice Name: d_and
+.model u27 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_or, Ngspice Name: d_or
+.model u30 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
.tran 0e-00 0e-00 0e-00
* Control Statements
diff --git a/library/SubcircuitLibrary/74HC157/74HC157.kicad_sch b/library/SubcircuitLibrary/74HC157/74HC157.kicad_sch
new file mode 100644
index 000000000..3f0b9b17b
--- /dev/null
+++ b/library/SubcircuitLibrary/74HC157/74HC157.kicad_sch
@@ -0,0 +1,1812 @@
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diff --git a/library/SubcircuitLibrary/74HC157/74HC157.sub b/library/SubcircuitLibrary/74HC157/74HC157.sub
index cebb49853..bcbebdbac 100644
--- a/library/SubcircuitLibrary/74HC157/74HC157.sub
+++ b/library/SubcircuitLibrary/74HC157/74HC157.sub
@@ -1,31 +1,82 @@
* Subcircuit 74HC157
-.subckt 74HC157 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ net-_u1-pad8_ net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad13_ net-_u1-pad14_
-* c:\fossee\esim\library\subcircuitlibrary\74hc157\74hc157.cir
-.include mux.sub
-x1 net-_u1-pad9_ net-_u1-pad1_ net-_u1-pad2_ net-_u3-pad1_ mux
-x2 net-_u1-pad9_ net-_u1-pad3_ net-_u1-pad4_ net-_u4-pad1_ mux
-x3 net-_u1-pad9_ net-_u1-pad5_ net-_u1-pad6_ net-_u5-pad1_ mux
-x4 net-_u1-pad9_ net-_u1-pad7_ net-_u1-pad8_ net-_u6-pad1_ mux
-* u3 net-_u3-pad1_ net-_u2-pad2_ net-_u1-pad11_ d_and
-* u4 net-_u4-pad1_ net-_u2-pad2_ net-_u1-pad12_ d_and
-* u5 net-_u5-pad1_ net-_u2-pad2_ net-_u1-pad13_ d_and
-* u6 net-_u6-pad1_ net-_u2-pad2_ net-_u1-pad14_ d_and
-* u2 net-_u1-pad10_ net-_u2-pad2_ d_inverter
-a1 [net-_u3-pad1_ net-_u2-pad2_ ] net-_u1-pad11_ u3
-a2 [net-_u4-pad1_ net-_u2-pad2_ ] net-_u1-pad12_ u4
-a3 [net-_u5-pad1_ net-_u2-pad2_ ] net-_u1-pad13_ u5
-a4 [net-_u6-pad1_ net-_u2-pad2_ ] net-_u1-pad14_ u6
-a5 net-_u1-pad10_ net-_u2-pad2_ u2
-* Schematic Name: d_and, NgSpice Name: d_and
-.model u3 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
-* Schematic Name: d_and, NgSpice Name: d_and
-.model u4 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
-* Schematic Name: d_and, NgSpice Name: d_and
-.model u5 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
-* Schematic Name: d_and, NgSpice Name: d_and
-.model u6 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
-* Schematic Name: d_inverter, NgSpice Name: d_inverter
-.model u2 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+.subckt 74HC157 /1 /2 /3 /4 /5 /6 /7 unconnected-_u1-pad8_ /9 /10 /11 /12 /13 /14 /15 unconnected-_u1-pad16_
+.title kicad schematic
+* u16 /15 net-_u16-pad2_ d_inverter
+* u17 net-_u13-pad2_ net-_u17-pad2_ d_inverter
+* u15 /1 net-_u15-pad2_ d_inverter
+* u14 /15 net-_u14-pad2_ d_inverter
+* u19 net-_u16-pad2_ net-_u17-pad2_ net-_u19-pad3_ d_and
+* u18 net-_u14-pad2_ net-_u15-pad2_ net-_u18-pad3_ d_and
+* u13 /1 net-_u13-pad2_ d_inverter
+* u22 /5 net-_u18-pad3_ net-_u22-pad3_ d_and
+* u23 /6 net-_u19-pad3_ net-_u23-pad3_ d_and
+* u24 /11 net-_u18-pad3_ net-_u24-pad3_ d_and
+* u25 /10 net-_u19-pad3_ net-_u25-pad3_ d_and
+* u29 net-_u22-pad3_ net-_u23-pad3_ /7 d_or
+* u21 /3 net-_u19-pad3_ net-_u21-pad3_ d_and
+* u28 net-_u20-pad3_ net-_u21-pad3_ /4 d_or
+* u20 /2 net-_u18-pad3_ net-_u20-pad3_ d_and
+* u31 net-_u26-pad3_ net-_u27-pad3_ /12 d_or
+* u26 /14 net-_u18-pad3_ net-_u26-pad3_ d_and
+* u27 /13 net-_u19-pad3_ net-_u27-pad3_ d_and
+* u30 net-_u24-pad3_ net-_u25-pad3_ /9 d_or
+a1 /15 net-_u16-pad2_ u16
+a2 net-_u13-pad2_ net-_u17-pad2_ u17
+a3 /1 net-_u15-pad2_ u15
+a4 /15 net-_u14-pad2_ u14
+a5 [net-_u16-pad2_ net-_u17-pad2_ ] net-_u19-pad3_ u19
+a6 [net-_u14-pad2_ net-_u15-pad2_ ] net-_u18-pad3_ u18
+a7 /1 net-_u13-pad2_ u13
+a8 [/5 net-_u18-pad3_ ] net-_u22-pad3_ u22
+a9 [/6 net-_u19-pad3_ ] net-_u23-pad3_ u23
+a10 [/11 net-_u18-pad3_ ] net-_u24-pad3_ u24
+a11 [/10 net-_u19-pad3_ ] net-_u25-pad3_ u25
+a12 [net-_u22-pad3_ net-_u23-pad3_ ] /7 u29
+a13 [/3 net-_u19-pad3_ ] net-_u21-pad3_ u21
+a14 [net-_u20-pad3_ net-_u21-pad3_ ] /4 u28
+a15 [/2 net-_u18-pad3_ ] net-_u20-pad3_ u20
+a16 [net-_u26-pad3_ net-_u27-pad3_ ] /12 u31
+a17 [/14 net-_u18-pad3_ ] net-_u26-pad3_ u26
+a18 [/13 net-_u19-pad3_ ] net-_u27-pad3_ u27
+a19 [net-_u24-pad3_ net-_u25-pad3_ ] /9 u30
+* Schematic Name: d_inverter, Ngspice Name: d_inverter
+.model u16 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, Ngspice Name: d_inverter
+.model u17 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, Ngspice Name: d_inverter
+.model u15 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, Ngspice Name: d_inverter
+.model u14 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, Ngspice Name: d_and
+.model u19 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, Ngspice Name: d_and
+.model u18 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, Ngspice Name: d_inverter
+.model u13 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, Ngspice Name: d_and
+.model u22 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, Ngspice Name: d_and
+.model u23 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, Ngspice Name: d_and
+.model u24 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, Ngspice Name: d_and
+.model u25 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_or, Ngspice Name: d_or
+.model u29 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, Ngspice Name: d_and
+.model u21 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_or, Ngspice Name: d_or
+.model u28 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, Ngspice Name: d_and
+.model u20 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_or, Ngspice Name: d_or
+.model u31 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, Ngspice Name: d_and
+.model u26 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, Ngspice Name: d_and
+.model u27 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_or, Ngspice Name: d_or
+.model u30 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
* Control Statements
.ends 74HC157
\ No newline at end of file
diff --git a/library/SubcircuitLibrary/74HC157/74HC157_Previous_Values.xml b/library/SubcircuitLibrary/74HC157/74HC157_Previous_Values.xml
index a72a8ef0d..04fa4209b 100644
--- a/library/SubcircuitLibrary/74HC157/74HC157_Previous_Values.xml
+++ b/library/SubcircuitLibrary/74HC157/74HC157_Previous_Values.xml
@@ -1 +1 @@
-d_andd_andd_andd_andd_inverterC:\FOSSEE\eSim\library\SubcircuitLibrary\muxC:\FOSSEE\eSim\library\SubcircuitLibrary\muxC:\FOSSEE\eSim\library\SubcircuitLibrary\muxC:\FOSSEE\eSim\library\SubcircuitLibrary\muxtruefalsefalseHzHz0Volts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or Amperessecsecsec
\ No newline at end of file
+truefalsefalseHzHz0Volts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or Amperessecsecsecd_inverterd_inverterd_inverterd_inverterd_andd_andd_inverterd_andd_andd_andd_andd_ord_andd_ord_andd_ord_andd_andd_or
\ No newline at end of file
diff --git a/library/SubcircuitLibrary/74HC157/_autosave-74HC157.kicad_prl b/library/SubcircuitLibrary/74HC157/_autosave-74HC157.kicad_prl
new file mode 100644
index 000000000..262eb8f77
--- /dev/null
+++ b/library/SubcircuitLibrary/74HC157/_autosave-74HC157.kicad_prl
@@ -0,0 +1,75 @@
+{
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+ "active_layer_preset": "",
+ "auto_track_width": true,
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+ "tracks": 1.0,
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+ "zones": 0.6
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+ "footprints": true,
+ "graphics": true,
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+ "lockedItems": true,
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+ },
+ "meta": {
+ "filename": "_autosave-74HC157.kicad_prl",
+ "version": 3
+ },
+ "project": {
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+ }
+}
diff --git a/library/SubcircuitLibrary/74HC157/_autosave-74HC157.kicad_pro b/library/SubcircuitLibrary/74HC157/_autosave-74HC157.kicad_pro
new file mode 100644
index 000000000..10661d58e
--- /dev/null
+++ b/library/SubcircuitLibrary/74HC157/_autosave-74HC157.kicad_pro
@@ -0,0 +1,298 @@
+{
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+ },
+ "boards": [],
+ "cvpcb": {
+ "equivalence_files": []
+ },
+ "erc": {
+ "erc_exclusions": [],
+ "meta": {
+ "version": 0
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+ "pin_map": [
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+ "bus_label_syntax": "error",
+ "bus_to_bus_conflict": "error",
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+ "different_unit_footprint": "error",
+ "different_unit_net": "error",
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+ "net_not_bus_member": "warning",
+ "no_connect_connected": "warning",
+ "no_connect_dangling": "warning",
+ "pin_not_connected": "error",
+ "pin_not_driven": "error",
+ "pin_to_pin": "warning",
+ "power_pin_not_driven": "error",
+ "similar_labels": "warning",
+ "unannotated": "error",
+ "unit_value_mismatch": "error",
+ "unresolved_variable": "error",
+ "wire_dangling": "error"
+ }
+ },
+ "libraries": {
+ "pinned_footprint_libs": [],
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+ },
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+ "version": 1
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+ "ngspice": {
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diff --git a/library/SubcircuitLibrary/74HC157/_autosave-74HC157.sch b/library/SubcircuitLibrary/74HC157/_autosave-74HC157.sch
new file mode 100644
index 000000000..3bc1851ea
--- /dev/null
+++ b/library/SubcircuitLibrary/74HC157/_autosave-74HC157.sch
@@ -0,0 +1,552 @@
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+F 1 "PORT" H 4225 3650 30 0000 C CNN
+F 2 "" H 4200 3550 60 0000 C CNN
+F 3 "" H 4200 3550 60 0000 C CNN
+ 5 4200 3550
+ 1 0 0 -1
+$EndComp
+$Comp
+L eSim_Miscellaneous:PORT U?
+U 6 1 00000000
+P 4200 4300
+F 0 "U?" H 4225 4500 30 0000 C CNN
+F 1 "PORT" H 4225 4400 30 0000 C CNN
+F 2 "" H 4200 4300 60 0000 C CNN
+F 3 "" H 4200 4300 60 0000 C CNN
+ 6 4200 4300
+ 1 0 0 -1
+$EndComp
+$Comp
+L eSim_Miscellaneous:PORT U?
+U 11 1 00000000
+P 4200 5250
+F 0 "U?" H 4225 5450 30 0000 C CNN
+F 1 "PORT" H 4225 5350 30 0000 C CNN
+F 2 "" H 4200 5250 60 0000 C CNN
+F 3 "" H 4200 5250 60 0000 C CNN
+ 11 4200 5250
+ 1 0 0 -1
+$EndComp
+$Comp
+L eSim_Miscellaneous:PORT U?
+U 10 1 00000000
+P 4200 6000
+F 0 "U?" H 4225 6200 30 0000 C CNN
+F 1 "PORT" H 4225 6100 30 0000 C CNN
+F 2 "" H 4200 6000 60 0000 C CNN
+F 3 "" H 4200 6000 60 0000 C CNN
+ 10 4200 6000
+ 1 0 0 -1
+$EndComp
+$Comp
+L eSim_Miscellaneous:PORT U?
+U 14 1 00000000
+P 4200 6950
+F 0 "U?" H 4225 7150 30 0000 C CNN
+F 1 "PORT" H 4225 7050 30 0000 C CNN
+F 2 "" H 4200 6950 60 0000 C CNN
+F 3 "" H 4200 6950 60 0000 C CNN
+ 14 4200 6950
+ 1 0 0 -1
+$EndComp
+$Comp
+L eSim_Miscellaneous:PORT U?
+U 13 1 00000000
+P 4200 7700
+F 0 "U?" H 4225 7900 30 0000 C CNN
+F 1 "PORT" H 4225 7800 30 0000 C CNN
+F 2 "" H 4200 7700 60 0000 C CNN
+F 3 "" H 4200 7700 60 0000 C CNN
+ 13 4200 7700
+ 1 0 0 -1
+$EndComp
+$Comp
+L eSim_Miscellaneous:PORT U?
+U 15 1 00000000
+P 4200 8450
+F 0 "U?" H 4225 8650 30 0000 C CNN
+F 1 "PORT" H 4225 8550 30 0000 C CNN
+F 2 "" H 4200 8450 60 0000 C CNN
+F 3 "" H 4200 8450 60 0000 C CNN
+ 15 4200 8450
+ 1 0 0 -1
+$EndComp
+$Comp
+L eSim_Miscellaneous:PORT U?
+U 1 1 00000000
+P 4200 8550
+F 0 "U?" H 4225 8750 30 0000 C CNN
+F 1 "PORT" H 4225 8650 30 0000 C CNN
+F 2 "" H 4200 8550 60 0000 C CNN
+F 3 "" H 4200 8550 60 0000 C CNN
+ 1 4200 8550
+ 1 0 0 -1
+$EndComp
+$Comp
+L eSim_Miscellaneous:PORT U?
+U 4 1 00000000
+P 13400 2300
+F 0 "U?" H 13250 2275 30 0000 R CNN
+F 1 "PORT" H 13250 2375 30 0000 R CNN
+F 2 "" H 13400 2300 60 0000 C CNN
+F 3 "" H 13400 2300 60 0000 C CNN
+ 4 13400 2300
+ -1 0 0 1
+$EndComp
+$Comp
+L eSim_Miscellaneous:PORT U?
+U 7 1 00000000
+P 13400 3950
+F 0 "U?" H 13250 3925 30 0000 R CNN
+F 1 "PORT" H 13250 4025 30 0000 R CNN
+F 2 "" H 13400 3950 60 0000 C CNN
+F 3 "" H 13400 3950 60 0000 C CNN
+ 7 13400 3950
+ -1 0 0 1
+$EndComp
+$Comp
+L eSim_Miscellaneous:PORT U?
+U 9 1 00000000
+P 13400 5650
+F 0 "U?" H 13250 5625 30 0000 R CNN
+F 1 "PORT" H 13250 5725 30 0000 R CNN
+F 2 "" H 13400 5650 60 0000 C CNN
+F 3 "" H 13400 5650 60 0000 C CNN
+ 9 13400 5650
+ -1 0 0 1
+$EndComp
+$Comp
+L eSim_Miscellaneous:PORT U?
+U 12 1 00000000
+P 13400 7350
+F 0 "U?" H 13250 7325 30 0000 R CNN
+F 1 "PORT" H 13250 7425 30 0000 R CNN
+F 2 "" H 13400 7350 60 0000 C CNN
+F 3 "" H 13400 7350 60 0000 C CNN
+ 12 13400 7350
+ -1 0 0 1
+$EndComp
+$Comp
+L eSim_Miscellaneous:PORT U?
+U 8 1 00000000
+P 13400 8300
+F 0 "U?" H 13250 8275 30 0000 R CNN
+F 1 "PORT" H 13250 8375 30 0000 R CNN
+F 2 "" H 13400 8300 60 0000 C CNN
+F 3 "" H 13400 8300 60 0000 C CNN
+ 8 13400 8300
+ -1 0 0 1
+$EndComp
+$Comp
+L eSim_Miscellaneous:PORT U?
+U 16 1 00000000
+P 13400 8500
+F 0 "U?" H 13250 8475 30 0000 R CNN
+F 1 "PORT" H 13250 8575 30 0000 R CNN
+F 2 "" H 13400 8500 60 0000 C CNN
+F 3 "" H 13400 8500 60 0000 C CNN
+ 16 13400 8500
+ -1 0 0 1
+$EndComp
+$Comp
+L eSim_Digital:d_inverter U13
+U 1 1 00000000
+P 6250 9100
+F 0 "U13" H 6250 9350 60 0000 C CNN
+F 1 "d_inverter" H 6250 9200 60 0000 C CNN
+F 2 "" H 6300 9050 60 0000 C CNN
+F 3 "" H 6300 9050 60 0000 C CNN
+ 1 6250 9100
+ 1 0 0 -1
+$EndComp
+$Comp
+L eSim_Digital:d_inverter U14
+U 1 1 00000000
+P 7300 8450
+F 0 "U14" H 7300 8700 60 0000 C CNN
+F 1 "d_inverter" H 7300 8550 60 0000 C CNN
+F 2 "" H 7350 8400 60 0000 C CNN
+F 3 "" H 7350 8400 60 0000 C CNN
+ 1 7300 8450
+ 1 0 0 -1
+$EndComp
+$Comp
+L eSim_Digital:d_inverter U15
+U 1 1 00000000
+P 7300 8550
+F 0 "U15" H 7300 8800 60 0000 C CNN
+F 1 "d_inverter" H 7300 8650 60 0000 C CNN
+F 2 "" H 7350 8500 60 0000 C CNN
+F 3 "" H 7350 8500 60 0000 C CNN
+ 1 7300 8550
+ 1 0 0 -1
+$EndComp
+$Comp
+L eSim_Digital:d_inverter U16
+U 1 1 00000000
+P 7300 9000
+F 0 "U16" H 7300 9250 60 0000 C CNN
+F 1 "d_inverter" H 7300 9100 60 0000 C CNN
+F 2 "" H 7350 8950 60 0000 C CNN
+F 3 "" H 7350 8950 60 0000 C CNN
+ 1 7300 9000
+ 1 0 0 -1
+$EndComp
+$Comp
+L eSim_Digital:d_inverter U17
+U 1 1 00000000
+P 7300 9100
+F 0 "U17" H 7300 9350 60 0000 C CNN
+F 1 "d_inverter" H 7300 9200 60 0000 C CNN
+F 2 "" H 7350 9050 60 0000 C CNN
+F 3 "" H 7350 9050 60 0000 C CNN
+ 1 7300 9100
+ 1 0 0 -1
+$EndComp
+$Comp
+L eSim_Digital:d_and U18
+U 1 1 00000000
+P 8050 8550
+F 0 "U18" H 8050 8900 60 0000 C CNN
+F 1 "d_and" H 8050 8750 60 0000 C CNN
+F 2 "" H 8050 8550 60 0000 C CNN
+F 3 "" H 8050 8550 60 0000 C CNN
+ 1 8050 8550
+ 1 0 0 -1
+$EndComp
+$Comp
+L eSim_Digital:d_and U19
+U 1 1 00000000
+P 8050 9100
+F 0 "U19" H 8050 9450 60 0000 C CNN
+F 1 "d_and" H 8050 9300 60 0000 C CNN
+F 2 "" H 8050 9100 60 0000 C CNN
+F 3 "" H 8050 9100 60 0000 C CNN
+ 1 8050 9100
+ 1 0 0 -1
+$EndComp
+$Comp
+L eSim_Digital:d_and U20
+U 1 1 00000000
+P 10850 2000
+F 0 "U20" H 10850 2350 60 0000 C CNN
+F 1 "d_and" H 10850 2200 60 0000 C CNN
+F 2 "" H 10850 2000 60 0000 C CNN
+F 3 "" H 10850 2000 60 0000 C CNN
+ 1 10850 2000
+ 1 0 0 -1
+$EndComp
+$Comp
+L eSim_Digital:d_and U21
+U 1 1 00000000
+P 10850 2750
+F 0 "U21" H 10850 3100 60 0000 C CNN
+F 1 "d_and" H 10850 2950 60 0000 C CNN
+F 2 "" H 10850 2750 60 0000 C CNN
+F 3 "" H 10850 2750 60 0000 C CNN
+ 1 10850 2750
+ 1 0 0 -1
+$EndComp
+$Comp
+L eSim_Digital:d_and U22
+U 1 1 00000000
+P 10850 3650
+F 0 "U22" H 10850 4000 60 0000 C CNN
+F 1 "d_and" H 10850 3850 60 0000 C CNN
+F 2 "" H 10850 3650 60 0000 C CNN
+F 3 "" H 10850 3650 60 0000 C CNN
+ 1 10850 3650
+ 1 0 0 -1
+$EndComp
+$Comp
+L eSim_Digital:d_and U23
+U 1 1 00000000
+P 10850 4400
+F 0 "U23" H 10850 4750 60 0000 C CNN
+F 1 "d_and" H 10850 4600 60 0000 C CNN
+F 2 "" H 10850 4400 60 0000 C CNN
+F 3 "" H 10850 4400 60 0000 C CNN
+ 1 10850 4400
+ 1 0 0 -1
+$EndComp
+$Comp
+L eSim_Digital:d_and U24
+U 1 1 00000000
+P 10850 5350
+F 0 "U24" H 10850 5700 60 0000 C CNN
+F 1 "d_and" H 10850 5550 60 0000 C CNN
+F 2 "" H 10850 5350 60 0000 C CNN
+F 3 "" H 10850 5350 60 0000 C CNN
+ 1 10850 5350
+ 1 0 0 -1
+$EndComp
+$Comp
+L eSim_Digital:d_and U25
+U 1 1 00000000
+P 10850 6100
+F 0 "U25" H 10850 6450 60 0000 C CNN
+F 1 "d_and" H 10850 6300 60 0000 C CNN
+F 2 "" H 10850 6100 60 0000 C CNN
+F 3 "" H 10850 6100 60 0000 C CNN
+ 1 10850 6100
+ 1 0 0 -1
+$EndComp
+$Comp
+L eSim_Digital:d_and U26
+U 1 1 00000000
+P 10850 7050
+F 0 "U26" H 10850 7400 60 0000 C CNN
+F 1 "d_and" H 10850 7250 60 0000 C CNN
+F 2 "" H 10850 7050 60 0000 C CNN
+F 3 "" H 10850 7050 60 0000 C CNN
+ 1 10850 7050
+ 1 0 0 -1
+$EndComp
+$Comp
+L eSim_Digital:d_and U27
+U 1 1 00000000
+P 10850 7800
+F 0 "U27" H 10850 8150 60 0000 C CNN
+F 1 "d_and" H 10850 8000 60 0000 C CNN
+F 2 "" H 10850 7800 60 0000 C CNN
+F 3 "" H 10850 7800 60 0000 C CNN
+ 1 10850 7800
+ 1 0 0 -1
+$EndComp
+$Comp
+L eSim_Digital:d_or U28
+U 1 1 00000000
+P 12050 2350
+F 0 "U28" H 12050 2700 60 0000 C CNN
+F 1 "d_or" H 12050 2550 60 0000 C CNN
+F 2 "" H 12050 2350 60 0000 C CNN
+F 3 "" H 12050 2350 60 0000 C CNN
+ 1 12050 2350
+ 1 0 0 -1
+$EndComp
+$Comp
+L eSim_Digital:d_or U29
+U 1 1 00000000
+P 12050 4000
+F 0 "U29" H 12050 4350 60 0000 C CNN
+F 1 "d_or" H 12050 4200 60 0000 C CNN
+F 2 "" H 12050 4000 60 0000 C CNN
+F 3 "" H 12050 4000 60 0000 C CNN
+ 1 12050 4000
+ 1 0 0 -1
+$EndComp
+$Comp
+L eSim_Digital:d_or U30
+U 1 1 00000000
+P 12050 5700
+F 0 "U30" H 12050 6050 60 0000 C CNN
+F 1 "d_or" H 12050 5900 60 0000 C CNN
+F 2 "" H 12050 5700 60 0000 C CNN
+F 3 "" H 12050 5700 60 0000 C CNN
+ 1 12050 5700
+ 1 0 0 -1
+$EndComp
+$Comp
+L eSim_Digital:d_or U31
+U 1 1 00000000
+P 12050 7400
+F 0 "U31" H 12050 7750 60 0000 C CNN
+F 1 "d_or" H 12050 7600 60 0000 C CNN
+F 2 "" H 12050 7400 60 0000 C CNN
+F 3 "" H 12050 7400 60 0000 C CNN
+ 1 12050 7400
+ 1 0 0 -1
+$EndComp
+$EndSCHEMATC
diff --git a/library/SubcircuitLibrary/74LS173/74LS173.cir b/library/SubcircuitLibrary/74LS173/74LS173.cir
new file mode 100644
index 000000000..48b197fc4
--- /dev/null
+++ b/library/SubcircuitLibrary/74LS173/74LS173.cir
@@ -0,0 +1,44 @@
+.title KiCad schematic
+U26 Net-_U23-Pad1_ Net-_U26-Pad2_ d_inverter
+U22 Net-_U17-Pad3_ Net-_U18-Pad3_ Net-_U22-Pad3_ d_or
+U18 Net-_U1-Pad11_ Net-_U10-Pad1_ Net-_U18-Pad3_ d_and
+U17 Net-_U17-Pad1_ Net-_U10-Pad2_ Net-_U17-Pad3_ d_and
+U16 Net-_U1-Pad12_ Net-_U10-Pad1_ Net-_U16-Pad3_ d_and
+U25 Net-_U23-Pad1_ Net-_U25-Pad2_ d_inverter
+U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ Net-_U1-Pad6_ Net-_U1-Pad7_ unconnected-_U1-Pad8_ Net-_U1-Pad9_ Net-_U1-Pad10_ Net-_U1-Pad11_ Net-_U1-Pad12_ Net-_U1-Pad13_ Net-_U1-Pad14_ Net-_U1-Pad15_ unconnected-_U1-Pad16_ PORT
+U9 Net-_U1-Pad15_ Net-_U27-Pad1_ d_inverter
+U7 Net-_U1-Pad7_ Net-_U23-Pad1_ d_inverter
+U31 Net-_U19-Pad3_ Net-_U23-Pad2_ unconnected-_U31-Pad3_ Net-_U27-Pad2_ Net-_U11-Pad1_ Net-_U31-Pad6_ d_dff
+U28 Net-_U27-Pad1_ Net-_U28-Pad2_ d_inverter
+U15 Net-_U15-Pad1_ Net-_U10-Pad2_ Net-_U15-Pad3_ d_and
+U14 Net-_U1-Pad13_ Net-_U10-Pad1_ Net-_U14-Pad3_ d_and
+U24 Net-_U23-Pad1_ Net-_U24-Pad2_ d_inverter
+U20 Net-_U13-Pad3_ Net-_U14-Pad3_ Net-_U20-Pad3_ d_or
+U32 Net-_U20-Pad3_ Net-_U24-Pad2_ unconnected-_U32-Pad3_ Net-_U28-Pad2_ Net-_U13-Pad1_ Net-_U32-Pad6_ d_dff
+U13 Net-_U13-Pad1_ Net-_U10-Pad2_ Net-_U13-Pad3_ d_and
+U33 Net-_U21-Pad3_ Net-_U25-Pad2_ unconnected-_U33-Pad3_ Net-_U29-Pad2_ Net-_U15-Pad1_ Net-_U33-Pad6_ d_dff
+U29 Net-_U27-Pad1_ Net-_U29-Pad2_ d_inverter
+U21 Net-_U15-Pad3_ Net-_U16-Pad3_ Net-_U21-Pad3_ d_or
+U5 Net-_U1-Pad2_ Net-_U5-Pad2_ d_inverter
+U8 Net-_U4-Pad2_ Net-_U5-Pad2_ Net-_U39-Pad2_ d_and
+U4 Net-_U1-Pad1_ Net-_U4-Pad2_ d_inverter
+U3 Net-_U1-Pad10_ Net-_U3-Pad2_ d_inverter
+U2 Net-_U1-Pad9_ Net-_U2-Pad2_ d_inverter
+U6 Net-_U2-Pad2_ Net-_U3-Pad2_ Net-_U10-Pad1_ d_and
+U10 Net-_U10-Pad1_ Net-_U10-Pad2_ d_inverter
+U11 Net-_U11-Pad1_ Net-_U10-Pad2_ Net-_U11-Pad3_ d_and
+U12 Net-_U1-Pad14_ Net-_U10-Pad1_ Net-_U12-Pad3_ d_and
+U27 Net-_U27-Pad1_ Net-_U27-Pad2_ d_inverter
+U19 Net-_U11-Pad3_ Net-_U12-Pad3_ Net-_U19-Pad3_ d_or
+U23 Net-_U23-Pad1_ Net-_U23-Pad2_ d_inverter
+U39 Net-_U36-Pad2_ Net-_U39-Pad2_ Net-_U1-Pad4_ d_tristate
+U36 Net-_U32-Pad6_ Net-_U36-Pad2_ d_inverter
+U40 Net-_U35-Pad2_ Net-_U39-Pad2_ Net-_U1-Pad3_ d_tristate
+U35 Net-_U31-Pad6_ Net-_U35-Pad2_ d_inverter
+U37 Net-_U33-Pad6_ Net-_U37-Pad2_ d_inverter
+U41 Net-_U37-Pad2_ Net-_U39-Pad2_ Net-_U1-Pad5_ d_tristate
+U42 Net-_U38-Pad2_ Net-_U39-Pad2_ Net-_U1-Pad6_ d_tristate
+U38 Net-_U34-Pad6_ Net-_U38-Pad2_ d_inverter
+U30 Net-_U27-Pad1_ Net-_U30-Pad2_ d_inverter
+U34 Net-_U22-Pad3_ Net-_U26-Pad2_ unconnected-_U34-Pad3_ Net-_U30-Pad2_ Net-_U17-Pad1_ Net-_U34-Pad6_ d_dff
+.end
diff --git a/library/SubcircuitLibrary/74LS173/74LS173.cir.out b/library/SubcircuitLibrary/74LS173/74LS173.cir.out
new file mode 100644
index 000000000..1552f7028
--- /dev/null
+++ b/library/SubcircuitLibrary/74LS173/74LS173.cir.out
@@ -0,0 +1,176 @@
+.title kicad schematic
+
+* u26 net-_u23-pad1_ net-_u26-pad2_ d_inverter
+* u22 net-_u17-pad3_ net-_u18-pad3_ net-_u22-pad3_ d_or
+* u18 net-_u1-pad11_ net-_u10-pad1_ net-_u18-pad3_ d_and
+* u17 net-_u17-pad1_ net-_u10-pad2_ net-_u17-pad3_ d_and
+* u16 net-_u1-pad12_ net-_u10-pad1_ net-_u16-pad3_ d_and
+* u25 net-_u23-pad1_ net-_u25-pad2_ d_inverter
+* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ unconnected-_u1-pad8_ net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad13_ net-_u1-pad14_ net-_u1-pad15_ unconnected-_u1-pad16_ port
+* u9 net-_u1-pad15_ net-_u27-pad1_ d_inverter
+* u7 net-_u1-pad7_ net-_u23-pad1_ d_inverter
+* u31 net-_u19-pad3_ net-_u23-pad2_ unconnected-_u31-pad3_ net-_u27-pad2_ net-_u11-pad1_ net-_u31-pad6_ d_dff
+* u28 net-_u27-pad1_ net-_u28-pad2_ d_inverter
+* u15 net-_u15-pad1_ net-_u10-pad2_ net-_u15-pad3_ d_and
+* u14 net-_u1-pad13_ net-_u10-pad1_ net-_u14-pad3_ d_and
+* u24 net-_u23-pad1_ net-_u24-pad2_ d_inverter
+* u20 net-_u13-pad3_ net-_u14-pad3_ net-_u20-pad3_ d_or
+* u32 net-_u20-pad3_ net-_u24-pad2_ unconnected-_u32-pad3_ net-_u28-pad2_ net-_u13-pad1_ net-_u32-pad6_ d_dff
+* u13 net-_u13-pad1_ net-_u10-pad2_ net-_u13-pad3_ d_and
+* u33 net-_u21-pad3_ net-_u25-pad2_ unconnected-_u33-pad3_ net-_u29-pad2_ net-_u15-pad1_ net-_u33-pad6_ d_dff
+* u29 net-_u27-pad1_ net-_u29-pad2_ d_inverter
+* u21 net-_u15-pad3_ net-_u16-pad3_ net-_u21-pad3_ d_or
+* u5 net-_u1-pad2_ net-_u5-pad2_ d_inverter
+* u8 net-_u4-pad2_ net-_u5-pad2_ net-_u39-pad2_ d_and
+* u4 net-_u1-pad1_ net-_u4-pad2_ d_inverter
+* u3 net-_u1-pad10_ net-_u3-pad2_ d_inverter
+* u2 net-_u1-pad9_ net-_u2-pad2_ d_inverter
+* u6 net-_u2-pad2_ net-_u3-pad2_ net-_u10-pad1_ d_and
+* u10 net-_u10-pad1_ net-_u10-pad2_ d_inverter
+* u11 net-_u11-pad1_ net-_u10-pad2_ net-_u11-pad3_ d_and
+* u12 net-_u1-pad14_ net-_u10-pad1_ net-_u12-pad3_ d_and
+* u27 net-_u27-pad1_ net-_u27-pad2_ d_inverter
+* u19 net-_u11-pad3_ net-_u12-pad3_ net-_u19-pad3_ d_or
+* u23 net-_u23-pad1_ net-_u23-pad2_ d_inverter
+* u39 net-_u36-pad2_ net-_u39-pad2_ net-_u1-pad4_ d_tristate
+* u36 net-_u32-pad6_ net-_u36-pad2_ d_inverter
+* u40 net-_u35-pad2_ net-_u39-pad2_ net-_u1-pad3_ d_tristate
+* u35 net-_u31-pad6_ net-_u35-pad2_ d_inverter
+* u37 net-_u33-pad6_ net-_u37-pad2_ d_inverter
+* u41 net-_u37-pad2_ net-_u39-pad2_ net-_u1-pad5_ d_tristate
+* u42 net-_u38-pad2_ net-_u39-pad2_ net-_u1-pad6_ d_tristate
+* u38 net-_u34-pad6_ net-_u38-pad2_ d_inverter
+* u30 net-_u27-pad1_ net-_u30-pad2_ d_inverter
+* u34 net-_u22-pad3_ net-_u26-pad2_ unconnected-_u34-pad3_ net-_u30-pad2_ net-_u17-pad1_ net-_u34-pad6_ d_dff
+a1 net-_u23-pad1_ net-_u26-pad2_ u26
+a2 [net-_u17-pad3_ net-_u18-pad3_ ] net-_u22-pad3_ u22
+a3 [net-_u1-pad11_ net-_u10-pad1_ ] net-_u18-pad3_ u18
+a4 [net-_u17-pad1_ net-_u10-pad2_ ] net-_u17-pad3_ u17
+a5 [net-_u1-pad12_ net-_u10-pad1_ ] net-_u16-pad3_ u16
+a6 net-_u23-pad1_ net-_u25-pad2_ u25
+a7 net-_u1-pad15_ net-_u27-pad1_ u9
+a8 net-_u1-pad7_ net-_u23-pad1_ u7
+a9 net-_u19-pad3_ net-_u23-pad2_ unconnected-_u31-pad3_ net-_u27-pad2_ net-_u11-pad1_ net-_u31-pad6_ u31
+a10 net-_u27-pad1_ net-_u28-pad2_ u28
+a11 [net-_u15-pad1_ net-_u10-pad2_ ] net-_u15-pad3_ u15
+a12 [net-_u1-pad13_ net-_u10-pad1_ ] net-_u14-pad3_ u14
+a13 net-_u23-pad1_ net-_u24-pad2_ u24
+a14 [net-_u13-pad3_ net-_u14-pad3_ ] net-_u20-pad3_ u20
+a15 net-_u20-pad3_ net-_u24-pad2_ unconnected-_u32-pad3_ net-_u28-pad2_ net-_u13-pad1_ net-_u32-pad6_ u32
+a16 [net-_u13-pad1_ net-_u10-pad2_ ] net-_u13-pad3_ u13
+a17 net-_u21-pad3_ net-_u25-pad2_ unconnected-_u33-pad3_ net-_u29-pad2_ net-_u15-pad1_ net-_u33-pad6_ u33
+a18 net-_u27-pad1_ net-_u29-pad2_ u29
+a19 [net-_u15-pad3_ net-_u16-pad3_ ] net-_u21-pad3_ u21
+a20 net-_u1-pad2_ net-_u5-pad2_ u5
+a21 [net-_u4-pad2_ net-_u5-pad2_ ] net-_u39-pad2_ u8
+a22 net-_u1-pad1_ net-_u4-pad2_ u4
+a23 net-_u1-pad10_ net-_u3-pad2_ u3
+a24 net-_u1-pad9_ net-_u2-pad2_ u2
+a25 [net-_u2-pad2_ net-_u3-pad2_ ] net-_u10-pad1_ u6
+a26 net-_u10-pad1_ net-_u10-pad2_ u10
+a27 [net-_u11-pad1_ net-_u10-pad2_ ] net-_u11-pad3_ u11
+a28 [net-_u1-pad14_ net-_u10-pad1_ ] net-_u12-pad3_ u12
+a29 net-_u27-pad1_ net-_u27-pad2_ u27
+a30 [net-_u11-pad3_ net-_u12-pad3_ ] net-_u19-pad3_ u19
+a31 net-_u23-pad1_ net-_u23-pad2_ u23
+a32 net-_u36-pad2_ net-_u39-pad2_ net-_u1-pad4_ u39
+a33 net-_u32-pad6_ net-_u36-pad2_ u36
+a34 net-_u35-pad2_ net-_u39-pad2_ net-_u1-pad3_ u40
+a35 net-_u31-pad6_ net-_u35-pad2_ u35
+a36 net-_u33-pad6_ net-_u37-pad2_ u37
+a37 net-_u37-pad2_ net-_u39-pad2_ net-_u1-pad5_ u41
+a38 net-_u38-pad2_ net-_u39-pad2_ net-_u1-pad6_ u42
+a39 net-_u34-pad6_ net-_u38-pad2_ u38
+a40 net-_u27-pad1_ net-_u30-pad2_ u30
+a41 net-_u22-pad3_ net-_u26-pad2_ unconnected-_u34-pad3_ net-_u30-pad2_ net-_u17-pad1_ net-_u34-pad6_ u34
+* Schematic Name: d_inverter, Ngspice Name: d_inverter
+.model u26 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_or, Ngspice Name: d_or
+.model u22 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, Ngspice Name: d_and
+.model u18 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, Ngspice Name: d_and
+.model u17 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, Ngspice Name: d_and
+.model u16 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, Ngspice Name: d_inverter
+.model u25 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, Ngspice Name: d_inverter
+.model u9 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, Ngspice Name: d_inverter
+.model u7 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_dff, Ngspice Name: d_dff
+.model u31 d_dff(clk_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0 ic=0 data_load=1.0e-12 clk_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 )
+* Schematic Name: d_inverter, Ngspice Name: d_inverter
+.model u28 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, Ngspice Name: d_and
+.model u15 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, Ngspice Name: d_and
+.model u14 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, Ngspice Name: d_inverter
+.model u24 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_or, Ngspice Name: d_or
+.model u20 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_dff, Ngspice Name: d_dff
+.model u32 d_dff(clk_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0 ic=0 data_load=1.0e-12 clk_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 )
+* Schematic Name: d_and, Ngspice Name: d_and
+.model u13 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_dff, Ngspice Name: d_dff
+.model u33 d_dff(clk_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0 ic=0 data_load=1.0e-12 clk_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 )
+* Schematic Name: d_inverter, Ngspice Name: d_inverter
+.model u29 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_or, Ngspice Name: d_or
+.model u21 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, Ngspice Name: d_inverter
+.model u5 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, Ngspice Name: d_and
+.model u8 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, Ngspice Name: d_inverter
+.model u4 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, Ngspice Name: d_inverter
+.model u3 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, Ngspice Name: d_inverter
+.model u2 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, Ngspice Name: d_and
+.model u6 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, Ngspice Name: d_inverter
+.model u10 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, Ngspice Name: d_and
+.model u11 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, Ngspice Name: d_and
+.model u12 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, Ngspice Name: d_inverter
+.model u27 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_or, Ngspice Name: d_or
+.model u19 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, Ngspice Name: d_inverter
+.model u23 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_tristate, Ngspice Name: d_tristate
+.model u39 d_tristate(delay=1.0e-9 input_load=1.0e-12 enable_load=1.0e-12 )
+* Schematic Name: d_inverter, Ngspice Name: d_inverter
+.model u36 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_tristate, Ngspice Name: d_tristate
+.model u40 d_tristate(delay=1.0e-9 input_load=1.0e-12 enable_load=1.0e-12 )
+* Schematic Name: d_inverter, Ngspice Name: d_inverter
+.model u35 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, Ngspice Name: d_inverter
+.model u37 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_tristate, Ngspice Name: d_tristate
+.model u41 d_tristate(delay=1.0e-9 input_load=1.0e-12 enable_load=1.0e-12 )
+* Schematic Name: d_tristate, Ngspice Name: d_tristate
+.model u42 d_tristate(delay=1.0e-9 input_load=1.0e-12 enable_load=1.0e-12 )
+* Schematic Name: d_inverter, Ngspice Name: d_inverter
+.model u38 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, Ngspice Name: d_inverter
+.model u30 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_dff, Ngspice Name: d_dff
+.model u34 d_dff(clk_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0 ic=0 data_load=1.0e-12 clk_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 )
+.tran 0e-00 0e-00 0e-00
+
+* Control Statements
+.control
+run
+print allv > plot_data_v.txt
+print alli > plot_data_i.txt
+.endc
+.end
diff --git a/library/SubcircuitLibrary/74LS173/74LS173.kicad_sch b/library/SubcircuitLibrary/74LS173/74LS173.kicad_sch
new file mode 100644
index 000000000..28c9e2a54
--- /dev/null
+++ b/library/SubcircuitLibrary/74LS173/74LS173.kicad_sch
@@ -0,0 +1,2694 @@
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+ (reference "U1") (unit 13) (value "PORT") (footprint "")
+ )
+ (path "/c7a39c57-2c88-4d39-b821-7f021d6e1c15"
+ (reference "U1") (unit 14) (value "PORT") (footprint "")
+ )
+ (path "/4742a841-0f12-4e19-a580-f51c5e40b968"
+ (reference "U1") (unit 15) (value "PORT") (footprint "")
+ )
+ (path "/1f932b8c-45a6-4d9f-beaa-52b9a60db991"
+ (reference "U1") (unit 16) (value "PORT") (footprint "")
+ )
+ (path "/f1b9ef47-b176-46ce-bcaa-d7d6eceb44e0"
+ (reference "U2") (unit 1) (value "d_inverter") (footprint "")
+ )
+ (path "/b9a6eee6-2e52-4daf-a2d2-676207a86cfb"
+ (reference "U3") (unit 1) (value "d_inverter") (footprint "")
+ )
+ (path "/d1dfc054-cb02-4325-82c3-8d4530222963"
+ (reference "U4") (unit 1) (value "d_inverter") (footprint "")
+ )
+ (path "/f19f10d3-8f64-4751-859a-b24740ec79e8"
+ (reference "U5") (unit 1) (value "d_inverter") (footprint "")
+ )
+ (path "/caaa75b0-3d7a-43e6-9f21-2fd8be03ea25"
+ (reference "U6") (unit 1) (value "d_and") (footprint "")
+ )
+ (path "/68e6b763-0b81-4f6e-9ae5-ad8776480d42"
+ (reference "U7") (unit 1) (value "d_inverter") (footprint "")
+ )
+ (path "/217b0d92-82a3-4f73-a413-5fd51e9f225d"
+ (reference "U8") (unit 1) (value "d_and") (footprint "")
+ )
+ (path "/85384d06-cb9c-4ce0-a40c-b78845ab970e"
+ (reference "U9") (unit 1) (value "d_inverter") (footprint "")
+ )
+ (path "/7a052a0f-43ab-4400-954f-55a2e965456e"
+ (reference "U10") (unit 1) (value "d_inverter") (footprint "")
+ )
+ (path "/c53cf343-baaa-4e5f-b6c3-766bdb99da4e"
+ (reference "U11") (unit 1) (value "d_and") (footprint "")
+ )
+ (path "/4c250ddd-8b9e-46f7-b82e-2ee82dc69ef0"
+ (reference "U12") (unit 1) (value "d_and") (footprint "")
+ )
+ (path "/e4f1c46b-d2fb-4842-ab7e-0bbec5406f57"
+ (reference "U13") (unit 1) (value "d_and") (footprint "")
+ )
+ (path "/e1f11a9a-bf66-4558-a3e2-016f0c417e18"
+ (reference "U14") (unit 1) (value "d_and") (footprint "")
+ )
+ (path "/3320d1b6-21e6-4705-9558-f525308c2cfc"
+ (reference "U15") (unit 1) (value "d_and") (footprint "")
+ )
+ (path "/56f0398a-ccc6-46db-84c1-1403855d860c"
+ (reference "U16") (unit 1) (value "d_and") (footprint "")
+ )
+ (path "/641768ab-9085-412a-ad50-f955f602df98"
+ (reference "U17") (unit 1) (value "d_and") (footprint "")
+ )
+ (path "/bda12229-daaf-4b78-8ff8-920addedc33a"
+ (reference "U18") (unit 1) (value "d_and") (footprint "")
+ )
+ (path "/ff97f45b-4fc6-443c-9416-53ee84fbc54a"
+ (reference "U19") (unit 1) (value "d_or") (footprint "")
+ )
+ (path "/a3b0e5da-9f19-4e7b-ab18-118e4d0661a2"
+ (reference "U20") (unit 1) (value "d_or") (footprint "")
+ )
+ (path "/43e4fdbe-6256-4783-94cb-2f194972adf9"
+ (reference "U21") (unit 1) (value "d_or") (footprint "")
+ )
+ (path "/705036dc-3b72-42c7-9bb7-58710f52729a"
+ (reference "U22") (unit 1) (value "d_or") (footprint "")
+ )
+ (path "/fdd1ee19-29b5-4215-a11f-aa19461c0a22"
+ (reference "U23") (unit 1) (value "d_inverter") (footprint "")
+ )
+ (path "/90e8b774-bd58-4543-a13f-1645f2dbb32b"
+ (reference "U24") (unit 1) (value "d_inverter") (footprint "")
+ )
+ (path "/8717c7a1-2152-4110-8c32-ce003679851f"
+ (reference "U25") (unit 1) (value "d_inverter") (footprint "")
+ )
+ (path "/16a9de2d-b580-4e43-9c76-4335c55b873b"
+ (reference "U26") (unit 1) (value "d_inverter") (footprint "")
+ )
+ (path "/43c88a7e-9063-4b74-8c5c-89787f49723c"
+ (reference "U27") (unit 1) (value "d_inverter") (footprint "")
+ )
+ (path "/b3ff4268-dc59-48c8-aad1-1e8e3c03ec79"
+ (reference "U28") (unit 1) (value "d_inverter") (footprint "")
+ )
+ (path "/14c46af8-be8f-4eb2-bef1-beeab041da1a"
+ (reference "U29") (unit 1) (value "d_inverter") (footprint "")
+ )
+ (path "/b1f0aaf1-cb1b-4a2f-919a-5187c0493f09"
+ (reference "U30") (unit 1) (value "d_inverter") (footprint "")
+ )
+ (path "/c98b45a8-ee96-4d9c-9b09-918841797fc3"
+ (reference "U31") (unit 1) (value "d_dff") (footprint "")
+ )
+ (path "/6970ac0e-2da3-4606-8eac-5e3ca70bb43e"
+ (reference "U32") (unit 1) (value "d_dff") (footprint "")
+ )
+ (path "/5746bb11-3ab1-4776-9745-3a462918a57a"
+ (reference "U33") (unit 1) (value "d_dff") (footprint "")
+ )
+ (path "/280072d1-9fa3-4944-b61a-84dc384558db"
+ (reference "U34") (unit 1) (value "d_dff") (footprint "")
+ )
+ (path "/732fa9d4-0a48-4520-a78a-28e21fb721ae"
+ (reference "U35") (unit 1) (value "d_inverter") (footprint "")
+ )
+ (path "/4a6602e6-8401-4f05-9bc1-77d16428c425"
+ (reference "U36") (unit 1) (value "d_inverter") (footprint "")
+ )
+ (path "/35390633-f81f-40f8-96ef-1e2694be8e47"
+ (reference "U37") (unit 1) (value "d_inverter") (footprint "")
+ )
+ (path "/475465e7-750f-46fa-bb72-7592286875f4"
+ (reference "U38") (unit 1) (value "d_inverter") (footprint "")
+ )
+ (path "/8a1332e6-3da0-4c44-ab86-7c7e04d26e21"
+ (reference "U39") (unit 1) (value "d_tristate") (footprint "")
+ )
+ (path "/36ad6de5-6528-4106-b426-01811900ce7f"
+ (reference "U40") (unit 1) (value "d_tristate") (footprint "")
+ )
+ (path "/5942ba6b-94d0-4ad2-b23d-fe5c3d9afcb8"
+ (reference "U41") (unit 1) (value "d_tristate") (footprint "")
+ )
+ (path "/9da50722-1b39-4f62-b10b-610dbdfef6ca"
+ (reference "U42") (unit 1) (value "d_tristate") (footprint "")
+ )
+ )
+)
diff --git a/library/SubcircuitLibrary/74LS173/74LS173.sub b/library/SubcircuitLibrary/74LS173/74LS173.sub
new file mode 100644
index 000000000..8e506f3f8
--- /dev/null
+++ b/library/SubcircuitLibrary/74LS173/74LS173.sub
@@ -0,0 +1,170 @@
+* Subcircuit 74LS173
+.subckt 74LS173 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ unconnected-_u1-pad8_ net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad13_ net-_u1-pad14_ net-_u1-pad15_ unconnected-_u1-pad16_
+.title kicad schematic
+* u26 net-_u23-pad1_ net-_u26-pad2_ d_inverter
+* u22 net-_u17-pad3_ net-_u18-pad3_ net-_u22-pad3_ d_or
+* u18 net-_u1-pad11_ net-_u10-pad1_ net-_u18-pad3_ d_and
+* u17 net-_u17-pad1_ net-_u10-pad2_ net-_u17-pad3_ d_and
+* u16 net-_u1-pad12_ net-_u10-pad1_ net-_u16-pad3_ d_and
+* u25 net-_u23-pad1_ net-_u25-pad2_ d_inverter
+* u9 net-_u1-pad15_ net-_u27-pad1_ d_inverter
+* u7 net-_u1-pad7_ net-_u23-pad1_ d_inverter
+* u31 net-_u19-pad3_ net-_u23-pad2_ unconnected-_u31-pad3_ net-_u27-pad2_ net-_u11-pad1_ net-_u31-pad6_ d_dff
+* u28 net-_u27-pad1_ net-_u28-pad2_ d_inverter
+* u15 net-_u15-pad1_ net-_u10-pad2_ net-_u15-pad3_ d_and
+* u14 net-_u1-pad13_ net-_u10-pad1_ net-_u14-pad3_ d_and
+* u24 net-_u23-pad1_ net-_u24-pad2_ d_inverter
+* u20 net-_u13-pad3_ net-_u14-pad3_ net-_u20-pad3_ d_or
+* u32 net-_u20-pad3_ net-_u24-pad2_ unconnected-_u32-pad3_ net-_u28-pad2_ net-_u13-pad1_ net-_u32-pad6_ d_dff
+* u13 net-_u13-pad1_ net-_u10-pad2_ net-_u13-pad3_ d_and
+* u33 net-_u21-pad3_ net-_u25-pad2_ unconnected-_u33-pad3_ net-_u29-pad2_ net-_u15-pad1_ net-_u33-pad6_ d_dff
+* u29 net-_u27-pad1_ net-_u29-pad2_ d_inverter
+* u21 net-_u15-pad3_ net-_u16-pad3_ net-_u21-pad3_ d_or
+* u5 net-_u1-pad2_ net-_u5-pad2_ d_inverter
+* u8 net-_u4-pad2_ net-_u5-pad2_ net-_u39-pad2_ d_and
+* u4 net-_u1-pad1_ net-_u4-pad2_ d_inverter
+* u3 net-_u1-pad10_ net-_u3-pad2_ d_inverter
+* u2 net-_u1-pad9_ net-_u2-pad2_ d_inverter
+* u6 net-_u2-pad2_ net-_u3-pad2_ net-_u10-pad1_ d_and
+* u10 net-_u10-pad1_ net-_u10-pad2_ d_inverter
+* u11 net-_u11-pad1_ net-_u10-pad2_ net-_u11-pad3_ d_and
+* u12 net-_u1-pad14_ net-_u10-pad1_ net-_u12-pad3_ d_and
+* u27 net-_u27-pad1_ net-_u27-pad2_ d_inverter
+* u19 net-_u11-pad3_ net-_u12-pad3_ net-_u19-pad3_ d_or
+* u23 net-_u23-pad1_ net-_u23-pad2_ d_inverter
+* u39 net-_u36-pad2_ net-_u39-pad2_ net-_u1-pad4_ d_tristate
+* u36 net-_u32-pad6_ net-_u36-pad2_ d_inverter
+* u40 net-_u35-pad2_ net-_u39-pad2_ net-_u1-pad3_ d_tristate
+* u35 net-_u31-pad6_ net-_u35-pad2_ d_inverter
+* u37 net-_u33-pad6_ net-_u37-pad2_ d_inverter
+* u41 net-_u37-pad2_ net-_u39-pad2_ net-_u1-pad5_ d_tristate
+* u42 net-_u38-pad2_ net-_u39-pad2_ net-_u1-pad6_ d_tristate
+* u38 net-_u34-pad6_ net-_u38-pad2_ d_inverter
+* u30 net-_u27-pad1_ net-_u30-pad2_ d_inverter
+* u34 net-_u22-pad3_ net-_u26-pad2_ unconnected-_u34-pad3_ net-_u30-pad2_ net-_u17-pad1_ net-_u34-pad6_ d_dff
+a1 net-_u23-pad1_ net-_u26-pad2_ u26
+a2 [net-_u17-pad3_ net-_u18-pad3_ ] net-_u22-pad3_ u22
+a3 [net-_u1-pad11_ net-_u10-pad1_ ] net-_u18-pad3_ u18
+a4 [net-_u17-pad1_ net-_u10-pad2_ ] net-_u17-pad3_ u17
+a5 [net-_u1-pad12_ net-_u10-pad1_ ] net-_u16-pad3_ u16
+a6 net-_u23-pad1_ net-_u25-pad2_ u25
+a7 net-_u1-pad15_ net-_u27-pad1_ u9
+a8 net-_u1-pad7_ net-_u23-pad1_ u7
+a9 net-_u19-pad3_ net-_u23-pad2_ unconnected-_u31-pad3_ net-_u27-pad2_ net-_u11-pad1_ net-_u31-pad6_ u31
+a10 net-_u27-pad1_ net-_u28-pad2_ u28
+a11 [net-_u15-pad1_ net-_u10-pad2_ ] net-_u15-pad3_ u15
+a12 [net-_u1-pad13_ net-_u10-pad1_ ] net-_u14-pad3_ u14
+a13 net-_u23-pad1_ net-_u24-pad2_ u24
+a14 [net-_u13-pad3_ net-_u14-pad3_ ] net-_u20-pad3_ u20
+a15 net-_u20-pad3_ net-_u24-pad2_ unconnected-_u32-pad3_ net-_u28-pad2_ net-_u13-pad1_ net-_u32-pad6_ u32
+a16 [net-_u13-pad1_ net-_u10-pad2_ ] net-_u13-pad3_ u13
+a17 net-_u21-pad3_ net-_u25-pad2_ unconnected-_u33-pad3_ net-_u29-pad2_ net-_u15-pad1_ net-_u33-pad6_ u33
+a18 net-_u27-pad1_ net-_u29-pad2_ u29
+a19 [net-_u15-pad3_ net-_u16-pad3_ ] net-_u21-pad3_ u21
+a20 net-_u1-pad2_ net-_u5-pad2_ u5
+a21 [net-_u4-pad2_ net-_u5-pad2_ ] net-_u39-pad2_ u8
+a22 net-_u1-pad1_ net-_u4-pad2_ u4
+a23 net-_u1-pad10_ net-_u3-pad2_ u3
+a24 net-_u1-pad9_ net-_u2-pad2_ u2
+a25 [net-_u2-pad2_ net-_u3-pad2_ ] net-_u10-pad1_ u6
+a26 net-_u10-pad1_ net-_u10-pad2_ u10
+a27 [net-_u11-pad1_ net-_u10-pad2_ ] net-_u11-pad3_ u11
+a28 [net-_u1-pad14_ net-_u10-pad1_ ] net-_u12-pad3_ u12
+a29 net-_u27-pad1_ net-_u27-pad2_ u27
+a30 [net-_u11-pad3_ net-_u12-pad3_ ] net-_u19-pad3_ u19
+a31 net-_u23-pad1_ net-_u23-pad2_ u23
+a32 net-_u36-pad2_ net-_u39-pad2_ net-_u1-pad4_ u39
+a33 net-_u32-pad6_ net-_u36-pad2_ u36
+a34 net-_u35-pad2_ net-_u39-pad2_ net-_u1-pad3_ u40
+a35 net-_u31-pad6_ net-_u35-pad2_ u35
+a36 net-_u33-pad6_ net-_u37-pad2_ u37
+a37 net-_u37-pad2_ net-_u39-pad2_ net-_u1-pad5_ u41
+a38 net-_u38-pad2_ net-_u39-pad2_ net-_u1-pad6_ u42
+a39 net-_u34-pad6_ net-_u38-pad2_ u38
+a40 net-_u27-pad1_ net-_u30-pad2_ u30
+a41 net-_u22-pad3_ net-_u26-pad2_ unconnected-_u34-pad3_ net-_u30-pad2_ net-_u17-pad1_ net-_u34-pad6_ u34
+* Schematic Name: d_inverter, Ngspice Name: d_inverter
+.model u26 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_or, Ngspice Name: d_or
+.model u22 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, Ngspice Name: d_and
+.model u18 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, Ngspice Name: d_and
+.model u17 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, Ngspice Name: d_and
+.model u16 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, Ngspice Name: d_inverter
+.model u25 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, Ngspice Name: d_inverter
+.model u9 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, Ngspice Name: d_inverter
+.model u7 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_dff, Ngspice Name: d_dff
+.model u31 d_dff(clk_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0 ic=0 data_load=1.0e-12 clk_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 )
+* Schematic Name: d_inverter, Ngspice Name: d_inverter
+.model u28 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, Ngspice Name: d_and
+.model u15 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, Ngspice Name: d_and
+.model u14 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, Ngspice Name: d_inverter
+.model u24 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_or, Ngspice Name: d_or
+.model u20 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_dff, Ngspice Name: d_dff
+.model u32 d_dff(clk_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0 ic=0 data_load=1.0e-12 clk_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 )
+* Schematic Name: d_and, Ngspice Name: d_and
+.model u13 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_dff, Ngspice Name: d_dff
+.model u33 d_dff(clk_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0 ic=0 data_load=1.0e-12 clk_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 )
+* Schematic Name: d_inverter, Ngspice Name: d_inverter
+.model u29 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_or, Ngspice Name: d_or
+.model u21 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, Ngspice Name: d_inverter
+.model u5 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, Ngspice Name: d_and
+.model u8 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, Ngspice Name: d_inverter
+.model u4 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, Ngspice Name: d_inverter
+.model u3 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, Ngspice Name: d_inverter
+.model u2 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, Ngspice Name: d_and
+.model u6 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, Ngspice Name: d_inverter
+.model u10 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, Ngspice Name: d_and
+.model u11 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, Ngspice Name: d_and
+.model u12 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, Ngspice Name: d_inverter
+.model u27 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_or, Ngspice Name: d_or
+.model u19 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, Ngspice Name: d_inverter
+.model u23 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_tristate, Ngspice Name: d_tristate
+.model u39 d_tristate(delay=1.0e-9 input_load=1.0e-12 enable_load=1.0e-12 )
+* Schematic Name: d_inverter, Ngspice Name: d_inverter
+.model u36 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_tristate, Ngspice Name: d_tristate
+.model u40 d_tristate(delay=1.0e-9 input_load=1.0e-12 enable_load=1.0e-12 )
+* Schematic Name: d_inverter, Ngspice Name: d_inverter
+.model u35 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, Ngspice Name: d_inverter
+.model u37 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_tristate, Ngspice Name: d_tristate
+.model u41 d_tristate(delay=1.0e-9 input_load=1.0e-12 enable_load=1.0e-12 )
+* Schematic Name: d_tristate, Ngspice Name: d_tristate
+.model u42 d_tristate(delay=1.0e-9 input_load=1.0e-12 enable_load=1.0e-12 )
+* Schematic Name: d_inverter, Ngspice Name: d_inverter
+.model u38 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, Ngspice Name: d_inverter
+.model u30 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_dff, Ngspice Name: d_dff
+.model u34 d_dff(clk_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0 ic=0 data_load=1.0e-12 clk_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 )
+* Control Statements
+
+.ends 74LS173
\ No newline at end of file
diff --git a/library/SubcircuitLibrary/74LS173/74LS173_Previous_Values.xml b/library/SubcircuitLibrary/74LS173/74LS173_Previous_Values.xml
new file mode 100644
index 000000000..1ec2bb491
--- /dev/null
+++ b/library/SubcircuitLibrary/74LS173/74LS173_Previous_Values.xml
@@ -0,0 +1 @@
+truefalsefalseHzHz0Volts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or Amperessecsecsecd_inverterd_ord_andd_andd_andd_inverterd_inverterd_inverterd_dffd_inverterd_andd_andd_inverterd_ord_dffd_andd_dffd_inverterd_ord_inverterd_andd_inverterd_inverterd_inverterd_andd_inverterd_andd_andd_inverterd_ord_inverterd_tristated_inverterd_tristated_inverterd_inverterd_tristated_tristated_inverterd_inverterd_dff
\ No newline at end of file
diff --git a/library/SubcircuitLibrary/74LS173/_autosave-74LS173.sch b/library/SubcircuitLibrary/74LS173/_autosave-74LS173.sch
new file mode 100644
index 000000000..aef09742e
--- /dev/null
+++ b/library/SubcircuitLibrary/74LS173/_autosave-74LS173.sch
@@ -0,0 +1,939 @@
+EESchema Schematic File Version 5
+EELAYER 36 0
+EELAYER END
+$Descr A2 23386 16535
+encoding utf-8
+Sheet 1 1
+Title ""
+Date ""
+Rev ""
+Comp ""
+Comment1 ""
+Comment2 ""
+Comment3 ""
+Comment4 ""
+Comment5 ""
+Comment6 ""
+Comment7 ""
+Comment8 ""
+Comment9 ""
+$EndDescr
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+F 0 "U12" H 11500 4850 60 0000 C CNN
+F 1 "d_and" H 11500 4700 60 0000 C CNN
+F 2 "" H 11500 4500 60 0000 C CNN
+F 3 "" H 11500 4500 60 0000 C CNN
+ 1 11500 4500
+ 1 0 0 -1
+$EndComp
+$Comp
+L eSim_Digital:d_and U13
+U 1 1 00000000
+P 11500 6150
+F 0 "U13" H 11500 6500 60 0000 C CNN
+F 1 "d_and" H 11500 6350 60 0000 C CNN
+F 2 "" H 11500 6150 60 0000 C CNN
+F 3 "" H 11500 6150 60 0000 C CNN
+ 1 11500 6150
+ 1 0 0 -1
+$EndComp
+$Comp
+L eSim_Digital:d_and U14
+U 1 1 00000000
+P 11500 7100
+F 0 "U14" H 11500 7450 60 0000 C CNN
+F 1 "d_and" H 11500 7300 60 0000 C CNN
+F 2 "" H 11500 7100 60 0000 C CNN
+F 3 "" H 11500 7100 60 0000 C CNN
+ 1 11500 7100
+ 1 0 0 -1
+$EndComp
+$Comp
+L eSim_Digital:d_and U15
+U 1 1 00000000
+P 11500 8800
+F 0 "U15" H 11500 9150 60 0000 C CNN
+F 1 "d_and" H 11500 9000 60 0000 C CNN
+F 2 "" H 11500 8800 60 0000 C CNN
+F 3 "" H 11500 8800 60 0000 C CNN
+ 1 11500 8800
+ 1 0 0 -1
+$EndComp
+$Comp
+L eSim_Digital:d_and U16
+U 1 1 00000000
+P 11550 9750
+F 0 "U16" H 11550 10100 60 0000 C CNN
+F 1 "d_and" H 11550 9950 60 0000 C CNN
+F 2 "" H 11550 9750 60 0000 C CNN
+F 3 "" H 11550 9750 60 0000 C CNN
+ 1 11550 9750
+ 1 0 0 -1
+$EndComp
+$Comp
+L eSim_Digital:d_and U17
+U 1 1 00000000
+P 11550 11300
+F 0 "U17" H 11550 11650 60 0000 C CNN
+F 1 "d_and" H 11550 11500 60 0000 C CNN
+F 2 "" H 11550 11300 60 0000 C CNN
+F 3 "" H 11550 11300 60 0000 C CNN
+ 1 11550 11300
+ 1 0 0 -1
+$EndComp
+$Comp
+L eSim_Digital:d_and U18
+U 1 1 00000000
+P 11600 12200
+F 0 "U18" H 11600 12550 60 0000 C CNN
+F 1 "d_and" H 11600 12400 60 0000 C CNN
+F 2 "" H 11600 12200 60 0000 C CNN
+F 3 "" H 11600 12200 60 0000 C CNN
+ 1 11600 12200
+ 1 0 0 -1
+$EndComp
+$Comp
+L eSim_Digital:d_or U19
+U 1 1 00000000
+P 14150 4000
+F 0 "U19" H 14150 4350 60 0000 C CNN
+F 1 "d_or" H 14150 4200 60 0000 C CNN
+F 2 "" H 14150 4000 60 0000 C CNN
+F 3 "" H 14150 4000 60 0000 C CNN
+ 1 14150 4000
+ 1 0 0 -1
+$EndComp
+$Comp
+L eSim_Digital:d_or U20
+U 1 1 00000000
+P 14150 6600
+F 0 "U20" H 14150 6950 60 0000 C CNN
+F 1 "d_or" H 14150 6800 60 0000 C CNN
+F 2 "" H 14150 6600 60 0000 C CNN
+F 3 "" H 14150 6600 60 0000 C CNN
+ 1 14150 6600
+ 1 0 0 -1
+$EndComp
+$Comp
+L eSim_Digital:d_or U21
+U 1 1 00000000
+P 14200 9250
+F 0 "U21" H 14200 9600 60 0000 C CNN
+F 1 "d_or" H 14200 9450 60 0000 C CNN
+F 2 "" H 14200 9250 60 0000 C CNN
+F 3 "" H 14200 9250 60 0000 C CNN
+ 1 14200 9250
+ 1 0 0 -1
+$EndComp
+$Comp
+L eSim_Digital:d_or U22
+U 1 1 00000000
+P 14200 11750
+F 0 "U22" H 14200 12100 60 0000 C CNN
+F 1 "d_or" H 14200 11950 60 0000 C CNN
+F 2 "" H 14200 11750 60 0000 C CNN
+F 3 "" H 14200 11750 60 0000 C CNN
+ 1 14200 11750
+ 1 0 0 -1
+$EndComp
+$Comp
+L eSim_Digital:d_tristate U39
+U 1 1 00000000
+P 17100 6450
+F 0 "U39" H 17075 7100 60 0000 C CNN
+F 1 "d_tristate" H 17075 7250 60 0000 C CNN
+F 2 "" H 17000 6800 60 0000 C CNN
+F 3 "" H 17000 6800 60 0000 C CNN
+ 1 17100 6450
+ 1 0 0 1
+$EndComp
+$Comp
+L eSim_Digital:d_tristate U40
+U 1 1 00000000
+P 17150 3900
+F 0 "U40" H 17125 4550 60 0000 C CNN
+F 1 "d_tristate" H 17125 4700 60 0000 C CNN
+F 2 "" H 17050 4250 60 0000 C CNN
+F 3 "" H 17050 4250 60 0000 C CNN
+ 1 17150 3900
+ 1 0 0 1
+$EndComp
+$Comp
+L eSim_Digital:d_tristate U41
+U 1 1 00000000
+P 17150 9150
+F 0 "U41" H 17125 9800 60 0000 C CNN
+F 1 "d_tristate" H 17125 9950 60 0000 C CNN
+F 2 "" H 17050 9500 60 0000 C CNN
+F 3 "" H 17050 9500 60 0000 C CNN
+ 1 17150 9150
+ 1 0 0 1
+$EndComp
+$Comp
+L eSim_Digital:d_tristate U42
+U 1 1 00000000
+P 17200 11650
+F 0 "U42" H 17175 12300 60 0000 C CNN
+F 1 "d_tristate" H 17175 12450 60 0000 C CNN
+F 2 "" H 17100 12000 60 0000 C CNN
+F 3 "" H 17100 12000 60 0000 C CNN
+ 1 17200 11650
+ 1 0 0 1
+$EndComp
+$Comp
+L eSim_Digital:d_dff U31
+U 1 1 00000000
+P 15200 3950
+F 0 "U31" H 15280 4600 60 0000 L CNN
+F 1 "d_dff" H 15280 4450 60 0000 L CNN
+F 2 "" H 15200 3950 60 0000 C CNN
+F 3 "" H 15200 3950 60 0000 C CNN
+ 1 15200 3950
+ 1 0 0 -1
+$EndComp
+$Comp
+L eSim_Digital:d_dff U32
+U 1 1 00000000
+P 15200 6500
+F 0 "U32" H 15280 7150 60 0000 L CNN
+F 1 "d_dff" H 15280 7000 60 0000 L CNN
+F 2 "" H 15200 6500 60 0000 C CNN
+F 3 "" H 15200 6500 60 0000 C CNN
+ 1 15200 6500
+ 1 0 0 -1
+$EndComp
+$Comp
+L eSim_Digital:d_dff U33
+U 1 1 00000000
+P 15250 9200
+F 0 "U33" H 15330 9850 60 0000 L CNN
+F 1 "d_dff" H 15330 9700 60 0000 L CNN
+F 2 "" H 15250 9200 60 0000 C CNN
+F 3 "" H 15250 9200 60 0000 C CNN
+ 1 15250 9200
+ 1 0 0 -1
+$EndComp
+$Comp
+L eSim_Digital:d_dff U34
+U 1 1 00000000
+P 15250 11700
+F 0 "U34" H 15330 12350 60 0000 L CNN
+F 1 "d_dff" H 15330 12200 60 0000 L CNN
+F 2 "" H 15250 11700 60 0000 C CNN
+F 3 "" H 15250 11700 60 0000 C CNN
+ 1 15250 11700
+ 1 0 0 -1
+$EndComp
+$EndSCHEMATC
diff --git a/library/SubcircuitLibrary/74LS173/analysis b/library/SubcircuitLibrary/74LS173/analysis
new file mode 100644
index 000000000..ebd5c0a94
--- /dev/null
+++ b/library/SubcircuitLibrary/74LS173/analysis
@@ -0,0 +1 @@
+.tran 0e-00 0e-00 0e-00
\ No newline at end of file
diff --git a/library/SubcircuitLibrary/74ls164/74ls164.cir b/library/SubcircuitLibrary/74ls164/74ls164.cir
new file mode 100644
index 000000000..c76f456d7
--- /dev/null
+++ b/library/SubcircuitLibrary/74ls164/74ls164.cir
@@ -0,0 +1,15 @@
+.title KiCad schematic
+U1 /in1 /in2 Net-_U8-Pad1_ Net-_U8-Pad6_ Net-_U10-Pad6_ Net-_U12-Pad6_ unconnected-_U1-Pad7_ /clock /clear Net-_U11-Pad1_ Net-_U9-Pad1_ Net-_U9-Pad6_ Net-_U7-Pad6_ unconnected-_U1-Pad14_ PORT
+U11 Net-_U11-Pad1_ Net-_U11-Pad2_ Net-_U8-Pad3_ unconnected-_U11-Pad4_ Net-_U8-Pad5_ Net-_U9-Pad1_ Net-_U9-Pad2_ d_srff
+U10 Net-_U8-Pad6_ Net-_U8-Pad7_ Net-_U8-Pad3_ unconnected-_U10-Pad4_ Net-_U8-Pad5_ Net-_U10-Pad6_ Net-_U10-Pad7_ d_srff
+U6 Net-_U4-Pad2_ Net-_U2-Pad3_ Net-_U8-Pad3_ unconnected-_U6-Pad4_ Net-_U8-Pad5_ Net-_U8-Pad1_ Net-_U8-Pad2_ d_srff
+U8 Net-_U8-Pad1_ Net-_U8-Pad2_ Net-_U8-Pad3_ unconnected-_U8-Pad4_ Net-_U8-Pad5_ Net-_U8-Pad6_ Net-_U8-Pad7_ d_srff
+U9 Net-_U9-Pad1_ Net-_U9-Pad2_ Net-_U8-Pad3_ unconnected-_U9-Pad4_ Net-_U8-Pad5_ Net-_U9-Pad6_ Net-_U9-Pad7_ d_srff
+U7 Net-_U9-Pad6_ Net-_U9-Pad7_ Net-_U8-Pad3_ unconnected-_U7-Pad4_ Net-_U8-Pad5_ Net-_U7-Pad6_ unconnected-_U7-Pad7_ d_srff
+U13 Net-_U12-Pad6_ Net-_U12-Pad7_ Net-_U8-Pad3_ unconnected-_U13-Pad4_ Net-_U8-Pad5_ Net-_U11-Pad1_ Net-_U11-Pad2_ d_srff
+U12 Net-_U10-Pad6_ Net-_U10-Pad7_ Net-_U8-Pad3_ unconnected-_U12-Pad4_ Net-_U8-Pad5_ Net-_U12-Pad6_ Net-_U12-Pad7_ d_srff
+U2 /in1 /in2 Net-_U2-Pad3_ d_nand
+U5 /clock Net-_U8-Pad3_ d_inverter
+U4 Net-_U2-Pad3_ Net-_U4-Pad2_ d_inverter
+U3 /clear Net-_U8-Pad5_ d_inverter
+.end
diff --git a/library/SubcircuitLibrary/74ls164/74ls164.cir.out b/library/SubcircuitLibrary/74ls164/74ls164.cir.out
new file mode 100644
index 000000000..bf8b5bab3
--- /dev/null
+++ b/library/SubcircuitLibrary/74ls164/74ls164.cir.out
@@ -0,0 +1,60 @@
+.title kicad schematic
+
+* u1 /in1 /in2 net-_u8-pad1_ net-_u8-pad6_ net-_u10-pad6_ net-_u12-pad6_ unconnected-_u1-pad7_ /clock /clear net-_u11-pad1_ net-_u9-pad1_ net-_u9-pad6_ net-_u7-pad6_ unconnected-_u1-pad14_ port
+* u11 net-_u11-pad1_ net-_u11-pad2_ net-_u8-pad3_ unconnected-_u11-pad4_ net-_u8-pad5_ net-_u9-pad1_ net-_u9-pad2_ d_srff
+* u10 net-_u8-pad6_ net-_u8-pad7_ net-_u8-pad3_ unconnected-_u10-pad4_ net-_u8-pad5_ net-_u10-pad6_ net-_u10-pad7_ d_srff
+* u6 net-_u4-pad2_ net-_u2-pad3_ net-_u8-pad3_ unconnected-_u6-pad4_ net-_u8-pad5_ net-_u8-pad1_ net-_u8-pad2_ d_srff
+* u8 net-_u8-pad1_ net-_u8-pad2_ net-_u8-pad3_ unconnected-_u8-pad4_ net-_u8-pad5_ net-_u8-pad6_ net-_u8-pad7_ d_srff
+* u9 net-_u9-pad1_ net-_u9-pad2_ net-_u8-pad3_ unconnected-_u9-pad4_ net-_u8-pad5_ net-_u9-pad6_ net-_u9-pad7_ d_srff
+* u7 net-_u9-pad6_ net-_u9-pad7_ net-_u8-pad3_ unconnected-_u7-pad4_ net-_u8-pad5_ net-_u7-pad6_ unconnected-_u7-pad7_ d_srff
+* u13 net-_u12-pad6_ net-_u12-pad7_ net-_u8-pad3_ unconnected-_u13-pad4_ net-_u8-pad5_ net-_u11-pad1_ net-_u11-pad2_ d_srff
+* u12 net-_u10-pad6_ net-_u10-pad7_ net-_u8-pad3_ unconnected-_u12-pad4_ net-_u8-pad5_ net-_u12-pad6_ net-_u12-pad7_ d_srff
+* u2 /in1 /in2 net-_u2-pad3_ d_nand
+* u5 /clock net-_u8-pad3_ d_inverter
+* u4 net-_u2-pad3_ net-_u4-pad2_ d_inverter
+* u3 /clear net-_u8-pad5_ d_inverter
+a1 net-_u11-pad1_ net-_u11-pad2_ net-_u8-pad3_ unconnected-_u11-pad4_ net-_u8-pad5_ net-_u9-pad1_ net-_u9-pad2_ u11
+a2 net-_u8-pad6_ net-_u8-pad7_ net-_u8-pad3_ unconnected-_u10-pad4_ net-_u8-pad5_ net-_u10-pad6_ net-_u10-pad7_ u10
+a3 net-_u4-pad2_ net-_u2-pad3_ net-_u8-pad3_ unconnected-_u6-pad4_ net-_u8-pad5_ net-_u8-pad1_ net-_u8-pad2_ u6
+a4 net-_u8-pad1_ net-_u8-pad2_ net-_u8-pad3_ unconnected-_u8-pad4_ net-_u8-pad5_ net-_u8-pad6_ net-_u8-pad7_ u8
+a5 net-_u9-pad1_ net-_u9-pad2_ net-_u8-pad3_ unconnected-_u9-pad4_ net-_u8-pad5_ net-_u9-pad6_ net-_u9-pad7_ u9
+a6 net-_u9-pad6_ net-_u9-pad7_ net-_u8-pad3_ unconnected-_u7-pad4_ net-_u8-pad5_ net-_u7-pad6_ unconnected-_u7-pad7_ u7
+a7 net-_u12-pad6_ net-_u12-pad7_ net-_u8-pad3_ unconnected-_u13-pad4_ net-_u8-pad5_ net-_u11-pad1_ net-_u11-pad2_ u13
+a8 net-_u10-pad6_ net-_u10-pad7_ net-_u8-pad3_ unconnected-_u12-pad4_ net-_u8-pad5_ net-_u12-pad6_ net-_u12-pad7_ u12
+a9 [/in1 /in2 ] net-_u2-pad3_ u2
+a10 /clock net-_u8-pad3_ u5
+a11 net-_u2-pad3_ net-_u4-pad2_ u4
+a12 /clear net-_u8-pad5_ u3
+* Schematic Name: d_srff, Ngspice Name: d_srff
+.model u11 d_srff(clk_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0 ic=0 sr_load=1.0e-12 clk_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 )
+* Schematic Name: d_srff, Ngspice Name: d_srff
+.model u10 d_srff(clk_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0 ic=0 sr_load=1.0e-12 clk_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 )
+* Schematic Name: d_srff, Ngspice Name: d_srff
+.model u6 d_srff(clk_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0 ic=0 sr_load=1.0e-12 clk_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 )
+* Schematic Name: d_srff, Ngspice Name: d_srff
+.model u8 d_srff(clk_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0 ic=0 sr_load=1.0e-12 clk_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 )
+* Schematic Name: d_srff, Ngspice Name: d_srff
+.model u9 d_srff(clk_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0 ic=0 sr_load=1.0e-12 clk_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 )
+* Schematic Name: d_srff, Ngspice Name: d_srff
+.model u7 d_srff(clk_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0 ic=0 sr_load=1.0e-12 clk_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 )
+* Schematic Name: d_srff, Ngspice Name: d_srff
+.model u13 d_srff(clk_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0 ic=0 sr_load=1.0e-12 clk_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 )
+* Schematic Name: d_srff, Ngspice Name: d_srff
+.model u12 d_srff(clk_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0 ic=0 sr_load=1.0e-12 clk_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 )
+* Schematic Name: d_nand, Ngspice Name: d_nand
+.model u2 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, Ngspice Name: d_inverter
+.model u5 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, Ngspice Name: d_inverter
+.model u4 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, Ngspice Name: d_inverter
+.model u3 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+.tran 0e-00 0e-00 0e-00
+
+* Control Statements
+.control
+run
+print allv > plot_data_v.txt
+print alli > plot_data_i.txt
+.endc
+.end
diff --git a/library/SubcircuitLibrary/74ls164/74ls164.kicad_sch b/library/SubcircuitLibrary/74ls164/74ls164.kicad_sch
new file mode 100644
index 000000000..aa6f8085d
--- /dev/null
+++ b/library/SubcircuitLibrary/74ls164/74ls164.kicad_sch
@@ -0,0 +1,1724 @@
+(kicad_sch (version 20211123) (generator eeschema)
+
+ (uuid 6c6ed0f7-a55e-411e-98a2-c3ee23afdc64)
+
+ (paper "A1")
+
+ (lib_symbols
+ (symbol "eSim_Digital:d_inverter" (pin_names (offset 1.016)) (in_bom yes) (on_board yes)
+ (property "Reference" "U" (id 0) (at 0 -2.54 0)
+ (effects (font (size 1.524 1.524)))
+ )
+ (property "Value" "d_inverter" (id 1) (at 0 3.81 0)
+ (effects (font (size 1.524 1.524)))
+ )
+ (property "Footprint" "" (id 2) (at 1.27 -1.27 0)
+ (effects (font (size 1.524 1.524)))
+ )
+ (property "Datasheet" "" (id 3) (at 1.27 -1.27 0)
+ (effects (font (size 1.524 1.524)))
+ )
+ (symbol "d_inverter_0_1"
+ (polyline
+ (pts
+ (xy -2.54 1.27)
+ (xy -2.54 -1.27)
+ (xy 2.54 0)
+ (xy -2.54 1.27)
+ )
+ (stroke (width 0) (type default) (color 0 0 0 0))
+ (fill (type none))
+ )
+ )
+ (symbol "d_inverter_1_1"
+ (pin input line (at -7.62 0 0) (length 5.08)
+ (name "~" (effects (font (size 1.27 1.27))))
+ (number "1" (effects (font (size 1.27 1.27))))
+ )
+ (pin output inverted (at 7.62 0 180) (length 5.08)
+ (name "~" (effects (font (size 1.27 1.27))))
+ (number "2" (effects (font (size 1.27 1.27))))
+ )
+ )
+ )
+ (symbol "eSim_Digital:d_nand" (pin_names (offset 1.016)) (in_bom yes) (on_board yes)
+ (property "Reference" "U" (id 0) (at 0 0 0)
+ (effects (font (size 1.524 1.524)))
+ )
+ (property "Value" "d_nand" (id 1) (at 1.27 2.54 0)
+ (effects (font (size 1.524 1.524)))
+ )
+ (property "Footprint" "" (id 2) (at 0 0 0)
+ (effects (font (size 1.524 1.524)))
+ )
+ (property "Datasheet" "" (id 3) (at 0 0 0)
+ (effects (font (size 1.524 1.524)))
+ )
+ (symbol "d_nand_0_1"
+ (polyline
+ (pts
+ (xy 3.81 -1.27)
+ (xy -6.35 -1.27)
+ (xy -6.35 3.81)
+ (xy 3.81 3.81)
+ )
+ (stroke (width 0) (type default) (color 0 0 0 0))
+ (fill (type none))
+ )
+ (arc (start 3.81 -1.27) (mid 5.5897 -0.5171) (end 6.35 1.27)
+ (stroke (width 0) (type default) (color 0 0 0 0))
+ (fill (type none))
+ )
+ (arc (start 6.35 1.27) (mid 5.5971 3.0497) (end 3.81 3.81)
+ (stroke (width 0) (type default) (color 0 0 0 0))
+ (fill (type none))
+ )
+ )
+ (symbol "d_nand_1_1"
+ (pin input line (at -11.43 2.54 0) (length 5.08)
+ (name "IN1" (effects (font (size 1.27 1.27))))
+ (number "1" (effects (font (size 1.27 1.27))))
+ )
+ (pin input line (at -11.43 0 0) (length 5.08)
+ (name "IN2" (effects (font (size 1.27 1.27))))
+ (number "2" (effects (font (size 1.27 1.27))))
+ )
+ (pin output inverted (at 11.43 1.27 180) (length 5.08)
+ (name "OUT" (effects (font (size 1.27 1.27))))
+ (number "3" (effects (font (size 1.27 1.27))))
+ )
+ )
+ )
+ (symbol "eSim_Digital:d_srff" (pin_names (offset 1.016)) (in_bom yes) (on_board yes)
+ (property "Reference" "U" (id 0) (at 0 0 0)
+ (effects (font (size 1.524 1.524)))
+ )
+ (property "Value" "d_srff" (id 1) (at 1.27 3.81 0)
+ (effects (font (size 1.524 1.524)))
+ )
+ (property "Footprint" "" (id 2) (at 0 0 0)
+ (effects (font (size 1.524 1.524)))
+ )
+ (property "Datasheet" "" (id 3) (at 0 0 0)
+ (effects (font (size 1.524 1.524)))
+ )
+ (symbol "d_srff_0_1"
+ (rectangle (start 15.24 13.97) (end -15.24 -15.24)
+ (stroke (width 0) (type default) (color 0 0 0 0))
+ (fill (type none))
+ )
+ )
+ (symbol "d_srff_1_1"
+ (pin input line (at -20.32 10.16 0) (length 5.08)
+ (name "S" (effects (font (size 1.27 1.27))))
+ (number "1" (effects (font (size 1.27 1.27))))
+ )
+ (pin input line (at -20.32 -11.43 0) (length 5.08)
+ (name "R" (effects (font (size 1.27 1.27))))
+ (number "2" (effects (font (size 1.27 1.27))))
+ )
+ (pin input clock (at -20.32 0 0) (length 5.08)
+ (name "Clk" (effects (font (size 1.27 1.27))))
+ (number "3" (effects (font (size 1.27 1.27))))
+ )
+ (pin input line (at 0 19.05 270) (length 5.08)
+ (name "Set" (effects (font (size 1.27 1.27))))
+ (number "4" (effects (font (size 1.27 1.27))))
+ )
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+ (pin "7" (uuid 6017bd68-6a41-4985-9dd9-ec092bf4ac00))
+ )
+
+ (symbol (lib_id "eSim_Miscellaneous:PORT") (at 443.23 323.85 90) (unit 5)
+ (in_bom yes) (on_board yes) (fields_autoplaced)
+ (uuid e3ca152b-661b-4ea2-ad26-084225905afd)
+ (property "Reference" "U1" (id 0) (at 445.77 322.58 90)
+ (effects (font (size 0.762 0.762)) (justify right))
+ )
+ (property "Value" "PORT" (id 1) (at 445.77 325.12 90)
+ (effects (font (size 0.762 0.762)) (justify right))
+ )
+ (property "Footprint" "" (id 2) (at 443.23 323.85 0)
+ (effects (font (size 1.524 1.524)))
+ )
+ (property "Datasheet" "" (id 3) (at 443.23 323.85 0)
+ (effects (font (size 1.524 1.524)))
+ )
+ (pin "1" (uuid 9c4fc821-978d-47d3-9c1c-b057e6b8dd54))
+ (pin "2" (uuid 414530db-b43c-4e4f-9561-43f703209154))
+ (pin "3" (uuid 0fc2b78f-dd4a-4757-af65-44ed64ab7aca))
+ (pin "4" (uuid adec8f1a-e6b8-4bf2-8ca3-3555b5a7d3ae))
+ (pin "5" (uuid cc37f1c4-944e-4720-b095-c8779da15cf3))
+ (pin "6" (uuid cd409c8f-a890-46b3-9300-45e6ca6ff103))
+ (pin "7" (uuid d410411a-70a5-48c1-bd96-d41d26b75814))
+ (pin "8" (uuid 57025f8a-4cfd-4a84-b785-8a667c1e2f15))
+ (pin "9" (uuid f951dfef-afa3-47bd-8ef5-db111e84a38a))
+ (pin "10" (uuid 484cf94c-9092-4fc9-9c31-5a0034d66781))
+ (pin "11" (uuid 941f674c-2495-434c-9951-235ab552a256))
+ (pin "12" (uuid bcc31e67-03b0-4c7e-9dad-1919bca47a3e))
+ (pin "13" (uuid fdd6b73a-a5a9-4e86-a59f-f96291679487))
+ (pin "14" (uuid d8c450e5-c27f-46eb-9bf4-0d4bdab0d439))
+ (pin "15" (uuid 54e700a4-409f-4447-9bc0-4a855d6bc767))
+ (pin "16" (uuid ff2d6b7c-db45-48da-ac23-5694dca4f4d3))
+ (pin "17" (uuid 12c523fe-001b-470d-b70c-d0102c2d5c08))
+ (pin "18" (uuid 485ef0ad-403a-4579-a498-f411b9f069ad))
+ (pin "19" (uuid b5e2f4b6-308d-40f8-b477-fe237fc5190d))
+ (pin "20" (uuid 1989172c-d5c0-4af3-b827-f00d2528e5d6))
+ (pin "21" (uuid 38810dae-ff0e-4dbc-96fc-08d2f4b2db34))
+ (pin "22" (uuid 98dee358-7765-415f-a5d9-6584dcfc6f32))
+ (pin "23" (uuid f2c48e19-aa40-47fd-a780-297ae3d2c01b))
+ (pin "24" (uuid 2f9f4598-a0dc-4190-b9a9-d4333033ebe2))
+ (pin "25" (uuid c75d8b3c-6f3e-4844-b51d-48b465bb50fe))
+ (pin "26" (uuid f29a8404-5bab-405f-bdb0-6a6ffb78e472))
+ )
+
+ (symbol (lib_id "eSim_Digital:d_srff") (at 375.92 358.14 180) (unit 1)
+ (in_bom yes) (on_board yes) (fields_autoplaced)
+ (uuid f62489b4-0411-4b07-999f-f3600f63a488)
+ (property "Reference" "U9" (id 0) (at 373.9006 337.82 0)
+ (effects (font (size 1.524 1.524)) (justify left))
+ )
+ (property "Value" "d_srff" (id 1) (at 373.9006 341.63 0)
+ (effects (font (size 1.524 1.524)) (justify left))
+ )
+ (property "Footprint" "" (id 2) (at 375.92 358.14 0)
+ (effects (font (size 1.524 1.524)))
+ )
+ (property "Datasheet" "" (id 3) (at 375.92 358.14 0)
+ (effects (font (size 1.524 1.524)))
+ )
+ (pin "1" (uuid a0c20a92-f6ae-45f7-9217-9d67f51ec8c0))
+ (pin "2" (uuid 320cfd7b-a0e3-4417-8c62-51f23584085a))
+ (pin "3" (uuid 90c9289c-7b26-48e3-8bec-099246526f5d))
+ (pin "4" (uuid 275070cb-b04b-420a-9741-5510df13a695))
+ (pin "5" (uuid 32405949-7cc6-4869-ae3f-35d1c8a0d0bf))
+ (pin "6" (uuid b769fdb4-17b7-47d5-acab-d56bf132d2ac))
+ (pin "7" (uuid 9fd00196-a5bd-4828-b03c-3e49b2778a03))
+ )
+
+ (sheet_instances
+ (path "/" (page "1"))
+ )
+
+ (symbol_instances
+ (path "/1ba34487-b5a3-4eec-b790-d0d6f5f0cfc3"
+ (reference "U1") (unit 1) (value "PORT") (footprint "")
+ )
+ (path "/0e121aef-6522-4f8c-857a-c02adce85391"
+ (reference "U1") (unit 2) (value "PORT") (footprint "")
+ )
+ (path "/6a0a4830-3eb3-46c9-9554-5e10e503ca19"
+ (reference "U1") (unit 3) (value "PORT") (footprint "")
+ )
+ (path "/9d8c71da-59a0-404a-8aac-4e9d7f13b4f1"
+ (reference "U1") (unit 4) (value "PORT") (footprint "")
+ )
+ (path "/e3ca152b-661b-4ea2-ad26-084225905afd"
+ (reference "U1") (unit 5) (value "PORT") (footprint "")
+ )
+ (path "/cfcf96d1-cff2-465f-87fb-e6d067bd4c1c"
+ (reference "U1") (unit 6) (value "PORT") (footprint "")
+ )
+ (path "/931871ae-5884-4fe7-9bc5-99abc51adc4f"
+ (reference "U1") (unit 7) (value "PORT") (footprint "")
+ )
+ (path "/b71f53a5-b8ed-4748-b45f-1533a90a0820"
+ (reference "U1") (unit 8) (value "PORT") (footprint "")
+ )
+ (path "/2bad7f76-a65a-42cd-ac3c-c278d784abce"
+ (reference "U1") (unit 9) (value "PORT") (footprint "")
+ )
+ (path "/4193beae-c98f-495a-8277-0683735301a5"
+ (reference "U1") (unit 10) (value "PORT") (footprint "")
+ )
+ (path "/272039e5-648e-488b-ad7a-63cda9a75344"
+ (reference "U1") (unit 11) (value "PORT") (footprint "")
+ )
+ (path "/9d1cce23-fd06-4cb1-9078-91c505b17fe2"
+ (reference "U1") (unit 12) (value "PORT") (footprint "")
+ )
+ (path "/6f7d6a2c-0871-4472-8a27-25c9c14219eb"
+ (reference "U1") (unit 13) (value "PORT") (footprint "")
+ )
+ (path "/30b633bc-29c2-488c-a9dd-2b98b751321a"
+ (reference "U1") (unit 14) (value "PORT") (footprint "")
+ )
+ (path "/2b9b695e-63b2-4f61-a961-7ada66f454e6"
+ (reference "U2") (unit 1) (value "d_nand") (footprint "")
+ )
+ (path "/d41c9a86-8a91-4856-9ec6-6055135007fb"
+ (reference "U3") (unit 1) (value "d_inverter") (footprint "")
+ )
+ (path "/4e2e1fe4-f15e-4ed3-9f3b-92b7596a71e5"
+ (reference "U4") (unit 1) (value "d_inverter") (footprint "")
+ )
+ (path "/6965c170-59d0-46a5-9894-e892bb288e3c"
+ (reference "U5") (unit 1) (value "d_inverter") (footprint "")
+ )
+ (path "/c960c7dd-7115-40a8-83fa-2ed08a3877b6"
+ (reference "U6") (unit 1) (value "d_srff") (footprint "")
+ )
+ (path "/33cc8869-f67b-4f12-b409-a83915f8fcb1"
+ (reference "U7") (unit 1) (value "d_srff") (footprint "")
+ )
+ (path "/a991faf1-6730-41b9-8311-f3e9875332a8"
+ (reference "U8") (unit 1) (value "d_srff") (footprint "")
+ )
+ (path "/f62489b4-0411-4b07-999f-f3600f63a488"
+ (reference "U9") (unit 1) (value "d_srff") (footprint "")
+ )
+ (path "/89483b88-5c99-429f-bee3-ebe721b5ecd6"
+ (reference "U10") (unit 1) (value "d_srff") (footprint "")
+ )
+ (path "/0d965701-c921-46c7-82f1-1c586346ef31"
+ (reference "U11") (unit 1) (value "d_srff") (footprint "")
+ )
+ (path "/de3ea695-7fec-4637-9678-6f60494dca66"
+ (reference "U12") (unit 1) (value "d_srff") (footprint "")
+ )
+ (path "/7ced4055-c1a1-4f4e-a2c7-8b7c0d68a50d"
+ (reference "U13") (unit 1) (value "d_srff") (footprint "")
+ )
+ )
+)
diff --git a/library/SubcircuitLibrary/74ls164/74ls164.sub b/library/SubcircuitLibrary/74ls164/74ls164.sub
new file mode 100644
index 000000000..3bf260717
--- /dev/null
+++ b/library/SubcircuitLibrary/74ls164/74ls164.sub
@@ -0,0 +1,54 @@
+* Subcircuit 74ls164
+.subckt 74ls164 /in1 /in2 net-_u8-pad1_ net-_u8-pad6_ net-_u10-pad6_ net-_u12-pad6_ unconnected-_u1-pad7_ /clock /clear net-_u11-pad1_ net-_u9-pad1_ net-_u9-pad6_ net-_u7-pad6_ unconnected-_u1-pad14_
+.title kicad schematic
+* u11 net-_u11-pad1_ net-_u11-pad2_ net-_u8-pad3_ unconnected-_u11-pad4_ net-_u8-pad5_ net-_u9-pad1_ net-_u9-pad2_ d_srff
+* u10 net-_u8-pad6_ net-_u8-pad7_ net-_u8-pad3_ unconnected-_u10-pad4_ net-_u8-pad5_ net-_u10-pad6_ net-_u10-pad7_ d_srff
+* u6 net-_u4-pad2_ net-_u2-pad3_ net-_u8-pad3_ unconnected-_u6-pad4_ net-_u8-pad5_ net-_u8-pad1_ net-_u8-pad2_ d_srff
+* u8 net-_u8-pad1_ net-_u8-pad2_ net-_u8-pad3_ unconnected-_u8-pad4_ net-_u8-pad5_ net-_u8-pad6_ net-_u8-pad7_ d_srff
+* u9 net-_u9-pad1_ net-_u9-pad2_ net-_u8-pad3_ unconnected-_u9-pad4_ net-_u8-pad5_ net-_u9-pad6_ net-_u9-pad7_ d_srff
+* u7 net-_u9-pad6_ net-_u9-pad7_ net-_u8-pad3_ unconnected-_u7-pad4_ net-_u8-pad5_ net-_u7-pad6_ unconnected-_u7-pad7_ d_srff
+* u13 net-_u12-pad6_ net-_u12-pad7_ net-_u8-pad3_ unconnected-_u13-pad4_ net-_u8-pad5_ net-_u11-pad1_ net-_u11-pad2_ d_srff
+* u12 net-_u10-pad6_ net-_u10-pad7_ net-_u8-pad3_ unconnected-_u12-pad4_ net-_u8-pad5_ net-_u12-pad6_ net-_u12-pad7_ d_srff
+* u2 /in1 /in2 net-_u2-pad3_ d_nand
+* u5 /clock net-_u8-pad3_ d_inverter
+* u4 net-_u2-pad3_ net-_u4-pad2_ d_inverter
+* u3 /clear net-_u8-pad5_ d_inverter
+a1 net-_u11-pad1_ net-_u11-pad2_ net-_u8-pad3_ unconnected-_u11-pad4_ net-_u8-pad5_ net-_u9-pad1_ net-_u9-pad2_ u11
+a2 net-_u8-pad6_ net-_u8-pad7_ net-_u8-pad3_ unconnected-_u10-pad4_ net-_u8-pad5_ net-_u10-pad6_ net-_u10-pad7_ u10
+a3 net-_u4-pad2_ net-_u2-pad3_ net-_u8-pad3_ unconnected-_u6-pad4_ net-_u8-pad5_ net-_u8-pad1_ net-_u8-pad2_ u6
+a4 net-_u8-pad1_ net-_u8-pad2_ net-_u8-pad3_ unconnected-_u8-pad4_ net-_u8-pad5_ net-_u8-pad6_ net-_u8-pad7_ u8
+a5 net-_u9-pad1_ net-_u9-pad2_ net-_u8-pad3_ unconnected-_u9-pad4_ net-_u8-pad5_ net-_u9-pad6_ net-_u9-pad7_ u9
+a6 net-_u9-pad6_ net-_u9-pad7_ net-_u8-pad3_ unconnected-_u7-pad4_ net-_u8-pad5_ net-_u7-pad6_ unconnected-_u7-pad7_ u7
+a7 net-_u12-pad6_ net-_u12-pad7_ net-_u8-pad3_ unconnected-_u13-pad4_ net-_u8-pad5_ net-_u11-pad1_ net-_u11-pad2_ u13
+a8 net-_u10-pad6_ net-_u10-pad7_ net-_u8-pad3_ unconnected-_u12-pad4_ net-_u8-pad5_ net-_u12-pad6_ net-_u12-pad7_ u12
+a9 [/in1 /in2 ] net-_u2-pad3_ u2
+a10 /clock net-_u8-pad3_ u5
+a11 net-_u2-pad3_ net-_u4-pad2_ u4
+a12 /clear net-_u8-pad5_ u3
+* Schematic Name: d_srff, Ngspice Name: d_srff
+.model u11 d_srff(clk_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0 ic=0 sr_load=1.0e-12 clk_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 )
+* Schematic Name: d_srff, Ngspice Name: d_srff
+.model u10 d_srff(clk_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0 ic=0 sr_load=1.0e-12 clk_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 )
+* Schematic Name: d_srff, Ngspice Name: d_srff
+.model u6 d_srff(clk_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0 ic=0 sr_load=1.0e-12 clk_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 )
+* Schematic Name: d_srff, Ngspice Name: d_srff
+.model u8 d_srff(clk_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0 ic=0 sr_load=1.0e-12 clk_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 )
+* Schematic Name: d_srff, Ngspice Name: d_srff
+.model u9 d_srff(clk_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0 ic=0 sr_load=1.0e-12 clk_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 )
+* Schematic Name: d_srff, Ngspice Name: d_srff
+.model u7 d_srff(clk_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0 ic=0 sr_load=1.0e-12 clk_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 )
+* Schematic Name: d_srff, Ngspice Name: d_srff
+.model u13 d_srff(clk_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0 ic=0 sr_load=1.0e-12 clk_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 )
+* Schematic Name: d_srff, Ngspice Name: d_srff
+.model u12 d_srff(clk_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0 ic=0 sr_load=1.0e-12 clk_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 )
+* Schematic Name: d_nand, Ngspice Name: d_nand
+.model u2 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, Ngspice Name: d_inverter
+.model u5 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, Ngspice Name: d_inverter
+.model u4 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, Ngspice Name: d_inverter
+.model u3 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Control Statements
+
+.ends 74ls164
\ No newline at end of file
diff --git a/library/SubcircuitLibrary/74ls164/74ls164_Previous_Values.xml b/library/SubcircuitLibrary/74ls164/74ls164_Previous_Values.xml
new file mode 100644
index 000000000..184971a12
--- /dev/null
+++ b/library/SubcircuitLibrary/74ls164/74ls164_Previous_Values.xml
@@ -0,0 +1 @@
+d_srffd_srffd_srffd_srffd_srffd_srffd_srffd_srffd_nandd_inverterd_inverterd_inverterd_srffd_srffd_srffd_srffd_nandd_invertertruefalsefalseHzHz0Volts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or Amperessecsecsec
\ No newline at end of file
diff --git a/library/SubcircuitLibrary/74ls164/analysis b/library/SubcircuitLibrary/74ls164/analysis
new file mode 100644
index 000000000..ebd5c0a94
--- /dev/null
+++ b/library/SubcircuitLibrary/74ls164/analysis
@@ -0,0 +1 @@
+.tran 0e-00 0e-00 0e-00
\ No newline at end of file
diff --git a/library/SubcircuitLibrary/74ls169/3_and-cache.lib b/library/SubcircuitLibrary/74ls169/3_and-cache.lib
new file mode 100644
index 000000000..af0586415
--- /dev/null
+++ b/library/SubcircuitLibrary/74ls169/3_and-cache.lib
@@ -0,0 +1,61 @@
+EESchema-LIBRARY Version 2.3
+#encoding utf-8
+#
+# PORT
+#
+DEF PORT U 0 40 Y Y 26 F N
+F0 "U" 50 100 30 H V C CNN
+F1 "PORT" 0 0 30 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0
+A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50
+S -100 50 100 -50 0 1 0 N
+X ~ 1 250 0 100 L 30 30 1 1 B
+X ~ 2 250 0 100 L 30 30 2 1 B
+X ~ 3 250 0 100 L 30 30 3 1 B
+X ~ 4 250 0 100 L 30 30 4 1 B
+X ~ 5 250 0 100 L 30 30 5 1 B
+X ~ 6 250 0 100 L 30 30 6 1 B
+X ~ 7 250 0 100 L 30 30 7 1 B
+X ~ 8 250 0 100 L 30 30 8 1 B
+X ~ 9 250 0 100 L 30 30 9 1 B
+X ~ 10 250 0 100 L 30 30 10 1 B
+X ~ 11 250 0 100 L 30 30 11 1 B
+X ~ 12 250 0 100 L 30 30 12 1 B
+X ~ 13 250 0 100 L 30 30 13 1 B
+X ~ 14 250 0 100 L 30 30 14 1 B
+X ~ 15 250 0 100 L 30 30 15 1 B
+X ~ 16 250 0 100 L 30 30 16 1 B
+X ~ 17 250 0 100 L 30 30 17 1 B
+X ~ 18 250 0 100 L 30 30 18 1 B
+X ~ 19 250 0 100 L 30 30 19 1 B
+X ~ 20 250 0 100 L 30 30 20 1 B
+X ~ 21 250 0 100 L 30 30 21 1 B
+X ~ 22 250 0 100 L 30 30 22 1 B
+X ~ 23 250 0 100 L 30 30 23 1 B
+X ~ 24 250 0 100 L 30 30 24 1 B
+X ~ 25 250 0 100 L 30 30 25 1 B
+X ~ 26 250 0 100 L 30 30 26 1 B
+ENDDRAW
+ENDDEF
+#
+# d_and
+#
+DEF d_and U 0 40 Y Y 1 F N
+F0 "U" 0 0 60 H V C CNN
+F1 "d_and" 50 100 60 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A 149 50 100 -894 0 0 1 0 N 150 -50 250 50
+A 150 49 100 6 900 0 1 0 N 250 50 150 150
+P 4 0 1 0 150 -50 -250 -50 -250 150 150 150 N
+X IN1 1 -450 100 200 R 50 50 1 1 I
+X IN2 2 -450 0 200 R 50 50 1 1 I
+X OUT 3 450 50 200 L 50 50 1 1 O
+ENDDRAW
+ENDDEF
+#
+#End Library
diff --git a/library/SubcircuitLibrary/74ls169/3_and.cir b/library/SubcircuitLibrary/74ls169/3_and.cir
new file mode 100644
index 000000000..ba296cf01
--- /dev/null
+++ b/library/SubcircuitLibrary/74ls169/3_and.cir
@@ -0,0 +1,13 @@
+* C:\Users\malli\eSim\src\SubcircuitLibrary\3_and\3_and.cir
+
+* EESchema Netlist Version 1.1 (Spice format) creation date: 03/26/19 18:42:57
+
+* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N
+* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0
+
+* Sheet Name: /
+U2 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U2-Pad3_ d_and
+U3 Net-_U2-Pad3_ Net-_U1-Pad3_ Net-_U1-Pad4_ d_and
+U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ PORT
+
+.end
diff --git a/library/SubcircuitLibrary/74ls169/3_and.cir.out b/library/SubcircuitLibrary/74ls169/3_and.cir.out
new file mode 100644
index 000000000..d7cf79a07
--- /dev/null
+++ b/library/SubcircuitLibrary/74ls169/3_and.cir.out
@@ -0,0 +1,20 @@
+* c:\users\malli\esim\src\subcircuitlibrary\3_and\3_and.cir
+
+* u2 net-_u1-pad1_ net-_u1-pad2_ net-_u2-pad3_ d_and
+* u3 net-_u2-pad3_ net-_u1-pad3_ net-_u1-pad4_ d_and
+* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ port
+a1 [net-_u1-pad1_ net-_u1-pad2_ ] net-_u2-pad3_ u2
+a2 [net-_u2-pad3_ net-_u1-pad3_ ] net-_u1-pad4_ u3
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u3 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+.tran 0e-00 0e-00 0e-00
+
+* Control Statements
+.control
+run
+print allv > plot_data_v.txt
+print alli > plot_data_i.txt
+.endc
+.end
diff --git a/library/SubcircuitLibrary/74ls169/3_and.pro b/library/SubcircuitLibrary/74ls169/3_and.pro
new file mode 100644
index 000000000..00597a5ad
--- /dev/null
+++ b/library/SubcircuitLibrary/74ls169/3_and.pro
@@ -0,0 +1,43 @@
+update=05/31/19 15:26:09
+version=1
+last_client=eeschema
+[general]
+version=1
+RootSch=
+BoardNm=
+[pcbnew]
+version=1
+LastNetListRead=
+UseCmpFile=1
+PadDrill=0.600000000000
+PadDrillOvalY=0.600000000000
+PadSizeH=1.500000000000
+PadSizeV=1.500000000000
+PcbTextSizeV=1.500000000000
+PcbTextSizeH=1.500000000000
+PcbTextThickness=0.300000000000
+ModuleTextSizeV=1.000000000000
+ModuleTextSizeH=1.000000000000
+ModuleTextSizeThickness=0.150000000000
+SolderMaskClearance=0.000000000000
+SolderMaskMinWidth=0.000000000000
+DrawSegmentWidth=0.200000000000
+BoardOutlineThickness=0.100000000000
+ModuleOutlineThickness=0.150000000000
+[cvpcb]
+version=1
+NetIExt=net
+[eeschema]
+version=1
+LibDir=../../../kicadSchematicLibrary
+[eeschema/libraries]
+LibName1=eSim_Analog
+LibName2=eSim_Devices
+LibName3=eSim_Digital
+LibName4=eSim_Hybrid
+LibName5=eSim_Miscellaneous
+LibName6=eSim_Plot
+LibName7=eSim_Power
+LibName8=eSim_User
+LibName9=eSim_Sources
+LibName10=eSim_Subckt
diff --git a/library/SubcircuitLibrary/74ls169/3_and.sch b/library/SubcircuitLibrary/74ls169/3_and.sch
new file mode 100644
index 000000000..d6ac89f95
--- /dev/null
+++ b/library/SubcircuitLibrary/74ls169/3_and.sch
@@ -0,0 +1,130 @@
+EESchema Schematic File Version 2
+LIBS:power
+LIBS:texas
+LIBS:intel
+LIBS:audio
+LIBS:interface
+LIBS:digital-audio
+LIBS:philips
+LIBS:display
+LIBS:cypress
+LIBS:siliconi
+LIBS:opto
+LIBS:atmel
+LIBS:contrib
+LIBS:valves
+LIBS:eSim_Analog
+LIBS:eSim_Devices
+LIBS:eSim_Digital
+LIBS:eSim_Hybrid
+LIBS:eSim_Miscellaneous
+LIBS:eSim_Plot
+LIBS:eSim_Power
+LIBS:eSim_PSpice
+LIBS:eSim_Sources
+LIBS:eSim_Subckt
+LIBS:eSim_User
+LIBS:3_and-cache
+EELAYER 25 0
+EELAYER END
+$Descr A4 11693 8268
+encoding utf-8
+Sheet 1 1
+Title ""
+Date ""
+Rev ""
+Comp ""
+Comment1 ""
+Comment2 ""
+Comment3 ""
+Comment4 ""
+$EndDescr
+$Comp
+L d_and U2
+U 1 1 5C9A24D8
+P 4250 2700
+F 0 "U2" H 4250 2700 60 0000 C CNN
+F 1 "d_and" H 4300 2800 60 0000 C CNN
+F 2 "" H 4250 2700 60 0000 C CNN
+F 3 "" H 4250 2700 60 0000 C CNN
+ 1 4250 2700
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_and U3
+U 1 1 5C9A2538
+P 5150 2900
+F 0 "U3" H 5150 2900 60 0000 C CNN
+F 1 "d_and" H 5200 3000 60 0000 C CNN
+F 2 "" H 5150 2900 60 0000 C CNN
+F 3 "" H 5150 2900 60 0000 C CNN
+ 1 5150 2900
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 1 1 5C9A259A
+P 3050 2600
+F 0 "U1" H 3100 2700 30 0000 C CNN
+F 1 "PORT" H 3050 2600 30 0000 C CNN
+F 2 "" H 3050 2600 60 0000 C CNN
+F 3 "" H 3050 2600 60 0000 C CNN
+ 1 3050 2600
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 2 1 5C9A25D9
+P 3050 2800
+F 0 "U1" H 3100 2900 30 0000 C CNN
+F 1 "PORT" H 3050 2800 30 0000 C CNN
+F 2 "" H 3050 2800 60 0000 C CNN
+F 3 "" H 3050 2800 60 0000 C CNN
+ 2 3050 2800
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 3 1 5C9A260A
+P 3050 3100
+F 0 "U1" H 3100 3200 30 0000 C CNN
+F 1 "PORT" H 3050 3100 30 0000 C CNN
+F 2 "" H 3050 3100 60 0000 C CNN
+F 3 "" H 3050 3100 60 0000 C CNN
+ 3 3050 3100
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 4 1 5C9A2637
+P 6900 2850
+F 0 "U1" H 6950 2950 30 0000 C CNN
+F 1 "PORT" H 6900 2850 30 0000 C CNN
+F 2 "" H 6900 2850 60 0000 C CNN
+F 3 "" H 6900 2850 60 0000 C CNN
+ 4 6900 2850
+ -1 0 0 1
+$EndComp
+Wire Wire Line
+ 4700 2650 4700 2800
+Wire Wire Line
+ 5600 2850 6650 2850
+Wire Wire Line
+ 3800 2600 3300 2600
+Wire Wire Line
+ 3800 2700 3300 2700
+Wire Wire Line
+ 3300 2700 3300 2800
+Wire Wire Line
+ 3300 3100 4700 3100
+Wire Wire Line
+ 4700 3100 4700 2900
+Text Notes 3500 2600 0 60 ~ 12
+in1
+Text Notes 3450 2800 0 60 ~ 12
+in2\n
+Text Notes 3500 3100 0 60 ~ 12
+in3
+Text Notes 6100 2850 0 60 ~ 12
+out
+$EndSCHEMATC
diff --git a/library/SubcircuitLibrary/74ls169/3_and.sub b/library/SubcircuitLibrary/74ls169/3_and.sub
new file mode 100644
index 000000000..3d9120bb6
--- /dev/null
+++ b/library/SubcircuitLibrary/74ls169/3_and.sub
@@ -0,0 +1,14 @@
+* Subcircuit 3_and
+.subckt 3_and net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_
+* c:\users\malli\esim\src\subcircuitlibrary\3_and\3_and.cir
+* u2 net-_u1-pad1_ net-_u1-pad2_ net-_u2-pad3_ d_and
+* u3 net-_u2-pad3_ net-_u1-pad3_ net-_u1-pad4_ d_and
+a1 [net-_u1-pad1_ net-_u1-pad2_ ] net-_u2-pad3_ u2
+a2 [net-_u2-pad3_ net-_u1-pad3_ ] net-_u1-pad4_ u3
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u3 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+* Control Statements
+
+.ends 3_and
\ No newline at end of file
diff --git a/library/SubcircuitLibrary/74ls169/3_and_Previous_Values.xml b/library/SubcircuitLibrary/74ls169/3_and_Previous_Values.xml
new file mode 100644
index 000000000..abc5faaae
--- /dev/null
+++ b/library/SubcircuitLibrary/74ls169/3_and_Previous_Values.xml
@@ -0,0 +1 @@
+d_andd_andtruefalsefalseHzHz0Volts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesSecSecSec
\ No newline at end of file
diff --git a/library/SubcircuitLibrary/74ls169/4_OR-cache.lib b/library/SubcircuitLibrary/74ls169/4_OR-cache.lib
new file mode 100644
index 000000000..155f5e601
--- /dev/null
+++ b/library/SubcircuitLibrary/74ls169/4_OR-cache.lib
@@ -0,0 +1,63 @@
+EESchema-LIBRARY Version 2.3
+#encoding utf-8
+#
+# PORT
+#
+DEF PORT U 0 40 Y Y 26 F N
+F0 "U" 50 100 30 H V C CNN
+F1 "PORT" 0 0 30 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0
+A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50
+S -100 50 100 -50 0 1 0 N
+X ~ 1 250 0 100 L 30 30 1 1 B
+X ~ 2 250 0 100 L 30 30 2 1 B
+X ~ 3 250 0 100 L 30 30 3 1 B
+X ~ 4 250 0 100 L 30 30 4 1 B
+X ~ 5 250 0 100 L 30 30 5 1 B
+X ~ 6 250 0 100 L 30 30 6 1 B
+X ~ 7 250 0 100 L 30 30 7 1 B
+X ~ 8 250 0 100 L 30 30 8 1 B
+X ~ 9 250 0 100 L 30 30 9 1 B
+X ~ 10 250 0 100 L 30 30 10 1 B
+X ~ 11 250 0 100 L 30 30 11 1 B
+X ~ 12 250 0 100 L 30 30 12 1 B
+X ~ 13 250 0 100 L 30 30 13 1 B
+X ~ 14 250 0 100 L 30 30 14 1 B
+X ~ 15 250 0 100 L 30 30 15 1 B
+X ~ 16 250 0 100 L 30 30 16 1 B
+X ~ 17 250 0 100 L 30 30 17 1 B
+X ~ 18 250 0 100 L 30 30 18 1 B
+X ~ 19 250 0 100 L 30 30 19 1 B
+X ~ 20 250 0 100 L 30 30 20 1 B
+X ~ 21 250 0 100 L 30 30 21 1 B
+X ~ 22 250 0 100 L 30 30 22 1 B
+X ~ 23 250 0 100 L 30 30 23 1 B
+X ~ 24 250 0 100 L 30 30 24 1 B
+X ~ 25 250 0 100 L 30 30 25 1 B
+X ~ 26 250 0 100 L 30 30 26 1 B
+ENDDRAW
+ENDDEF
+#
+# d_or
+#
+DEF d_or U 0 40 Y Y 1 F N
+F0 "U" 0 0 60 H V C CNN
+F1 "d_or" 0 100 60 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A -450 50 224 266 -266 0 1 0 N -250 150 -250 -50
+A -25 -124 325 574 323 0 1 0 N 150 150 250 50
+A 74 125 191 -665 -231 0 1 0 N 150 -50 250 50
+P 2 0 1 0 -250 -50 150 -50 N
+P 2 0 1 0 -250 150 150 150 N
+X IN1 1 -450 100 215 R 50 50 1 1 I
+X IN2 2 -450 0 215 R 50 50 1 1 I
+X OUT 3 450 50 200 L 50 50 1 1 O
+ENDDRAW
+ENDDEF
+#
+#End Library
diff --git a/library/SubcircuitLibrary/74ls169/4_OR.cir b/library/SubcircuitLibrary/74ls169/4_OR.cir
new file mode 100644
index 000000000..b338b7b5f
--- /dev/null
+++ b/library/SubcircuitLibrary/74ls169/4_OR.cir
@@ -0,0 +1,14 @@
+* C:\Users\malli\eSim\src\SubcircuitLibrary\4_OR\4_OR.cir
+
+* EESchema Netlist Version 1.1 (Spice format) creation date: 03/28/19 22:47:12
+
+* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N
+* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0
+
+* Sheet Name: /
+U2 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U2-Pad3_ d_or
+U3 Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U3-Pad3_ d_or
+U4 Net-_U2-Pad3_ Net-_U3-Pad3_ Net-_U1-Pad5_ d_or
+U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ PORT
+
+.end
diff --git a/library/SubcircuitLibrary/74ls169/4_OR.cir.out b/library/SubcircuitLibrary/74ls169/4_OR.cir.out
new file mode 100644
index 000000000..adb6b01be
--- /dev/null
+++ b/library/SubcircuitLibrary/74ls169/4_OR.cir.out
@@ -0,0 +1,24 @@
+* c:\users\malli\esim\src\subcircuitlibrary\4_or\4_or.cir
+
+* u2 net-_u1-pad1_ net-_u1-pad2_ net-_u2-pad3_ d_or
+* u3 net-_u1-pad3_ net-_u1-pad4_ net-_u3-pad3_ d_or
+* u4 net-_u2-pad3_ net-_u3-pad3_ net-_u1-pad5_ d_or
+* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ port
+a1 [net-_u1-pad1_ net-_u1-pad2_ ] net-_u2-pad3_ u2
+a2 [net-_u1-pad3_ net-_u1-pad4_ ] net-_u3-pad3_ u3
+a3 [net-_u2-pad3_ net-_u3-pad3_ ] net-_u1-pad5_ u4
+* Schematic Name: d_or, NgSpice Name: d_or
+.model u2 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+* Schematic Name: d_or, NgSpice Name: d_or
+.model u3 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+* Schematic Name: d_or, NgSpice Name: d_or
+.model u4 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+.tran 0e-00 0e-00 0e-00
+
+* Control Statements
+.control
+run
+print allv > plot_data_v.txt
+print alli > plot_data_i.txt
+.endc
+.end
diff --git a/library/SubcircuitLibrary/74ls169/4_OR.pro b/library/SubcircuitLibrary/74ls169/4_OR.pro
new file mode 100644
index 000000000..881563ebd
--- /dev/null
+++ b/library/SubcircuitLibrary/74ls169/4_OR.pro
@@ -0,0 +1,44 @@
+update=06/01/19 12:36:09
+version=1
+last_client=eeschema
+[general]
+version=1
+RootSch=
+BoardNm=
+[pcbnew]
+version=1
+LastNetListRead=
+UseCmpFile=1
+PadDrill=0.600000000000
+PadDrillOvalY=0.600000000000
+PadSizeH=1.500000000000
+PadSizeV=1.500000000000
+PcbTextSizeV=1.500000000000
+PcbTextSizeH=1.500000000000
+PcbTextThickness=0.300000000000
+ModuleTextSizeV=1.000000000000
+ModuleTextSizeH=1.000000000000
+ModuleTextSizeThickness=0.150000000000
+SolderMaskClearance=0.000000000000
+SolderMaskMinWidth=0.000000000000
+DrawSegmentWidth=0.200000000000
+BoardOutlineThickness=0.100000000000
+ModuleOutlineThickness=0.150000000000
+[cvpcb]
+version=1
+NetIExt=net
+[eeschema]
+version=1
+LibDir=../../../kicadSchematicLibrary
+[eeschema/libraries]
+LibName1=power
+LibName2=eSim_Analog
+LibName3=eSim_Devices
+LibName4=eSim_Digital
+LibName5=eSim_Hybrid
+LibName6=eSim_Miscellaneous
+LibName7=eSim_Plot
+LibName8=eSim_Power
+LibName9=eSim_User
+LibName10=eSim_Sources
+LibName11=eSim_Subckt
diff --git a/library/SubcircuitLibrary/74ls169/4_OR.sch b/library/SubcircuitLibrary/74ls169/4_OR.sch
new file mode 100644
index 000000000..118968656
--- /dev/null
+++ b/library/SubcircuitLibrary/74ls169/4_OR.sch
@@ -0,0 +1,150 @@
+EESchema Schematic File Version 2
+LIBS:power
+LIBS:eSim_Analog
+LIBS:eSim_Devices
+LIBS:eSim_Digital
+LIBS:eSim_Hybrid
+LIBS:eSim_Miscellaneous
+LIBS:eSim_Plot
+LIBS:eSim_Power
+LIBS:eSim_PSpice
+LIBS:eSim_Sources
+LIBS:eSim_Subckt
+LIBS:eSim_User
+EELAYER 25 0
+EELAYER END
+$Descr A4 11693 8268
+encoding utf-8
+Sheet 1 1
+Title ""
+Date ""
+Rev ""
+Comp ""
+Comment1 ""
+Comment2 ""
+Comment3 ""
+Comment4 ""
+$EndDescr
+$Comp
+L d_or U2
+U 1 1 5C9D00E1
+P 4300 2950
+F 0 "U2" H 4300 2950 60 0000 C CNN
+F 1 "d_or" H 4300 3050 60 0000 C CNN
+F 2 "" H 4300 2950 60 0000 C CNN
+F 3 "" H 4300 2950 60 0000 C CNN
+ 1 4300 2950
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_or U3
+U 1 1 5C9D011F
+P 4300 3350
+F 0 "U3" H 4300 3350 60 0000 C CNN
+F 1 "d_or" H 4300 3450 60 0000 C CNN
+F 2 "" H 4300 3350 60 0000 C CNN
+F 3 "" H 4300 3350 60 0000 C CNN
+ 1 4300 3350
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_or U4
+U 1 1 5C9D0141
+P 5250 3150
+F 0 "U4" H 5250 3150 60 0000 C CNN
+F 1 "d_or" H 5250 3250 60 0000 C CNN
+F 2 "" H 5250 3150 60 0000 C CNN
+F 3 "" H 5250 3150 60 0000 C CNN
+ 1 5250 3150
+ 1 0 0 -1
+$EndComp
+Wire Wire Line
+ 4800 3050 4800 2900
+Wire Wire Line
+ 4800 2900 4750 2900
+Wire Wire Line
+ 4800 3150 4800 3300
+Wire Wire Line
+ 4800 3300 4750 3300
+Wire Wire Line
+ 3350 2850 3850 2850
+Wire Wire Line
+ 3850 2950 3600 2950
+Wire Wire Line
+ 3850 3250 3350 3250
+Wire Wire Line
+ 3600 2950 3600 3000
+Wire Wire Line
+ 3600 3000 3350 3000
+Wire Wire Line
+ 3850 3350 3850 3400
+Wire Wire Line
+ 3850 3400 3350 3400
+Wire Wire Line
+ 5700 3100 6200 3100
+$Comp
+L PORT U1
+U 1 1 5C9D01F4
+P 3100 2850
+F 0 "U1" H 3150 2950 30 0000 C CNN
+F 1 "PORT" H 3100 2850 30 0000 C CNN
+F 2 "" H 3100 2850 60 0000 C CNN
+F 3 "" H 3100 2850 60 0000 C CNN
+ 1 3100 2850
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 2 1 5C9D022F
+P 3100 3000
+F 0 "U1" H 3150 3100 30 0000 C CNN
+F 1 "PORT" H 3100 3000 30 0000 C CNN
+F 2 "" H 3100 3000 60 0000 C CNN
+F 3 "" H 3100 3000 60 0000 C CNN
+ 2 3100 3000
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 3 1 5C9D0271
+P 3100 3250
+F 0 "U1" H 3150 3350 30 0000 C CNN
+F 1 "PORT" H 3100 3250 30 0000 C CNN
+F 2 "" H 3100 3250 60 0000 C CNN
+F 3 "" H 3100 3250 60 0000 C CNN
+ 3 3100 3250
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 4 1 5C9D0299
+P 3100 3400
+F 0 "U1" H 3150 3500 30 0000 C CNN
+F 1 "PORT" H 3100 3400 30 0000 C CNN
+F 2 "" H 3100 3400 60 0000 C CNN
+F 3 "" H 3100 3400 60 0000 C CNN
+ 4 3100 3400
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 5 1 5C9D02C2
+P 6450 3100
+F 0 "U1" H 6500 3200 30 0000 C CNN
+F 1 "PORT" H 6450 3100 30 0000 C CNN
+F 2 "" H 6450 3100 60 0000 C CNN
+F 3 "" H 6450 3100 60 0000 C CNN
+ 5 6450 3100
+ -1 0 0 1
+$EndComp
+Text Notes 3450 2850 0 60 ~ 12
+in1
+Text Notes 3450 3000 0 60 ~ 12
+in2
+Text Notes 3450 3250 0 60 ~ 12
+in3
+Text Notes 3450 3400 0 60 ~ 12
+in4
+Text Notes 5800 3100 0 60 ~ 12
+out
+$EndSCHEMATC
diff --git a/library/SubcircuitLibrary/74ls169/4_OR.sub b/library/SubcircuitLibrary/74ls169/4_OR.sub
new file mode 100644
index 000000000..d1fd3a241
--- /dev/null
+++ b/library/SubcircuitLibrary/74ls169/4_OR.sub
@@ -0,0 +1,18 @@
+* Subcircuit 4_OR
+.subckt 4_OR net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_
+* c:\users\malli\esim\src\subcircuitlibrary\4_or\4_or.cir
+* u2 net-_u1-pad1_ net-_u1-pad2_ net-_u2-pad3_ d_or
+* u3 net-_u1-pad3_ net-_u1-pad4_ net-_u3-pad3_ d_or
+* u4 net-_u2-pad3_ net-_u3-pad3_ net-_u1-pad5_ d_or
+a1 [net-_u1-pad1_ net-_u1-pad2_ ] net-_u2-pad3_ u2
+a2 [net-_u1-pad3_ net-_u1-pad4_ ] net-_u3-pad3_ u3
+a3 [net-_u2-pad3_ net-_u3-pad3_ ] net-_u1-pad5_ u4
+* Schematic Name: d_or, NgSpice Name: d_or
+.model u2 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+* Schematic Name: d_or, NgSpice Name: d_or
+.model u3 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+* Schematic Name: d_or, NgSpice Name: d_or
+.model u4 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+* Control Statements
+
+.ends 4_OR
\ No newline at end of file
diff --git a/library/SubcircuitLibrary/74ls169/4_OR_Previous_Values.xml b/library/SubcircuitLibrary/74ls169/4_OR_Previous_Values.xml
new file mode 100644
index 000000000..0683d9eb6
--- /dev/null
+++ b/library/SubcircuitLibrary/74ls169/4_OR_Previous_Values.xml
@@ -0,0 +1 @@
+d_ord_ord_ortruefalsefalseHzHz0Volts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesSecSecSec
\ No newline at end of file
diff --git a/library/SubcircuitLibrary/74ls169/4_and-cache.lib b/library/SubcircuitLibrary/74ls169/4_and-cache.lib
new file mode 100644
index 000000000..60f1a83d4
--- /dev/null
+++ b/library/SubcircuitLibrary/74ls169/4_and-cache.lib
@@ -0,0 +1,79 @@
+EESchema-LIBRARY Version 2.3
+#encoding utf-8
+#
+# 3_and-RESCUE-4_and
+#
+DEF 3_and-RESCUE-4_and X 0 40 Y Y 1 F N
+F0 "X" 900 300 60 H V C CNN
+F1 "3_and-RESCUE-4_and" 950 500 60 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A 950 400 158 716 -716 0 1 0 N 1000 550 1000 250
+P 2 0 1 0 650 550 1000 550 N
+P 3 0 1 0 650 550 650 250 1000 250 N
+X in1 1 450 500 200 R 50 50 1 1 I
+X in2 2 450 400 200 R 50 50 1 1 I
+X in3 3 450 300 200 R 50 50 1 1 I
+X out 4 1300 400 200 L 50 50 1 1 O
+ENDDRAW
+ENDDEF
+#
+# PORT
+#
+DEF PORT U 0 40 Y Y 26 F N
+F0 "U" 50 100 30 H V C CNN
+F1 "PORT" 0 0 30 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0
+A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50
+S -100 50 100 -50 0 1 0 N
+X ~ 1 250 0 100 L 30 30 1 1 B
+X ~ 2 250 0 100 L 30 30 2 1 B
+X ~ 3 250 0 100 L 30 30 3 1 B
+X ~ 4 250 0 100 L 30 30 4 1 B
+X ~ 5 250 0 100 L 30 30 5 1 B
+X ~ 6 250 0 100 L 30 30 6 1 B
+X ~ 7 250 0 100 L 30 30 7 1 B
+X ~ 8 250 0 100 L 30 30 8 1 B
+X ~ 9 250 0 100 L 30 30 9 1 B
+X ~ 10 250 0 100 L 30 30 10 1 B
+X ~ 11 250 0 100 L 30 30 11 1 B
+X ~ 12 250 0 100 L 30 30 12 1 B
+X ~ 13 250 0 100 L 30 30 13 1 B
+X ~ 14 250 0 100 L 30 30 14 1 B
+X ~ 15 250 0 100 L 30 30 15 1 B
+X ~ 16 250 0 100 L 30 30 16 1 B
+X ~ 17 250 0 100 L 30 30 17 1 B
+X ~ 18 250 0 100 L 30 30 18 1 B
+X ~ 19 250 0 100 L 30 30 19 1 B
+X ~ 20 250 0 100 L 30 30 20 1 B
+X ~ 21 250 0 100 L 30 30 21 1 B
+X ~ 22 250 0 100 L 30 30 22 1 B
+X ~ 23 250 0 100 L 30 30 23 1 B
+X ~ 24 250 0 100 L 30 30 24 1 B
+X ~ 25 250 0 100 L 30 30 25 1 B
+X ~ 26 250 0 100 L 30 30 26 1 B
+ENDDRAW
+ENDDEF
+#
+# d_and
+#
+DEF d_and U 0 40 Y Y 1 F N
+F0 "U" 0 0 60 H V C CNN
+F1 "d_and" 50 100 60 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A 149 50 100 -894 0 0 1 0 N 150 -50 250 50
+A 150 49 100 6 900 0 1 0 N 250 50 150 150
+P 4 0 1 0 150 -50 -250 -50 -250 150 150 150 N
+X IN1 1 -450 100 200 R 50 50 1 1 I
+X IN2 2 -450 0 200 R 50 50 1 1 I
+X OUT 3 450 50 200 L 50 50 1 1 O
+ENDDRAW
+ENDDEF
+#
+#End Library
diff --git a/library/SubcircuitLibrary/74ls169/4_and-rescue.lib b/library/SubcircuitLibrary/74ls169/4_and-rescue.lib
new file mode 100644
index 000000000..e38330518
--- /dev/null
+++ b/library/SubcircuitLibrary/74ls169/4_and-rescue.lib
@@ -0,0 +1,22 @@
+EESchema-LIBRARY Version 2.3
+#encoding utf-8
+#
+# 3_and-RESCUE-4_and
+#
+DEF 3_and-RESCUE-4_and X 0 40 Y Y 1 F N
+F0 "X" 900 300 60 H V C CNN
+F1 "3_and-RESCUE-4_and" 950 500 60 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A 950 400 158 716 -716 0 1 0 N 1000 550 1000 250
+P 2 0 1 0 650 550 1000 550 N
+P 3 0 1 0 650 550 650 250 1000 250 N
+X in1 1 450 500 200 R 50 50 1 1 I
+X in2 2 450 400 200 R 50 50 1 1 I
+X in3 3 450 300 200 R 50 50 1 1 I
+X out 4 1300 400 200 L 50 50 1 1 O
+ENDDRAW
+ENDDEF
+#
+#End Library
diff --git a/library/SubcircuitLibrary/74ls169/4_and.cir b/library/SubcircuitLibrary/74ls169/4_and.cir
new file mode 100644
index 000000000..fdf2e1074
--- /dev/null
+++ b/library/SubcircuitLibrary/74ls169/4_and.cir
@@ -0,0 +1,13 @@
+* C:\Users\malli\eSim\src\SubcircuitLibrary\4_and\4_and.cir
+
+* EESchema Netlist Version 1.1 (Spice format) creation date: 06/01/19 13:09:58
+
+* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N
+* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0
+
+* Sheet Name: /
+X1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U2-Pad1_ 3_and
+U2 Net-_U2-Pad1_ Net-_U1-Pad4_ Net-_U1-Pad5_ d_and
+U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ PORT
+
+.end
diff --git a/library/SubcircuitLibrary/74ls169/4_and.cir.out b/library/SubcircuitLibrary/74ls169/4_and.cir.out
new file mode 100644
index 000000000..f40e5bc62
--- /dev/null
+++ b/library/SubcircuitLibrary/74ls169/4_and.cir.out
@@ -0,0 +1,18 @@
+* c:\users\malli\esim\src\subcircuitlibrary\4_and\4_and.cir
+
+.include 3_and.sub
+x1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u2-pad1_ 3_and
+* u2 net-_u2-pad1_ net-_u1-pad4_ net-_u1-pad5_ d_and
+* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ port
+a1 [net-_u2-pad1_ net-_u1-pad4_ ] net-_u1-pad5_ u2
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+.tran 0e-00 0e-00 0e-00
+
+* Control Statements
+.control
+run
+print allv > plot_data_v.txt
+print alli > plot_data_i.txt
+.endc
+.end
diff --git a/library/SubcircuitLibrary/74ls169/4_and.pro b/library/SubcircuitLibrary/74ls169/4_and.pro
new file mode 100644
index 000000000..b13a0a825
--- /dev/null
+++ b/library/SubcircuitLibrary/74ls169/4_and.pro
@@ -0,0 +1,57 @@
+update=Wed Mar 18 19:54:24 2020
+version=1
+last_client=eeschema
+[general]
+version=1
+RootSch=
+BoardNm=
+[pcbnew]
+version=1
+LastNetListRead=
+UseCmpFile=1
+PadDrill=0.600000000000
+PadDrillOvalY=0.600000000000
+PadSizeH=1.500000000000
+PadSizeV=1.500000000000
+PcbTextSizeV=1.500000000000
+PcbTextSizeH=1.500000000000
+PcbTextThickness=0.300000000000
+ModuleTextSizeV=1.000000000000
+ModuleTextSizeH=1.000000000000
+ModuleTextSizeThickness=0.150000000000
+SolderMaskClearance=0.000000000000
+SolderMaskMinWidth=0.000000000000
+DrawSegmentWidth=0.200000000000
+BoardOutlineThickness=0.100000000000
+ModuleOutlineThickness=0.150000000000
+[cvpcb]
+version=1
+NetIExt=net
+[eeschema]
+version=1
+LibDir=../../../kicadSchematicLibrary
+[eeschema/libraries]
+LibName1=4_and-rescue
+LibName2=texas
+LibName3=intel
+LibName4=audio
+LibName5=interface
+LibName6=digital-audio
+LibName7=philips
+LibName8=display
+LibName9=cypress
+LibName10=siliconi
+LibName11=opto
+LibName12=atmel
+LibName13=contrib
+LibName14=valves
+LibName15=eSim_Analog
+LibName16=eSim_Devices
+LibName17=eSim_Digital
+LibName18=eSim_Hybrid
+LibName19=eSim_Miscellaneous
+LibName20=eSim_Plot
+LibName21=eSim_Power
+LibName22=eSim_Sources
+LibName23=eSim_Subckt
+LibName24=eSim_User
diff --git a/library/SubcircuitLibrary/74ls169/4_and.sch b/library/SubcircuitLibrary/74ls169/4_and.sch
new file mode 100644
index 000000000..f5e8febdc
--- /dev/null
+++ b/library/SubcircuitLibrary/74ls169/4_and.sch
@@ -0,0 +1,151 @@
+EESchema Schematic File Version 2
+LIBS:4_and-rescue
+LIBS:texas
+LIBS:intel
+LIBS:audio
+LIBS:interface
+LIBS:digital-audio
+LIBS:philips
+LIBS:display
+LIBS:cypress
+LIBS:siliconi
+LIBS:opto
+LIBS:atmel
+LIBS:contrib
+LIBS:valves
+LIBS:eSim_Analog
+LIBS:eSim_Devices
+LIBS:eSim_Digital
+LIBS:eSim_Hybrid
+LIBS:eSim_Miscellaneous
+LIBS:eSim_Plot
+LIBS:eSim_Power
+LIBS:eSim_PSpice
+LIBS:eSim_Sources
+LIBS:eSim_Subckt
+LIBS:eSim_User
+LIBS:4_and-cache
+EELAYER 25 0
+EELAYER END
+$Descr A4 11693 8268
+encoding utf-8
+Sheet 1 1
+Title ""
+Date ""
+Rev ""
+Comp ""
+Comment1 ""
+Comment2 ""
+Comment3 ""
+Comment4 ""
+$EndDescr
+$Comp
+L 3_and-RESCUE-4_and X1
+U 1 1 5C9A2915
+P 3700 3500
+F 0 "X1" H 4600 3800 60 0000 C CNN
+F 1 "3_and" H 4650 4000 60 0000 C CNN
+F 2 "" H 3700 3500 60 0000 C CNN
+F 3 "" H 3700 3500 60 0000 C CNN
+ 1 3700 3500
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_and U2
+U 1 1 5C9A2940
+P 5450 3400
+F 0 "U2" H 5450 3400 60 0000 C CNN
+F 1 "d_and" H 5500 3500 60 0000 C CNN
+F 2 "" H 5450 3400 60 0000 C CNN
+F 3 "" H 5450 3400 60 0000 C CNN
+ 1 5450 3400
+ 1 0 0 -1
+$EndComp
+Wire Wire Line
+ 5000 3100 5000 3300
+Wire Wire Line
+ 4150 3000 4150 2700
+Wire Wire Line
+ 4150 2700 3200 2700
+Wire Wire Line
+ 4150 3100 4000 3100
+Wire Wire Line
+ 4000 3100 4000 3000
+Wire Wire Line
+ 4000 3000 3200 3000
+Wire Wire Line
+ 4150 3200 4150 3300
+Wire Wire Line
+ 4150 3300 3250 3300
+Wire Wire Line
+ 5000 3400 5000 3550
+Wire Wire Line
+ 5000 3550 3250 3550
+Wire Wire Line
+ 5900 3350 6500 3350
+$Comp
+L PORT U1
+U 1 1 5C9A29B1
+P 2950 2700
+F 0 "U1" H 3000 2800 30 0000 C CNN
+F 1 "PORT" H 2950 2700 30 0000 C CNN
+F 2 "" H 2950 2700 60 0000 C CNN
+F 3 "" H 2950 2700 60 0000 C CNN
+ 1 2950 2700
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 2 1 5C9A29E9
+P 2950 3000
+F 0 "U1" H 3000 3100 30 0000 C CNN
+F 1 "PORT" H 2950 3000 30 0000 C CNN
+F 2 "" H 2950 3000 60 0000 C CNN
+F 3 "" H 2950 3000 60 0000 C CNN
+ 2 2950 3000
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 3 1 5C9A2A0D
+P 3000 3300
+F 0 "U1" H 3050 3400 30 0000 C CNN
+F 1 "PORT" H 3000 3300 30 0000 C CNN
+F 2 "" H 3000 3300 60 0000 C CNN
+F 3 "" H 3000 3300 60 0000 C CNN
+ 3 3000 3300
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 4 1 5C9A2A3C
+P 3000 3550
+F 0 "U1" H 3050 3650 30 0000 C CNN
+F 1 "PORT" H 3000 3550 30 0000 C CNN
+F 2 "" H 3000 3550 60 0000 C CNN
+F 3 "" H 3000 3550 60 0000 C CNN
+ 4 3000 3550
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 5 1 5C9A2A68
+P 6750 3350
+F 0 "U1" H 6800 3450 30 0000 C CNN
+F 1 "PORT" H 6750 3350 30 0000 C CNN
+F 2 "" H 6750 3350 60 0000 C CNN
+F 3 "" H 6750 3350 60 0000 C CNN
+ 5 6750 3350
+ -1 0 0 1
+$EndComp
+Text Notes 3450 2650 0 60 ~ 12
+in1
+Text Notes 3450 2950 0 60 ~ 12
+in2
+Text Notes 3500 3300 0 60 ~ 12
+in3
+Text Notes 3500 3550 0 60 ~ 12
+in4
+Text Notes 6150 3350 0 60 ~ 12
+out
+$EndSCHEMATC
diff --git a/library/SubcircuitLibrary/74ls169/4_and.sub b/library/SubcircuitLibrary/74ls169/4_and.sub
new file mode 100644
index 000000000..8663f37e6
--- /dev/null
+++ b/library/SubcircuitLibrary/74ls169/4_and.sub
@@ -0,0 +1,12 @@
+* Subcircuit 4_and
+.subckt 4_and net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_
+* c:\users\malli\esim\src\subcircuitlibrary\4_and\4_and.cir
+.include 3_and.sub
+x1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u2-pad1_ 3_and
+* u2 net-_u2-pad1_ net-_u1-pad4_ net-_u1-pad5_ d_and
+a1 [net-_u2-pad1_ net-_u1-pad4_ ] net-_u1-pad5_ u2
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+* Control Statements
+
+.ends 4_and
\ No newline at end of file
diff --git a/library/SubcircuitLibrary/74ls169/4_and_Previous_Values.xml b/library/SubcircuitLibrary/74ls169/4_and_Previous_Values.xml
new file mode 100644
index 000000000..f2ba0130e
--- /dev/null
+++ b/library/SubcircuitLibrary/74ls169/4_and_Previous_Values.xml
@@ -0,0 +1 @@
+d_andC:\Users\malli\eSim\src\SubcircuitLibrary\3_andtruefalsefalseHzHz0Volts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesSecSecSec
\ No newline at end of file
diff --git a/library/SubcircuitLibrary/74ls169/5_and-cache.lib b/library/SubcircuitLibrary/74ls169/5_and-cache.lib
new file mode 100644
index 000000000..fc177c1f9
--- /dev/null
+++ b/library/SubcircuitLibrary/74ls169/5_and-cache.lib
@@ -0,0 +1,79 @@
+EESchema-LIBRARY Version 2.3
+#encoding utf-8
+#
+# 3_and-RESCUE-5_and
+#
+DEF 3_and-RESCUE-5_and X 0 40 Y Y 1 F N
+F0 "X" 900 300 60 H V C CNN
+F1 "3_and-RESCUE-5_and" 950 500 60 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A 950 400 158 716 -716 0 1 0 N 1000 550 1000 250
+P 2 0 1 0 650 550 1000 550 N
+P 3 0 1 0 650 550 650 250 1000 250 N
+X in1 1 450 500 200 R 50 50 1 1 I
+X in2 2 450 400 200 R 50 50 1 1 I
+X in3 3 450 300 200 R 50 50 1 1 I
+X out 4 1300 400 200 L 50 50 1 1 O
+ENDDRAW
+ENDDEF
+#
+# PORT
+#
+DEF PORT U 0 40 Y Y 26 F N
+F0 "U" 50 100 30 H V C CNN
+F1 "PORT" 0 0 30 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0
+A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50
+S -100 50 100 -50 0 1 0 N
+X ~ 1 250 0 100 L 30 30 1 1 B
+X ~ 2 250 0 100 L 30 30 2 1 B
+X ~ 3 250 0 100 L 30 30 3 1 B
+X ~ 4 250 0 100 L 30 30 4 1 B
+X ~ 5 250 0 100 L 30 30 5 1 B
+X ~ 6 250 0 100 L 30 30 6 1 B
+X ~ 7 250 0 100 L 30 30 7 1 B
+X ~ 8 250 0 100 L 30 30 8 1 B
+X ~ 9 250 0 100 L 30 30 9 1 B
+X ~ 10 250 0 100 L 30 30 10 1 B
+X ~ 11 250 0 100 L 30 30 11 1 B
+X ~ 12 250 0 100 L 30 30 12 1 B
+X ~ 13 250 0 100 L 30 30 13 1 B
+X ~ 14 250 0 100 L 30 30 14 1 B
+X ~ 15 250 0 100 L 30 30 15 1 B
+X ~ 16 250 0 100 L 30 30 16 1 B
+X ~ 17 250 0 100 L 30 30 17 1 B
+X ~ 18 250 0 100 L 30 30 18 1 B
+X ~ 19 250 0 100 L 30 30 19 1 B
+X ~ 20 250 0 100 L 30 30 20 1 B
+X ~ 21 250 0 100 L 30 30 21 1 B
+X ~ 22 250 0 100 L 30 30 22 1 B
+X ~ 23 250 0 100 L 30 30 23 1 B
+X ~ 24 250 0 100 L 30 30 24 1 B
+X ~ 25 250 0 100 L 30 30 25 1 B
+X ~ 26 250 0 100 L 30 30 26 1 B
+ENDDRAW
+ENDDEF
+#
+# d_and
+#
+DEF d_and U 0 40 Y Y 1 F N
+F0 "U" 0 0 60 H V C CNN
+F1 "d_and" 50 100 60 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A 149 50 100 -894 0 0 1 0 N 150 -50 250 50
+A 150 49 100 6 900 0 1 0 N 250 50 150 150
+P 4 0 1 0 150 -50 -250 -50 -250 150 150 150 N
+X IN1 1 -450 100 200 R 50 50 1 1 I
+X IN2 2 -450 0 200 R 50 50 1 1 I
+X OUT 3 450 50 200 L 50 50 1 1 O
+ENDDRAW
+ENDDEF
+#
+#End Library
diff --git a/library/SubcircuitLibrary/74ls169/5_and-rescue.lib b/library/SubcircuitLibrary/74ls169/5_and-rescue.lib
new file mode 100644
index 000000000..483b8efb8
--- /dev/null
+++ b/library/SubcircuitLibrary/74ls169/5_and-rescue.lib
@@ -0,0 +1,22 @@
+EESchema-LIBRARY Version 2.3
+#encoding utf-8
+#
+# 3_and-RESCUE-5_and
+#
+DEF 3_and-RESCUE-5_and X 0 40 Y Y 1 F N
+F0 "X" 900 300 60 H V C CNN
+F1 "3_and-RESCUE-5_and" 950 500 60 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A 950 400 158 716 -716 0 1 0 N 1000 550 1000 250
+P 2 0 1 0 650 550 1000 550 N
+P 3 0 1 0 650 550 650 250 1000 250 N
+X in1 1 450 500 200 R 50 50 1 1 I
+X in2 2 450 400 200 R 50 50 1 1 I
+X in3 3 450 300 200 R 50 50 1 1 I
+X out 4 1300 400 200 L 50 50 1 1 O
+ENDDRAW
+ENDDEF
+#
+#End Library
diff --git a/library/SubcircuitLibrary/74ls169/5_and.cir b/library/SubcircuitLibrary/74ls169/5_and.cir
new file mode 100644
index 000000000..6a05b9b5d
--- /dev/null
+++ b/library/SubcircuitLibrary/74ls169/5_and.cir
@@ -0,0 +1,14 @@
+* C:\Users\malli\eSim\src\SubcircuitLibrary\5_and\5_and.cir
+
+* EESchema Netlist Version 1.1 (Spice format) creation date: 03/26/19 18:53:13
+
+* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N
+* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0
+
+* Sheet Name: /
+X1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U3-Pad1_ 3_and
+U2 Net-_U1-Pad4_ Net-_U1-Pad5_ Net-_U2-Pad3_ d_and
+U3 Net-_U3-Pad1_ Net-_U2-Pad3_ Net-_U1-Pad6_ d_and
+U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ Net-_U1-Pad6_ PORT
+
+.end
diff --git a/library/SubcircuitLibrary/74ls169/5_and.cir.out b/library/SubcircuitLibrary/74ls169/5_and.cir.out
new file mode 100644
index 000000000..6a6b126a7
--- /dev/null
+++ b/library/SubcircuitLibrary/74ls169/5_and.cir.out
@@ -0,0 +1,22 @@
+* c:\users\malli\esim\src\subcircuitlibrary\5_and\5_and.cir
+
+.include 3_and.sub
+x1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u3-pad1_ 3_and
+* u2 net-_u1-pad4_ net-_u1-pad5_ net-_u2-pad3_ d_and
+* u3 net-_u3-pad1_ net-_u2-pad3_ net-_u1-pad6_ d_and
+* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ port
+a1 [net-_u1-pad4_ net-_u1-pad5_ ] net-_u2-pad3_ u2
+a2 [net-_u3-pad1_ net-_u2-pad3_ ] net-_u1-pad6_ u3
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u3 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+.tran 0e-00 0e-00 0e-00
+
+* Control Statements
+.control
+run
+print allv > plot_data_v.txt
+print alli > plot_data_i.txt
+.endc
+.end
diff --git a/library/SubcircuitLibrary/74ls169/5_and.pro b/library/SubcircuitLibrary/74ls169/5_and.pro
new file mode 100644
index 000000000..c16a3f858
--- /dev/null
+++ b/library/SubcircuitLibrary/74ls169/5_and.pro
@@ -0,0 +1,49 @@
+update=Wed Mar 18 19:59:53 2020
+version=1
+last_client=eeschema
+[general]
+version=1
+RootSch=
+BoardNm=
+[pcbnew]
+version=1
+LastNetListRead=
+UseCmpFile=1
+PadDrill=0.600000000000
+PadDrillOvalY=0.600000000000
+PadSizeH=1.500000000000
+PadSizeV=1.500000000000
+PcbTextSizeV=1.500000000000
+PcbTextSizeH=1.500000000000
+PcbTextThickness=0.300000000000
+ModuleTextSizeV=1.000000000000
+ModuleTextSizeH=1.000000000000
+ModuleTextSizeThickness=0.150000000000
+SolderMaskClearance=0.000000000000
+SolderMaskMinWidth=0.000000000000
+DrawSegmentWidth=0.200000000000
+BoardOutlineThickness=0.100000000000
+ModuleOutlineThickness=0.150000000000
+[cvpcb]
+version=1
+NetIExt=net
+[eeschema]
+version=1
+LibDir=../../../kicadSchematicLibrary
+[eeschema/libraries]
+LibName1=cypress
+LibName2=siliconi
+LibName3=opto
+LibName4=atmel
+LibName5=contrib
+LibName6=valves
+LibName7=eSim_Analog
+LibName8=eSim_Devices
+LibName9=eSim_Digital
+LibName10=eSim_Hybrid
+LibName11=eSim_Miscellaneous
+LibName12=eSim_Plot
+LibName13=eSim_Power
+LibName14=eSim_User
+LibName15=eSim_Sources
+LibName16=eSim_Subckt
diff --git a/library/SubcircuitLibrary/74ls169/5_and.sch b/library/SubcircuitLibrary/74ls169/5_and.sch
new file mode 100644
index 000000000..aef3c0436
--- /dev/null
+++ b/library/SubcircuitLibrary/74ls169/5_and.sch
@@ -0,0 +1,171 @@
+EESchema Schematic File Version 2
+LIBS:5_and-rescue
+LIBS:cypress
+LIBS:siliconi
+LIBS:opto
+LIBS:atmel
+LIBS:contrib
+LIBS:valves
+LIBS:eSim_Analog
+LIBS:eSim_Devices
+LIBS:eSim_Digital
+LIBS:eSim_Hybrid
+LIBS:eSim_Miscellaneous
+LIBS:eSim_Plot
+LIBS:eSim_Power
+LIBS:eSim_User
+LIBS:eSim_Sources
+LIBS:eSim_Subckt
+LIBS:5_and-cache
+EELAYER 25 0
+EELAYER END
+$Descr A4 11693 8268
+encoding utf-8
+Sheet 1 1
+Title ""
+Date ""
+Rev ""
+Comp ""
+Comment1 ""
+Comment2 ""
+Comment3 ""
+Comment4 ""
+$EndDescr
+$Comp
+L 3_and-RESCUE-5_and X1
+U 1 1 5C9A2741
+P 3800 3350
+F 0 "X1" H 4700 3650 60 0000 C CNN
+F 1 "3_and" H 4750 3850 60 0000 C CNN
+F 2 "" H 3800 3350 60 0000 C CNN
+F 3 "" H 3800 3350 60 0000 C CNN
+ 1 3800 3350
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_and U2
+U 1 1 5C9A2764
+P 4650 3400
+F 0 "U2" H 4650 3400 60 0000 C CNN
+F 1 "d_and" H 4700 3500 60 0000 C CNN
+F 2 "" H 4650 3400 60 0000 C CNN
+F 3 "" H 4650 3400 60 0000 C CNN
+ 1 4650 3400
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_and U3
+U 1 1 5C9A2791
+P 5550 3200
+F 0 "U3" H 5550 3200 60 0000 C CNN
+F 1 "d_and" H 5600 3300 60 0000 C CNN
+F 2 "" H 5550 3200 60 0000 C CNN
+F 3 "" H 5550 3200 60 0000 C CNN
+ 1 5550 3200
+ 1 0 0 -1
+$EndComp
+Wire Wire Line
+ 5100 3100 5100 2950
+Wire Wire Line
+ 5100 3200 5100 3350
+Wire Wire Line
+ 4250 2850 4250 2700
+Wire Wire Line
+ 4250 2700 3600 2700
+Wire Wire Line
+ 4250 2950 4150 2950
+Wire Wire Line
+ 4150 2950 4150 2900
+Wire Wire Line
+ 4150 2900 3600 2900
+Wire Wire Line
+ 4200 3300 3600 3300
+Wire Wire Line
+ 4250 3050 4250 3100
+Wire Wire Line
+ 4250 3100 3600 3100
+Wire Wire Line
+ 4200 3400 4200 3500
+Wire Wire Line
+ 4200 3500 3600 3500
+Wire Wire Line
+ 6000 3150 6500 3150
+$Comp
+L PORT U1
+U 1 1 5C9A2865
+P 3350 2700
+F 0 "U1" H 3400 2800 30 0000 C CNN
+F 1 "PORT" H 3350 2700 30 0000 C CNN
+F 2 "" H 3350 2700 60 0000 C CNN
+F 3 "" H 3350 2700 60 0000 C CNN
+ 1 3350 2700
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 2 1 5C9A28B6
+P 3350 2900
+F 0 "U1" H 3400 3000 30 0000 C CNN
+F 1 "PORT" H 3350 2900 30 0000 C CNN
+F 2 "" H 3350 2900 60 0000 C CNN
+F 3 "" H 3350 2900 60 0000 C CNN
+ 2 3350 2900
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 3 1 5C9A28D9
+P 3350 3100
+F 0 "U1" H 3400 3200 30 0000 C CNN
+F 1 "PORT" H 3350 3100 30 0000 C CNN
+F 2 "" H 3350 3100 60 0000 C CNN
+F 3 "" H 3350 3100 60 0000 C CNN
+ 3 3350 3100
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 4 1 5C9A28FF
+P 3350 3300
+F 0 "U1" H 3400 3400 30 0000 C CNN
+F 1 "PORT" H 3350 3300 30 0000 C CNN
+F 2 "" H 3350 3300 60 0000 C CNN
+F 3 "" H 3350 3300 60 0000 C CNN
+ 4 3350 3300
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 5 1 5C9A2928
+P 3350 3500
+F 0 "U1" H 3400 3600 30 0000 C CNN
+F 1 "PORT" H 3350 3500 30 0000 C CNN
+F 2 "" H 3350 3500 60 0000 C CNN
+F 3 "" H 3350 3500 60 0000 C CNN
+ 5 3350 3500
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 6 1 5C9A2958
+P 6750 3150
+F 0 "U1" H 6800 3250 30 0000 C CNN
+F 1 "PORT" H 6750 3150 30 0000 C CNN
+F 2 "" H 6750 3150 60 0000 C CNN
+F 3 "" H 6750 3150 60 0000 C CNN
+ 6 6750 3150
+ -1 0 0 1
+$EndComp
+Text Notes 3800 2700 0 60 ~ 12
+in1
+Text Notes 3800 2900 0 60 ~ 12
+in2
+Text Notes 3800 3100 0 60 ~ 12
+in3
+Text Notes 3800 3300 0 60 ~ 12
+in4
+Text Notes 3800 3500 0 60 ~ 12
+in5
+Text Notes 6150 3150 0 60 ~ 12
+out
+$EndSCHEMATC
diff --git a/library/SubcircuitLibrary/74ls169/5_and.sub b/library/SubcircuitLibrary/74ls169/5_and.sub
new file mode 100644
index 000000000..35b10e173
--- /dev/null
+++ b/library/SubcircuitLibrary/74ls169/5_and.sub
@@ -0,0 +1,16 @@
+* Subcircuit 5_and
+.subckt 5_and net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_
+* c:\users\malli\esim\src\subcircuitlibrary\5_and\5_and.cir
+.include 3_and.sub
+x1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u3-pad1_ 3_and
+* u2 net-_u1-pad4_ net-_u1-pad5_ net-_u2-pad3_ d_and
+* u3 net-_u3-pad1_ net-_u2-pad3_ net-_u1-pad6_ d_and
+a1 [net-_u1-pad4_ net-_u1-pad5_ ] net-_u2-pad3_ u2
+a2 [net-_u3-pad1_ net-_u2-pad3_ ] net-_u1-pad6_ u3
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u3 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+* Control Statements
+
+.ends 5_and
\ No newline at end of file
diff --git a/library/SubcircuitLibrary/74ls169/5_and_Previous_Values.xml b/library/SubcircuitLibrary/74ls169/5_and_Previous_Values.xml
new file mode 100644
index 000000000..ae2c08a7f
--- /dev/null
+++ b/library/SubcircuitLibrary/74ls169/5_and_Previous_Values.xml
@@ -0,0 +1 @@
+d_andd_andC:\Users\malli\eSim\src\SubcircuitLibrary\3_andtruefalsefalseHzHz0Volts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesSecSecSec
\ No newline at end of file
diff --git a/library/SubcircuitLibrary/74ls169/74LS169.cir b/library/SubcircuitLibrary/74ls169/74LS169.cir
new file mode 100644
index 000000000..ac59f9586
--- /dev/null
+++ b/library/SubcircuitLibrary/74ls169/74LS169.cir
@@ -0,0 +1,73 @@
+.title KiCad schematic
+X10 Net-_U21-Pad1_ Net-_U27-Pad1_ Net-_U23-Pad3_ Net-_U24-Pad3_ Net-_U25-Pad3_ Net-_X10-Pad6_ 5_and
+X3 Net-_U23-Pad3_ Net-_U24-Pad3_ Net-_U25-Pad3_ Net-_U26-Pad3_ Net-_U14-Pad2_ Net-_U41-Pad1_ 5_and
+X7 Net-_X2-Pad5_ Net-_U13-Pad2_ Net-_U22-Pad2_ Net-_X14-Pad2_ 3_and
+X9 Net-_U39-Pad3_ Net-_U13-Pad2_ Net-_U20-Pad2_ Net-_X13-Pad2_ 3_and
+X8 Net-_U19-Pad1_ Net-_U27-Pad1_ Net-_U23-Pad3_ Net-_U24-Pad3_ Net-_X13-Pad1_ 4_and
+U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ Net-_U1-Pad6_ Net-_U1-Pad7_ unconnected-_U1-Pad8_ Net-_U1-Pad9_ Net-_U1-Pad10_ Net-_U1-Pad11_ Net-_U1-Pad12_ Net-_U1-Pad13_ Net-_U1-Pad14_ Net-_U1-Pad15_ unconnected-_U1-Pad16_ PORT
+U7 Net-_U13-Pad2_ Net-_U1-Pad5_ Net-_U7-Pad3_ d_nor
+U8 Net-_U13-Pad2_ Net-_U1-Pad6_ Net-_U8-Pad3_ d_nor
+U26 Net-_U21-Pad3_ Net-_U22-Pad3_ Net-_U26-Pad3_ d_nor
+U25 Net-_U19-Pad3_ Net-_U20-Pad3_ Net-_U25-Pad3_ d_nor
+U22 Net-_U12-Pad1_ Net-_U22-Pad2_ Net-_U22-Pad3_ d_and
+U21 Net-_U21-Pad1_ Net-_U12-Pad2_ Net-_U21-Pad3_ d_and
+U20 Net-_U12-Pad1_ Net-_U20-Pad2_ Net-_U20-Pad3_ d_and
+U19 Net-_U19-Pad1_ Net-_U12-Pad2_ Net-_U19-Pad3_ d_and
+U18 Net-_U12-Pad1_ Net-_U18-Pad2_ Net-_U18-Pad3_ d_and
+U17 Net-_U17-Pad1_ Net-_U12-Pad2_ Net-_U17-Pad3_ d_and
+U4 Net-_U1-Pad2_ Net-_U4-Pad2_ d_inverter
+U2 Net-_U1-Pad1_ Net-_U12-Pad1_ d_inverter
+U6 Net-_U13-Pad2_ Net-_U1-Pad4_ Net-_U6-Pad3_ d_nor
+U5 Net-_U13-Pad2_ Net-_U1-Pad3_ Net-_U5-Pad3_ d_nor
+U3 Net-_U1-Pad9_ Net-_U13-Pad1_ d_inverter
+U31 Net-_U27-Pad2_ Net-_U28-Pad2_ Net-_U31-Pad3_ d_or
+U27 Net-_U27-Pad1_ Net-_U27-Pad2_ d_inverter
+U28 Net-_U23-Pad3_ Net-_U28-Pad2_ d_inverter
+U39 Net-_U31-Pad3_ Net-_U36-Pad2_ Net-_U39-Pad3_ d_or
+U36 Net-_U24-Pad3_ Net-_U36-Pad2_ d_inverter
+X2 Net-_U32-Pad2_ Net-_U33-Pad2_ Net-_U34-Pad2_ Net-_U35-Pad2_ Net-_X2-Pad5_ 4_OR
+U32 Net-_U27-Pad1_ Net-_U32-Pad2_ d_inverter
+U34 Net-_U24-Pad3_ Net-_U34-Pad2_ d_inverter
+U35 Net-_U25-Pad3_ Net-_U35-Pad2_ d_inverter
+U33 Net-_U23-Pad3_ Net-_U33-Pad2_ d_inverter
+U11 Net-_U1-Pad10_ Net-_U11-Pad2_ d_inverter
+U10 Net-_U1-Pad7_ Net-_U10-Pad2_ d_inverter
+U9 Net-_U13-Pad1_ Net-_U9-Pad2_ d_inverter
+U12 Net-_U12-Pad1_ Net-_U12-Pad2_ d_inverter
+U13 Net-_U13-Pad1_ Net-_U13-Pad2_ d_inverter
+X1 Net-_U9-Pad2_ Net-_U10-Pad2_ Net-_U11-Pad2_ Net-_U27-Pad1_ 3_and
+U14 Net-_U1-Pad10_ Net-_U14-Pad2_ d_inverter
+U30 Net-_U23-Pad3_ Net-_U30-Pad2_ d_inverter
+U37 Net-_U29-Pad2_ Net-_U30-Pad2_ Net-_U37-Pad3_ d_or
+U29 Net-_U27-Pad1_ Net-_U29-Pad2_ d_inverter
+X6 Net-_U37-Pad3_ Net-_U13-Pad2_ Net-_U18-Pad2_ Net-_X12-Pad2_ 3_and
+U24 Net-_U17-Pad3_ Net-_U18-Pad3_ Net-_U24-Pad3_ d_nor
+X4 Net-_U38-Pad2_ Net-_U13-Pad2_ Net-_U16-Pad2_ Net-_X11-Pad2_ 3_and
+X5 Net-_U17-Pad1_ Net-_U27-Pad1_ Net-_U23-Pad3_ Net-_X12-Pad1_ 3_and
+U40 Net-_U15-Pad1_ Net-_U27-Pad1_ Net-_U40-Pad3_ d_and
+U38 Net-_U27-Pad1_ Net-_U38-Pad2_ d_inverter
+U23 Net-_U15-Pad3_ Net-_U16-Pad3_ Net-_U23-Pad3_ d_nor
+U16 Net-_U12-Pad1_ Net-_U16-Pad2_ Net-_U16-Pad3_ d_and
+U15 Net-_U15-Pad1_ Net-_U12-Pad2_ Net-_U15-Pad3_ d_and
+U41 Net-_U41-Pad1_ Net-_U1-Pad15_ d_inverter
+U45 Net-_U45-Pad1_ Net-_U45-Pad2_ d_inverter
+X14 Net-_X10-Pad6_ Net-_X14-Pad2_ Net-_U8-Pad3_ unconnected-_X14-Pad4_ Net-_U45-Pad1_ 4_OR
+U53 Net-_U42-Pad2_ Net-_U49-Pad2_ unconnected-_U53-Pad3_ unconnected-_U53-Pad4_ Net-_U15-Pad1_ Net-_U16-Pad2_ d_dff
+U42 Net-_U42-Pad1_ Net-_U42-Pad2_ d_inverter
+X11 Net-_U40-Pad3_ Net-_X11-Pad2_ Net-_U5-Pad3_ unconnected-_X11-Pad4_ Net-_U42-Pad1_ 4_OR
+X12 Net-_X12-Pad1_ Net-_X12-Pad2_ Net-_U6-Pad3_ unconnected-_X12-Pad4_ Net-_U43-Pad1_ 4_OR
+U51 Net-_U44-Pad2_ Net-_U47-Pad2_ unconnected-_U51-Pad3_ unconnected-_U51-Pad4_ Net-_U19-Pad1_ Net-_U20-Pad2_ d_dff
+X13 Net-_X13-Pad1_ Net-_X13-Pad2_ Net-_U7-Pad3_ unconnected-_X13-Pad4_ Net-_U44-Pad1_ 4_OR
+U43 Net-_U43-Pad1_ Net-_U43-Pad2_ d_inverter
+U44 Net-_U44-Pad1_ Net-_U44-Pad2_ d_inverter
+U49 Net-_U4-Pad2_ Net-_U49-Pad2_ d_inverter
+U50 Net-_U43-Pad2_ Net-_U46-Pad2_ unconnected-_U50-Pad3_ unconnected-_U50-Pad4_ Net-_U17-Pad1_ Net-_U18-Pad2_ d_dff
+U46 Net-_U4-Pad2_ Net-_U46-Pad2_ d_inverter
+U57 Net-_U16-Pad2_ Net-_U1-Pad14_ d_inverter
+U54 Net-_U18-Pad2_ Net-_U1-Pad13_ d_inverter
+U47 Net-_U4-Pad2_ Net-_U47-Pad2_ d_inverter
+U55 Net-_U20-Pad2_ Net-_U1-Pad12_ d_inverter
+U52 Net-_U45-Pad2_ Net-_U48-Pad2_ unconnected-_U52-Pad3_ unconnected-_U52-Pad4_ Net-_U21-Pad1_ Net-_U22-Pad2_ d_dff
+U48 Net-_U4-Pad2_ Net-_U48-Pad2_ d_inverter
+U56 Net-_U22-Pad2_ Net-_U1-Pad11_ d_inverter
+.end
diff --git a/library/SubcircuitLibrary/74ls169/74LS169.cir.out b/library/SubcircuitLibrary/74ls169/74LS169.cir.out
new file mode 100644
index 000000000..51000de16
--- /dev/null
+++ b/library/SubcircuitLibrary/74ls169/74LS169.cir.out
@@ -0,0 +1,254 @@
+.title kicad schematic
+
+.include 5_and.sub
+.include 3_and.sub
+.include 4_OR.sub
+.include 4_and.sub
+x10 net-_u21-pad1_ net-_u27-pad1_ net-_u23-pad3_ net-_u24-pad3_ net-_u25-pad3_ net-_x10-pad6_ 5_and
+x3 net-_u23-pad3_ net-_u24-pad3_ net-_u25-pad3_ net-_u26-pad3_ net-_u14-pad2_ net-_u41-pad1_ 5_and
+x7 net-_x2-pad5_ net-_u13-pad2_ net-_u22-pad2_ net-_x14-pad2_ 3_and
+x9 net-_u39-pad3_ net-_u13-pad2_ net-_u20-pad2_ net-_x13-pad2_ 3_and
+x8 net-_u19-pad1_ net-_u27-pad1_ net-_u23-pad3_ net-_u24-pad3_ net-_x13-pad1_ 4_and
+* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ unconnected-_u1-pad8_ net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad13_ net-_u1-pad14_ net-_u1-pad15_ unconnected-_u1-pad16_ port
+* u7 net-_u13-pad2_ net-_u1-pad5_ net-_u7-pad3_ d_nor
+* u8 net-_u13-pad2_ net-_u1-pad6_ net-_u8-pad3_ d_nor
+* u26 net-_u21-pad3_ net-_u22-pad3_ net-_u26-pad3_ d_nor
+* u25 net-_u19-pad3_ net-_u20-pad3_ net-_u25-pad3_ d_nor
+* u22 net-_u12-pad1_ net-_u22-pad2_ net-_u22-pad3_ d_and
+* u21 net-_u21-pad1_ net-_u12-pad2_ net-_u21-pad3_ d_and
+* u20 net-_u12-pad1_ net-_u20-pad2_ net-_u20-pad3_ d_and
+* u19 net-_u19-pad1_ net-_u12-pad2_ net-_u19-pad3_ d_and
+* u18 net-_u12-pad1_ net-_u18-pad2_ net-_u18-pad3_ d_and
+* u17 net-_u17-pad1_ net-_u12-pad2_ net-_u17-pad3_ d_and
+* u4 net-_u1-pad2_ net-_u4-pad2_ d_inverter
+* u2 net-_u1-pad1_ net-_u12-pad1_ d_inverter
+* u6 net-_u13-pad2_ net-_u1-pad4_ net-_u6-pad3_ d_nor
+* u5 net-_u13-pad2_ net-_u1-pad3_ net-_u5-pad3_ d_nor
+* u3 net-_u1-pad9_ net-_u13-pad1_ d_inverter
+* u31 net-_u27-pad2_ net-_u28-pad2_ net-_u31-pad3_ d_or
+* u27 net-_u27-pad1_ net-_u27-pad2_ d_inverter
+* u28 net-_u23-pad3_ net-_u28-pad2_ d_inverter
+* u39 net-_u31-pad3_ net-_u36-pad2_ net-_u39-pad3_ d_or
+* u36 net-_u24-pad3_ net-_u36-pad2_ d_inverter
+x2 net-_u32-pad2_ net-_u33-pad2_ net-_u34-pad2_ net-_u35-pad2_ net-_x2-pad5_ 4_OR
+* u32 net-_u27-pad1_ net-_u32-pad2_ d_inverter
+* u34 net-_u24-pad3_ net-_u34-pad2_ d_inverter
+* u35 net-_u25-pad3_ net-_u35-pad2_ d_inverter
+* u33 net-_u23-pad3_ net-_u33-pad2_ d_inverter
+* u11 net-_u1-pad10_ net-_u11-pad2_ d_inverter
+* u10 net-_u1-pad7_ net-_u10-pad2_ d_inverter
+* u9 net-_u13-pad1_ net-_u9-pad2_ d_inverter
+* u12 net-_u12-pad1_ net-_u12-pad2_ d_inverter
+* u13 net-_u13-pad1_ net-_u13-pad2_ d_inverter
+x1 net-_u9-pad2_ net-_u10-pad2_ net-_u11-pad2_ net-_u27-pad1_ 3_and
+* u14 net-_u1-pad10_ net-_u14-pad2_ d_inverter
+* u30 net-_u23-pad3_ net-_u30-pad2_ d_inverter
+* u37 net-_u29-pad2_ net-_u30-pad2_ net-_u37-pad3_ d_or
+* u29 net-_u27-pad1_ net-_u29-pad2_ d_inverter
+x6 net-_u37-pad3_ net-_u13-pad2_ net-_u18-pad2_ net-_x12-pad2_ 3_and
+* u24 net-_u17-pad3_ net-_u18-pad3_ net-_u24-pad3_ d_nor
+x4 net-_u38-pad2_ net-_u13-pad2_ net-_u16-pad2_ net-_x11-pad2_ 3_and
+x5 net-_u17-pad1_ net-_u27-pad1_ net-_u23-pad3_ net-_x12-pad1_ 3_and
+* u40 net-_u15-pad1_ net-_u27-pad1_ net-_u40-pad3_ d_and
+* u38 net-_u27-pad1_ net-_u38-pad2_ d_inverter
+* u23 net-_u15-pad3_ net-_u16-pad3_ net-_u23-pad3_ d_nor
+* u16 net-_u12-pad1_ net-_u16-pad2_ net-_u16-pad3_ d_and
+* u15 net-_u15-pad1_ net-_u12-pad2_ net-_u15-pad3_ d_and
+* u41 net-_u41-pad1_ net-_u1-pad15_ d_inverter
+* u45 net-_u45-pad1_ net-_u45-pad2_ d_inverter
+x14 net-_x10-pad6_ net-_x14-pad2_ net-_u8-pad3_ unconnected-_x14-pad4_ net-_u45-pad1_ 4_OR
+* u53 net-_u42-pad2_ net-_u49-pad2_ unconnected-_u53-pad3_ unconnected-_u53-pad4_ net-_u15-pad1_ net-_u16-pad2_ d_dff
+* u42 net-_u42-pad1_ net-_u42-pad2_ d_inverter
+x11 net-_u40-pad3_ net-_x11-pad2_ net-_u5-pad3_ unconnected-_x11-pad4_ net-_u42-pad1_ 4_OR
+x12 net-_x12-pad1_ net-_x12-pad2_ net-_u6-pad3_ unconnected-_x12-pad4_ net-_u43-pad1_ 4_OR
+* u51 net-_u44-pad2_ net-_u47-pad2_ unconnected-_u51-pad3_ unconnected-_u51-pad4_ net-_u19-pad1_ net-_u20-pad2_ d_dff
+x13 net-_x13-pad1_ net-_x13-pad2_ net-_u7-pad3_ unconnected-_x13-pad4_ net-_u44-pad1_ 4_OR
+* u43 net-_u43-pad1_ net-_u43-pad2_ d_inverter
+* u44 net-_u44-pad1_ net-_u44-pad2_ d_inverter
+* u49 net-_u4-pad2_ net-_u49-pad2_ d_inverter
+* u50 net-_u43-pad2_ net-_u46-pad2_ unconnected-_u50-pad3_ unconnected-_u50-pad4_ net-_u17-pad1_ net-_u18-pad2_ d_dff
+* u46 net-_u4-pad2_ net-_u46-pad2_ d_inverter
+* u57 net-_u16-pad2_ net-_u1-pad14_ d_inverter
+* u54 net-_u18-pad2_ net-_u1-pad13_ d_inverter
+* u47 net-_u4-pad2_ net-_u47-pad2_ d_inverter
+* u55 net-_u20-pad2_ net-_u1-pad12_ d_inverter
+* u52 net-_u45-pad2_ net-_u48-pad2_ unconnected-_u52-pad3_ unconnected-_u52-pad4_ net-_u21-pad1_ net-_u22-pad2_ d_dff
+* u48 net-_u4-pad2_ net-_u48-pad2_ d_inverter
+* u56 net-_u22-pad2_ net-_u1-pad11_ d_inverter
+a1 [net-_u13-pad2_ net-_u1-pad5_ ] net-_u7-pad3_ u7
+a2 [net-_u13-pad2_ net-_u1-pad6_ ] net-_u8-pad3_ u8
+a3 [net-_u21-pad3_ net-_u22-pad3_ ] net-_u26-pad3_ u26
+a4 [net-_u19-pad3_ net-_u20-pad3_ ] net-_u25-pad3_ u25
+a5 [net-_u12-pad1_ net-_u22-pad2_ ] net-_u22-pad3_ u22
+a6 [net-_u21-pad1_ net-_u12-pad2_ ] net-_u21-pad3_ u21
+a7 [net-_u12-pad1_ net-_u20-pad2_ ] net-_u20-pad3_ u20
+a8 [net-_u19-pad1_ net-_u12-pad2_ ] net-_u19-pad3_ u19
+a9 [net-_u12-pad1_ net-_u18-pad2_ ] net-_u18-pad3_ u18
+a10 [net-_u17-pad1_ net-_u12-pad2_ ] net-_u17-pad3_ u17
+a11 net-_u1-pad2_ net-_u4-pad2_ u4
+a12 net-_u1-pad1_ net-_u12-pad1_ u2
+a13 [net-_u13-pad2_ net-_u1-pad4_ ] net-_u6-pad3_ u6
+a14 [net-_u13-pad2_ net-_u1-pad3_ ] net-_u5-pad3_ u5
+a15 net-_u1-pad9_ net-_u13-pad1_ u3
+a16 [net-_u27-pad2_ net-_u28-pad2_ ] net-_u31-pad3_ u31
+a17 net-_u27-pad1_ net-_u27-pad2_ u27
+a18 net-_u23-pad3_ net-_u28-pad2_ u28
+a19 [net-_u31-pad3_ net-_u36-pad2_ ] net-_u39-pad3_ u39
+a20 net-_u24-pad3_ net-_u36-pad2_ u36
+a21 net-_u27-pad1_ net-_u32-pad2_ u32
+a22 net-_u24-pad3_ net-_u34-pad2_ u34
+a23 net-_u25-pad3_ net-_u35-pad2_ u35
+a24 net-_u23-pad3_ net-_u33-pad2_ u33
+a25 net-_u1-pad10_ net-_u11-pad2_ u11
+a26 net-_u1-pad7_ net-_u10-pad2_ u10
+a27 net-_u13-pad1_ net-_u9-pad2_ u9
+a28 net-_u12-pad1_ net-_u12-pad2_ u12
+a29 net-_u13-pad1_ net-_u13-pad2_ u13
+a30 net-_u1-pad10_ net-_u14-pad2_ u14
+a31 net-_u23-pad3_ net-_u30-pad2_ u30
+a32 [net-_u29-pad2_ net-_u30-pad2_ ] net-_u37-pad3_ u37
+a33 net-_u27-pad1_ net-_u29-pad2_ u29
+a34 [net-_u17-pad3_ net-_u18-pad3_ ] net-_u24-pad3_ u24
+a35 [net-_u15-pad1_ net-_u27-pad1_ ] net-_u40-pad3_ u40
+a36 net-_u27-pad1_ net-_u38-pad2_ u38
+a37 [net-_u15-pad3_ net-_u16-pad3_ ] net-_u23-pad3_ u23
+a38 [net-_u12-pad1_ net-_u16-pad2_ ] net-_u16-pad3_ u16
+a39 [net-_u15-pad1_ net-_u12-pad2_ ] net-_u15-pad3_ u15
+a40 net-_u41-pad1_ net-_u1-pad15_ u41
+a41 net-_u45-pad1_ net-_u45-pad2_ u45
+a42 net-_u42-pad2_ net-_u49-pad2_ unconnected-_u53-pad3_ unconnected-_u53-pad4_ net-_u15-pad1_ net-_u16-pad2_ u53
+a43 net-_u42-pad1_ net-_u42-pad2_ u42
+a44 net-_u44-pad2_ net-_u47-pad2_ unconnected-_u51-pad3_ unconnected-_u51-pad4_ net-_u19-pad1_ net-_u20-pad2_ u51
+a45 net-_u43-pad1_ net-_u43-pad2_ u43
+a46 net-_u44-pad1_ net-_u44-pad2_ u44
+a47 net-_u4-pad2_ net-_u49-pad2_ u49
+a48 net-_u43-pad2_ net-_u46-pad2_ unconnected-_u50-pad3_ unconnected-_u50-pad4_ net-_u17-pad1_ net-_u18-pad2_ u50
+a49 net-_u4-pad2_ net-_u46-pad2_ u46
+a50 net-_u16-pad2_ net-_u1-pad14_ u57
+a51 net-_u18-pad2_ net-_u1-pad13_ u54
+a52 net-_u4-pad2_ net-_u47-pad2_ u47
+a53 net-_u20-pad2_ net-_u1-pad12_ u55
+a54 net-_u45-pad2_ net-_u48-pad2_ unconnected-_u52-pad3_ unconnected-_u52-pad4_ net-_u21-pad1_ net-_u22-pad2_ u52
+a55 net-_u4-pad2_ net-_u48-pad2_ u48
+a56 net-_u22-pad2_ net-_u1-pad11_ u56
+* Schematic Name: d_nor, Ngspice Name: d_nor
+.model u7 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_nor, Ngspice Name: d_nor
+.model u8 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_nor, Ngspice Name: d_nor
+.model u26 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_nor, Ngspice Name: d_nor
+.model u25 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, Ngspice Name: d_and
+.model u22 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, Ngspice Name: d_and
+.model u21 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, Ngspice Name: d_and
+.model u20 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, Ngspice Name: d_and
+.model u19 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, Ngspice Name: d_and
+.model u18 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, Ngspice Name: d_and
+.model u17 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, Ngspice Name: d_inverter
+.model u4 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, Ngspice Name: d_inverter
+.model u2 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_nor, Ngspice Name: d_nor
+.model u6 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_nor, Ngspice Name: d_nor
+.model u5 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, Ngspice Name: d_inverter
+.model u3 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_or, Ngspice Name: d_or
+.model u31 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, Ngspice Name: d_inverter
+.model u27 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, Ngspice Name: d_inverter
+.model u28 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_or, Ngspice Name: d_or
+.model u39 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, Ngspice Name: d_inverter
+.model u36 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, Ngspice Name: d_inverter
+.model u32 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, Ngspice Name: d_inverter
+.model u34 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, Ngspice Name: d_inverter
+.model u35 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, Ngspice Name: d_inverter
+.model u33 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, Ngspice Name: d_inverter
+.model u11 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, Ngspice Name: d_inverter
+.model u10 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, Ngspice Name: d_inverter
+.model u9 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, Ngspice Name: d_inverter
+.model u12 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, Ngspice Name: d_inverter
+.model u13 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, Ngspice Name: d_inverter
+.model u14 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, Ngspice Name: d_inverter
+.model u30 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_or, Ngspice Name: d_or
+.model u37 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, Ngspice Name: d_inverter
+.model u29 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_nor, Ngspice Name: d_nor
+.model u24 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, Ngspice Name: d_and
+.model u40 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, Ngspice Name: d_inverter
+.model u38 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_nor, Ngspice Name: d_nor
+.model u23 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, Ngspice Name: d_and
+.model u16 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, Ngspice Name: d_and
+.model u15 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, Ngspice Name: d_inverter
+.model u41 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, Ngspice Name: d_inverter
+.model u45 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_dff, Ngspice Name: d_dff
+.model u53 d_dff(clk_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0 ic=0 data_load=1.0e-12 clk_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 )
+* Schematic Name: d_inverter, Ngspice Name: d_inverter
+.model u42 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_dff, Ngspice Name: d_dff
+.model u51 d_dff(clk_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0 ic=0 data_load=1.0e-12 clk_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 )
+* Schematic Name: d_inverter, Ngspice Name: d_inverter
+.model u43 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, Ngspice Name: d_inverter
+.model u44 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, Ngspice Name: d_inverter
+.model u49 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_dff, Ngspice Name: d_dff
+.model u50 d_dff(clk_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0 ic=0 data_load=1.0e-12 clk_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 )
+* Schematic Name: d_inverter, Ngspice Name: d_inverter
+.model u46 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, Ngspice Name: d_inverter
+.model u57 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, Ngspice Name: d_inverter
+.model u54 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, Ngspice Name: d_inverter
+.model u47 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, Ngspice Name: d_inverter
+.model u55 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_dff, Ngspice Name: d_dff
+.model u52 d_dff(clk_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0 ic=0 data_load=1.0e-12 clk_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 )
+* Schematic Name: d_inverter, Ngspice Name: d_inverter
+.model u48 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, Ngspice Name: d_inverter
+.model u56 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+.tran 0e-00 0e-00 0e-00
+
+* Control Statements
+.control
+run
+print allv > plot_data_v.txt
+print alli > plot_data_i.txt
+.endc
+.end
diff --git a/library/SubcircuitLibrary/74ls169/74LS169.kicad_sch b/library/SubcircuitLibrary/74ls169/74LS169.kicad_sch
new file mode 100644
index 000000000..435ec9371
--- /dev/null
+++ b/library/SubcircuitLibrary/74ls169/74LS169.kicad_sch
@@ -0,0 +1,4283 @@
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+ (reference "U43") (unit 1) (value "d_inverter") (footprint "")
+ )
+ (path "/4855e623-75a1-471d-8737-880dd2f3d419"
+ (reference "U44") (unit 1) (value "d_inverter") (footprint "")
+ )
+ (path "/ac93b201-30eb-417b-b87e-1131a74752c4"
+ (reference "U45") (unit 1) (value "d_inverter") (footprint "")
+ )
+ (path "/9cc036be-e087-471d-b3dd-1bf6fdc7cfcc"
+ (reference "U46") (unit 1) (value "d_inverter") (footprint "")
+ )
+ (path "/d4e221ff-a0a8-4f6a-b7e8-357cbe471891"
+ (reference "U47") (unit 1) (value "d_inverter") (footprint "")
+ )
+ (path "/70ba39aa-db98-4c31-8207-9c4df540e4fa"
+ (reference "U48") (unit 1) (value "d_inverter") (footprint "")
+ )
+ (path "/2681f2fe-ad93-4b87-a592-b8ad29ba87de"
+ (reference "U49") (unit 1) (value "d_inverter") (footprint "")
+ )
+ (path "/4f1dada7-7e4b-4156-96d4-b2ece2930d58"
+ (reference "U50") (unit 1) (value "d_dff") (footprint "")
+ )
+ (path "/a31c2199-56a9-428c-9cb1-03f8fa89d097"
+ (reference "U51") (unit 1) (value "d_dff") (footprint "")
+ )
+ (path "/01c4a998-f298-4cbf-a299-deed1e24a294"
+ (reference "U52") (unit 1) (value "d_dff") (footprint "")
+ )
+ (path "/dffc2bee-5622-40b3-a0a3-cba46966088a"
+ (reference "U53") (unit 1) (value "d_dff") (footprint "")
+ )
+ (path "/83ec739e-8fd2-4117-adc2-d7a5fb9df5fc"
+ (reference "U54") (unit 1) (value "d_inverter") (footprint "")
+ )
+ (path "/87086941-3f23-443a-ba26-6be40a74c362"
+ (reference "U55") (unit 1) (value "d_inverter") (footprint "")
+ )
+ (path "/8825c0ac-70ef-4698-bc86-aac07b7547eb"
+ (reference "U56") (unit 1) (value "d_inverter") (footprint "")
+ )
+ (path "/6f1ed631-244d-40c5-b794-ef791dc3abe3"
+ (reference "U57") (unit 1) (value "d_inverter") (footprint "")
+ )
+ (path "/6cdbfa29-31e0-4ab1-9d4c-e5b9a25922f2"
+ (reference "X1") (unit 1) (value "3_and") (footprint "")
+ )
+ (path "/b1c6f69f-f553-467e-b95d-d0d087257be7"
+ (reference "X2") (unit 1) (value "4_OR") (footprint "")
+ )
+ (path "/05b69e02-6a72-4c18-a82d-3f9e9dd5ac53"
+ (reference "X3") (unit 1) (value "5_and") (footprint "")
+ )
+ (path "/2d4d0937-34c7-403a-b7b6-b1d59b76d9bd"
+ (reference "X4") (unit 1) (value "3_and") (footprint "")
+ )
+ (path "/02870e95-51b0-4c41-a55b-e270799e5c67"
+ (reference "X5") (unit 1) (value "3_and") (footprint "")
+ )
+ (path "/b700fad6-6f08-4296-98df-95253b875f5e"
+ (reference "X6") (unit 1) (value "3_and") (footprint "")
+ )
+ (path "/127b2304-ca24-48c6-836a-3527412ffcca"
+ (reference "X7") (unit 1) (value "3_and") (footprint "")
+ )
+ (path "/ac190e46-daa4-4c71-b035-3386547102a2"
+ (reference "X8") (unit 1) (value "4_and") (footprint "")
+ )
+ (path "/61f21e70-0b3e-4394-8750-c225b8daa6d5"
+ (reference "X9") (unit 1) (value "3_and") (footprint "")
+ )
+ (path "/33b51808-c568-4e12-b75e-f55a73c756ed"
+ (reference "X10") (unit 1) (value "5_and") (footprint "")
+ )
+ (path "/459d9d23-d37f-4e62-ab70-f1a248c60ef0"
+ (reference "X11") (unit 1) (value "4_OR") (footprint "")
+ )
+ (path "/ce1cd20d-d8a2-47d9-8909-0a2fe6afd438"
+ (reference "X12") (unit 1) (value "4_OR") (footprint "")
+ )
+ (path "/625288a8-a4ea-414d-93e6-5545db7d4118"
+ (reference "X13") (unit 1) (value "4_OR") (footprint "")
+ )
+ (path "/3c4538fe-547d-43cd-aace-3e2de939ca33"
+ (reference "X14") (unit 1) (value "4_OR") (footprint "")
+ )
+ )
+)
diff --git a/library/SubcircuitLibrary/74ls169/74LS169.sub b/library/SubcircuitLibrary/74ls169/74LS169.sub
new file mode 100644
index 000000000..3aa4367f9
--- /dev/null
+++ b/library/SubcircuitLibrary/74ls169/74LS169.sub
@@ -0,0 +1,248 @@
+* Subcircuit 74LS169
+.subckt 74LS169 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ unconnected-_u1-pad8_ net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad13_ net-_u1-pad14_ net-_u1-pad15_ unconnected-_u1-pad16_
+.title kicad schematic
+.include 5_and.sub
+.include 3_and.sub
+.include 4_OR.sub
+.include 4_and.sub
+x10 net-_u21-pad1_ net-_u27-pad1_ net-_u23-pad3_ net-_u24-pad3_ net-_u25-pad3_ net-_x10-pad6_ 5_and
+x3 net-_u23-pad3_ net-_u24-pad3_ net-_u25-pad3_ net-_u26-pad3_ net-_u14-pad2_ net-_u41-pad1_ 5_and
+x7 net-_x2-pad5_ net-_u13-pad2_ net-_u22-pad2_ net-_x14-pad2_ 3_and
+x9 net-_u39-pad3_ net-_u13-pad2_ net-_u20-pad2_ net-_x13-pad2_ 3_and
+x8 net-_u19-pad1_ net-_u27-pad1_ net-_u23-pad3_ net-_u24-pad3_ net-_x13-pad1_ 4_and
+* u7 net-_u13-pad2_ net-_u1-pad5_ net-_u7-pad3_ d_nor
+* u8 net-_u13-pad2_ net-_u1-pad6_ net-_u8-pad3_ d_nor
+* u26 net-_u21-pad3_ net-_u22-pad3_ net-_u26-pad3_ d_nor
+* u25 net-_u19-pad3_ net-_u20-pad3_ net-_u25-pad3_ d_nor
+* u22 net-_u12-pad1_ net-_u22-pad2_ net-_u22-pad3_ d_and
+* u21 net-_u21-pad1_ net-_u12-pad2_ net-_u21-pad3_ d_and
+* u20 net-_u12-pad1_ net-_u20-pad2_ net-_u20-pad3_ d_and
+* u19 net-_u19-pad1_ net-_u12-pad2_ net-_u19-pad3_ d_and
+* u18 net-_u12-pad1_ net-_u18-pad2_ net-_u18-pad3_ d_and
+* u17 net-_u17-pad1_ net-_u12-pad2_ net-_u17-pad3_ d_and
+* u4 net-_u1-pad2_ net-_u4-pad2_ d_inverter
+* u2 net-_u1-pad1_ net-_u12-pad1_ d_inverter
+* u6 net-_u13-pad2_ net-_u1-pad4_ net-_u6-pad3_ d_nor
+* u5 net-_u13-pad2_ net-_u1-pad3_ net-_u5-pad3_ d_nor
+* u3 net-_u1-pad9_ net-_u13-pad1_ d_inverter
+* u31 net-_u27-pad2_ net-_u28-pad2_ net-_u31-pad3_ d_or
+* u27 net-_u27-pad1_ net-_u27-pad2_ d_inverter
+* u28 net-_u23-pad3_ net-_u28-pad2_ d_inverter
+* u39 net-_u31-pad3_ net-_u36-pad2_ net-_u39-pad3_ d_or
+* u36 net-_u24-pad3_ net-_u36-pad2_ d_inverter
+x2 net-_u32-pad2_ net-_u33-pad2_ net-_u34-pad2_ net-_u35-pad2_ net-_x2-pad5_ 4_OR
+* u32 net-_u27-pad1_ net-_u32-pad2_ d_inverter
+* u34 net-_u24-pad3_ net-_u34-pad2_ d_inverter
+* u35 net-_u25-pad3_ net-_u35-pad2_ d_inverter
+* u33 net-_u23-pad3_ net-_u33-pad2_ d_inverter
+* u11 net-_u1-pad10_ net-_u11-pad2_ d_inverter
+* u10 net-_u1-pad7_ net-_u10-pad2_ d_inverter
+* u9 net-_u13-pad1_ net-_u9-pad2_ d_inverter
+* u12 net-_u12-pad1_ net-_u12-pad2_ d_inverter
+* u13 net-_u13-pad1_ net-_u13-pad2_ d_inverter
+x1 net-_u9-pad2_ net-_u10-pad2_ net-_u11-pad2_ net-_u27-pad1_ 3_and
+* u14 net-_u1-pad10_ net-_u14-pad2_ d_inverter
+* u30 net-_u23-pad3_ net-_u30-pad2_ d_inverter
+* u37 net-_u29-pad2_ net-_u30-pad2_ net-_u37-pad3_ d_or
+* u29 net-_u27-pad1_ net-_u29-pad2_ d_inverter
+x6 net-_u37-pad3_ net-_u13-pad2_ net-_u18-pad2_ net-_x12-pad2_ 3_and
+* u24 net-_u17-pad3_ net-_u18-pad3_ net-_u24-pad3_ d_nor
+x4 net-_u38-pad2_ net-_u13-pad2_ net-_u16-pad2_ net-_x11-pad2_ 3_and
+x5 net-_u17-pad1_ net-_u27-pad1_ net-_u23-pad3_ net-_x12-pad1_ 3_and
+* u40 net-_u15-pad1_ net-_u27-pad1_ net-_u40-pad3_ d_and
+* u38 net-_u27-pad1_ net-_u38-pad2_ d_inverter
+* u23 net-_u15-pad3_ net-_u16-pad3_ net-_u23-pad3_ d_nor
+* u16 net-_u12-pad1_ net-_u16-pad2_ net-_u16-pad3_ d_and
+* u15 net-_u15-pad1_ net-_u12-pad2_ net-_u15-pad3_ d_and
+* u41 net-_u41-pad1_ net-_u1-pad15_ d_inverter
+* u45 net-_u45-pad1_ net-_u45-pad2_ d_inverter
+x14 net-_x10-pad6_ net-_x14-pad2_ net-_u8-pad3_ unconnected-_x14-pad4_ net-_u45-pad1_ 4_OR
+* u53 net-_u42-pad2_ net-_u49-pad2_ unconnected-_u53-pad3_ unconnected-_u53-pad4_ net-_u15-pad1_ net-_u16-pad2_ d_dff
+* u42 net-_u42-pad1_ net-_u42-pad2_ d_inverter
+x11 net-_u40-pad3_ net-_x11-pad2_ net-_u5-pad3_ unconnected-_x11-pad4_ net-_u42-pad1_ 4_OR
+x12 net-_x12-pad1_ net-_x12-pad2_ net-_u6-pad3_ unconnected-_x12-pad4_ net-_u43-pad1_ 4_OR
+* u51 net-_u44-pad2_ net-_u47-pad2_ unconnected-_u51-pad3_ unconnected-_u51-pad4_ net-_u19-pad1_ net-_u20-pad2_ d_dff
+x13 net-_x13-pad1_ net-_x13-pad2_ net-_u7-pad3_ unconnected-_x13-pad4_ net-_u44-pad1_ 4_OR
+* u43 net-_u43-pad1_ net-_u43-pad2_ d_inverter
+* u44 net-_u44-pad1_ net-_u44-pad2_ d_inverter
+* u49 net-_u4-pad2_ net-_u49-pad2_ d_inverter
+* u50 net-_u43-pad2_ net-_u46-pad2_ unconnected-_u50-pad3_ unconnected-_u50-pad4_ net-_u17-pad1_ net-_u18-pad2_ d_dff
+* u46 net-_u4-pad2_ net-_u46-pad2_ d_inverter
+* u57 net-_u16-pad2_ net-_u1-pad14_ d_inverter
+* u54 net-_u18-pad2_ net-_u1-pad13_ d_inverter
+* u47 net-_u4-pad2_ net-_u47-pad2_ d_inverter
+* u55 net-_u20-pad2_ net-_u1-pad12_ d_inverter
+* u52 net-_u45-pad2_ net-_u48-pad2_ unconnected-_u52-pad3_ unconnected-_u52-pad4_ net-_u21-pad1_ net-_u22-pad2_ d_dff
+* u48 net-_u4-pad2_ net-_u48-pad2_ d_inverter
+* u56 net-_u22-pad2_ net-_u1-pad11_ d_inverter
+a1 [net-_u13-pad2_ net-_u1-pad5_ ] net-_u7-pad3_ u7
+a2 [net-_u13-pad2_ net-_u1-pad6_ ] net-_u8-pad3_ u8
+a3 [net-_u21-pad3_ net-_u22-pad3_ ] net-_u26-pad3_ u26
+a4 [net-_u19-pad3_ net-_u20-pad3_ ] net-_u25-pad3_ u25
+a5 [net-_u12-pad1_ net-_u22-pad2_ ] net-_u22-pad3_ u22
+a6 [net-_u21-pad1_ net-_u12-pad2_ ] net-_u21-pad3_ u21
+a7 [net-_u12-pad1_ net-_u20-pad2_ ] net-_u20-pad3_ u20
+a8 [net-_u19-pad1_ net-_u12-pad2_ ] net-_u19-pad3_ u19
+a9 [net-_u12-pad1_ net-_u18-pad2_ ] net-_u18-pad3_ u18
+a10 [net-_u17-pad1_ net-_u12-pad2_ ] net-_u17-pad3_ u17
+a11 net-_u1-pad2_ net-_u4-pad2_ u4
+a12 net-_u1-pad1_ net-_u12-pad1_ u2
+a13 [net-_u13-pad2_ net-_u1-pad4_ ] net-_u6-pad3_ u6
+a14 [net-_u13-pad2_ net-_u1-pad3_ ] net-_u5-pad3_ u5
+a15 net-_u1-pad9_ net-_u13-pad1_ u3
+a16 [net-_u27-pad2_ net-_u28-pad2_ ] net-_u31-pad3_ u31
+a17 net-_u27-pad1_ net-_u27-pad2_ u27
+a18 net-_u23-pad3_ net-_u28-pad2_ u28
+a19 [net-_u31-pad3_ net-_u36-pad2_ ] net-_u39-pad3_ u39
+a20 net-_u24-pad3_ net-_u36-pad2_ u36
+a21 net-_u27-pad1_ net-_u32-pad2_ u32
+a22 net-_u24-pad3_ net-_u34-pad2_ u34
+a23 net-_u25-pad3_ net-_u35-pad2_ u35
+a24 net-_u23-pad3_ net-_u33-pad2_ u33
+a25 net-_u1-pad10_ net-_u11-pad2_ u11
+a26 net-_u1-pad7_ net-_u10-pad2_ u10
+a27 net-_u13-pad1_ net-_u9-pad2_ u9
+a28 net-_u12-pad1_ net-_u12-pad2_ u12
+a29 net-_u13-pad1_ net-_u13-pad2_ u13
+a30 net-_u1-pad10_ net-_u14-pad2_ u14
+a31 net-_u23-pad3_ net-_u30-pad2_ u30
+a32 [net-_u29-pad2_ net-_u30-pad2_ ] net-_u37-pad3_ u37
+a33 net-_u27-pad1_ net-_u29-pad2_ u29
+a34 [net-_u17-pad3_ net-_u18-pad3_ ] net-_u24-pad3_ u24
+a35 [net-_u15-pad1_ net-_u27-pad1_ ] net-_u40-pad3_ u40
+a36 net-_u27-pad1_ net-_u38-pad2_ u38
+a37 [net-_u15-pad3_ net-_u16-pad3_ ] net-_u23-pad3_ u23
+a38 [net-_u12-pad1_ net-_u16-pad2_ ] net-_u16-pad3_ u16
+a39 [net-_u15-pad1_ net-_u12-pad2_ ] net-_u15-pad3_ u15
+a40 net-_u41-pad1_ net-_u1-pad15_ u41
+a41 net-_u45-pad1_ net-_u45-pad2_ u45
+a42 net-_u42-pad2_ net-_u49-pad2_ unconnected-_u53-pad3_ unconnected-_u53-pad4_ net-_u15-pad1_ net-_u16-pad2_ u53
+a43 net-_u42-pad1_ net-_u42-pad2_ u42
+a44 net-_u44-pad2_ net-_u47-pad2_ unconnected-_u51-pad3_ unconnected-_u51-pad4_ net-_u19-pad1_ net-_u20-pad2_ u51
+a45 net-_u43-pad1_ net-_u43-pad2_ u43
+a46 net-_u44-pad1_ net-_u44-pad2_ u44
+a47 net-_u4-pad2_ net-_u49-pad2_ u49
+a48 net-_u43-pad2_ net-_u46-pad2_ unconnected-_u50-pad3_ unconnected-_u50-pad4_ net-_u17-pad1_ net-_u18-pad2_ u50
+a49 net-_u4-pad2_ net-_u46-pad2_ u46
+a50 net-_u16-pad2_ net-_u1-pad14_ u57
+a51 net-_u18-pad2_ net-_u1-pad13_ u54
+a52 net-_u4-pad2_ net-_u47-pad2_ u47
+a53 net-_u20-pad2_ net-_u1-pad12_ u55
+a54 net-_u45-pad2_ net-_u48-pad2_ unconnected-_u52-pad3_ unconnected-_u52-pad4_ net-_u21-pad1_ net-_u22-pad2_ u52
+a55 net-_u4-pad2_ net-_u48-pad2_ u48
+a56 net-_u22-pad2_ net-_u1-pad11_ u56
+* Schematic Name: d_nor, Ngspice Name: d_nor
+.model u7 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_nor, Ngspice Name: d_nor
+.model u8 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_nor, Ngspice Name: d_nor
+.model u26 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_nor, Ngspice Name: d_nor
+.model u25 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, Ngspice Name: d_and
+.model u22 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, Ngspice Name: d_and
+.model u21 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, Ngspice Name: d_and
+.model u20 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, Ngspice Name: d_and
+.model u19 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, Ngspice Name: d_and
+.model u18 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, Ngspice Name: d_and
+.model u17 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, Ngspice Name: d_inverter
+.model u4 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, Ngspice Name: d_inverter
+.model u2 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_nor, Ngspice Name: d_nor
+.model u6 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_nor, Ngspice Name: d_nor
+.model u5 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, Ngspice Name: d_inverter
+.model u3 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_or, Ngspice Name: d_or
+.model u31 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, Ngspice Name: d_inverter
+.model u27 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, Ngspice Name: d_inverter
+.model u28 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_or, Ngspice Name: d_or
+.model u39 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, Ngspice Name: d_inverter
+.model u36 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, Ngspice Name: d_inverter
+.model u32 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, Ngspice Name: d_inverter
+.model u34 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, Ngspice Name: d_inverter
+.model u35 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, Ngspice Name: d_inverter
+.model u33 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, Ngspice Name: d_inverter
+.model u11 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, Ngspice Name: d_inverter
+.model u10 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, Ngspice Name: d_inverter
+.model u9 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, Ngspice Name: d_inverter
+.model u12 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, Ngspice Name: d_inverter
+.model u13 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, Ngspice Name: d_inverter
+.model u14 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, Ngspice Name: d_inverter
+.model u30 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_or, Ngspice Name: d_or
+.model u37 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, Ngspice Name: d_inverter
+.model u29 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_nor, Ngspice Name: d_nor
+.model u24 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, Ngspice Name: d_and
+.model u40 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, Ngspice Name: d_inverter
+.model u38 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_nor, Ngspice Name: d_nor
+.model u23 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, Ngspice Name: d_and
+.model u16 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, Ngspice Name: d_and
+.model u15 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, Ngspice Name: d_inverter
+.model u41 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, Ngspice Name: d_inverter
+.model u45 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_dff, Ngspice Name: d_dff
+.model u53 d_dff(clk_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0 ic=0 data_load=1.0e-12 clk_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 )
+* Schematic Name: d_inverter, Ngspice Name: d_inverter
+.model u42 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_dff, Ngspice Name: d_dff
+.model u51 d_dff(clk_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0 ic=0 data_load=1.0e-12 clk_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 )
+* Schematic Name: d_inverter, Ngspice Name: d_inverter
+.model u43 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, Ngspice Name: d_inverter
+.model u44 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, Ngspice Name: d_inverter
+.model u49 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_dff, Ngspice Name: d_dff
+.model u50 d_dff(clk_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0 ic=0 data_load=1.0e-12 clk_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 )
+* Schematic Name: d_inverter, Ngspice Name: d_inverter
+.model u46 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, Ngspice Name: d_inverter
+.model u57 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, Ngspice Name: d_inverter
+.model u54 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, Ngspice Name: d_inverter
+.model u47 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, Ngspice Name: d_inverter
+.model u55 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_dff, Ngspice Name: d_dff
+.model u52 d_dff(clk_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0 ic=0 data_load=1.0e-12 clk_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 )
+* Schematic Name: d_inverter, Ngspice Name: d_inverter
+.model u48 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, Ngspice Name: d_inverter
+.model u56 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Control Statements
+
+.ends 74LS169
\ No newline at end of file
diff --git a/library/SubcircuitLibrary/74ls169/74LS169_Previous_Values.xml b/library/SubcircuitLibrary/74ls169/74LS169_Previous_Values.xml
new file mode 100644
index 000000000..d1d2995d2
--- /dev/null
+++ b/library/SubcircuitLibrary/74ls169/74LS169_Previous_Values.xml
@@ -0,0 +1 @@
+truefalsefalseHzHz0Volts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or Amperessecsecsecd_nord_nord_nord_nord_andd_andd_andd_andd_andd_andd_inverterd_inverterd_nord_nord_inverterd_ord_inverterd_inverterd_ord_inverterd_inverterd_inverterd_inverterd_inverterd_inverterd_inverterd_inverterd_inverterd_inverterd_inverterd_inverterd_ord_inverterd_nord_andd_inverterd_nord_andd_andd_inverterd_inverterd_dffd_inverterd_dffd_inverterd_inverterd_inverterd_dffd_inverterd_inverterd_inverterd_inverterd_inverterd_dffd_inverterd_inverterC:\Users\Sakhi\FOSSEE\eSim\library\SubcircuitLibrary\5_andC:\Users\Sakhi\FOSSEE\eSim\library\SubcircuitLibrary\5_andC:\Users\Sakhi\FOSSEE\eSim\library\SubcircuitLibrary\3_andC:\Users\Sakhi\FOSSEE\eSim\library\SubcircuitLibrary\3_andC:\Users\Sakhi\FOSSEE\eSim\library\SubcircuitLibrary\4_andC:\Users\Sakhi\FOSSEE\eSim\library\SubcircuitLibrary\4_ORC:\Users\Sakhi\FOSSEE\eSim\library\SubcircuitLibrary\3_andC:\Users\Sakhi\FOSSEE\eSim\library\SubcircuitLibrary\3_andC:\Users\Sakhi\FOSSEE\eSim\library\SubcircuitLibrary\3_andC:\Users\Sakhi\FOSSEE\eSim\library\SubcircuitLibrary\3_andC:\Users\Sakhi\FOSSEE\eSim\library\SubcircuitLibrary\4_ORC:\Users\Sakhi\FOSSEE\eSim\library\SubcircuitLibrary\4_ORC:\Users\Sakhi\FOSSEE\eSim\library\SubcircuitLibrary\4_ORC:\Users\Sakhi\FOSSEE\eSim\library\SubcircuitLibrary\4_OR
\ No newline at end of file
diff --git a/library/SubcircuitLibrary/74ls169/analysis b/library/SubcircuitLibrary/74ls169/analysis
new file mode 100644
index 000000000..ebd5c0a94
--- /dev/null
+++ b/library/SubcircuitLibrary/74ls169/analysis
@@ -0,0 +1 @@
+.tran 0e-00 0e-00 0e-00
\ No newline at end of file
diff --git a/library/SubcircuitLibrary/MC14532B/3_and-cache.lib b/library/SubcircuitLibrary/MC14532B/3_and-cache.lib
new file mode 100644
index 000000000..af0586415
--- /dev/null
+++ b/library/SubcircuitLibrary/MC14532B/3_and-cache.lib
@@ -0,0 +1,61 @@
+EESchema-LIBRARY Version 2.3
+#encoding utf-8
+#
+# PORT
+#
+DEF PORT U 0 40 Y Y 26 F N
+F0 "U" 50 100 30 H V C CNN
+F1 "PORT" 0 0 30 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0
+A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50
+S -100 50 100 -50 0 1 0 N
+X ~ 1 250 0 100 L 30 30 1 1 B
+X ~ 2 250 0 100 L 30 30 2 1 B
+X ~ 3 250 0 100 L 30 30 3 1 B
+X ~ 4 250 0 100 L 30 30 4 1 B
+X ~ 5 250 0 100 L 30 30 5 1 B
+X ~ 6 250 0 100 L 30 30 6 1 B
+X ~ 7 250 0 100 L 30 30 7 1 B
+X ~ 8 250 0 100 L 30 30 8 1 B
+X ~ 9 250 0 100 L 30 30 9 1 B
+X ~ 10 250 0 100 L 30 30 10 1 B
+X ~ 11 250 0 100 L 30 30 11 1 B
+X ~ 12 250 0 100 L 30 30 12 1 B
+X ~ 13 250 0 100 L 30 30 13 1 B
+X ~ 14 250 0 100 L 30 30 14 1 B
+X ~ 15 250 0 100 L 30 30 15 1 B
+X ~ 16 250 0 100 L 30 30 16 1 B
+X ~ 17 250 0 100 L 30 30 17 1 B
+X ~ 18 250 0 100 L 30 30 18 1 B
+X ~ 19 250 0 100 L 30 30 19 1 B
+X ~ 20 250 0 100 L 30 30 20 1 B
+X ~ 21 250 0 100 L 30 30 21 1 B
+X ~ 22 250 0 100 L 30 30 22 1 B
+X ~ 23 250 0 100 L 30 30 23 1 B
+X ~ 24 250 0 100 L 30 30 24 1 B
+X ~ 25 250 0 100 L 30 30 25 1 B
+X ~ 26 250 0 100 L 30 30 26 1 B
+ENDDRAW
+ENDDEF
+#
+# d_and
+#
+DEF d_and U 0 40 Y Y 1 F N
+F0 "U" 0 0 60 H V C CNN
+F1 "d_and" 50 100 60 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A 149 50 100 -894 0 0 1 0 N 150 -50 250 50
+A 150 49 100 6 900 0 1 0 N 250 50 150 150
+P 4 0 1 0 150 -50 -250 -50 -250 150 150 150 N
+X IN1 1 -450 100 200 R 50 50 1 1 I
+X IN2 2 -450 0 200 R 50 50 1 1 I
+X OUT 3 450 50 200 L 50 50 1 1 O
+ENDDRAW
+ENDDEF
+#
+#End Library
diff --git a/library/SubcircuitLibrary/MC14532B/3_and.cir b/library/SubcircuitLibrary/MC14532B/3_and.cir
new file mode 100644
index 000000000..ba296cf01
--- /dev/null
+++ b/library/SubcircuitLibrary/MC14532B/3_and.cir
@@ -0,0 +1,13 @@
+* C:\Users\malli\eSim\src\SubcircuitLibrary\3_and\3_and.cir
+
+* EESchema Netlist Version 1.1 (Spice format) creation date: 03/26/19 18:42:57
+
+* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N
+* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0
+
+* Sheet Name: /
+U2 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U2-Pad3_ d_and
+U3 Net-_U2-Pad3_ Net-_U1-Pad3_ Net-_U1-Pad4_ d_and
+U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ PORT
+
+.end
diff --git a/library/SubcircuitLibrary/MC14532B/3_and.cir.out b/library/SubcircuitLibrary/MC14532B/3_and.cir.out
new file mode 100644
index 000000000..d7cf79a07
--- /dev/null
+++ b/library/SubcircuitLibrary/MC14532B/3_and.cir.out
@@ -0,0 +1,20 @@
+* c:\users\malli\esim\src\subcircuitlibrary\3_and\3_and.cir
+
+* u2 net-_u1-pad1_ net-_u1-pad2_ net-_u2-pad3_ d_and
+* u3 net-_u2-pad3_ net-_u1-pad3_ net-_u1-pad4_ d_and
+* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ port
+a1 [net-_u1-pad1_ net-_u1-pad2_ ] net-_u2-pad3_ u2
+a2 [net-_u2-pad3_ net-_u1-pad3_ ] net-_u1-pad4_ u3
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u3 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+.tran 0e-00 0e-00 0e-00
+
+* Control Statements
+.control
+run
+print allv > plot_data_v.txt
+print alli > plot_data_i.txt
+.endc
+.end
diff --git a/library/SubcircuitLibrary/MC14532B/3_and.pro b/library/SubcircuitLibrary/MC14532B/3_and.pro
new file mode 100644
index 000000000..06813ca78
--- /dev/null
+++ b/library/SubcircuitLibrary/MC14532B/3_and.pro
@@ -0,0 +1,43 @@
+update=Wed Mar 18 19:54:53 2020
+version=1
+last_client=eeschema
+[general]
+version=1
+RootSch=
+BoardNm=
+[pcbnew]
+version=1
+LastNetListRead=
+UseCmpFile=1
+PadDrill=0.600000000000
+PadDrillOvalY=0.600000000000
+PadSizeH=1.500000000000
+PadSizeV=1.500000000000
+PcbTextSizeV=1.500000000000
+PcbTextSizeH=1.500000000000
+PcbTextThickness=0.300000000000
+ModuleTextSizeV=1.000000000000
+ModuleTextSizeH=1.000000000000
+ModuleTextSizeThickness=0.150000000000
+SolderMaskClearance=0.000000000000
+SolderMaskMinWidth=0.000000000000
+DrawSegmentWidth=0.200000000000
+BoardOutlineThickness=0.100000000000
+ModuleOutlineThickness=0.150000000000
+[cvpcb]
+version=1
+NetIExt=net
+[eeschema]
+version=1
+LibDir=../../../kicadSchematicLibrary
+[eeschema/libraries]
+LibName1=eSim_Analog
+LibName2=eSim_Devices
+LibName3=eSim_Digital
+LibName4=eSim_Hybrid
+LibName5=eSim_Miscellaneous
+LibName6=eSim_Plot
+LibName7=eSim_Power
+LibName8=eSim_Sources
+LibName9=eSim_Subckt
+LibName10=eSim_User
diff --git a/library/SubcircuitLibrary/MC14532B/3_and.sch b/library/SubcircuitLibrary/MC14532B/3_and.sch
new file mode 100644
index 000000000..d6ac89f95
--- /dev/null
+++ b/library/SubcircuitLibrary/MC14532B/3_and.sch
@@ -0,0 +1,130 @@
+EESchema Schematic File Version 2
+LIBS:power
+LIBS:texas
+LIBS:intel
+LIBS:audio
+LIBS:interface
+LIBS:digital-audio
+LIBS:philips
+LIBS:display
+LIBS:cypress
+LIBS:siliconi
+LIBS:opto
+LIBS:atmel
+LIBS:contrib
+LIBS:valves
+LIBS:eSim_Analog
+LIBS:eSim_Devices
+LIBS:eSim_Digital
+LIBS:eSim_Hybrid
+LIBS:eSim_Miscellaneous
+LIBS:eSim_Plot
+LIBS:eSim_Power
+LIBS:eSim_PSpice
+LIBS:eSim_Sources
+LIBS:eSim_Subckt
+LIBS:eSim_User
+LIBS:3_and-cache
+EELAYER 25 0
+EELAYER END
+$Descr A4 11693 8268
+encoding utf-8
+Sheet 1 1
+Title ""
+Date ""
+Rev ""
+Comp ""
+Comment1 ""
+Comment2 ""
+Comment3 ""
+Comment4 ""
+$EndDescr
+$Comp
+L d_and U2
+U 1 1 5C9A24D8
+P 4250 2700
+F 0 "U2" H 4250 2700 60 0000 C CNN
+F 1 "d_and" H 4300 2800 60 0000 C CNN
+F 2 "" H 4250 2700 60 0000 C CNN
+F 3 "" H 4250 2700 60 0000 C CNN
+ 1 4250 2700
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_and U3
+U 1 1 5C9A2538
+P 5150 2900
+F 0 "U3" H 5150 2900 60 0000 C CNN
+F 1 "d_and" H 5200 3000 60 0000 C CNN
+F 2 "" H 5150 2900 60 0000 C CNN
+F 3 "" H 5150 2900 60 0000 C CNN
+ 1 5150 2900
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 1 1 5C9A259A
+P 3050 2600
+F 0 "U1" H 3100 2700 30 0000 C CNN
+F 1 "PORT" H 3050 2600 30 0000 C CNN
+F 2 "" H 3050 2600 60 0000 C CNN
+F 3 "" H 3050 2600 60 0000 C CNN
+ 1 3050 2600
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 2 1 5C9A25D9
+P 3050 2800
+F 0 "U1" H 3100 2900 30 0000 C CNN
+F 1 "PORT" H 3050 2800 30 0000 C CNN
+F 2 "" H 3050 2800 60 0000 C CNN
+F 3 "" H 3050 2800 60 0000 C CNN
+ 2 3050 2800
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 3 1 5C9A260A
+P 3050 3100
+F 0 "U1" H 3100 3200 30 0000 C CNN
+F 1 "PORT" H 3050 3100 30 0000 C CNN
+F 2 "" H 3050 3100 60 0000 C CNN
+F 3 "" H 3050 3100 60 0000 C CNN
+ 3 3050 3100
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 4 1 5C9A2637
+P 6900 2850
+F 0 "U1" H 6950 2950 30 0000 C CNN
+F 1 "PORT" H 6900 2850 30 0000 C CNN
+F 2 "" H 6900 2850 60 0000 C CNN
+F 3 "" H 6900 2850 60 0000 C CNN
+ 4 6900 2850
+ -1 0 0 1
+$EndComp
+Wire Wire Line
+ 4700 2650 4700 2800
+Wire Wire Line
+ 5600 2850 6650 2850
+Wire Wire Line
+ 3800 2600 3300 2600
+Wire Wire Line
+ 3800 2700 3300 2700
+Wire Wire Line
+ 3300 2700 3300 2800
+Wire Wire Line
+ 3300 3100 4700 3100
+Wire Wire Line
+ 4700 3100 4700 2900
+Text Notes 3500 2600 0 60 ~ 12
+in1
+Text Notes 3450 2800 0 60 ~ 12
+in2\n
+Text Notes 3500 3100 0 60 ~ 12
+in3
+Text Notes 6100 2850 0 60 ~ 12
+out
+$EndSCHEMATC
diff --git a/library/SubcircuitLibrary/MC14532B/3_and.sub b/library/SubcircuitLibrary/MC14532B/3_and.sub
new file mode 100644
index 000000000..3d9120bb6
--- /dev/null
+++ b/library/SubcircuitLibrary/MC14532B/3_and.sub
@@ -0,0 +1,14 @@
+* Subcircuit 3_and
+.subckt 3_and net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_
+* c:\users\malli\esim\src\subcircuitlibrary\3_and\3_and.cir
+* u2 net-_u1-pad1_ net-_u1-pad2_ net-_u2-pad3_ d_and
+* u3 net-_u2-pad3_ net-_u1-pad3_ net-_u1-pad4_ d_and
+a1 [net-_u1-pad1_ net-_u1-pad2_ ] net-_u2-pad3_ u2
+a2 [net-_u2-pad3_ net-_u1-pad3_ ] net-_u1-pad4_ u3
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u3 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+* Control Statements
+
+.ends 3_and
\ No newline at end of file
diff --git a/library/SubcircuitLibrary/MC14532B/3_and_Previous_Values.xml b/library/SubcircuitLibrary/MC14532B/3_and_Previous_Values.xml
new file mode 100644
index 000000000..abc5faaae
--- /dev/null
+++ b/library/SubcircuitLibrary/MC14532B/3_and_Previous_Values.xml
@@ -0,0 +1 @@
+d_andd_andtruefalsefalseHzHz0Volts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesSecSecSec
\ No newline at end of file
diff --git a/library/SubcircuitLibrary/MC14532B/4_OR-cache.lib b/library/SubcircuitLibrary/MC14532B/4_OR-cache.lib
new file mode 100644
index 000000000..155f5e601
--- /dev/null
+++ b/library/SubcircuitLibrary/MC14532B/4_OR-cache.lib
@@ -0,0 +1,63 @@
+EESchema-LIBRARY Version 2.3
+#encoding utf-8
+#
+# PORT
+#
+DEF PORT U 0 40 Y Y 26 F N
+F0 "U" 50 100 30 H V C CNN
+F1 "PORT" 0 0 30 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0
+A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50
+S -100 50 100 -50 0 1 0 N
+X ~ 1 250 0 100 L 30 30 1 1 B
+X ~ 2 250 0 100 L 30 30 2 1 B
+X ~ 3 250 0 100 L 30 30 3 1 B
+X ~ 4 250 0 100 L 30 30 4 1 B
+X ~ 5 250 0 100 L 30 30 5 1 B
+X ~ 6 250 0 100 L 30 30 6 1 B
+X ~ 7 250 0 100 L 30 30 7 1 B
+X ~ 8 250 0 100 L 30 30 8 1 B
+X ~ 9 250 0 100 L 30 30 9 1 B
+X ~ 10 250 0 100 L 30 30 10 1 B
+X ~ 11 250 0 100 L 30 30 11 1 B
+X ~ 12 250 0 100 L 30 30 12 1 B
+X ~ 13 250 0 100 L 30 30 13 1 B
+X ~ 14 250 0 100 L 30 30 14 1 B
+X ~ 15 250 0 100 L 30 30 15 1 B
+X ~ 16 250 0 100 L 30 30 16 1 B
+X ~ 17 250 0 100 L 30 30 17 1 B
+X ~ 18 250 0 100 L 30 30 18 1 B
+X ~ 19 250 0 100 L 30 30 19 1 B
+X ~ 20 250 0 100 L 30 30 20 1 B
+X ~ 21 250 0 100 L 30 30 21 1 B
+X ~ 22 250 0 100 L 30 30 22 1 B
+X ~ 23 250 0 100 L 30 30 23 1 B
+X ~ 24 250 0 100 L 30 30 24 1 B
+X ~ 25 250 0 100 L 30 30 25 1 B
+X ~ 26 250 0 100 L 30 30 26 1 B
+ENDDRAW
+ENDDEF
+#
+# d_or
+#
+DEF d_or U 0 40 Y Y 1 F N
+F0 "U" 0 0 60 H V C CNN
+F1 "d_or" 0 100 60 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A -450 50 224 266 -266 0 1 0 N -250 150 -250 -50
+A -25 -124 325 574 323 0 1 0 N 150 150 250 50
+A 74 125 191 -665 -231 0 1 0 N 150 -50 250 50
+P 2 0 1 0 -250 -50 150 -50 N
+P 2 0 1 0 -250 150 150 150 N
+X IN1 1 -450 100 215 R 50 50 1 1 I
+X IN2 2 -450 0 215 R 50 50 1 1 I
+X OUT 3 450 50 200 L 50 50 1 1 O
+ENDDRAW
+ENDDEF
+#
+#End Library
diff --git a/library/SubcircuitLibrary/MC14532B/4_OR.cir b/library/SubcircuitLibrary/MC14532B/4_OR.cir
new file mode 100644
index 000000000..b338b7b5f
--- /dev/null
+++ b/library/SubcircuitLibrary/MC14532B/4_OR.cir
@@ -0,0 +1,14 @@
+* C:\Users\malli\eSim\src\SubcircuitLibrary\4_OR\4_OR.cir
+
+* EESchema Netlist Version 1.1 (Spice format) creation date: 03/28/19 22:47:12
+
+* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N
+* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0
+
+* Sheet Name: /
+U2 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U2-Pad3_ d_or
+U3 Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U3-Pad3_ d_or
+U4 Net-_U2-Pad3_ Net-_U3-Pad3_ Net-_U1-Pad5_ d_or
+U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ PORT
+
+.end
diff --git a/library/SubcircuitLibrary/MC14532B/4_OR.cir.out b/library/SubcircuitLibrary/MC14532B/4_OR.cir.out
new file mode 100644
index 000000000..adb6b01be
--- /dev/null
+++ b/library/SubcircuitLibrary/MC14532B/4_OR.cir.out
@@ -0,0 +1,24 @@
+* c:\users\malli\esim\src\subcircuitlibrary\4_or\4_or.cir
+
+* u2 net-_u1-pad1_ net-_u1-pad2_ net-_u2-pad3_ d_or
+* u3 net-_u1-pad3_ net-_u1-pad4_ net-_u3-pad3_ d_or
+* u4 net-_u2-pad3_ net-_u3-pad3_ net-_u1-pad5_ d_or
+* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ port
+a1 [net-_u1-pad1_ net-_u1-pad2_ ] net-_u2-pad3_ u2
+a2 [net-_u1-pad3_ net-_u1-pad4_ ] net-_u3-pad3_ u3
+a3 [net-_u2-pad3_ net-_u3-pad3_ ] net-_u1-pad5_ u4
+* Schematic Name: d_or, NgSpice Name: d_or
+.model u2 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+* Schematic Name: d_or, NgSpice Name: d_or
+.model u3 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+* Schematic Name: d_or, NgSpice Name: d_or
+.model u4 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+.tran 0e-00 0e-00 0e-00
+
+* Control Statements
+.control
+run
+print allv > plot_data_v.txt
+print alli > plot_data_i.txt
+.endc
+.end
diff --git a/library/SubcircuitLibrary/MC14532B/4_OR.pro b/library/SubcircuitLibrary/MC14532B/4_OR.pro
new file mode 100644
index 000000000..881563ebd
--- /dev/null
+++ b/library/SubcircuitLibrary/MC14532B/4_OR.pro
@@ -0,0 +1,44 @@
+update=06/01/19 12:36:09
+version=1
+last_client=eeschema
+[general]
+version=1
+RootSch=
+BoardNm=
+[pcbnew]
+version=1
+LastNetListRead=
+UseCmpFile=1
+PadDrill=0.600000000000
+PadDrillOvalY=0.600000000000
+PadSizeH=1.500000000000
+PadSizeV=1.500000000000
+PcbTextSizeV=1.500000000000
+PcbTextSizeH=1.500000000000
+PcbTextThickness=0.300000000000
+ModuleTextSizeV=1.000000000000
+ModuleTextSizeH=1.000000000000
+ModuleTextSizeThickness=0.150000000000
+SolderMaskClearance=0.000000000000
+SolderMaskMinWidth=0.000000000000
+DrawSegmentWidth=0.200000000000
+BoardOutlineThickness=0.100000000000
+ModuleOutlineThickness=0.150000000000
+[cvpcb]
+version=1
+NetIExt=net
+[eeschema]
+version=1
+LibDir=../../../kicadSchematicLibrary
+[eeschema/libraries]
+LibName1=power
+LibName2=eSim_Analog
+LibName3=eSim_Devices
+LibName4=eSim_Digital
+LibName5=eSim_Hybrid
+LibName6=eSim_Miscellaneous
+LibName7=eSim_Plot
+LibName8=eSim_Power
+LibName9=eSim_User
+LibName10=eSim_Sources
+LibName11=eSim_Subckt
diff --git a/library/SubcircuitLibrary/MC14532B/4_OR.sch b/library/SubcircuitLibrary/MC14532B/4_OR.sch
new file mode 100644
index 000000000..118968656
--- /dev/null
+++ b/library/SubcircuitLibrary/MC14532B/4_OR.sch
@@ -0,0 +1,150 @@
+EESchema Schematic File Version 2
+LIBS:power
+LIBS:eSim_Analog
+LIBS:eSim_Devices
+LIBS:eSim_Digital
+LIBS:eSim_Hybrid
+LIBS:eSim_Miscellaneous
+LIBS:eSim_Plot
+LIBS:eSim_Power
+LIBS:eSim_PSpice
+LIBS:eSim_Sources
+LIBS:eSim_Subckt
+LIBS:eSim_User
+EELAYER 25 0
+EELAYER END
+$Descr A4 11693 8268
+encoding utf-8
+Sheet 1 1
+Title ""
+Date ""
+Rev ""
+Comp ""
+Comment1 ""
+Comment2 ""
+Comment3 ""
+Comment4 ""
+$EndDescr
+$Comp
+L d_or U2
+U 1 1 5C9D00E1
+P 4300 2950
+F 0 "U2" H 4300 2950 60 0000 C CNN
+F 1 "d_or" H 4300 3050 60 0000 C CNN
+F 2 "" H 4300 2950 60 0000 C CNN
+F 3 "" H 4300 2950 60 0000 C CNN
+ 1 4300 2950
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_or U3
+U 1 1 5C9D011F
+P 4300 3350
+F 0 "U3" H 4300 3350 60 0000 C CNN
+F 1 "d_or" H 4300 3450 60 0000 C CNN
+F 2 "" H 4300 3350 60 0000 C CNN
+F 3 "" H 4300 3350 60 0000 C CNN
+ 1 4300 3350
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_or U4
+U 1 1 5C9D0141
+P 5250 3150
+F 0 "U4" H 5250 3150 60 0000 C CNN
+F 1 "d_or" H 5250 3250 60 0000 C CNN
+F 2 "" H 5250 3150 60 0000 C CNN
+F 3 "" H 5250 3150 60 0000 C CNN
+ 1 5250 3150
+ 1 0 0 -1
+$EndComp
+Wire Wire Line
+ 4800 3050 4800 2900
+Wire Wire Line
+ 4800 2900 4750 2900
+Wire Wire Line
+ 4800 3150 4800 3300
+Wire Wire Line
+ 4800 3300 4750 3300
+Wire Wire Line
+ 3350 2850 3850 2850
+Wire Wire Line
+ 3850 2950 3600 2950
+Wire Wire Line
+ 3850 3250 3350 3250
+Wire Wire Line
+ 3600 2950 3600 3000
+Wire Wire Line
+ 3600 3000 3350 3000
+Wire Wire Line
+ 3850 3350 3850 3400
+Wire Wire Line
+ 3850 3400 3350 3400
+Wire Wire Line
+ 5700 3100 6200 3100
+$Comp
+L PORT U1
+U 1 1 5C9D01F4
+P 3100 2850
+F 0 "U1" H 3150 2950 30 0000 C CNN
+F 1 "PORT" H 3100 2850 30 0000 C CNN
+F 2 "" H 3100 2850 60 0000 C CNN
+F 3 "" H 3100 2850 60 0000 C CNN
+ 1 3100 2850
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 2 1 5C9D022F
+P 3100 3000
+F 0 "U1" H 3150 3100 30 0000 C CNN
+F 1 "PORT" H 3100 3000 30 0000 C CNN
+F 2 "" H 3100 3000 60 0000 C CNN
+F 3 "" H 3100 3000 60 0000 C CNN
+ 2 3100 3000
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 3 1 5C9D0271
+P 3100 3250
+F 0 "U1" H 3150 3350 30 0000 C CNN
+F 1 "PORT" H 3100 3250 30 0000 C CNN
+F 2 "" H 3100 3250 60 0000 C CNN
+F 3 "" H 3100 3250 60 0000 C CNN
+ 3 3100 3250
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 4 1 5C9D0299
+P 3100 3400
+F 0 "U1" H 3150 3500 30 0000 C CNN
+F 1 "PORT" H 3100 3400 30 0000 C CNN
+F 2 "" H 3100 3400 60 0000 C CNN
+F 3 "" H 3100 3400 60 0000 C CNN
+ 4 3100 3400
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 5 1 5C9D02C2
+P 6450 3100
+F 0 "U1" H 6500 3200 30 0000 C CNN
+F 1 "PORT" H 6450 3100 30 0000 C CNN
+F 2 "" H 6450 3100 60 0000 C CNN
+F 3 "" H 6450 3100 60 0000 C CNN
+ 5 6450 3100
+ -1 0 0 1
+$EndComp
+Text Notes 3450 2850 0 60 ~ 12
+in1
+Text Notes 3450 3000 0 60 ~ 12
+in2
+Text Notes 3450 3250 0 60 ~ 12
+in3
+Text Notes 3450 3400 0 60 ~ 12
+in4
+Text Notes 5800 3100 0 60 ~ 12
+out
+$EndSCHEMATC
diff --git a/library/SubcircuitLibrary/MC14532B/4_OR.sub b/library/SubcircuitLibrary/MC14532B/4_OR.sub
new file mode 100644
index 000000000..d1fd3a241
--- /dev/null
+++ b/library/SubcircuitLibrary/MC14532B/4_OR.sub
@@ -0,0 +1,18 @@
+* Subcircuit 4_OR
+.subckt 4_OR net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_
+* c:\users\malli\esim\src\subcircuitlibrary\4_or\4_or.cir
+* u2 net-_u1-pad1_ net-_u1-pad2_ net-_u2-pad3_ d_or
+* u3 net-_u1-pad3_ net-_u1-pad4_ net-_u3-pad3_ d_or
+* u4 net-_u2-pad3_ net-_u3-pad3_ net-_u1-pad5_ d_or
+a1 [net-_u1-pad1_ net-_u1-pad2_ ] net-_u2-pad3_ u2
+a2 [net-_u1-pad3_ net-_u1-pad4_ ] net-_u3-pad3_ u3
+a3 [net-_u2-pad3_ net-_u3-pad3_ ] net-_u1-pad5_ u4
+* Schematic Name: d_or, NgSpice Name: d_or
+.model u2 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+* Schematic Name: d_or, NgSpice Name: d_or
+.model u3 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+* Schematic Name: d_or, NgSpice Name: d_or
+.model u4 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+* Control Statements
+
+.ends 4_OR
\ No newline at end of file
diff --git a/library/SubcircuitLibrary/MC14532B/4_OR_Previous_Values.xml b/library/SubcircuitLibrary/MC14532B/4_OR_Previous_Values.xml
new file mode 100644
index 000000000..0683d9eb6
--- /dev/null
+++ b/library/SubcircuitLibrary/MC14532B/4_OR_Previous_Values.xml
@@ -0,0 +1 @@
+d_ord_ord_ortruefalsefalseHzHz0Volts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesSecSecSec
\ No newline at end of file
diff --git a/library/SubcircuitLibrary/MC14532B/4_and-cache.lib b/library/SubcircuitLibrary/MC14532B/4_and-cache.lib
new file mode 100644
index 000000000..60f1a83d4
--- /dev/null
+++ b/library/SubcircuitLibrary/MC14532B/4_and-cache.lib
@@ -0,0 +1,79 @@
+EESchema-LIBRARY Version 2.3
+#encoding utf-8
+#
+# 3_and-RESCUE-4_and
+#
+DEF 3_and-RESCUE-4_and X 0 40 Y Y 1 F N
+F0 "X" 900 300 60 H V C CNN
+F1 "3_and-RESCUE-4_and" 950 500 60 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A 950 400 158 716 -716 0 1 0 N 1000 550 1000 250
+P 2 0 1 0 650 550 1000 550 N
+P 3 0 1 0 650 550 650 250 1000 250 N
+X in1 1 450 500 200 R 50 50 1 1 I
+X in2 2 450 400 200 R 50 50 1 1 I
+X in3 3 450 300 200 R 50 50 1 1 I
+X out 4 1300 400 200 L 50 50 1 1 O
+ENDDRAW
+ENDDEF
+#
+# PORT
+#
+DEF PORT U 0 40 Y Y 26 F N
+F0 "U" 50 100 30 H V C CNN
+F1 "PORT" 0 0 30 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0
+A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50
+S -100 50 100 -50 0 1 0 N
+X ~ 1 250 0 100 L 30 30 1 1 B
+X ~ 2 250 0 100 L 30 30 2 1 B
+X ~ 3 250 0 100 L 30 30 3 1 B
+X ~ 4 250 0 100 L 30 30 4 1 B
+X ~ 5 250 0 100 L 30 30 5 1 B
+X ~ 6 250 0 100 L 30 30 6 1 B
+X ~ 7 250 0 100 L 30 30 7 1 B
+X ~ 8 250 0 100 L 30 30 8 1 B
+X ~ 9 250 0 100 L 30 30 9 1 B
+X ~ 10 250 0 100 L 30 30 10 1 B
+X ~ 11 250 0 100 L 30 30 11 1 B
+X ~ 12 250 0 100 L 30 30 12 1 B
+X ~ 13 250 0 100 L 30 30 13 1 B
+X ~ 14 250 0 100 L 30 30 14 1 B
+X ~ 15 250 0 100 L 30 30 15 1 B
+X ~ 16 250 0 100 L 30 30 16 1 B
+X ~ 17 250 0 100 L 30 30 17 1 B
+X ~ 18 250 0 100 L 30 30 18 1 B
+X ~ 19 250 0 100 L 30 30 19 1 B
+X ~ 20 250 0 100 L 30 30 20 1 B
+X ~ 21 250 0 100 L 30 30 21 1 B
+X ~ 22 250 0 100 L 30 30 22 1 B
+X ~ 23 250 0 100 L 30 30 23 1 B
+X ~ 24 250 0 100 L 30 30 24 1 B
+X ~ 25 250 0 100 L 30 30 25 1 B
+X ~ 26 250 0 100 L 30 30 26 1 B
+ENDDRAW
+ENDDEF
+#
+# d_and
+#
+DEF d_and U 0 40 Y Y 1 F N
+F0 "U" 0 0 60 H V C CNN
+F1 "d_and" 50 100 60 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A 149 50 100 -894 0 0 1 0 N 150 -50 250 50
+A 150 49 100 6 900 0 1 0 N 250 50 150 150
+P 4 0 1 0 150 -50 -250 -50 -250 150 150 150 N
+X IN1 1 -450 100 200 R 50 50 1 1 I
+X IN2 2 -450 0 200 R 50 50 1 1 I
+X OUT 3 450 50 200 L 50 50 1 1 O
+ENDDRAW
+ENDDEF
+#
+#End Library
diff --git a/library/SubcircuitLibrary/MC14532B/4_and-rescue.lib b/library/SubcircuitLibrary/MC14532B/4_and-rescue.lib
new file mode 100644
index 000000000..e38330518
--- /dev/null
+++ b/library/SubcircuitLibrary/MC14532B/4_and-rescue.lib
@@ -0,0 +1,22 @@
+EESchema-LIBRARY Version 2.3
+#encoding utf-8
+#
+# 3_and-RESCUE-4_and
+#
+DEF 3_and-RESCUE-4_and X 0 40 Y Y 1 F N
+F0 "X" 900 300 60 H V C CNN
+F1 "3_and-RESCUE-4_and" 950 500 60 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A 950 400 158 716 -716 0 1 0 N 1000 550 1000 250
+P 2 0 1 0 650 550 1000 550 N
+P 3 0 1 0 650 550 650 250 1000 250 N
+X in1 1 450 500 200 R 50 50 1 1 I
+X in2 2 450 400 200 R 50 50 1 1 I
+X in3 3 450 300 200 R 50 50 1 1 I
+X out 4 1300 400 200 L 50 50 1 1 O
+ENDDRAW
+ENDDEF
+#
+#End Library
diff --git a/library/SubcircuitLibrary/MC14532B/4_and.cir b/library/SubcircuitLibrary/MC14532B/4_and.cir
new file mode 100644
index 000000000..fdf2e1074
--- /dev/null
+++ b/library/SubcircuitLibrary/MC14532B/4_and.cir
@@ -0,0 +1,13 @@
+* C:\Users\malli\eSim\src\SubcircuitLibrary\4_and\4_and.cir
+
+* EESchema Netlist Version 1.1 (Spice format) creation date: 06/01/19 13:09:58
+
+* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N
+* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0
+
+* Sheet Name: /
+X1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U2-Pad1_ 3_and
+U2 Net-_U2-Pad1_ Net-_U1-Pad4_ Net-_U1-Pad5_ d_and
+U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ PORT
+
+.end
diff --git a/library/SubcircuitLibrary/MC14532B/4_and.cir.out b/library/SubcircuitLibrary/MC14532B/4_and.cir.out
new file mode 100644
index 000000000..f40e5bc62
--- /dev/null
+++ b/library/SubcircuitLibrary/MC14532B/4_and.cir.out
@@ -0,0 +1,18 @@
+* c:\users\malli\esim\src\subcircuitlibrary\4_and\4_and.cir
+
+.include 3_and.sub
+x1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u2-pad1_ 3_and
+* u2 net-_u2-pad1_ net-_u1-pad4_ net-_u1-pad5_ d_and
+* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ port
+a1 [net-_u2-pad1_ net-_u1-pad4_ ] net-_u1-pad5_ u2
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+.tran 0e-00 0e-00 0e-00
+
+* Control Statements
+.control
+run
+print allv > plot_data_v.txt
+print alli > plot_data_i.txt
+.endc
+.end
diff --git a/library/SubcircuitLibrary/MC14532B/4_and.pro b/library/SubcircuitLibrary/MC14532B/4_and.pro
new file mode 100644
index 000000000..b13a0a825
--- /dev/null
+++ b/library/SubcircuitLibrary/MC14532B/4_and.pro
@@ -0,0 +1,57 @@
+update=Wed Mar 18 19:54:24 2020
+version=1
+last_client=eeschema
+[general]
+version=1
+RootSch=
+BoardNm=
+[pcbnew]
+version=1
+LastNetListRead=
+UseCmpFile=1
+PadDrill=0.600000000000
+PadDrillOvalY=0.600000000000
+PadSizeH=1.500000000000
+PadSizeV=1.500000000000
+PcbTextSizeV=1.500000000000
+PcbTextSizeH=1.500000000000
+PcbTextThickness=0.300000000000
+ModuleTextSizeV=1.000000000000
+ModuleTextSizeH=1.000000000000
+ModuleTextSizeThickness=0.150000000000
+SolderMaskClearance=0.000000000000
+SolderMaskMinWidth=0.000000000000
+DrawSegmentWidth=0.200000000000
+BoardOutlineThickness=0.100000000000
+ModuleOutlineThickness=0.150000000000
+[cvpcb]
+version=1
+NetIExt=net
+[eeschema]
+version=1
+LibDir=../../../kicadSchematicLibrary
+[eeschema/libraries]
+LibName1=4_and-rescue
+LibName2=texas
+LibName3=intel
+LibName4=audio
+LibName5=interface
+LibName6=digital-audio
+LibName7=philips
+LibName8=display
+LibName9=cypress
+LibName10=siliconi
+LibName11=opto
+LibName12=atmel
+LibName13=contrib
+LibName14=valves
+LibName15=eSim_Analog
+LibName16=eSim_Devices
+LibName17=eSim_Digital
+LibName18=eSim_Hybrid
+LibName19=eSim_Miscellaneous
+LibName20=eSim_Plot
+LibName21=eSim_Power
+LibName22=eSim_Sources
+LibName23=eSim_Subckt
+LibName24=eSim_User
diff --git a/library/SubcircuitLibrary/MC14532B/4_and.sch b/library/SubcircuitLibrary/MC14532B/4_and.sch
new file mode 100644
index 000000000..f5e8febdc
--- /dev/null
+++ b/library/SubcircuitLibrary/MC14532B/4_and.sch
@@ -0,0 +1,151 @@
+EESchema Schematic File Version 2
+LIBS:4_and-rescue
+LIBS:texas
+LIBS:intel
+LIBS:audio
+LIBS:interface
+LIBS:digital-audio
+LIBS:philips
+LIBS:display
+LIBS:cypress
+LIBS:siliconi
+LIBS:opto
+LIBS:atmel
+LIBS:contrib
+LIBS:valves
+LIBS:eSim_Analog
+LIBS:eSim_Devices
+LIBS:eSim_Digital
+LIBS:eSim_Hybrid
+LIBS:eSim_Miscellaneous
+LIBS:eSim_Plot
+LIBS:eSim_Power
+LIBS:eSim_PSpice
+LIBS:eSim_Sources
+LIBS:eSim_Subckt
+LIBS:eSim_User
+LIBS:4_and-cache
+EELAYER 25 0
+EELAYER END
+$Descr A4 11693 8268
+encoding utf-8
+Sheet 1 1
+Title ""
+Date ""
+Rev ""
+Comp ""
+Comment1 ""
+Comment2 ""
+Comment3 ""
+Comment4 ""
+$EndDescr
+$Comp
+L 3_and-RESCUE-4_and X1
+U 1 1 5C9A2915
+P 3700 3500
+F 0 "X1" H 4600 3800 60 0000 C CNN
+F 1 "3_and" H 4650 4000 60 0000 C CNN
+F 2 "" H 3700 3500 60 0000 C CNN
+F 3 "" H 3700 3500 60 0000 C CNN
+ 1 3700 3500
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_and U2
+U 1 1 5C9A2940
+P 5450 3400
+F 0 "U2" H 5450 3400 60 0000 C CNN
+F 1 "d_and" H 5500 3500 60 0000 C CNN
+F 2 "" H 5450 3400 60 0000 C CNN
+F 3 "" H 5450 3400 60 0000 C CNN
+ 1 5450 3400
+ 1 0 0 -1
+$EndComp
+Wire Wire Line
+ 5000 3100 5000 3300
+Wire Wire Line
+ 4150 3000 4150 2700
+Wire Wire Line
+ 4150 2700 3200 2700
+Wire Wire Line
+ 4150 3100 4000 3100
+Wire Wire Line
+ 4000 3100 4000 3000
+Wire Wire Line
+ 4000 3000 3200 3000
+Wire Wire Line
+ 4150 3200 4150 3300
+Wire Wire Line
+ 4150 3300 3250 3300
+Wire Wire Line
+ 5000 3400 5000 3550
+Wire Wire Line
+ 5000 3550 3250 3550
+Wire Wire Line
+ 5900 3350 6500 3350
+$Comp
+L PORT U1
+U 1 1 5C9A29B1
+P 2950 2700
+F 0 "U1" H 3000 2800 30 0000 C CNN
+F 1 "PORT" H 2950 2700 30 0000 C CNN
+F 2 "" H 2950 2700 60 0000 C CNN
+F 3 "" H 2950 2700 60 0000 C CNN
+ 1 2950 2700
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 2 1 5C9A29E9
+P 2950 3000
+F 0 "U1" H 3000 3100 30 0000 C CNN
+F 1 "PORT" H 2950 3000 30 0000 C CNN
+F 2 "" H 2950 3000 60 0000 C CNN
+F 3 "" H 2950 3000 60 0000 C CNN
+ 2 2950 3000
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 3 1 5C9A2A0D
+P 3000 3300
+F 0 "U1" H 3050 3400 30 0000 C CNN
+F 1 "PORT" H 3000 3300 30 0000 C CNN
+F 2 "" H 3000 3300 60 0000 C CNN
+F 3 "" H 3000 3300 60 0000 C CNN
+ 3 3000 3300
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 4 1 5C9A2A3C
+P 3000 3550
+F 0 "U1" H 3050 3650 30 0000 C CNN
+F 1 "PORT" H 3000 3550 30 0000 C CNN
+F 2 "" H 3000 3550 60 0000 C CNN
+F 3 "" H 3000 3550 60 0000 C CNN
+ 4 3000 3550
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 5 1 5C9A2A68
+P 6750 3350
+F 0 "U1" H 6800 3450 30 0000 C CNN
+F 1 "PORT" H 6750 3350 30 0000 C CNN
+F 2 "" H 6750 3350 60 0000 C CNN
+F 3 "" H 6750 3350 60 0000 C CNN
+ 5 6750 3350
+ -1 0 0 1
+$EndComp
+Text Notes 3450 2650 0 60 ~ 12
+in1
+Text Notes 3450 2950 0 60 ~ 12
+in2
+Text Notes 3500 3300 0 60 ~ 12
+in3
+Text Notes 3500 3550 0 60 ~ 12
+in4
+Text Notes 6150 3350 0 60 ~ 12
+out
+$EndSCHEMATC
diff --git a/library/SubcircuitLibrary/MC14532B/4_and.sub b/library/SubcircuitLibrary/MC14532B/4_and.sub
new file mode 100644
index 000000000..8663f37e6
--- /dev/null
+++ b/library/SubcircuitLibrary/MC14532B/4_and.sub
@@ -0,0 +1,12 @@
+* Subcircuit 4_and
+.subckt 4_and net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_
+* c:\users\malli\esim\src\subcircuitlibrary\4_and\4_and.cir
+.include 3_and.sub
+x1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u2-pad1_ 3_and
+* u2 net-_u2-pad1_ net-_u1-pad4_ net-_u1-pad5_ d_and
+a1 [net-_u2-pad1_ net-_u1-pad4_ ] net-_u1-pad5_ u2
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+* Control Statements
+
+.ends 4_and
\ No newline at end of file
diff --git a/library/SubcircuitLibrary/MC14532B/4_and_Previous_Values.xml b/library/SubcircuitLibrary/MC14532B/4_and_Previous_Values.xml
new file mode 100644
index 000000000..f2ba0130e
--- /dev/null
+++ b/library/SubcircuitLibrary/MC14532B/4_and_Previous_Values.xml
@@ -0,0 +1 @@
+d_andC:\Users\malli\eSim\src\SubcircuitLibrary\3_andtruefalsefalseHzHz0Volts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesSecSecSec
\ No newline at end of file
diff --git a/library/SubcircuitLibrary/MC14532B/5_and-cache.lib b/library/SubcircuitLibrary/MC14532B/5_and-cache.lib
new file mode 100644
index 000000000..fc177c1f9
--- /dev/null
+++ b/library/SubcircuitLibrary/MC14532B/5_and-cache.lib
@@ -0,0 +1,79 @@
+EESchema-LIBRARY Version 2.3
+#encoding utf-8
+#
+# 3_and-RESCUE-5_and
+#
+DEF 3_and-RESCUE-5_and X 0 40 Y Y 1 F N
+F0 "X" 900 300 60 H V C CNN
+F1 "3_and-RESCUE-5_and" 950 500 60 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A 950 400 158 716 -716 0 1 0 N 1000 550 1000 250
+P 2 0 1 0 650 550 1000 550 N
+P 3 0 1 0 650 550 650 250 1000 250 N
+X in1 1 450 500 200 R 50 50 1 1 I
+X in2 2 450 400 200 R 50 50 1 1 I
+X in3 3 450 300 200 R 50 50 1 1 I
+X out 4 1300 400 200 L 50 50 1 1 O
+ENDDRAW
+ENDDEF
+#
+# PORT
+#
+DEF PORT U 0 40 Y Y 26 F N
+F0 "U" 50 100 30 H V C CNN
+F1 "PORT" 0 0 30 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0
+A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50
+S -100 50 100 -50 0 1 0 N
+X ~ 1 250 0 100 L 30 30 1 1 B
+X ~ 2 250 0 100 L 30 30 2 1 B
+X ~ 3 250 0 100 L 30 30 3 1 B
+X ~ 4 250 0 100 L 30 30 4 1 B
+X ~ 5 250 0 100 L 30 30 5 1 B
+X ~ 6 250 0 100 L 30 30 6 1 B
+X ~ 7 250 0 100 L 30 30 7 1 B
+X ~ 8 250 0 100 L 30 30 8 1 B
+X ~ 9 250 0 100 L 30 30 9 1 B
+X ~ 10 250 0 100 L 30 30 10 1 B
+X ~ 11 250 0 100 L 30 30 11 1 B
+X ~ 12 250 0 100 L 30 30 12 1 B
+X ~ 13 250 0 100 L 30 30 13 1 B
+X ~ 14 250 0 100 L 30 30 14 1 B
+X ~ 15 250 0 100 L 30 30 15 1 B
+X ~ 16 250 0 100 L 30 30 16 1 B
+X ~ 17 250 0 100 L 30 30 17 1 B
+X ~ 18 250 0 100 L 30 30 18 1 B
+X ~ 19 250 0 100 L 30 30 19 1 B
+X ~ 20 250 0 100 L 30 30 20 1 B
+X ~ 21 250 0 100 L 30 30 21 1 B
+X ~ 22 250 0 100 L 30 30 22 1 B
+X ~ 23 250 0 100 L 30 30 23 1 B
+X ~ 24 250 0 100 L 30 30 24 1 B
+X ~ 25 250 0 100 L 30 30 25 1 B
+X ~ 26 250 0 100 L 30 30 26 1 B
+ENDDRAW
+ENDDEF
+#
+# d_and
+#
+DEF d_and U 0 40 Y Y 1 F N
+F0 "U" 0 0 60 H V C CNN
+F1 "d_and" 50 100 60 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A 149 50 100 -894 0 0 1 0 N 150 -50 250 50
+A 150 49 100 6 900 0 1 0 N 250 50 150 150
+P 4 0 1 0 150 -50 -250 -50 -250 150 150 150 N
+X IN1 1 -450 100 200 R 50 50 1 1 I
+X IN2 2 -450 0 200 R 50 50 1 1 I
+X OUT 3 450 50 200 L 50 50 1 1 O
+ENDDRAW
+ENDDEF
+#
+#End Library
diff --git a/library/SubcircuitLibrary/MC14532B/5_and-rescue.lib b/library/SubcircuitLibrary/MC14532B/5_and-rescue.lib
new file mode 100644
index 000000000..483b8efb8
--- /dev/null
+++ b/library/SubcircuitLibrary/MC14532B/5_and-rescue.lib
@@ -0,0 +1,22 @@
+EESchema-LIBRARY Version 2.3
+#encoding utf-8
+#
+# 3_and-RESCUE-5_and
+#
+DEF 3_and-RESCUE-5_and X 0 40 Y Y 1 F N
+F0 "X" 900 300 60 H V C CNN
+F1 "3_and-RESCUE-5_and" 950 500 60 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A 950 400 158 716 -716 0 1 0 N 1000 550 1000 250
+P 2 0 1 0 650 550 1000 550 N
+P 3 0 1 0 650 550 650 250 1000 250 N
+X in1 1 450 500 200 R 50 50 1 1 I
+X in2 2 450 400 200 R 50 50 1 1 I
+X in3 3 450 300 200 R 50 50 1 1 I
+X out 4 1300 400 200 L 50 50 1 1 O
+ENDDRAW
+ENDDEF
+#
+#End Library
diff --git a/library/SubcircuitLibrary/MC14532B/5_and.cir b/library/SubcircuitLibrary/MC14532B/5_and.cir
new file mode 100644
index 000000000..6a05b9b5d
--- /dev/null
+++ b/library/SubcircuitLibrary/MC14532B/5_and.cir
@@ -0,0 +1,14 @@
+* C:\Users\malli\eSim\src\SubcircuitLibrary\5_and\5_and.cir
+
+* EESchema Netlist Version 1.1 (Spice format) creation date: 03/26/19 18:53:13
+
+* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N
+* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0
+
+* Sheet Name: /
+X1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U3-Pad1_ 3_and
+U2 Net-_U1-Pad4_ Net-_U1-Pad5_ Net-_U2-Pad3_ d_and
+U3 Net-_U3-Pad1_ Net-_U2-Pad3_ Net-_U1-Pad6_ d_and
+U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ Net-_U1-Pad6_ PORT
+
+.end
diff --git a/library/SubcircuitLibrary/MC14532B/5_and.cir.out b/library/SubcircuitLibrary/MC14532B/5_and.cir.out
new file mode 100644
index 000000000..6a6b126a7
--- /dev/null
+++ b/library/SubcircuitLibrary/MC14532B/5_and.cir.out
@@ -0,0 +1,22 @@
+* c:\users\malli\esim\src\subcircuitlibrary\5_and\5_and.cir
+
+.include 3_and.sub
+x1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u3-pad1_ 3_and
+* u2 net-_u1-pad4_ net-_u1-pad5_ net-_u2-pad3_ d_and
+* u3 net-_u3-pad1_ net-_u2-pad3_ net-_u1-pad6_ d_and
+* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ port
+a1 [net-_u1-pad4_ net-_u1-pad5_ ] net-_u2-pad3_ u2
+a2 [net-_u3-pad1_ net-_u2-pad3_ ] net-_u1-pad6_ u3
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u3 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+.tran 0e-00 0e-00 0e-00
+
+* Control Statements
+.control
+run
+print allv > plot_data_v.txt
+print alli > plot_data_i.txt
+.endc
+.end
diff --git a/library/SubcircuitLibrary/MC14532B/5_and.pro b/library/SubcircuitLibrary/MC14532B/5_and.pro
new file mode 100644
index 000000000..c16a3f858
--- /dev/null
+++ b/library/SubcircuitLibrary/MC14532B/5_and.pro
@@ -0,0 +1,49 @@
+update=Wed Mar 18 19:59:53 2020
+version=1
+last_client=eeschema
+[general]
+version=1
+RootSch=
+BoardNm=
+[pcbnew]
+version=1
+LastNetListRead=
+UseCmpFile=1
+PadDrill=0.600000000000
+PadDrillOvalY=0.600000000000
+PadSizeH=1.500000000000
+PadSizeV=1.500000000000
+PcbTextSizeV=1.500000000000
+PcbTextSizeH=1.500000000000
+PcbTextThickness=0.300000000000
+ModuleTextSizeV=1.000000000000
+ModuleTextSizeH=1.000000000000
+ModuleTextSizeThickness=0.150000000000
+SolderMaskClearance=0.000000000000
+SolderMaskMinWidth=0.000000000000
+DrawSegmentWidth=0.200000000000
+BoardOutlineThickness=0.100000000000
+ModuleOutlineThickness=0.150000000000
+[cvpcb]
+version=1
+NetIExt=net
+[eeschema]
+version=1
+LibDir=../../../kicadSchematicLibrary
+[eeschema/libraries]
+LibName1=cypress
+LibName2=siliconi
+LibName3=opto
+LibName4=atmel
+LibName5=contrib
+LibName6=valves
+LibName7=eSim_Analog
+LibName8=eSim_Devices
+LibName9=eSim_Digital
+LibName10=eSim_Hybrid
+LibName11=eSim_Miscellaneous
+LibName12=eSim_Plot
+LibName13=eSim_Power
+LibName14=eSim_User
+LibName15=eSim_Sources
+LibName16=eSim_Subckt
diff --git a/library/SubcircuitLibrary/MC14532B/5_and.sch b/library/SubcircuitLibrary/MC14532B/5_and.sch
new file mode 100644
index 000000000..aef3c0436
--- /dev/null
+++ b/library/SubcircuitLibrary/MC14532B/5_and.sch
@@ -0,0 +1,171 @@
+EESchema Schematic File Version 2
+LIBS:5_and-rescue
+LIBS:cypress
+LIBS:siliconi
+LIBS:opto
+LIBS:atmel
+LIBS:contrib
+LIBS:valves
+LIBS:eSim_Analog
+LIBS:eSim_Devices
+LIBS:eSim_Digital
+LIBS:eSim_Hybrid
+LIBS:eSim_Miscellaneous
+LIBS:eSim_Plot
+LIBS:eSim_Power
+LIBS:eSim_User
+LIBS:eSim_Sources
+LIBS:eSim_Subckt
+LIBS:5_and-cache
+EELAYER 25 0
+EELAYER END
+$Descr A4 11693 8268
+encoding utf-8
+Sheet 1 1
+Title ""
+Date ""
+Rev ""
+Comp ""
+Comment1 ""
+Comment2 ""
+Comment3 ""
+Comment4 ""
+$EndDescr
+$Comp
+L 3_and-RESCUE-5_and X1
+U 1 1 5C9A2741
+P 3800 3350
+F 0 "X1" H 4700 3650 60 0000 C CNN
+F 1 "3_and" H 4750 3850 60 0000 C CNN
+F 2 "" H 3800 3350 60 0000 C CNN
+F 3 "" H 3800 3350 60 0000 C CNN
+ 1 3800 3350
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_and U2
+U 1 1 5C9A2764
+P 4650 3400
+F 0 "U2" H 4650 3400 60 0000 C CNN
+F 1 "d_and" H 4700 3500 60 0000 C CNN
+F 2 "" H 4650 3400 60 0000 C CNN
+F 3 "" H 4650 3400 60 0000 C CNN
+ 1 4650 3400
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_and U3
+U 1 1 5C9A2791
+P 5550 3200
+F 0 "U3" H 5550 3200 60 0000 C CNN
+F 1 "d_and" H 5600 3300 60 0000 C CNN
+F 2 "" H 5550 3200 60 0000 C CNN
+F 3 "" H 5550 3200 60 0000 C CNN
+ 1 5550 3200
+ 1 0 0 -1
+$EndComp
+Wire Wire Line
+ 5100 3100 5100 2950
+Wire Wire Line
+ 5100 3200 5100 3350
+Wire Wire Line
+ 4250 2850 4250 2700
+Wire Wire Line
+ 4250 2700 3600 2700
+Wire Wire Line
+ 4250 2950 4150 2950
+Wire Wire Line
+ 4150 2950 4150 2900
+Wire Wire Line
+ 4150 2900 3600 2900
+Wire Wire Line
+ 4200 3300 3600 3300
+Wire Wire Line
+ 4250 3050 4250 3100
+Wire Wire Line
+ 4250 3100 3600 3100
+Wire Wire Line
+ 4200 3400 4200 3500
+Wire Wire Line
+ 4200 3500 3600 3500
+Wire Wire Line
+ 6000 3150 6500 3150
+$Comp
+L PORT U1
+U 1 1 5C9A2865
+P 3350 2700
+F 0 "U1" H 3400 2800 30 0000 C CNN
+F 1 "PORT" H 3350 2700 30 0000 C CNN
+F 2 "" H 3350 2700 60 0000 C CNN
+F 3 "" H 3350 2700 60 0000 C CNN
+ 1 3350 2700
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 2 1 5C9A28B6
+P 3350 2900
+F 0 "U1" H 3400 3000 30 0000 C CNN
+F 1 "PORT" H 3350 2900 30 0000 C CNN
+F 2 "" H 3350 2900 60 0000 C CNN
+F 3 "" H 3350 2900 60 0000 C CNN
+ 2 3350 2900
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 3 1 5C9A28D9
+P 3350 3100
+F 0 "U1" H 3400 3200 30 0000 C CNN
+F 1 "PORT" H 3350 3100 30 0000 C CNN
+F 2 "" H 3350 3100 60 0000 C CNN
+F 3 "" H 3350 3100 60 0000 C CNN
+ 3 3350 3100
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 4 1 5C9A28FF
+P 3350 3300
+F 0 "U1" H 3400 3400 30 0000 C CNN
+F 1 "PORT" H 3350 3300 30 0000 C CNN
+F 2 "" H 3350 3300 60 0000 C CNN
+F 3 "" H 3350 3300 60 0000 C CNN
+ 4 3350 3300
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 5 1 5C9A2928
+P 3350 3500
+F 0 "U1" H 3400 3600 30 0000 C CNN
+F 1 "PORT" H 3350 3500 30 0000 C CNN
+F 2 "" H 3350 3500 60 0000 C CNN
+F 3 "" H 3350 3500 60 0000 C CNN
+ 5 3350 3500
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 6 1 5C9A2958
+P 6750 3150
+F 0 "U1" H 6800 3250 30 0000 C CNN
+F 1 "PORT" H 6750 3150 30 0000 C CNN
+F 2 "" H 6750 3150 60 0000 C CNN
+F 3 "" H 6750 3150 60 0000 C CNN
+ 6 6750 3150
+ -1 0 0 1
+$EndComp
+Text Notes 3800 2700 0 60 ~ 12
+in1
+Text Notes 3800 2900 0 60 ~ 12
+in2
+Text Notes 3800 3100 0 60 ~ 12
+in3
+Text Notes 3800 3300 0 60 ~ 12
+in4
+Text Notes 3800 3500 0 60 ~ 12
+in5
+Text Notes 6150 3150 0 60 ~ 12
+out
+$EndSCHEMATC
diff --git a/library/SubcircuitLibrary/MC14532B/5_and.sub b/library/SubcircuitLibrary/MC14532B/5_and.sub
new file mode 100644
index 000000000..35b10e173
--- /dev/null
+++ b/library/SubcircuitLibrary/MC14532B/5_and.sub
@@ -0,0 +1,16 @@
+* Subcircuit 5_and
+.subckt 5_and net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_
+* c:\users\malli\esim\src\subcircuitlibrary\5_and\5_and.cir
+.include 3_and.sub
+x1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u3-pad1_ 3_and
+* u2 net-_u1-pad4_ net-_u1-pad5_ net-_u2-pad3_ d_and
+* u3 net-_u3-pad1_ net-_u2-pad3_ net-_u1-pad6_ d_and
+a1 [net-_u1-pad4_ net-_u1-pad5_ ] net-_u2-pad3_ u2
+a2 [net-_u3-pad1_ net-_u2-pad3_ ] net-_u1-pad6_ u3
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u3 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+* Control Statements
+
+.ends 5_and
\ No newline at end of file
diff --git a/library/SubcircuitLibrary/MC14532B/5_and_Previous_Values.xml b/library/SubcircuitLibrary/MC14532B/5_and_Previous_Values.xml
new file mode 100644
index 000000000..ae2c08a7f
--- /dev/null
+++ b/library/SubcircuitLibrary/MC14532B/5_and_Previous_Values.xml
@@ -0,0 +1 @@
+d_andd_andC:\Users\malli\eSim\src\SubcircuitLibrary\3_andtruefalsefalseHzHz0Volts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesSecSecSec
\ No newline at end of file
diff --git a/library/SubcircuitLibrary/MC14532B/MC14532B.cir b/library/SubcircuitLibrary/MC14532B/MC14532B.cir
new file mode 100644
index 000000000..f1580f3c3
--- /dev/null
+++ b/library/SubcircuitLibrary/MC14532B/MC14532B.cir
@@ -0,0 +1,45 @@
+.title KiCad schematic
+U50 Net-_U50-Pad1_ /7 d_inverter
+U1 /1 /2 /3 /4 /5 /6 /7 unconnected-_U1-Pad8_ /9 /10 /11 /12 /13 /14 /15 unconnected-_U1-Pad16_ PORT
+X10 Net-_X10-Pad1_ Net-_X10-Pad2_ Net-_U39-Pad3_ Net-_U42-Pad3_ Net-_U50-Pad1_ 4_and
+U44 Net-_U44-Pad1_ Net-_U26-Pad2_ Net-_U44-Pad3_ d_or
+X4 Net-_U20-Pad2_ Net-_U29-Pad2_ Net-_U29-Pad2_ Net-_U26-Pad2_ Net-_X10-Pad1_ 4_OR
+X3 Net-_U27-Pad2_ Net-_U28-Pad2_ Net-_U19-Pad2_ Net-_U30-Pad2_ Net-_U44-Pad1_ 4_OR
+X8 Net-_U44-Pad3_ Net-_X6-Pad5_ Net-_X7-Pad5_ Net-_U41-Pad3_ Net-_U46-Pad1_ 4_and
+U46 Net-_U46-Pad1_ /9 d_inverter
+X6 Net-_U21-Pad2_ Net-_U28-Pad2_ Net-_U30-Pad2_ Net-_U26-Pad2_ Net-_X6-Pad5_ 4_OR
+X5 Net-_U21-Pad2_ Net-_U28-Pad2_ Net-_U29-Pad2_ Net-_U26-Pad2_ Net-_X10-Pad2_ 4_OR
+U37 Net-_U22-Pad2_ Net-_U26-Pad2_ Net-_U37-Pad3_ d_or
+X7 Net-_U23-Pad2_ Net-_U30-Pad2_ Net-_U26-Pad2_ unconnected-_X7-Pad4_ Net-_X7-Pad5_ 4_OR
+U38 Net-_U23-Pad2_ Net-_U26-Pad2_ Net-_U38-Pad3_ d_or
+U41 Net-_U25-Pad2_ Net-_U26-Pad2_ Net-_U41-Pad3_ d_or
+U39 Net-_U24-Pad2_ Net-_U26-Pad2_ Net-_U39-Pad3_ d_or
+U42 Net-_U25-Pad2_ Net-_U26-Pad2_ Net-_U42-Pad3_ d_or
+U40 Net-_U24-Pad2_ Net-_U26-Pad2_ Net-_U40-Pad3_ d_or
+U49 Net-_U36-Pad2_ /15 d_inverter
+U43 Net-_U25-Pad2_ Net-_U26-Pad2_ Net-_U43-Pad3_ d_or
+X2 Net-_U33-Pad3_ Net-_U32-Pad3_ Net-_U31-Pad3_ Net-_U34-Pad3_ /5 Net-_U36-Pad1_ 5_and
+X1 Net-_U31-Pad3_ Net-_U32-Pad3_ Net-_U33-Pad3_ Net-_U34-Pad3_ Net-_U35-Pad1_ 4_and
+U36 Net-_U36-Pad1_ Net-_U36-Pad2_ d_inverter
+U35 Net-_U35-Pad1_ Net-_U35-Pad2_ d_inverter
+U47 Net-_U47-Pad1_ /6 d_inverter
+U48 Net-_U45-Pad3_ /14 d_inverter
+X9 Net-_U37-Pad3_ Net-_U38-Pad3_ Net-_U40-Pad3_ Net-_U43-Pad3_ Net-_U47-Pad1_ 4_and
+U45 Net-_U35-Pad2_ /5 Net-_U45-Pad3_ d_nand
+U30 Net-_U24-Pad2_ Net-_U30-Pad2_ d_inverter
+U29 Net-_U23-Pad2_ Net-_U29-Pad2_ d_inverter
+U23 /2 Net-_U23-Pad2_ d_inverter
+U24 /3 Net-_U24-Pad2_ d_inverter
+U25 /4 Net-_U25-Pad2_ d_inverter
+U33 /1 /2 Net-_U33-Pad3_ d_nor
+U26 /5 Net-_U26-Pad2_ d_inverter
+U31 /10 /11 Net-_U31-Pad3_ d_nor
+U32 /12 /13 Net-_U32-Pad3_ d_nor
+U22 /1 Net-_U22-Pad2_ d_inverter
+U21 /13 Net-_U21-Pad2_ d_inverter
+U20 /12 Net-_U20-Pad2_ d_inverter
+U19 /11 Net-_U19-Pad2_ d_inverter
+U27 Net-_U20-Pad2_ Net-_U27-Pad2_ d_inverter
+U28 Net-_U22-Pad2_ Net-_U28-Pad2_ d_inverter
+U34 /3 /4 Net-_U34-Pad3_ d_nor
+.end
diff --git a/library/SubcircuitLibrary/MC14532B/MC14532B.cir.out b/library/SubcircuitLibrary/MC14532B/MC14532B.cir.out
new file mode 100644
index 000000000..a5607e0cc
--- /dev/null
+++ b/library/SubcircuitLibrary/MC14532B/MC14532B.cir.out
@@ -0,0 +1,153 @@
+.title kicad schematic
+
+.include 5_and.sub
+.include 4_OR.sub
+.include 4_and.sub
+* u50 net-_u50-pad1_ /7 d_inverter
+* u1 /1 /2 /3 /4 /5 /6 /7 unconnected-_u1-pad8_ /9 /10 /11 /12 /13 /14 /15 unconnected-_u1-pad16_ port
+x10 net-_x10-pad1_ net-_x10-pad2_ net-_u39-pad3_ net-_u42-pad3_ net-_u50-pad1_ 4_and
+* u44 net-_u44-pad1_ net-_u26-pad2_ net-_u44-pad3_ d_or
+x4 net-_u20-pad2_ net-_u29-pad2_ net-_u29-pad2_ net-_u26-pad2_ net-_x10-pad1_ 4_OR
+x3 net-_u27-pad2_ net-_u28-pad2_ net-_u19-pad2_ net-_u30-pad2_ net-_u44-pad1_ 4_OR
+x8 net-_u44-pad3_ net-_x6-pad5_ net-_x7-pad5_ net-_u41-pad3_ net-_u46-pad1_ 4_and
+* u46 net-_u46-pad1_ /9 d_inverter
+x6 net-_u21-pad2_ net-_u28-pad2_ net-_u30-pad2_ net-_u26-pad2_ net-_x6-pad5_ 4_OR
+x5 net-_u21-pad2_ net-_u28-pad2_ net-_u29-pad2_ net-_u26-pad2_ net-_x10-pad2_ 4_OR
+* u37 net-_u22-pad2_ net-_u26-pad2_ net-_u37-pad3_ d_or
+x7 net-_u23-pad2_ net-_u30-pad2_ net-_u26-pad2_ unconnected-_x7-pad4_ net-_x7-pad5_ 4_OR
+* u38 net-_u23-pad2_ net-_u26-pad2_ net-_u38-pad3_ d_or
+* u41 net-_u25-pad2_ net-_u26-pad2_ net-_u41-pad3_ d_or
+* u39 net-_u24-pad2_ net-_u26-pad2_ net-_u39-pad3_ d_or
+* u42 net-_u25-pad2_ net-_u26-pad2_ net-_u42-pad3_ d_or
+* u40 net-_u24-pad2_ net-_u26-pad2_ net-_u40-pad3_ d_or
+* u49 net-_u36-pad2_ /15 d_inverter
+* u43 net-_u25-pad2_ net-_u26-pad2_ net-_u43-pad3_ d_or
+x2 net-_u33-pad3_ net-_u32-pad3_ net-_u31-pad3_ net-_u34-pad3_ /5 net-_u36-pad1_ 5_and
+x1 net-_u31-pad3_ net-_u32-pad3_ net-_u33-pad3_ net-_u34-pad3_ net-_u35-pad1_ 4_and
+* u36 net-_u36-pad1_ net-_u36-pad2_ d_inverter
+* u35 net-_u35-pad1_ net-_u35-pad2_ d_inverter
+* u47 net-_u47-pad1_ /6 d_inverter
+* u48 net-_u45-pad3_ /14 d_inverter
+x9 net-_u37-pad3_ net-_u38-pad3_ net-_u40-pad3_ net-_u43-pad3_ net-_u47-pad1_ 4_and
+* u45 net-_u35-pad2_ /5 net-_u45-pad3_ d_nand
+* u30 net-_u24-pad2_ net-_u30-pad2_ d_inverter
+* u29 net-_u23-pad2_ net-_u29-pad2_ d_inverter
+* u23 /2 net-_u23-pad2_ d_inverter
+* u24 /3 net-_u24-pad2_ d_inverter
+* u25 /4 net-_u25-pad2_ d_inverter
+* u33 /1 /2 net-_u33-pad3_ d_nor
+* u26 /5 net-_u26-pad2_ d_inverter
+* u31 /10 /11 net-_u31-pad3_ d_nor
+* u32 /12 /13 net-_u32-pad3_ d_nor
+* u22 /1 net-_u22-pad2_ d_inverter
+* u21 /13 net-_u21-pad2_ d_inverter
+* u20 /12 net-_u20-pad2_ d_inverter
+* u19 /11 net-_u19-pad2_ d_inverter
+* u27 net-_u20-pad2_ net-_u27-pad2_ d_inverter
+* u28 net-_u22-pad2_ net-_u28-pad2_ d_inverter
+* u34 /3 /4 net-_u34-pad3_ d_nor
+a1 net-_u50-pad1_ /7 u50
+a2 [net-_u44-pad1_ net-_u26-pad2_ ] net-_u44-pad3_ u44
+a3 net-_u46-pad1_ /9 u46
+a4 [net-_u22-pad2_ net-_u26-pad2_ ] net-_u37-pad3_ u37
+a5 [net-_u23-pad2_ net-_u26-pad2_ ] net-_u38-pad3_ u38
+a6 [net-_u25-pad2_ net-_u26-pad2_ ] net-_u41-pad3_ u41
+a7 [net-_u24-pad2_ net-_u26-pad2_ ] net-_u39-pad3_ u39
+a8 [net-_u25-pad2_ net-_u26-pad2_ ] net-_u42-pad3_ u42
+a9 [net-_u24-pad2_ net-_u26-pad2_ ] net-_u40-pad3_ u40
+a10 net-_u36-pad2_ /15 u49
+a11 [net-_u25-pad2_ net-_u26-pad2_ ] net-_u43-pad3_ u43
+a12 net-_u36-pad1_ net-_u36-pad2_ u36
+a13 net-_u35-pad1_ net-_u35-pad2_ u35
+a14 net-_u47-pad1_ /6 u47
+a15 net-_u45-pad3_ /14 u48
+a16 [net-_u35-pad2_ /5 ] net-_u45-pad3_ u45
+a17 net-_u24-pad2_ net-_u30-pad2_ u30
+a18 net-_u23-pad2_ net-_u29-pad2_ u29
+a19 /2 net-_u23-pad2_ u23
+a20 /3 net-_u24-pad2_ u24
+a21 /4 net-_u25-pad2_ u25
+a22 [/1 /2 ] net-_u33-pad3_ u33
+a23 /5 net-_u26-pad2_ u26
+a24 [/10 /11 ] net-_u31-pad3_ u31
+a25 [/12 /13 ] net-_u32-pad3_ u32
+a26 /1 net-_u22-pad2_ u22
+a27 /13 net-_u21-pad2_ u21
+a28 /12 net-_u20-pad2_ u20
+a29 /11 net-_u19-pad2_ u19
+a30 net-_u20-pad2_ net-_u27-pad2_ u27
+a31 net-_u22-pad2_ net-_u28-pad2_ u28
+a32 [/3 /4 ] net-_u34-pad3_ u34
+* Schematic Name: d_inverter, Ngspice Name: d_inverter
+.model u50 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_or, Ngspice Name: d_or
+.model u44 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, Ngspice Name: d_inverter
+.model u46 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_or, Ngspice Name: d_or
+.model u37 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_or, Ngspice Name: d_or
+.model u38 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_or, Ngspice Name: d_or
+.model u41 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_or, Ngspice Name: d_or
+.model u39 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_or, Ngspice Name: d_or
+.model u42 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_or, Ngspice Name: d_or
+.model u40 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, Ngspice Name: d_inverter
+.model u49 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_or, Ngspice Name: d_or
+.model u43 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, Ngspice Name: d_inverter
+.model u36 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, Ngspice Name: d_inverter
+.model u35 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, Ngspice Name: d_inverter
+.model u47 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, Ngspice Name: d_inverter
+.model u48 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_nand, Ngspice Name: d_nand
+.model u45 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, Ngspice Name: d_inverter
+.model u30 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, Ngspice Name: d_inverter
+.model u29 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, Ngspice Name: d_inverter
+.model u23 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, Ngspice Name: d_inverter
+.model u24 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, Ngspice Name: d_inverter
+.model u25 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_nor, Ngspice Name: d_nor
+.model u33 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, Ngspice Name: d_inverter
+.model u26 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_nor, Ngspice Name: d_nor
+.model u31 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_nor, Ngspice Name: d_nor
+.model u32 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, Ngspice Name: d_inverter
+.model u22 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, Ngspice Name: d_inverter
+.model u21 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, Ngspice Name: d_inverter
+.model u20 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, Ngspice Name: d_inverter
+.model u19 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, Ngspice Name: d_inverter
+.model u27 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, Ngspice Name: d_inverter
+.model u28 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_nor, Ngspice Name: d_nor
+.model u34 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+.tran 0e-00 0e-00 0e-00
+
+* Control Statements
+.control
+run
+print allv > plot_data_v.txt
+print alli > plot_data_i.txt
+.endc
+.end
diff --git a/library/SubcircuitLibrary/MC14532B/MC14532B.kicad_sch b/library/SubcircuitLibrary/MC14532B/MC14532B.kicad_sch
new file mode 100644
index 000000000..8e35d554b
--- /dev/null
+++ b/library/SubcircuitLibrary/MC14532B/MC14532B.kicad_sch
@@ -0,0 +1,3241 @@
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+
+ (uuid 72861bbc-34dd-433d-b6f9-76453da946b8)
+
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+
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+ (property "Value" "d_or" (id 1) (at 566.42 55.88 0)
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+ (property "Footprint" "" (id 2) (at 566.42 60.96 0)
+ (effects (font (size 1.524 1.524)))
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+ (in_bom yes) (on_board yes) (fields_autoplaced)
+ (uuid fb262f7f-562b-43e4-bdcf-8711b0b29098)
+ (property "Reference" "U47" (id 0) (at 664.21 405.13 0)
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+ (property "Value" "d_inverter" (id 1) (at 664.21 408.94 0)
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+ (pin "2" (uuid 8860629b-1fd7-4371-b006-e86a85b3e1be))
+ )
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+ (in_bom yes) (on_board yes) (fields_autoplaced)
+ (uuid ffcd859c-8132-4ba8-aa2e-e44bdec66b49)
+ (property "Reference" "U1" (id 0) (at 716.28 194.945 0)
+ (effects (font (size 0.762 0.762)) (justify right))
+ )
+ (property "Value" "PORT" (id 1) (at 716.28 197.485 0)
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+ (pin "26" (uuid babd991b-2beb-4396-a4b7-8e018eec9292))
+ )
+
+ (sheet_instances
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+ )
+
+ (symbol_instances
+ (path "/157c86e5-5cb8-4a5f-8d64-3a274da8fc70"
+ (reference "U1") (unit 1) (value "PORT") (footprint "")
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+ (path "/1178a095-c442-49f9-b4ce-1b1db6ad088c"
+ (reference "U1") (unit 2) (value "PORT") (footprint "")
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+ (path "/89e63f12-db1f-4284-bfd6-51529a9a6f31"
+ (reference "U1") (unit 3) (value "PORT") (footprint "")
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+ (path "/57d83473-8039-4db1-a52a-25581819478e"
+ (reference "U1") (unit 4) (value "PORT") (footprint "")
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+ (path "/ea8254db-917b-4201-ad5b-0a3d0bdb76b6"
+ (reference "U1") (unit 5) (value "PORT") (footprint "")
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+ )
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+ (reference "U1") (unit 7) (value "PORT") (footprint "")
+ )
+ (path "/f3b0e03d-ebfe-47e6-aa63-9ef5ab6a9161"
+ (reference "U1") (unit 8) (value "PORT") (footprint "")
+ )
+ (path "/29e489d3-7c83-426f-ab64-8e0214c6634e"
+ (reference "U1") (unit 9) (value "PORT") (footprint "")
+ )
+ (path "/dd47352d-0dbe-4fb9-b992-b04974b1d4fa"
+ (reference "U1") (unit 10) (value "PORT") (footprint "")
+ )
+ (path "/4c666c8e-e958-4ca2-ab84-7ca9f72b6fcf"
+ (reference "U1") (unit 11) (value "PORT") (footprint "")
+ )
+ (path "/27f420d5-eb1d-4208-a025-5f76b1478a9c"
+ (reference "U1") (unit 12) (value "PORT") (footprint "")
+ )
+ (path "/b033dd70-37d8-4079-9c35-f63ea65d4897"
+ (reference "U1") (unit 13) (value "PORT") (footprint "")
+ )
+ (path "/7a731d9f-3c0c-426c-8233-3dd2403ace7a"
+ (reference "U1") (unit 14) (value "PORT") (footprint "")
+ )
+ (path "/83e73e44-4e4a-435c-becb-44b83c7e6a53"
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+ )
+ (path "/676a1b51-f661-463b-981a-2950d4b520fd"
+ (reference "U1") (unit 16) (value "PORT") (footprint "")
+ )
+ (path "/032e7cd8-0c60-46bc-854c-885e48c48ef4"
+ (reference "U19") (unit 1) (value "d_inverter") (footprint "")
+ )
+ (path "/98b171b1-4ab5-46c7-81fc-6980d9e133cb"
+ (reference "U20") (unit 1) (value "d_inverter") (footprint "")
+ )
+ (path "/2b8f0bc4-2826-4d9e-9341-6d85c020e4f6"
+ (reference "U21") (unit 1) (value "d_inverter") (footprint "")
+ )
+ (path "/b7474044-a1b4-4504-8dee-e4d81fead057"
+ (reference "U22") (unit 1) (value "d_inverter") (footprint "")
+ )
+ (path "/949b72e0-2891-4fd0-858b-e3afba4f2e77"
+ (reference "U23") (unit 1) (value "d_inverter") (footprint "")
+ )
+ (path "/dc083b4d-ec42-4698-aacb-65685bffa5a6"
+ (reference "U24") (unit 1) (value "d_inverter") (footprint "")
+ )
+ (path "/b3ff32b4-2364-4884-be60-0e879dcec50c"
+ (reference "U25") (unit 1) (value "d_inverter") (footprint "")
+ )
+ (path "/ed6e410a-5b84-4849-8a6c-8f20b5caf7ea"
+ (reference "U26") (unit 1) (value "d_inverter") (footprint "")
+ )
+ (path "/47c1d066-e2a5-43e4-a5b3-3f269f045597"
+ (reference "U27") (unit 1) (value "d_inverter") (footprint "")
+ )
+ (path "/9b303e62-3dfb-48a7-9aa6-bdcdd14d28fd"
+ (reference "U28") (unit 1) (value "d_inverter") (footprint "")
+ )
+ (path "/317ab65a-2e58-4b5e-8a04-d2e34fb5fa45"
+ (reference "U29") (unit 1) (value "d_inverter") (footprint "")
+ )
+ (path "/d6f2b906-4687-41af-89bf-3c2b54801931"
+ (reference "U30") (unit 1) (value "d_inverter") (footprint "")
+ )
+ (path "/ba73063d-7a9c-493e-a027-85ea13e26b69"
+ (reference "U31") (unit 1) (value "d_nor") (footprint "")
+ )
+ (path "/7fc3765e-dad5-45ce-ad7a-73c93d444986"
+ (reference "U32") (unit 1) (value "d_nor") (footprint "")
+ )
+ (path "/c8feb461-3284-4df6-862e-06ff2a992e02"
+ (reference "U33") (unit 1) (value "d_nor") (footprint "")
+ )
+ (path "/e28893f4-6ca4-4858-8ba6-9f52581ad4e5"
+ (reference "U34") (unit 1) (value "d_nor") (footprint "")
+ )
+ (path "/6abc3541-fcf3-4398-9ff4-066d24727815"
+ (reference "U35") (unit 1) (value "d_inverter") (footprint "")
+ )
+ (path "/c409e624-7fa1-4365-a518-fdb7ff6d1ad5"
+ (reference "U36") (unit 1) (value "d_inverter") (footprint "")
+ )
+ (path "/827b2219-bb75-40f7-8632-03670fc6100e"
+ (reference "U37") (unit 1) (value "d_or") (footprint "")
+ )
+ (path "/4ed8bb0a-fcc9-46b5-86aa-32f33398b38c"
+ (reference "U38") (unit 1) (value "d_or") (footprint "")
+ )
+ (path "/5556cf35-fa99-4624-94d6-ed964f00f4e4"
+ (reference "U39") (unit 1) (value "d_or") (footprint "")
+ )
+ (path "/14e9425b-c975-4fce-a590-1d29a994234f"
+ (reference "U40") (unit 1) (value "d_or") (footprint "")
+ )
+ (path "/15b325f9-14e5-4c45-8dc8-36fb80169425"
+ (reference "U41") (unit 1) (value "d_or") (footprint "")
+ )
+ (path "/332bf13c-dcec-4057-8a7b-1327c19bc10f"
+ (reference "U42") (unit 1) (value "d_or") (footprint "")
+ )
+ (path "/62553a98-2324-429c-97ce-c9ca6be176bf"
+ (reference "U43") (unit 1) (value "d_or") (footprint "")
+ )
+ (path "/fa7a5126-7465-43b2-9817-c2df0303e0f4"
+ (reference "U44") (unit 1) (value "d_or") (footprint "")
+ )
+ (path "/7b99ef9a-e119-4a36-8216-3fe2247369d9"
+ (reference "U45") (unit 1) (value "d_nand") (footprint "")
+ )
+ (path "/465a7142-35c2-49da-8b5d-eefcda674b36"
+ (reference "U46") (unit 1) (value "d_inverter") (footprint "")
+ )
+ (path "/fb262f7f-562b-43e4-bdcf-8711b0b29098"
+ (reference "U47") (unit 1) (value "d_inverter") (footprint "")
+ )
+ (path "/ee64863d-87b8-4272-bd8f-2db2a3e0b1dd"
+ (reference "U48") (unit 1) (value "d_inverter") (footprint "")
+ )
+ (path "/c43ed1f9-50be-44cf-ac94-f67769981e65"
+ (reference "U49") (unit 1) (value "d_inverter") (footprint "")
+ )
+ (path "/61ce0bad-4efd-489e-8ba6-d4ce8c17d08f"
+ (reference "U50") (unit 1) (value "d_inverter") (footprint "")
+ )
+ (path "/48858916-5b77-43c3-9bae-9597ff9bfe1f"
+ (reference "X1") (unit 1) (value "4_and") (footprint "")
+ )
+ (path "/b1ae274e-12f7-4a47-92c8-168d1ebf13e9"
+ (reference "X2") (unit 1) (value "5_and") (footprint "")
+ )
+ (path "/8ef925f3-fb88-4391-a601-3f37a0479dc6"
+ (reference "X3") (unit 1) (value "4_OR") (footprint "")
+ )
+ (path "/982efe99-d25d-492c-887a-18a8cebdc3bb"
+ (reference "X4") (unit 1) (value "4_OR") (footprint "")
+ )
+ (path "/78d7c175-3ee4-4c12-8e2f-762a6e7eb2cd"
+ (reference "X5") (unit 1) (value "4_OR") (footprint "")
+ )
+ (path "/3b68b875-2bda-4bf1-8e9c-f51c4d23c5b0"
+ (reference "X6") (unit 1) (value "4_OR") (footprint "")
+ )
+ (path "/b9818c5b-f208-47ca-8ea7-1a98354f8589"
+ (reference "X7") (unit 1) (value "4_OR") (footprint "")
+ )
+ (path "/350c81d8-bfcc-49e4-9e14-047812ad80e5"
+ (reference "X8") (unit 1) (value "4_and") (footprint "")
+ )
+ (path "/730f45ff-827d-4250-82b5-aa390e295756"
+ (reference "X9") (unit 1) (value "4_and") (footprint "")
+ )
+ (path "/62b09981-def1-43fb-a722-edfbc026d653"
+ (reference "X10") (unit 1) (value "4_and") (footprint "")
+ )
+ )
+)
diff --git a/library/SubcircuitLibrary/MC14532B/MC14532B.sub b/library/SubcircuitLibrary/MC14532B/MC14532B.sub
new file mode 100644
index 000000000..3221ee3d6
--- /dev/null
+++ b/library/SubcircuitLibrary/MC14532B/MC14532B.sub
@@ -0,0 +1,147 @@
+* Subcircuit MC14532B
+.subckt MC14532B /1 /2 /3 /4 /5 /6 /7 unconnected-_u1-pad8_ /9 /10 /11 /12 /13 /14 /15 unconnected-_u1-pad16_
+.title kicad schematic
+.include 5_and.sub
+.include 4_OR.sub
+.include 4_and.sub
+* u50 net-_u50-pad1_ /7 d_inverter
+x10 net-_x10-pad1_ net-_x10-pad2_ net-_u39-pad3_ net-_u42-pad3_ net-_u50-pad1_ 4_and
+* u44 net-_u44-pad1_ net-_u26-pad2_ net-_u44-pad3_ d_or
+x4 net-_u20-pad2_ net-_u29-pad2_ net-_u29-pad2_ net-_u26-pad2_ net-_x10-pad1_ 4_OR
+x3 net-_u27-pad2_ net-_u28-pad2_ net-_u19-pad2_ net-_u30-pad2_ net-_u44-pad1_ 4_OR
+x8 net-_u44-pad3_ net-_x6-pad5_ net-_x7-pad5_ net-_u41-pad3_ net-_u46-pad1_ 4_and
+* u46 net-_u46-pad1_ /9 d_inverter
+x6 net-_u21-pad2_ net-_u28-pad2_ net-_u30-pad2_ net-_u26-pad2_ net-_x6-pad5_ 4_OR
+x5 net-_u21-pad2_ net-_u28-pad2_ net-_u29-pad2_ net-_u26-pad2_ net-_x10-pad2_ 4_OR
+* u37 net-_u22-pad2_ net-_u26-pad2_ net-_u37-pad3_ d_or
+x7 net-_u23-pad2_ net-_u30-pad2_ net-_u26-pad2_ unconnected-_x7-pad4_ net-_x7-pad5_ 4_OR
+* u38 net-_u23-pad2_ net-_u26-pad2_ net-_u38-pad3_ d_or
+* u41 net-_u25-pad2_ net-_u26-pad2_ net-_u41-pad3_ d_or
+* u39 net-_u24-pad2_ net-_u26-pad2_ net-_u39-pad3_ d_or
+* u42 net-_u25-pad2_ net-_u26-pad2_ net-_u42-pad3_ d_or
+* u40 net-_u24-pad2_ net-_u26-pad2_ net-_u40-pad3_ d_or
+* u49 net-_u36-pad2_ /15 d_inverter
+* u43 net-_u25-pad2_ net-_u26-pad2_ net-_u43-pad3_ d_or
+x2 net-_u33-pad3_ net-_u32-pad3_ net-_u31-pad3_ net-_u34-pad3_ /5 net-_u36-pad1_ 5_and
+x1 net-_u31-pad3_ net-_u32-pad3_ net-_u33-pad3_ net-_u34-pad3_ net-_u35-pad1_ 4_and
+* u36 net-_u36-pad1_ net-_u36-pad2_ d_inverter
+* u35 net-_u35-pad1_ net-_u35-pad2_ d_inverter
+* u47 net-_u47-pad1_ /6 d_inverter
+* u48 net-_u45-pad3_ /14 d_inverter
+x9 net-_u37-pad3_ net-_u38-pad3_ net-_u40-pad3_ net-_u43-pad3_ net-_u47-pad1_ 4_and
+* u45 net-_u35-pad2_ /5 net-_u45-pad3_ d_nand
+* u30 net-_u24-pad2_ net-_u30-pad2_ d_inverter
+* u29 net-_u23-pad2_ net-_u29-pad2_ d_inverter
+* u23 /2 net-_u23-pad2_ d_inverter
+* u24 /3 net-_u24-pad2_ d_inverter
+* u25 /4 net-_u25-pad2_ d_inverter
+* u33 /1 /2 net-_u33-pad3_ d_nor
+* u26 /5 net-_u26-pad2_ d_inverter
+* u31 /10 /11 net-_u31-pad3_ d_nor
+* u32 /12 /13 net-_u32-pad3_ d_nor
+* u22 /1 net-_u22-pad2_ d_inverter
+* u21 /13 net-_u21-pad2_ d_inverter
+* u20 /12 net-_u20-pad2_ d_inverter
+* u19 /11 net-_u19-pad2_ d_inverter
+* u27 net-_u20-pad2_ net-_u27-pad2_ d_inverter
+* u28 net-_u22-pad2_ net-_u28-pad2_ d_inverter
+* u34 /3 /4 net-_u34-pad3_ d_nor
+a1 net-_u50-pad1_ /7 u50
+a2 [net-_u44-pad1_ net-_u26-pad2_ ] net-_u44-pad3_ u44
+a3 net-_u46-pad1_ /9 u46
+a4 [net-_u22-pad2_ net-_u26-pad2_ ] net-_u37-pad3_ u37
+a5 [net-_u23-pad2_ net-_u26-pad2_ ] net-_u38-pad3_ u38
+a6 [net-_u25-pad2_ net-_u26-pad2_ ] net-_u41-pad3_ u41
+a7 [net-_u24-pad2_ net-_u26-pad2_ ] net-_u39-pad3_ u39
+a8 [net-_u25-pad2_ net-_u26-pad2_ ] net-_u42-pad3_ u42
+a9 [net-_u24-pad2_ net-_u26-pad2_ ] net-_u40-pad3_ u40
+a10 net-_u36-pad2_ /15 u49
+a11 [net-_u25-pad2_ net-_u26-pad2_ ] net-_u43-pad3_ u43
+a12 net-_u36-pad1_ net-_u36-pad2_ u36
+a13 net-_u35-pad1_ net-_u35-pad2_ u35
+a14 net-_u47-pad1_ /6 u47
+a15 net-_u45-pad3_ /14 u48
+a16 [net-_u35-pad2_ /5 ] net-_u45-pad3_ u45
+a17 net-_u24-pad2_ net-_u30-pad2_ u30
+a18 net-_u23-pad2_ net-_u29-pad2_ u29
+a19 /2 net-_u23-pad2_ u23
+a20 /3 net-_u24-pad2_ u24
+a21 /4 net-_u25-pad2_ u25
+a22 [/1 /2 ] net-_u33-pad3_ u33
+a23 /5 net-_u26-pad2_ u26
+a24 [/10 /11 ] net-_u31-pad3_ u31
+a25 [/12 /13 ] net-_u32-pad3_ u32
+a26 /1 net-_u22-pad2_ u22
+a27 /13 net-_u21-pad2_ u21
+a28 /12 net-_u20-pad2_ u20
+a29 /11 net-_u19-pad2_ u19
+a30 net-_u20-pad2_ net-_u27-pad2_ u27
+a31 net-_u22-pad2_ net-_u28-pad2_ u28
+a32 [/3 /4 ] net-_u34-pad3_ u34
+* Schematic Name: d_inverter, Ngspice Name: d_inverter
+.model u50 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_or, Ngspice Name: d_or
+.model u44 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, Ngspice Name: d_inverter
+.model u46 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_or, Ngspice Name: d_or
+.model u37 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_or, Ngspice Name: d_or
+.model u38 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_or, Ngspice Name: d_or
+.model u41 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_or, Ngspice Name: d_or
+.model u39 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_or, Ngspice Name: d_or
+.model u42 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_or, Ngspice Name: d_or
+.model u40 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, Ngspice Name: d_inverter
+.model u49 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_or, Ngspice Name: d_or
+.model u43 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, Ngspice Name: d_inverter
+.model u36 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, Ngspice Name: d_inverter
+.model u35 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, Ngspice Name: d_inverter
+.model u47 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, Ngspice Name: d_inverter
+.model u48 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_nand, Ngspice Name: d_nand
+.model u45 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, Ngspice Name: d_inverter
+.model u30 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, Ngspice Name: d_inverter
+.model u29 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, Ngspice Name: d_inverter
+.model u23 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, Ngspice Name: d_inverter
+.model u24 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, Ngspice Name: d_inverter
+.model u25 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_nor, Ngspice Name: d_nor
+.model u33 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, Ngspice Name: d_inverter
+.model u26 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_nor, Ngspice Name: d_nor
+.model u31 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_nor, Ngspice Name: d_nor
+.model u32 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, Ngspice Name: d_inverter
+.model u22 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, Ngspice Name: d_inverter
+.model u21 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, Ngspice Name: d_inverter
+.model u20 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, Ngspice Name: d_inverter
+.model u19 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, Ngspice Name: d_inverter
+.model u27 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, Ngspice Name: d_inverter
+.model u28 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_nor, Ngspice Name: d_nor
+.model u34 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Control Statements
+
+.ends MC14532B
\ No newline at end of file
diff --git a/library/SubcircuitLibrary/MC14532B/MC14532B_Previous_Values.xml b/library/SubcircuitLibrary/MC14532B/MC14532B_Previous_Values.xml
new file mode 100644
index 000000000..659059020
--- /dev/null
+++ b/library/SubcircuitLibrary/MC14532B/MC14532B_Previous_Values.xml
@@ -0,0 +1 @@
+truefalsefalseHzHz0Volts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or Amperessecsecsecd_inverterd_ord_inverterd_ord_ord_ord_ord_ord_ord_inverterd_ord_inverterd_inverterd_inverterd_inverterd_nandd_inverterd_inverterd_inverterd_inverterd_inverterd_nord_inverterd_nord_nord_inverterd_inverterd_inverterd_inverterd_inverterd_inverterd_norC:\Users\Sakhi\FOSSEE\eSim\library\SubcircuitLibrary\4_andC:\Users\Sakhi\FOSSEE\eSim\library\SubcircuitLibrary\4_ORC:\Users\Sakhi\FOSSEE\eSim\library\SubcircuitLibrary\4_ORC:\Users\Sakhi\FOSSEE\eSim\library\SubcircuitLibrary\4_andC:\Users\Sakhi\FOSSEE\eSim\library\SubcircuitLibrary\4_ORC:\Users\Sakhi\FOSSEE\eSim\library\SubcircuitLibrary\4_ORC:\Users\Sakhi\FOSSEE\eSim\library\SubcircuitLibrary\4_ORC:\Users\Sakhi\FOSSEE\eSim\library\SubcircuitLibrary\5_andC:\Users\Sakhi\FOSSEE\eSim\library\SubcircuitLibrary\4_andC:\Users\Sakhi\FOSSEE\eSim\library\SubcircuitLibrary\4_and
\ No newline at end of file
diff --git a/library/SubcircuitLibrary/MC14532B/_autosave-MC14532B.sch b/library/SubcircuitLibrary/MC14532B/_autosave-MC14532B.sch
new file mode 100644
index 000000000..b1394af8b
--- /dev/null
+++ b/library/SubcircuitLibrary/MC14532B/_autosave-MC14532B.sch
@@ -0,0 +1,935 @@
+EESchema Schematic File Version 5
+EELAYER 36 0
+EELAYER END
+$Descr A1 33110 23386
+encoding utf-8
+Sheet 1 1
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+Date ""
+Rev ""
+Comp ""
+Comment1 ""
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+Comment9 ""
+$EndDescr
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+L eSim_Digital:d_inverter U35
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+L eSim_Digital:d_inverter U36
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+$Comp
+L eSim_Digital:d_inverter U46
+U 1 1 00000000
+P 26150 2550
+F 0 "U46" H 26150 2800 60 0000 C CNN
+F 1 "d_inverter" H 26150 2650 60 0000 C CNN
+F 2 "" H 26200 2500 60 0000 C CNN
+F 3 "" H 26200 2500 60 0000 C CNN
+ 1 26150 2550
+ 1 0 0 -1
+$EndComp
+$Comp
+L eSim_Digital:d_inverter U47
+U 1 1 00000000
+P 26150 16200
+F 0 "U47" H 26150 16450 60 0000 C CNN
+F 1 "d_inverter" H 26150 16300 60 0000 C CNN
+F 2 "" H 26200 16150 60 0000 C CNN
+F 3 "" H 26200 16150 60 0000 C CNN
+ 1 26150 16200
+ 1 0 0 -1
+$EndComp
+$Comp
+L eSim_Digital:d_inverter U48
+U 1 1 00000000
+P 26150 17750
+F 0 "U48" H 26150 18000 60 0000 C CNN
+F 1 "d_inverter" H 26150 17850 60 0000 C CNN
+F 2 "" H 26200 17700 60 0000 C CNN
+F 3 "" H 26200 17700 60 0000 C CNN
+ 1 26150 17750
+ 1 0 0 -1
+$EndComp
+$Comp
+L eSim_Digital:d_inverter U49
+U 1 1 00000000
+P 26150 19900
+F 0 "U49" H 26150 20150 60 0000 C CNN
+F 1 "d_inverter" H 26150 20000 60 0000 C CNN
+F 2 "" H 26200 19850 60 0000 C CNN
+F 3 "" H 26200 19850 60 0000 C CNN
+ 1 26150 19900
+ 1 0 0 -1
+$EndComp
+$Comp
+L eSim_Digital:d_inverter U50
+U 1 1 00000000
+P 26450 7700
+F 0 "U50" H 26450 7950 60 0000 C CNN
+F 1 "d_inverter" H 26450 7800 60 0000 C CNN
+F 2 "" H 26500 7650 60 0000 C CNN
+F 3 "" H 26500 7650 60 0000 C CNN
+ 1 26450 7700
+ 1 0 0 -1
+$EndComp
+$Comp
+L eSim_Digital:d_nor U31
+U 1 1 00000000
+P 16300 17500
+F 0 "U31" H 16300 17850 60 0000 C CNN
+F 1 "d_nor" H 16300 17700 60 0000 C CNN
+F 2 "" H 16300 17500 60 0000 C CNN
+F 3 "" H 16300 17500 60 0000 C CNN
+ 1 16300 17500
+ 1 0 0 -1
+$EndComp
+$Comp
+L eSim_Digital:d_nor U32
+U 1 1 00000000
+P 16300 18500
+F 0 "U32" H 16300 18850 60 0000 C CNN
+F 1 "d_nor" H 16300 18700 60 0000 C CNN
+F 2 "" H 16300 18500 60 0000 C CNN
+F 3 "" H 16300 18500 60 0000 C CNN
+ 1 16300 18500
+ 1 0 0 -1
+$EndComp
+$Comp
+L eSim_Digital:d_nor U33
+U 1 1 00000000
+P 16300 19500
+F 0 "U33" H 16300 19850 60 0000 C CNN
+F 1 "d_nor" H 16300 19700 60 0000 C CNN
+F 2 "" H 16300 19500 60 0000 C CNN
+F 3 "" H 16300 19500 60 0000 C CNN
+ 1 16300 19500
+ 1 0 0 -1
+$EndComp
+$Comp
+L eSim_Digital:d_nor U34
+U 1 1 00000000
+P 16300 20500
+F 0 "U34" H 16300 20850 60 0000 C CNN
+F 1 "d_nor" H 16300 20700 60 0000 C CNN
+F 2 "" H 16300 20500 60 0000 C CNN
+F 3 "" H 16300 20500 60 0000 C CNN
+ 1 16300 20500
+ 1 0 0 -1
+$EndComp
+$Comp
+L eSim_Digital:d_or U37
+U 1 1 00000000
+P 21400 7350
+F 0 "U37" H 21400 7700 60 0000 C CNN
+F 1 "d_or" H 21400 7550 60 0000 C CNN
+F 2 "" H 21400 7350 60 0000 C CNN
+F 3 "" H 21400 7350 60 0000 C CNN
+ 1 21400 7350
+ 1 0 0 -1
+$EndComp
+$Comp
+L eSim_Digital:d_or U38
+U 1 1 00000000
+P 21400 10200
+F 0 "U38" H 21400 10550 60 0000 C CNN
+F 1 "d_or" H 21400 10400 60 0000 C CNN
+F 2 "" H 21400 10200 60 0000 C CNN
+F 3 "" H 21400 10200 60 0000 C CNN
+ 1 21400 10200
+ 1 0 0 -1
+$EndComp
+$Comp
+L eSim_Digital:d_or U39
+U 1 1 00000000
+P 21400 11450
+F 0 "U39" H 21400 11800 60 0000 C CNN
+F 1 "d_or" H 21400 11650 60 0000 C CNN
+F 2 "" H 21400 11450 60 0000 C CNN
+F 3 "" H 21400 11450 60 0000 C CNN
+ 1 21400 11450
+ 1 0 0 -1
+$EndComp
+$Comp
+L eSim_Digital:d_or U40
+U 1 1 00000000
+P 21400 12650
+F 0 "U40" H 21400 13000 60 0000 C CNN
+F 1 "d_or" H 21400 12850 60 0000 C CNN
+F 2 "" H 21400 12650 60 0000 C CNN
+F 3 "" H 21400 12650 60 0000 C CNN
+ 1 21400 12650
+ 1 0 0 -1
+$EndComp
+$Comp
+L eSim_Digital:d_or U41
+U 1 1 00000000
+P 21400 13850
+F 0 "U41" H 21400 14200 60 0000 C CNN
+F 1 "d_or" H 21400 14050 60 0000 C CNN
+F 2 "" H 21400 13850 60 0000 C CNN
+F 3 "" H 21400 13850 60 0000 C CNN
+ 1 21400 13850
+ 1 0 0 -1
+$EndComp
+$Comp
+L eSim_Digital:d_or U42
+U 1 1 00000000
+P 21400 15150
+F 0 "U42" H 21400 15500 60 0000 C CNN
+F 1 "d_or" H 21400 15350 60 0000 C CNN
+F 2 "" H 21400 15150 60 0000 C CNN
+F 3 "" H 21400 15150 60 0000 C CNN
+ 1 21400 15150
+ 1 0 0 -1
+$EndComp
+$Comp
+L eSim_Digital:d_or U43
+U 1 1 00000000
+P 21400 16400
+F 0 "U43" H 21350 16500 60 0000 C CNN
+F 1 "d_or" H 21400 16600 60 0000 C CNN
+F 2 "" H 21400 16400 60 0000 C CNN
+F 3 "" H 21400 16400 60 0000 C CNN
+ 1 21400 16400
+ 1 0 0 -1
+$EndComp
+$Comp
+L eSim_Digital:d_or U44
+U 1 1 00000000
+P 22300 2400
+F 0 "U44" H 22300 2750 60 0000 C CNN
+F 1 "d_or" H 22300 2600 60 0000 C CNN
+F 2 "" H 22300 2400 60 0000 C CNN
+F 3 "" H 22300 2400 60 0000 C CNN
+ 1 22300 2400
+ 1 0 0 -1
+$EndComp
+$Comp
+L eSim_Digital:d_nand U45
+U 1 1 00000000
+P 25400 17800
+F 0 "U45" H 25400 18150 60 0000 C CNN
+F 1 "d_nand" H 25400 18000 60 0000 C CNN
+F 2 "" H 25400 17800 60 0000 C CNN
+F 3 "" H 25400 17800 60 0000 C CNN
+ 1 25400 17800
+ 1 0 0 -1
+$EndComp
+$Comp
+L eSim_Subckt:4_and X1
+U 1 1 00000000
+P 18850 17700
+F 0 "X1" H 18903 18100 60 0000 C CNN
+F 1 "4_and" H 18903 17950 60 0000 C CNN
+F 2 "" H 18850 17700 60 0000 C CNN
+F 3 "" H 18850 17700 60 0000 C CNN
+ 1 18850 17700
+ 1 0 0 -1
+$EndComp
+$Comp
+L eSim_Subckt:4_and X8
+U 1 1 00000000
+P 25350 2550
+F 0 "X8" H 25403 2950 60 0000 C CNN
+F 1 "4_and" H 25403 2800 60 0000 C CNN
+F 2 "" H 25350 2550 60 0000 C CNN
+F 3 "" H 25350 2550 60 0000 C CNN
+ 1 25350 2550
+ 1 0 0 -1
+$EndComp
+$Comp
+L eSim_Subckt:4_and X9
+U 1 1 00000000
+P 25350 16200
+F 0 "X9" H 25403 16600 60 0000 C CNN
+F 1 "4_and" H 25403 16450 60 0000 C CNN
+F 2 "" H 25350 16200 60 0000 C CNN
+F 3 "" H 25350 16200 60 0000 C CNN
+ 1 25350 16200
+ 1 0 0 -1
+$EndComp
+$Comp
+L eSim_Subckt:4_and X10
+U 1 1 00000000
+P 25550 7700
+F 0 "X10" H 25603 8100 60 0000 C CNN
+F 1 "4_and" H 25603 7950 60 0000 C CNN
+F 2 "" H 25550 7700 60 0000 C CNN
+F 3 "" H 25550 7700 60 0000 C CNN
+ 1 25550 7700
+ 1 0 0 -1
+$EndComp
+$Comp
+L eSim_Subckt:4_OR X3
+U 1 1 00000000
+P 21300 2300
+F 0 "X3" H 21375 2750 60 0000 C CNN
+F 1 "4_OR" H 21375 2600 60 0000 C CNN
+F 2 "" H 21300 2300 60 0000 C CNN
+F 3 "" H 21300 2300 60 0000 C CNN
+ 1 21300 2300
+ 1 0 0 -1
+$EndComp
+$Comp
+L eSim_Subckt:4_OR X4
+U 1 1 00000000
+P 21300 3650
+F 0 "X4" H 21375 4100 60 0000 C CNN
+F 1 "4_OR" H 21375 3950 60 0000 C CNN
+F 2 "" H 21300 3650 60 0000 C CNN
+F 3 "" H 21300 3650 60 0000 C CNN
+ 1 21300 3650
+ 1 0 0 -1
+$EndComp
+$Comp
+L eSim_Subckt:4_OR X5
+U 1 1 00000000
+P 21300 4850
+F 0 "X5" H 21375 5300 60 0000 C CNN
+F 1 "4_OR" H 21375 5150 60 0000 C CNN
+F 2 "" H 21300 4850 60 0000 C CNN
+F 3 "" H 21300 4850 60 0000 C CNN
+ 1 21300 4850
+ 1 0 0 -1
+$EndComp
+$Comp
+L eSim_Subckt:4_OR X6
+U 1 1 00000000
+P 21300 6100
+F 0 "X6" H 21375 6550 60 0000 C CNN
+F 1 "4_OR" H 21375 6400 60 0000 C CNN
+F 2 "" H 21300 6100 60 0000 C CNN
+F 3 "" H 21300 6100 60 0000 C CNN
+ 1 21300 6100
+ 1 0 0 -1
+$EndComp
+$Comp
+L eSim_Subckt:4_OR X7
+U 1 1 00000000
+P 21300 8600
+F 0 "X7" H 21375 9050 60 0000 C CNN
+F 1 "4_OR" H 21375 8900 60 0000 C CNN
+F 2 "" H 21300 8600 60 0000 C CNN
+F 3 "" H 21300 8600 60 0000 C CNN
+ 1 21300 8600
+ 1 0 0 -1
+$EndComp
+$Comp
+L eSim_Subckt:5_and X2
+U 1 1 00000000
+P 18900 19900
+F 0 "X2" H 18952 20350 60 0000 C CNN
+F 1 "5_and" H 18952 20200 60 0000 C CNN
+F 2 "" H 18900 19900 60 0000 C CNN
+F 3 "" H 18900 19900 60 0000 C CNN
+ 1 18900 19900
+ 1 0 0 -1
+$EndComp
+$EndSCHEMATC
diff --git a/library/SubcircuitLibrary/MC14532B/analysis b/library/SubcircuitLibrary/MC14532B/analysis
new file mode 100644
index 000000000..ebd5c0a94
--- /dev/null
+++ b/library/SubcircuitLibrary/MC14532B/analysis
@@ -0,0 +1 @@
+.tran 0e-00 0e-00 0e-00
\ No newline at end of file
diff --git a/library/SubcircuitLibrary/SN74F257/SN74F257.cir b/library/SubcircuitLibrary/SN74F257/SN74F257.cir
new file mode 100644
index 000000000..822d9052d
--- /dev/null
+++ b/library/SubcircuitLibrary/SN74F257/SN74F257.cir
@@ -0,0 +1,22 @@
+.title KiCad schematic
+U8 Net-_U10-Pad1_ Net-_U8-Pad2_ Net-_U15-Pad1_ d_and
+U7 Net-_U11-Pad1_ Net-_U7-Pad2_ Net-_U14-Pad2_ d_and
+U6 Net-_U10-Pad1_ Net-_U6-Pad2_ Net-_U14-Pad1_ d_and
+U10 Net-_U10-Pad1_ Net-_U10-Pad2_ Net-_U10-Pad3_ d_and
+U9 Net-_U11-Pad1_ Net-_U9-Pad2_ Net-_U15-Pad2_ d_and
+U5 Net-_U4-Pad1_ Net-_U11-Pad1_ d_buffer
+U3 Net-_U3-Pad1_ Net-_U18-Pad2_ d_inverter
+U4 Net-_U4-Pad1_ Net-_U10-Pad1_ d_inverter
+U1 Net-_U4-Pad1_ Net-_U6-Pad2_ Net-_U7-Pad2_ Net-_U18-Pad3_ Net-_U8-Pad2_ Net-_U9-Pad2_ Net-_U19-Pad3_ unconnected-_U1-Pad8_ Net-_U20-Pad3_ Net-_U11-Pad2_ Net-_U10-Pad2_ Net-_U21-Pad3_ Net-_U13-Pad2_ Net-_U12-Pad2_ Net-_U3-Pad1_ unconnected-_U1-Pad16_ PORT
+U17 Net-_U12-Pad3_ Net-_U13-Pad3_ Net-_U17-Pad3_ d_or
+U16 Net-_U10-Pad3_ Net-_U11-Pad3_ Net-_U16-Pad3_ d_or
+U15 Net-_U15-Pad1_ Net-_U15-Pad2_ Net-_U15-Pad3_ d_or
+U19 Net-_U15-Pad3_ Net-_U18-Pad2_ Net-_U19-Pad3_ d_tristate
+U21 Net-_U17-Pad3_ Net-_U18-Pad2_ Net-_U21-Pad3_ d_tristate
+U20 Net-_U16-Pad3_ Net-_U18-Pad2_ Net-_U20-Pad3_ d_tristate
+U18 Net-_U14-Pad3_ Net-_U18-Pad2_ Net-_U18-Pad3_ d_tristate
+U14 Net-_U14-Pad1_ Net-_U14-Pad2_ Net-_U14-Pad3_ d_or
+U13 Net-_U11-Pad1_ Net-_U13-Pad2_ Net-_U13-Pad3_ d_and
+U12 Net-_U10-Pad1_ Net-_U12-Pad2_ Net-_U12-Pad3_ d_and
+U11 Net-_U11-Pad1_ Net-_U11-Pad2_ Net-_U11-Pad3_ d_and
+.end
diff --git a/library/SubcircuitLibrary/SN74F257/SN74F257.cir.out b/library/SubcircuitLibrary/SN74F257/SN74F257.cir.out
new file mode 100644
index 000000000..b0e38adca
--- /dev/null
+++ b/library/SubcircuitLibrary/SN74F257/SN74F257.cir.out
@@ -0,0 +1,88 @@
+.title kicad schematic
+
+* u8 net-_u10-pad1_ net-_u8-pad2_ net-_u15-pad1_ d_and
+* u7 net-_u11-pad1_ net-_u7-pad2_ net-_u14-pad2_ d_and
+* u6 net-_u10-pad1_ net-_u6-pad2_ net-_u14-pad1_ d_and
+* u10 net-_u10-pad1_ net-_u10-pad2_ net-_u10-pad3_ d_and
+* u9 net-_u11-pad1_ net-_u9-pad2_ net-_u15-pad2_ d_and
+* u5 net-_u4-pad1_ net-_u11-pad1_ d_buffer
+* u3 net-_u3-pad1_ net-_u18-pad2_ d_inverter
+* u4 net-_u4-pad1_ net-_u10-pad1_ d_inverter
+* u1 net-_u4-pad1_ net-_u6-pad2_ net-_u7-pad2_ net-_u18-pad3_ net-_u8-pad2_ net-_u9-pad2_ net-_u19-pad3_ unconnected-_u1-pad8_ net-_u20-pad3_ net-_u11-pad2_ net-_u10-pad2_ net-_u21-pad3_ net-_u13-pad2_ net-_u12-pad2_ net-_u3-pad1_ unconnected-_u1-pad16_ port
+* u17 net-_u12-pad3_ net-_u13-pad3_ net-_u17-pad3_ d_or
+* u16 net-_u10-pad3_ net-_u11-pad3_ net-_u16-pad3_ d_or
+* u15 net-_u15-pad1_ net-_u15-pad2_ net-_u15-pad3_ d_or
+* u19 net-_u15-pad3_ net-_u18-pad2_ net-_u19-pad3_ d_tristate
+* u21 net-_u17-pad3_ net-_u18-pad2_ net-_u21-pad3_ d_tristate
+* u20 net-_u16-pad3_ net-_u18-pad2_ net-_u20-pad3_ d_tristate
+* u18 net-_u14-pad3_ net-_u18-pad2_ net-_u18-pad3_ d_tristate
+* u14 net-_u14-pad1_ net-_u14-pad2_ net-_u14-pad3_ d_or
+* u13 net-_u11-pad1_ net-_u13-pad2_ net-_u13-pad3_ d_and
+* u12 net-_u10-pad1_ net-_u12-pad2_ net-_u12-pad3_ d_and
+* u11 net-_u11-pad1_ net-_u11-pad2_ net-_u11-pad3_ d_and
+a1 [net-_u10-pad1_ net-_u8-pad2_ ] net-_u15-pad1_ u8
+a2 [net-_u11-pad1_ net-_u7-pad2_ ] net-_u14-pad2_ u7
+a3 [net-_u10-pad1_ net-_u6-pad2_ ] net-_u14-pad1_ u6
+a4 [net-_u10-pad1_ net-_u10-pad2_ ] net-_u10-pad3_ u10
+a5 [net-_u11-pad1_ net-_u9-pad2_ ] net-_u15-pad2_ u9
+a6 net-_u4-pad1_ net-_u11-pad1_ u5
+a7 net-_u3-pad1_ net-_u18-pad2_ u3
+a8 net-_u4-pad1_ net-_u10-pad1_ u4
+a9 [net-_u12-pad3_ net-_u13-pad3_ ] net-_u17-pad3_ u17
+a10 [net-_u10-pad3_ net-_u11-pad3_ ] net-_u16-pad3_ u16
+a11 [net-_u15-pad1_ net-_u15-pad2_ ] net-_u15-pad3_ u15
+a12 net-_u15-pad3_ net-_u18-pad2_ net-_u19-pad3_ u19
+a13 net-_u17-pad3_ net-_u18-pad2_ net-_u21-pad3_ u21
+a14 net-_u16-pad3_ net-_u18-pad2_ net-_u20-pad3_ u20
+a15 net-_u14-pad3_ net-_u18-pad2_ net-_u18-pad3_ u18
+a16 [net-_u14-pad1_ net-_u14-pad2_ ] net-_u14-pad3_ u14
+a17 [net-_u11-pad1_ net-_u13-pad2_ ] net-_u13-pad3_ u13
+a18 [net-_u10-pad1_ net-_u12-pad2_ ] net-_u12-pad3_ u12
+a19 [net-_u11-pad1_ net-_u11-pad2_ ] net-_u11-pad3_ u11
+* Schematic Name: d_and, Ngspice Name: d_and
+.model u8 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, Ngspice Name: d_and
+.model u7 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, Ngspice Name: d_and
+.model u6 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, Ngspice Name: d_and
+.model u10 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, Ngspice Name: d_and
+.model u9 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_buffer, Ngspice Name: d_buffer
+.model u5 d_buffer(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, Ngspice Name: d_inverter
+.model u3 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, Ngspice Name: d_inverter
+.model u4 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_or, Ngspice Name: d_or
+.model u17 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_or, Ngspice Name: d_or
+.model u16 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_or, Ngspice Name: d_or
+.model u15 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_tristate, Ngspice Name: d_tristate
+.model u19 d_tristate(delay=1.0e-9 input_load=1.0e-12 enable_load=1.0e-12 )
+* Schematic Name: d_tristate, Ngspice Name: d_tristate
+.model u21 d_tristate(delay=1.0e-9 input_load=1.0e-12 enable_load=1.0e-12 )
+* Schematic Name: d_tristate, Ngspice Name: d_tristate
+.model u20 d_tristate(delay=1.0e-9 input_load=1.0e-12 enable_load=1.0e-12 )
+* Schematic Name: d_tristate, Ngspice Name: d_tristate
+.model u18 d_tristate(delay=1.0e-9 input_load=1.0e-12 enable_load=1.0e-12 )
+* Schematic Name: d_or, Ngspice Name: d_or
+.model u14 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, Ngspice Name: d_and
+.model u13 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, Ngspice Name: d_and
+.model u12 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, Ngspice Name: d_and
+.model u11 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+.tran 0e-00 0e-00 0e-00
+
+* Control Statements
+.control
+run
+print allv > plot_data_v.txt
+print alli > plot_data_i.txt
+.endc
+.end
diff --git a/library/SubcircuitLibrary/SN74F257/SN74F257.kicad_sch b/library/SubcircuitLibrary/SN74F257/SN74F257.kicad_sch
new file mode 100644
index 000000000..f463068dd
--- /dev/null
+++ b/library/SubcircuitLibrary/SN74F257/SN74F257.kicad_sch
@@ -0,0 +1,1927 @@
+(kicad_sch (version 20211123) (generator eeschema)
+
+ (uuid 24a5a13f-2915-4329-8ef9-44ea4ddb5c45)
+
+ (paper "A2")
+
+ (lib_symbols
+ (symbol "eSim_Digital:d_and" (pin_names (offset 1.016)) (in_bom yes) (on_board yes)
+ (property "Reference" "U" (id 0) (at 0 0 0)
+ (effects (font (size 1.524 1.524)))
+ )
+ (property "Value" "d_and" (id 1) (at 1.27 2.54 0)
+ (effects (font (size 1.524 1.524)))
+ )
+ (property "Footprint" "" (id 2) (at 0 0 0)
+ (effects (font (size 1.524 1.524)))
+ )
+ (property "Datasheet" "" (id 3) (at 0 0 0)
+ (effects (font (size 1.524 1.524)))
+ )
+ (symbol "d_and_0_1"
+ (polyline
+ (pts
+ (xy 3.81 -1.27)
+ (xy -6.35 -1.27)
+ (xy -6.35 3.81)
+ (xy 3.81 3.81)
+ )
+ (stroke (width 0) (type default) (color 0 0 0 0))
+ (fill (type none))
+ )
+ (arc (start 3.81 -1.27) (mid 5.5897 -0.5171) (end 6.35 1.27)
+ (stroke (width 0) (type default) (color 0 0 0 0))
+ (fill (type none))
+ )
+ (arc (start 6.35 1.27) (mid 5.5971 3.0497) (end 3.81 3.81)
+ (stroke (width 0) (type default) (color 0 0 0 0))
+ (fill (type none))
+ )
+ )
+ (symbol "d_and_1_1"
+ (pin input line (at -11.43 2.54 0) (length 5.08)
+ (name "IN1" (effects (font (size 1.27 1.27))))
+ (number "1" (effects (font (size 1.27 1.27))))
+ )
+ (pin input line (at -11.43 0 0) (length 5.08)
+ (name "IN2" (effects (font (size 1.27 1.27))))
+ (number "2" (effects (font (size 1.27 1.27))))
+ )
+ (pin output line (at 11.43 1.27 180) (length 5.08)
+ (name "OUT" (effects (font (size 1.27 1.27))))
+ (number "3" (effects (font (size 1.27 1.27))))
+ )
+ )
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+ (reference "U19") (unit 1) (value "d_tristate") (footprint "")
+ )
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diff --git a/library/SubcircuitLibrary/SN74F257/SN74F257.sub b/library/SubcircuitLibrary/SN74F257/SN74F257.sub
new file mode 100644
index 000000000..67ae8782e
--- /dev/null
+++ b/library/SubcircuitLibrary/SN74F257/SN74F257.sub
@@ -0,0 +1,82 @@
+* Subcircuit SN74F257
+.subckt SN74F257 net-_u4-pad1_ net-_u6-pad2_ net-_u7-pad2_ net-_u18-pad3_ net-_u8-pad2_ net-_u9-pad2_ net-_u19-pad3_ unconnected-_u1-pad8_ net-_u20-pad3_ net-_u11-pad2_ net-_u10-pad2_ net-_u21-pad3_ net-_u13-pad2_ net-_u12-pad2_ net-_u3-pad1_ unconnected-_u1-pad16_
+.title kicad schematic
+* u8 net-_u10-pad1_ net-_u8-pad2_ net-_u15-pad1_ d_and
+* u7 net-_u11-pad1_ net-_u7-pad2_ net-_u14-pad2_ d_and
+* u6 net-_u10-pad1_ net-_u6-pad2_ net-_u14-pad1_ d_and
+* u10 net-_u10-pad1_ net-_u10-pad2_ net-_u10-pad3_ d_and
+* u9 net-_u11-pad1_ net-_u9-pad2_ net-_u15-pad2_ d_and
+* u5 net-_u4-pad1_ net-_u11-pad1_ d_buffer
+* u3 net-_u3-pad1_ net-_u18-pad2_ d_inverter
+* u4 net-_u4-pad1_ net-_u10-pad1_ d_inverter
+* u17 net-_u12-pad3_ net-_u13-pad3_ net-_u17-pad3_ d_or
+* u16 net-_u10-pad3_ net-_u11-pad3_ net-_u16-pad3_ d_or
+* u15 net-_u15-pad1_ net-_u15-pad2_ net-_u15-pad3_ d_or
+* u19 net-_u15-pad3_ net-_u18-pad2_ net-_u19-pad3_ d_tristate
+* u21 net-_u17-pad3_ net-_u18-pad2_ net-_u21-pad3_ d_tristate
+* u20 net-_u16-pad3_ net-_u18-pad2_ net-_u20-pad3_ d_tristate
+* u18 net-_u14-pad3_ net-_u18-pad2_ net-_u18-pad3_ d_tristate
+* u14 net-_u14-pad1_ net-_u14-pad2_ net-_u14-pad3_ d_or
+* u13 net-_u11-pad1_ net-_u13-pad2_ net-_u13-pad3_ d_and
+* u12 net-_u10-pad1_ net-_u12-pad2_ net-_u12-pad3_ d_and
+* u11 net-_u11-pad1_ net-_u11-pad2_ net-_u11-pad3_ d_and
+a1 [net-_u10-pad1_ net-_u8-pad2_ ] net-_u15-pad1_ u8
+a2 [net-_u11-pad1_ net-_u7-pad2_ ] net-_u14-pad2_ u7
+a3 [net-_u10-pad1_ net-_u6-pad2_ ] net-_u14-pad1_ u6
+a4 [net-_u10-pad1_ net-_u10-pad2_ ] net-_u10-pad3_ u10
+a5 [net-_u11-pad1_ net-_u9-pad2_ ] net-_u15-pad2_ u9
+a6 net-_u4-pad1_ net-_u11-pad1_ u5
+a7 net-_u3-pad1_ net-_u18-pad2_ u3
+a8 net-_u4-pad1_ net-_u10-pad1_ u4
+a9 [net-_u12-pad3_ net-_u13-pad3_ ] net-_u17-pad3_ u17
+a10 [net-_u10-pad3_ net-_u11-pad3_ ] net-_u16-pad3_ u16
+a11 [net-_u15-pad1_ net-_u15-pad2_ ] net-_u15-pad3_ u15
+a12 net-_u15-pad3_ net-_u18-pad2_ net-_u19-pad3_ u19
+a13 net-_u17-pad3_ net-_u18-pad2_ net-_u21-pad3_ u21
+a14 net-_u16-pad3_ net-_u18-pad2_ net-_u20-pad3_ u20
+a15 net-_u14-pad3_ net-_u18-pad2_ net-_u18-pad3_ u18
+a16 [net-_u14-pad1_ net-_u14-pad2_ ] net-_u14-pad3_ u14
+a17 [net-_u11-pad1_ net-_u13-pad2_ ] net-_u13-pad3_ u13
+a18 [net-_u10-pad1_ net-_u12-pad2_ ] net-_u12-pad3_ u12
+a19 [net-_u11-pad1_ net-_u11-pad2_ ] net-_u11-pad3_ u11
+* Schematic Name: d_and, Ngspice Name: d_and
+.model u8 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, Ngspice Name: d_and
+.model u7 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, Ngspice Name: d_and
+.model u6 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, Ngspice Name: d_and
+.model u10 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, Ngspice Name: d_and
+.model u9 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_buffer, Ngspice Name: d_buffer
+.model u5 d_buffer(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, Ngspice Name: d_inverter
+.model u3 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, Ngspice Name: d_inverter
+.model u4 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_or, Ngspice Name: d_or
+.model u17 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_or, Ngspice Name: d_or
+.model u16 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_or, Ngspice Name: d_or
+.model u15 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_tristate, Ngspice Name: d_tristate
+.model u19 d_tristate(delay=1.0e-9 input_load=1.0e-12 enable_load=1.0e-12 )
+* Schematic Name: d_tristate, Ngspice Name: d_tristate
+.model u21 d_tristate(delay=1.0e-9 input_load=1.0e-12 enable_load=1.0e-12 )
+* Schematic Name: d_tristate, Ngspice Name: d_tristate
+.model u20 d_tristate(delay=1.0e-9 input_load=1.0e-12 enable_load=1.0e-12 )
+* Schematic Name: d_tristate, Ngspice Name: d_tristate
+.model u18 d_tristate(delay=1.0e-9 input_load=1.0e-12 enable_load=1.0e-12 )
+* Schematic Name: d_or, Ngspice Name: d_or
+.model u14 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, Ngspice Name: d_and
+.model u13 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, Ngspice Name: d_and
+.model u12 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, Ngspice Name: d_and
+.model u11 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Control Statements
+
+.ends SN74F257
\ No newline at end of file
diff --git a/library/SubcircuitLibrary/SN74F257/SN74F257_Previous_Values.xml b/library/SubcircuitLibrary/SN74F257/SN74F257_Previous_Values.xml
new file mode 100644
index 000000000..308b1cbca
--- /dev/null
+++ b/library/SubcircuitLibrary/SN74F257/SN74F257_Previous_Values.xml
@@ -0,0 +1 @@
+truefalsefalseHzHz0Volts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or Amperessecsecsecd_andd_andd_andd_andd_andd_bufferd_inverterd_inverterd_ord_ord_ord_tristated_tristated_tristated_tristated_ord_andd_andd_and
\ No newline at end of file
diff --git a/library/SubcircuitLibrary/SN74F257/_autosave-SN74F257.sch b/library/SubcircuitLibrary/SN74F257/_autosave-SN74F257.sch
new file mode 100644
index 000000000..3fd0c697d
--- /dev/null
+++ b/library/SubcircuitLibrary/SN74F257/_autosave-SN74F257.sch
@@ -0,0 +1,570 @@
+EESchema Schematic File Version 5
+EELAYER 36 0
+EELAYER END
+$Descr A2 23386 16535
+encoding utf-8
+Sheet 1 1
+Title ""
+Date ""
+Rev ""
+Comp ""
+Comment1 ""
+Comment2 ""
+Comment3 ""
+Comment4 ""
+Comment5 ""
+Comment6 ""
+Comment7 ""
+Comment8 ""
+Comment9 ""
+$EndDescr
+Connection ~ 8050 3550
+Connection ~ 9850 5450
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+$Comp
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+F 3 "" H 6450 3050 60 0000 C CNN
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+$EndComp
+$Comp
+L eSim_Miscellaneous:PORT U?
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+$EndComp
+$Comp
+L eSim_Miscellaneous:PORT U?
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+$Comp
+L eSim_Miscellaneous:PORT U?
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+$Comp
+L eSim_Miscellaneous:PORT U?
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+$Comp
+L eSim_Miscellaneous:PORT U?
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+$EndComp
+$Comp
+L eSim_Miscellaneous:PORT U?
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+$EndComp
+$Comp
+L eSim_Miscellaneous:PORT U?
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+$EndComp
+$Comp
+L eSim_Miscellaneous:PORT U?
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+$EndComp
+$Comp
+L eSim_Miscellaneous:PORT U?
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+$EndComp
+$Comp
+L eSim_Miscellaneous:PORT U?
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+$EndComp
+$Comp
+L eSim_Miscellaneous:PORT U?
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+$EndComp
+$Comp
+L eSim_Miscellaneous:PORT U?
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+$EndComp
+$Comp
+L eSim_Miscellaneous:PORT U?
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+$EndComp
+$Comp
+L eSim_Miscellaneous:PORT U?
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+$EndComp
+$Comp
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+$EndComp
+$Comp
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+$EndComp
+$Comp
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+$EndComp
+$Comp
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+$Comp
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+F 0 "U21" H 15125 11300 60 0000 C CNN
+F 1 "d_tristate" H 15125 11450 60 0000 C CNN
+F 2 "" H 15050 11000 60 0000 C CNN
+F 3 "" H 15050 11000 60 0000 C CNN
+ 1 15150 10650
+ 1 0 0 1
+$EndComp
+$EndSCHEMATC
diff --git a/library/SubcircuitLibrary/SN74F257/analysis b/library/SubcircuitLibrary/SN74F257/analysis
new file mode 100644
index 000000000..ebd5c0a94
--- /dev/null
+++ b/library/SubcircuitLibrary/SN74F257/analysis
@@ -0,0 +1 @@
+.tran 0e-00 0e-00 0e-00
\ No newline at end of file
diff --git a/library/SubcircuitLibrary/SN74HC42/3_and-cache.lib b/library/SubcircuitLibrary/SN74HC42/3_and-cache.lib
new file mode 100644
index 000000000..af0586415
--- /dev/null
+++ b/library/SubcircuitLibrary/SN74HC42/3_and-cache.lib
@@ -0,0 +1,61 @@
+EESchema-LIBRARY Version 2.3
+#encoding utf-8
+#
+# PORT
+#
+DEF PORT U 0 40 Y Y 26 F N
+F0 "U" 50 100 30 H V C CNN
+F1 "PORT" 0 0 30 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0
+A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50
+S -100 50 100 -50 0 1 0 N
+X ~ 1 250 0 100 L 30 30 1 1 B
+X ~ 2 250 0 100 L 30 30 2 1 B
+X ~ 3 250 0 100 L 30 30 3 1 B
+X ~ 4 250 0 100 L 30 30 4 1 B
+X ~ 5 250 0 100 L 30 30 5 1 B
+X ~ 6 250 0 100 L 30 30 6 1 B
+X ~ 7 250 0 100 L 30 30 7 1 B
+X ~ 8 250 0 100 L 30 30 8 1 B
+X ~ 9 250 0 100 L 30 30 9 1 B
+X ~ 10 250 0 100 L 30 30 10 1 B
+X ~ 11 250 0 100 L 30 30 11 1 B
+X ~ 12 250 0 100 L 30 30 12 1 B
+X ~ 13 250 0 100 L 30 30 13 1 B
+X ~ 14 250 0 100 L 30 30 14 1 B
+X ~ 15 250 0 100 L 30 30 15 1 B
+X ~ 16 250 0 100 L 30 30 16 1 B
+X ~ 17 250 0 100 L 30 30 17 1 B
+X ~ 18 250 0 100 L 30 30 18 1 B
+X ~ 19 250 0 100 L 30 30 19 1 B
+X ~ 20 250 0 100 L 30 30 20 1 B
+X ~ 21 250 0 100 L 30 30 21 1 B
+X ~ 22 250 0 100 L 30 30 22 1 B
+X ~ 23 250 0 100 L 30 30 23 1 B
+X ~ 24 250 0 100 L 30 30 24 1 B
+X ~ 25 250 0 100 L 30 30 25 1 B
+X ~ 26 250 0 100 L 30 30 26 1 B
+ENDDRAW
+ENDDEF
+#
+# d_and
+#
+DEF d_and U 0 40 Y Y 1 F N
+F0 "U" 0 0 60 H V C CNN
+F1 "d_and" 50 100 60 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A 149 50 100 -894 0 0 1 0 N 150 -50 250 50
+A 150 49 100 6 900 0 1 0 N 250 50 150 150
+P 4 0 1 0 150 -50 -250 -50 -250 150 150 150 N
+X IN1 1 -450 100 200 R 50 50 1 1 I
+X IN2 2 -450 0 200 R 50 50 1 1 I
+X OUT 3 450 50 200 L 50 50 1 1 O
+ENDDRAW
+ENDDEF
+#
+#End Library
diff --git a/library/SubcircuitLibrary/SN74HC42/3_and.cir b/library/SubcircuitLibrary/SN74HC42/3_and.cir
new file mode 100644
index 000000000..ba296cf01
--- /dev/null
+++ b/library/SubcircuitLibrary/SN74HC42/3_and.cir
@@ -0,0 +1,13 @@
+* C:\Users\malli\eSim\src\SubcircuitLibrary\3_and\3_and.cir
+
+* EESchema Netlist Version 1.1 (Spice format) creation date: 03/26/19 18:42:57
+
+* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N
+* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0
+
+* Sheet Name: /
+U2 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U2-Pad3_ d_and
+U3 Net-_U2-Pad3_ Net-_U1-Pad3_ Net-_U1-Pad4_ d_and
+U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ PORT
+
+.end
diff --git a/library/SubcircuitLibrary/SN74HC42/3_and.cir.out b/library/SubcircuitLibrary/SN74HC42/3_and.cir.out
new file mode 100644
index 000000000..d7cf79a07
--- /dev/null
+++ b/library/SubcircuitLibrary/SN74HC42/3_and.cir.out
@@ -0,0 +1,20 @@
+* c:\users\malli\esim\src\subcircuitlibrary\3_and\3_and.cir
+
+* u2 net-_u1-pad1_ net-_u1-pad2_ net-_u2-pad3_ d_and
+* u3 net-_u2-pad3_ net-_u1-pad3_ net-_u1-pad4_ d_and
+* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ port
+a1 [net-_u1-pad1_ net-_u1-pad2_ ] net-_u2-pad3_ u2
+a2 [net-_u2-pad3_ net-_u1-pad3_ ] net-_u1-pad4_ u3
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u3 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+.tran 0e-00 0e-00 0e-00
+
+* Control Statements
+.control
+run
+print allv > plot_data_v.txt
+print alli > plot_data_i.txt
+.endc
+.end
diff --git a/library/SubcircuitLibrary/SN74HC42/3_and.pro b/library/SubcircuitLibrary/SN74HC42/3_and.pro
new file mode 100644
index 000000000..06813ca78
--- /dev/null
+++ b/library/SubcircuitLibrary/SN74HC42/3_and.pro
@@ -0,0 +1,43 @@
+update=Wed Mar 18 19:54:53 2020
+version=1
+last_client=eeschema
+[general]
+version=1
+RootSch=
+BoardNm=
+[pcbnew]
+version=1
+LastNetListRead=
+UseCmpFile=1
+PadDrill=0.600000000000
+PadDrillOvalY=0.600000000000
+PadSizeH=1.500000000000
+PadSizeV=1.500000000000
+PcbTextSizeV=1.500000000000
+PcbTextSizeH=1.500000000000
+PcbTextThickness=0.300000000000
+ModuleTextSizeV=1.000000000000
+ModuleTextSizeH=1.000000000000
+ModuleTextSizeThickness=0.150000000000
+SolderMaskClearance=0.000000000000
+SolderMaskMinWidth=0.000000000000
+DrawSegmentWidth=0.200000000000
+BoardOutlineThickness=0.100000000000
+ModuleOutlineThickness=0.150000000000
+[cvpcb]
+version=1
+NetIExt=net
+[eeschema]
+version=1
+LibDir=../../../kicadSchematicLibrary
+[eeschema/libraries]
+LibName1=eSim_Analog
+LibName2=eSim_Devices
+LibName3=eSim_Digital
+LibName4=eSim_Hybrid
+LibName5=eSim_Miscellaneous
+LibName6=eSim_Plot
+LibName7=eSim_Power
+LibName8=eSim_Sources
+LibName9=eSim_Subckt
+LibName10=eSim_User
diff --git a/library/SubcircuitLibrary/SN74HC42/3_and.sch b/library/SubcircuitLibrary/SN74HC42/3_and.sch
new file mode 100644
index 000000000..d6ac89f95
--- /dev/null
+++ b/library/SubcircuitLibrary/SN74HC42/3_and.sch
@@ -0,0 +1,130 @@
+EESchema Schematic File Version 2
+LIBS:power
+LIBS:texas
+LIBS:intel
+LIBS:audio
+LIBS:interface
+LIBS:digital-audio
+LIBS:philips
+LIBS:display
+LIBS:cypress
+LIBS:siliconi
+LIBS:opto
+LIBS:atmel
+LIBS:contrib
+LIBS:valves
+LIBS:eSim_Analog
+LIBS:eSim_Devices
+LIBS:eSim_Digital
+LIBS:eSim_Hybrid
+LIBS:eSim_Miscellaneous
+LIBS:eSim_Plot
+LIBS:eSim_Power
+LIBS:eSim_PSpice
+LIBS:eSim_Sources
+LIBS:eSim_Subckt
+LIBS:eSim_User
+LIBS:3_and-cache
+EELAYER 25 0
+EELAYER END
+$Descr A4 11693 8268
+encoding utf-8
+Sheet 1 1
+Title ""
+Date ""
+Rev ""
+Comp ""
+Comment1 ""
+Comment2 ""
+Comment3 ""
+Comment4 ""
+$EndDescr
+$Comp
+L d_and U2
+U 1 1 5C9A24D8
+P 4250 2700
+F 0 "U2" H 4250 2700 60 0000 C CNN
+F 1 "d_and" H 4300 2800 60 0000 C CNN
+F 2 "" H 4250 2700 60 0000 C CNN
+F 3 "" H 4250 2700 60 0000 C CNN
+ 1 4250 2700
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_and U3
+U 1 1 5C9A2538
+P 5150 2900
+F 0 "U3" H 5150 2900 60 0000 C CNN
+F 1 "d_and" H 5200 3000 60 0000 C CNN
+F 2 "" H 5150 2900 60 0000 C CNN
+F 3 "" H 5150 2900 60 0000 C CNN
+ 1 5150 2900
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 1 1 5C9A259A
+P 3050 2600
+F 0 "U1" H 3100 2700 30 0000 C CNN
+F 1 "PORT" H 3050 2600 30 0000 C CNN
+F 2 "" H 3050 2600 60 0000 C CNN
+F 3 "" H 3050 2600 60 0000 C CNN
+ 1 3050 2600
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 2 1 5C9A25D9
+P 3050 2800
+F 0 "U1" H 3100 2900 30 0000 C CNN
+F 1 "PORT" H 3050 2800 30 0000 C CNN
+F 2 "" H 3050 2800 60 0000 C CNN
+F 3 "" H 3050 2800 60 0000 C CNN
+ 2 3050 2800
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 3 1 5C9A260A
+P 3050 3100
+F 0 "U1" H 3100 3200 30 0000 C CNN
+F 1 "PORT" H 3050 3100 30 0000 C CNN
+F 2 "" H 3050 3100 60 0000 C CNN
+F 3 "" H 3050 3100 60 0000 C CNN
+ 3 3050 3100
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 4 1 5C9A2637
+P 6900 2850
+F 0 "U1" H 6950 2950 30 0000 C CNN
+F 1 "PORT" H 6900 2850 30 0000 C CNN
+F 2 "" H 6900 2850 60 0000 C CNN
+F 3 "" H 6900 2850 60 0000 C CNN
+ 4 6900 2850
+ -1 0 0 1
+$EndComp
+Wire Wire Line
+ 4700 2650 4700 2800
+Wire Wire Line
+ 5600 2850 6650 2850
+Wire Wire Line
+ 3800 2600 3300 2600
+Wire Wire Line
+ 3800 2700 3300 2700
+Wire Wire Line
+ 3300 2700 3300 2800
+Wire Wire Line
+ 3300 3100 4700 3100
+Wire Wire Line
+ 4700 3100 4700 2900
+Text Notes 3500 2600 0 60 ~ 12
+in1
+Text Notes 3450 2800 0 60 ~ 12
+in2\n
+Text Notes 3500 3100 0 60 ~ 12
+in3
+Text Notes 6100 2850 0 60 ~ 12
+out
+$EndSCHEMATC
diff --git a/library/SubcircuitLibrary/SN74HC42/3_and.sub b/library/SubcircuitLibrary/SN74HC42/3_and.sub
new file mode 100644
index 000000000..3d9120bb6
--- /dev/null
+++ b/library/SubcircuitLibrary/SN74HC42/3_and.sub
@@ -0,0 +1,14 @@
+* Subcircuit 3_and
+.subckt 3_and net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_
+* c:\users\malli\esim\src\subcircuitlibrary\3_and\3_and.cir
+* u2 net-_u1-pad1_ net-_u1-pad2_ net-_u2-pad3_ d_and
+* u3 net-_u2-pad3_ net-_u1-pad3_ net-_u1-pad4_ d_and
+a1 [net-_u1-pad1_ net-_u1-pad2_ ] net-_u2-pad3_ u2
+a2 [net-_u2-pad3_ net-_u1-pad3_ ] net-_u1-pad4_ u3
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u3 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+* Control Statements
+
+.ends 3_and
\ No newline at end of file
diff --git a/library/SubcircuitLibrary/SN74HC42/3_and_Previous_Values.xml b/library/SubcircuitLibrary/SN74HC42/3_and_Previous_Values.xml
new file mode 100644
index 000000000..abc5faaae
--- /dev/null
+++ b/library/SubcircuitLibrary/SN74HC42/3_and_Previous_Values.xml
@@ -0,0 +1 @@
+d_andd_andtruefalsefalseHzHz0Volts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesSecSecSec
\ No newline at end of file
diff --git a/library/SubcircuitLibrary/SN74HC42/4_and-cache.lib b/library/SubcircuitLibrary/SN74HC42/4_and-cache.lib
new file mode 100644
index 000000000..60f1a83d4
--- /dev/null
+++ b/library/SubcircuitLibrary/SN74HC42/4_and-cache.lib
@@ -0,0 +1,79 @@
+EESchema-LIBRARY Version 2.3
+#encoding utf-8
+#
+# 3_and-RESCUE-4_and
+#
+DEF 3_and-RESCUE-4_and X 0 40 Y Y 1 F N
+F0 "X" 900 300 60 H V C CNN
+F1 "3_and-RESCUE-4_and" 950 500 60 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A 950 400 158 716 -716 0 1 0 N 1000 550 1000 250
+P 2 0 1 0 650 550 1000 550 N
+P 3 0 1 0 650 550 650 250 1000 250 N
+X in1 1 450 500 200 R 50 50 1 1 I
+X in2 2 450 400 200 R 50 50 1 1 I
+X in3 3 450 300 200 R 50 50 1 1 I
+X out 4 1300 400 200 L 50 50 1 1 O
+ENDDRAW
+ENDDEF
+#
+# PORT
+#
+DEF PORT U 0 40 Y Y 26 F N
+F0 "U" 50 100 30 H V C CNN
+F1 "PORT" 0 0 30 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0
+A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50
+S -100 50 100 -50 0 1 0 N
+X ~ 1 250 0 100 L 30 30 1 1 B
+X ~ 2 250 0 100 L 30 30 2 1 B
+X ~ 3 250 0 100 L 30 30 3 1 B
+X ~ 4 250 0 100 L 30 30 4 1 B
+X ~ 5 250 0 100 L 30 30 5 1 B
+X ~ 6 250 0 100 L 30 30 6 1 B
+X ~ 7 250 0 100 L 30 30 7 1 B
+X ~ 8 250 0 100 L 30 30 8 1 B
+X ~ 9 250 0 100 L 30 30 9 1 B
+X ~ 10 250 0 100 L 30 30 10 1 B
+X ~ 11 250 0 100 L 30 30 11 1 B
+X ~ 12 250 0 100 L 30 30 12 1 B
+X ~ 13 250 0 100 L 30 30 13 1 B
+X ~ 14 250 0 100 L 30 30 14 1 B
+X ~ 15 250 0 100 L 30 30 15 1 B
+X ~ 16 250 0 100 L 30 30 16 1 B
+X ~ 17 250 0 100 L 30 30 17 1 B
+X ~ 18 250 0 100 L 30 30 18 1 B
+X ~ 19 250 0 100 L 30 30 19 1 B
+X ~ 20 250 0 100 L 30 30 20 1 B
+X ~ 21 250 0 100 L 30 30 21 1 B
+X ~ 22 250 0 100 L 30 30 22 1 B
+X ~ 23 250 0 100 L 30 30 23 1 B
+X ~ 24 250 0 100 L 30 30 24 1 B
+X ~ 25 250 0 100 L 30 30 25 1 B
+X ~ 26 250 0 100 L 30 30 26 1 B
+ENDDRAW
+ENDDEF
+#
+# d_and
+#
+DEF d_and U 0 40 Y Y 1 F N
+F0 "U" 0 0 60 H V C CNN
+F1 "d_and" 50 100 60 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A 149 50 100 -894 0 0 1 0 N 150 -50 250 50
+A 150 49 100 6 900 0 1 0 N 250 50 150 150
+P 4 0 1 0 150 -50 -250 -50 -250 150 150 150 N
+X IN1 1 -450 100 200 R 50 50 1 1 I
+X IN2 2 -450 0 200 R 50 50 1 1 I
+X OUT 3 450 50 200 L 50 50 1 1 O
+ENDDRAW
+ENDDEF
+#
+#End Library
diff --git a/library/SubcircuitLibrary/SN74HC42/4_and-rescue.lib b/library/SubcircuitLibrary/SN74HC42/4_and-rescue.lib
new file mode 100644
index 000000000..e38330518
--- /dev/null
+++ b/library/SubcircuitLibrary/SN74HC42/4_and-rescue.lib
@@ -0,0 +1,22 @@
+EESchema-LIBRARY Version 2.3
+#encoding utf-8
+#
+# 3_and-RESCUE-4_and
+#
+DEF 3_and-RESCUE-4_and X 0 40 Y Y 1 F N
+F0 "X" 900 300 60 H V C CNN
+F1 "3_and-RESCUE-4_and" 950 500 60 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A 950 400 158 716 -716 0 1 0 N 1000 550 1000 250
+P 2 0 1 0 650 550 1000 550 N
+P 3 0 1 0 650 550 650 250 1000 250 N
+X in1 1 450 500 200 R 50 50 1 1 I
+X in2 2 450 400 200 R 50 50 1 1 I
+X in3 3 450 300 200 R 50 50 1 1 I
+X out 4 1300 400 200 L 50 50 1 1 O
+ENDDRAW
+ENDDEF
+#
+#End Library
diff --git a/library/SubcircuitLibrary/SN74HC42/4_and.cir b/library/SubcircuitLibrary/SN74HC42/4_and.cir
new file mode 100644
index 000000000..fdf2e1074
--- /dev/null
+++ b/library/SubcircuitLibrary/SN74HC42/4_and.cir
@@ -0,0 +1,13 @@
+* C:\Users\malli\eSim\src\SubcircuitLibrary\4_and\4_and.cir
+
+* EESchema Netlist Version 1.1 (Spice format) creation date: 06/01/19 13:09:58
+
+* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N
+* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0
+
+* Sheet Name: /
+X1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U2-Pad1_ 3_and
+U2 Net-_U2-Pad1_ Net-_U1-Pad4_ Net-_U1-Pad5_ d_and
+U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ PORT
+
+.end
diff --git a/library/SubcircuitLibrary/SN74HC42/4_and.cir.out b/library/SubcircuitLibrary/SN74HC42/4_and.cir.out
new file mode 100644
index 000000000..f40e5bc62
--- /dev/null
+++ b/library/SubcircuitLibrary/SN74HC42/4_and.cir.out
@@ -0,0 +1,18 @@
+* c:\users\malli\esim\src\subcircuitlibrary\4_and\4_and.cir
+
+.include 3_and.sub
+x1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u2-pad1_ 3_and
+* u2 net-_u2-pad1_ net-_u1-pad4_ net-_u1-pad5_ d_and
+* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ port
+a1 [net-_u2-pad1_ net-_u1-pad4_ ] net-_u1-pad5_ u2
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+.tran 0e-00 0e-00 0e-00
+
+* Control Statements
+.control
+run
+print allv > plot_data_v.txt
+print alli > plot_data_i.txt
+.endc
+.end
diff --git a/library/SubcircuitLibrary/SN74HC42/4_and.pro b/library/SubcircuitLibrary/SN74HC42/4_and.pro
new file mode 100644
index 000000000..b13a0a825
--- /dev/null
+++ b/library/SubcircuitLibrary/SN74HC42/4_and.pro
@@ -0,0 +1,57 @@
+update=Wed Mar 18 19:54:24 2020
+version=1
+last_client=eeschema
+[general]
+version=1
+RootSch=
+BoardNm=
+[pcbnew]
+version=1
+LastNetListRead=
+UseCmpFile=1
+PadDrill=0.600000000000
+PadDrillOvalY=0.600000000000
+PadSizeH=1.500000000000
+PadSizeV=1.500000000000
+PcbTextSizeV=1.500000000000
+PcbTextSizeH=1.500000000000
+PcbTextThickness=0.300000000000
+ModuleTextSizeV=1.000000000000
+ModuleTextSizeH=1.000000000000
+ModuleTextSizeThickness=0.150000000000
+SolderMaskClearance=0.000000000000
+SolderMaskMinWidth=0.000000000000
+DrawSegmentWidth=0.200000000000
+BoardOutlineThickness=0.100000000000
+ModuleOutlineThickness=0.150000000000
+[cvpcb]
+version=1
+NetIExt=net
+[eeschema]
+version=1
+LibDir=../../../kicadSchematicLibrary
+[eeschema/libraries]
+LibName1=4_and-rescue
+LibName2=texas
+LibName3=intel
+LibName4=audio
+LibName5=interface
+LibName6=digital-audio
+LibName7=philips
+LibName8=display
+LibName9=cypress
+LibName10=siliconi
+LibName11=opto
+LibName12=atmel
+LibName13=contrib
+LibName14=valves
+LibName15=eSim_Analog
+LibName16=eSim_Devices
+LibName17=eSim_Digital
+LibName18=eSim_Hybrid
+LibName19=eSim_Miscellaneous
+LibName20=eSim_Plot
+LibName21=eSim_Power
+LibName22=eSim_Sources
+LibName23=eSim_Subckt
+LibName24=eSim_User
diff --git a/library/SubcircuitLibrary/SN74HC42/4_and.sch b/library/SubcircuitLibrary/SN74HC42/4_and.sch
new file mode 100644
index 000000000..f5e8febdc
--- /dev/null
+++ b/library/SubcircuitLibrary/SN74HC42/4_and.sch
@@ -0,0 +1,151 @@
+EESchema Schematic File Version 2
+LIBS:4_and-rescue
+LIBS:texas
+LIBS:intel
+LIBS:audio
+LIBS:interface
+LIBS:digital-audio
+LIBS:philips
+LIBS:display
+LIBS:cypress
+LIBS:siliconi
+LIBS:opto
+LIBS:atmel
+LIBS:contrib
+LIBS:valves
+LIBS:eSim_Analog
+LIBS:eSim_Devices
+LIBS:eSim_Digital
+LIBS:eSim_Hybrid
+LIBS:eSim_Miscellaneous
+LIBS:eSim_Plot
+LIBS:eSim_Power
+LIBS:eSim_PSpice
+LIBS:eSim_Sources
+LIBS:eSim_Subckt
+LIBS:eSim_User
+LIBS:4_and-cache
+EELAYER 25 0
+EELAYER END
+$Descr A4 11693 8268
+encoding utf-8
+Sheet 1 1
+Title ""
+Date ""
+Rev ""
+Comp ""
+Comment1 ""
+Comment2 ""
+Comment3 ""
+Comment4 ""
+$EndDescr
+$Comp
+L 3_and-RESCUE-4_and X1
+U 1 1 5C9A2915
+P 3700 3500
+F 0 "X1" H 4600 3800 60 0000 C CNN
+F 1 "3_and" H 4650 4000 60 0000 C CNN
+F 2 "" H 3700 3500 60 0000 C CNN
+F 3 "" H 3700 3500 60 0000 C CNN
+ 1 3700 3500
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_and U2
+U 1 1 5C9A2940
+P 5450 3400
+F 0 "U2" H 5450 3400 60 0000 C CNN
+F 1 "d_and" H 5500 3500 60 0000 C CNN
+F 2 "" H 5450 3400 60 0000 C CNN
+F 3 "" H 5450 3400 60 0000 C CNN
+ 1 5450 3400
+ 1 0 0 -1
+$EndComp
+Wire Wire Line
+ 5000 3100 5000 3300
+Wire Wire Line
+ 4150 3000 4150 2700
+Wire Wire Line
+ 4150 2700 3200 2700
+Wire Wire Line
+ 4150 3100 4000 3100
+Wire Wire Line
+ 4000 3100 4000 3000
+Wire Wire Line
+ 4000 3000 3200 3000
+Wire Wire Line
+ 4150 3200 4150 3300
+Wire Wire Line
+ 4150 3300 3250 3300
+Wire Wire Line
+ 5000 3400 5000 3550
+Wire Wire Line
+ 5000 3550 3250 3550
+Wire Wire Line
+ 5900 3350 6500 3350
+$Comp
+L PORT U1
+U 1 1 5C9A29B1
+P 2950 2700
+F 0 "U1" H 3000 2800 30 0000 C CNN
+F 1 "PORT" H 2950 2700 30 0000 C CNN
+F 2 "" H 2950 2700 60 0000 C CNN
+F 3 "" H 2950 2700 60 0000 C CNN
+ 1 2950 2700
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 2 1 5C9A29E9
+P 2950 3000
+F 0 "U1" H 3000 3100 30 0000 C CNN
+F 1 "PORT" H 2950 3000 30 0000 C CNN
+F 2 "" H 2950 3000 60 0000 C CNN
+F 3 "" H 2950 3000 60 0000 C CNN
+ 2 2950 3000
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 3 1 5C9A2A0D
+P 3000 3300
+F 0 "U1" H 3050 3400 30 0000 C CNN
+F 1 "PORT" H 3000 3300 30 0000 C CNN
+F 2 "" H 3000 3300 60 0000 C CNN
+F 3 "" H 3000 3300 60 0000 C CNN
+ 3 3000 3300
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 4 1 5C9A2A3C
+P 3000 3550
+F 0 "U1" H 3050 3650 30 0000 C CNN
+F 1 "PORT" H 3000 3550 30 0000 C CNN
+F 2 "" H 3000 3550 60 0000 C CNN
+F 3 "" H 3000 3550 60 0000 C CNN
+ 4 3000 3550
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 5 1 5C9A2A68
+P 6750 3350
+F 0 "U1" H 6800 3450 30 0000 C CNN
+F 1 "PORT" H 6750 3350 30 0000 C CNN
+F 2 "" H 6750 3350 60 0000 C CNN
+F 3 "" H 6750 3350 60 0000 C CNN
+ 5 6750 3350
+ -1 0 0 1
+$EndComp
+Text Notes 3450 2650 0 60 ~ 12
+in1
+Text Notes 3450 2950 0 60 ~ 12
+in2
+Text Notes 3500 3300 0 60 ~ 12
+in3
+Text Notes 3500 3550 0 60 ~ 12
+in4
+Text Notes 6150 3350 0 60 ~ 12
+out
+$EndSCHEMATC
diff --git a/library/SubcircuitLibrary/SN74HC42/4_and.sub b/library/SubcircuitLibrary/SN74HC42/4_and.sub
new file mode 100644
index 000000000..8663f37e6
--- /dev/null
+++ b/library/SubcircuitLibrary/SN74HC42/4_and.sub
@@ -0,0 +1,12 @@
+* Subcircuit 4_and
+.subckt 4_and net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_
+* c:\users\malli\esim\src\subcircuitlibrary\4_and\4_and.cir
+.include 3_and.sub
+x1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u2-pad1_ 3_and
+* u2 net-_u2-pad1_ net-_u1-pad4_ net-_u1-pad5_ d_and
+a1 [net-_u2-pad1_ net-_u1-pad4_ ] net-_u1-pad5_ u2
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+* Control Statements
+
+.ends 4_and
\ No newline at end of file
diff --git a/library/SubcircuitLibrary/SN74HC42/4_and_Previous_Values.xml b/library/SubcircuitLibrary/SN74HC42/4_and_Previous_Values.xml
new file mode 100644
index 000000000..f2ba0130e
--- /dev/null
+++ b/library/SubcircuitLibrary/SN74HC42/4_and_Previous_Values.xml
@@ -0,0 +1 @@
+d_andC:\Users\malli\eSim\src\SubcircuitLibrary\3_andtruefalsefalseHzHz0Volts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesSecSecSec
\ No newline at end of file
diff --git a/library/SubcircuitLibrary/SN74HC42/SN74HC42.cir b/library/SubcircuitLibrary/SN74HC42/SN74HC42.cir
new file mode 100644
index 000000000..c4988af7b
--- /dev/null
+++ b/library/SubcircuitLibrary/SN74HC42/SN74HC42.cir
@@ -0,0 +1,31 @@
+.title KiCad schematic
+X1 Net-_U13-Pad1_ Net-_U10-Pad2_ Net-_U11-Pad2_ Net-_U12-Pad2_ Net-_U17-Pad1_ 4_and
+X3 Net-_U13-Pad1_ Net-_U14-Pad2_ Net-_U11-Pad2_ Net-_U12-Pad2_ Net-_U19-Pad1_ 4_and
+X2 Net-_U13-Pad2_ Net-_U10-Pad2_ Net-_U11-Pad2_ Net-_U12-Pad2_ Net-_U18-Pad1_ 4_and
+U17 Net-_U17-Pad1_ Net-_U17-Pad2_ d_inverter
+U1 Net-_U17-Pad2_ Net-_U18-Pad2_ Net-_U19-Pad2_ Net-_U20-Pad2_ Net-_U21-Pad2_ Net-_U22-Pad2_ Net-_U23-Pad2_ unconnected-_U1-Pad8_ Net-_U24-Pad2_ Net-_U25-Pad2_ Net-_U26-Pad2_ Net-_U12-Pad1_ Net-_U11-Pad1_ Net-_U10-Pad1_ Net-_U9-Pad1_ unconnected-_U1-Pad16_ PORT
+U18 Net-_U18-Pad1_ Net-_U18-Pad2_ d_inverter
+U21 Net-_U21-Pad1_ Net-_U21-Pad2_ d_inverter
+U22 Net-_U22-Pad1_ Net-_U22-Pad2_ d_inverter
+U25 Net-_U25-Pad1_ Net-_U25-Pad2_ d_inverter
+U26 Net-_U26-Pad1_ Net-_U26-Pad2_ d_inverter
+X10 Net-_U13-Pad2_ Net-_U10-Pad2_ Net-_U11-Pad2_ Net-_U16-Pad2_ Net-_U26-Pad1_ 4_and
+X9 Net-_U13-Pad1_ Net-_U10-Pad2_ Net-_U11-Pad2_ Net-_U16-Pad2_ Net-_U25-Pad1_ 4_and
+X8 Net-_U13-Pad2_ Net-_U14-Pad2_ Net-_X5-Pad3_ Net-_U12-Pad2_ Net-_U24-Pad1_ 4_and
+U23 Net-_U23-Pad1_ Net-_U23-Pad2_ d_inverter
+U24 Net-_U24-Pad1_ Net-_U24-Pad2_ d_inverter
+X4 Net-_U13-Pad2_ Net-_U14-Pad2_ Net-_U11-Pad2_ Net-_U12-Pad2_ Net-_U20-Pad1_ 4_and
+U20 Net-_U20-Pad1_ Net-_U20-Pad2_ d_inverter
+U19 Net-_U19-Pad1_ Net-_U19-Pad2_ d_inverter
+X6 Net-_U13-Pad2_ Net-_U10-Pad2_ Net-_X5-Pad3_ Net-_U12-Pad2_ Net-_U22-Pad1_ 4_and
+X7 Net-_U13-Pad1_ Net-_U14-Pad2_ Net-_X5-Pad3_ Net-_U12-Pad2_ Net-_U23-Pad1_ 4_and
+X5 Net-_U13-Pad1_ Net-_U10-Pad2_ Net-_X5-Pad3_ Net-_U12-Pad2_ Net-_U21-Pad1_ 4_and
+U13 Net-_U13-Pad1_ Net-_U13-Pad2_ d_inverter
+U10 Net-_U10-Pad1_ Net-_U10-Pad2_ d_inverter
+U14 Net-_U10-Pad2_ Net-_U14-Pad2_ d_inverter
+U9 Net-_U9-Pad1_ Net-_U13-Pad1_ d_inverter
+U15 Net-_U11-Pad2_ Net-_U11-Pad2_ d_inverter
+U16 Net-_U12-Pad2_ Net-_U16-Pad2_ d_inverter
+U11 Net-_U11-Pad1_ Net-_U11-Pad2_ d_inverter
+U12 Net-_U12-Pad1_ Net-_U12-Pad2_ d_inverter
+.end
diff --git a/library/SubcircuitLibrary/SN74HC42/SN74HC42.cir.out b/library/SubcircuitLibrary/SN74HC42/SN74HC42.cir.out
new file mode 100644
index 000000000..5e2e7c98f
--- /dev/null
+++ b/library/SubcircuitLibrary/SN74HC42/SN74HC42.cir.out
@@ -0,0 +1,95 @@
+.title kicad schematic
+
+.include 4_and.sub
+x1 net-_u13-pad1_ net-_u10-pad2_ net-_u11-pad2_ net-_u12-pad2_ net-_u17-pad1_ 4_and
+x3 net-_u13-pad1_ net-_u14-pad2_ net-_u11-pad2_ net-_u12-pad2_ net-_u19-pad1_ 4_and
+x2 net-_u13-pad2_ net-_u10-pad2_ net-_u11-pad2_ net-_u12-pad2_ net-_u18-pad1_ 4_and
+* u17 net-_u17-pad1_ net-_u17-pad2_ d_inverter
+* u1 net-_u17-pad2_ net-_u18-pad2_ net-_u19-pad2_ net-_u20-pad2_ net-_u21-pad2_ net-_u22-pad2_ net-_u23-pad2_ unconnected-_u1-pad8_ net-_u24-pad2_ net-_u25-pad2_ net-_u26-pad2_ net-_u12-pad1_ net-_u11-pad1_ net-_u10-pad1_ net-_u9-pad1_ unconnected-_u1-pad16_ port
+* u18 net-_u18-pad1_ net-_u18-pad2_ d_inverter
+* u21 net-_u21-pad1_ net-_u21-pad2_ d_inverter
+* u22 net-_u22-pad1_ net-_u22-pad2_ d_inverter
+* u25 net-_u25-pad1_ net-_u25-pad2_ d_inverter
+* u26 net-_u26-pad1_ net-_u26-pad2_ d_inverter
+x10 net-_u13-pad2_ net-_u10-pad2_ net-_u11-pad2_ net-_u16-pad2_ net-_u26-pad1_ 4_and
+x9 net-_u13-pad1_ net-_u10-pad2_ net-_u11-pad2_ net-_u16-pad2_ net-_u25-pad1_ 4_and
+x8 net-_u13-pad2_ net-_u14-pad2_ net-_x5-pad3_ net-_u12-pad2_ net-_u24-pad1_ 4_and
+* u23 net-_u23-pad1_ net-_u23-pad2_ d_inverter
+* u24 net-_u24-pad1_ net-_u24-pad2_ d_inverter
+x4 net-_u13-pad2_ net-_u14-pad2_ net-_u11-pad2_ net-_u12-pad2_ net-_u20-pad1_ 4_and
+* u20 net-_u20-pad1_ net-_u20-pad2_ d_inverter
+* u19 net-_u19-pad1_ net-_u19-pad2_ d_inverter
+x6 net-_u13-pad2_ net-_u10-pad2_ net-_x5-pad3_ net-_u12-pad2_ net-_u22-pad1_ 4_and
+x7 net-_u13-pad1_ net-_u14-pad2_ net-_x5-pad3_ net-_u12-pad2_ net-_u23-pad1_ 4_and
+x5 net-_u13-pad1_ net-_u10-pad2_ net-_x5-pad3_ net-_u12-pad2_ net-_u21-pad1_ 4_and
+* u13 net-_u13-pad1_ net-_u13-pad2_ d_inverter
+* u10 net-_u10-pad1_ net-_u10-pad2_ d_inverter
+* u14 net-_u10-pad2_ net-_u14-pad2_ d_inverter
+* u9 net-_u9-pad1_ net-_u13-pad1_ d_inverter
+* u15 net-_u11-pad2_ net-_u11-pad2_ d_inverter
+* u16 net-_u12-pad2_ net-_u16-pad2_ d_inverter
+* u11 net-_u11-pad1_ net-_u11-pad2_ d_inverter
+* u12 net-_u12-pad1_ net-_u12-pad2_ d_inverter
+a1 net-_u17-pad1_ net-_u17-pad2_ u17
+a2 net-_u18-pad1_ net-_u18-pad2_ u18
+a3 net-_u21-pad1_ net-_u21-pad2_ u21
+a4 net-_u22-pad1_ net-_u22-pad2_ u22
+a5 net-_u25-pad1_ net-_u25-pad2_ u25
+a6 net-_u26-pad1_ net-_u26-pad2_ u26
+a7 net-_u23-pad1_ net-_u23-pad2_ u23
+a8 net-_u24-pad1_ net-_u24-pad2_ u24
+a9 net-_u20-pad1_ net-_u20-pad2_ u20
+a10 net-_u19-pad1_ net-_u19-pad2_ u19
+a11 net-_u13-pad1_ net-_u13-pad2_ u13
+a12 net-_u10-pad1_ net-_u10-pad2_ u10
+a13 net-_u10-pad2_ net-_u14-pad2_ u14
+a14 net-_u9-pad1_ net-_u13-pad1_ u9
+a15 net-_u11-pad2_ net-_u11-pad2_ u15
+a16 net-_u12-pad2_ net-_u16-pad2_ u16
+a17 net-_u11-pad1_ net-_u11-pad2_ u11
+a18 net-_u12-pad1_ net-_u12-pad2_ u12
+* Schematic Name: d_inverter, Ngspice Name: d_inverter
+.model u17 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, Ngspice Name: d_inverter
+.model u18 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, Ngspice Name: d_inverter
+.model u21 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, Ngspice Name: d_inverter
+.model u22 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, Ngspice Name: d_inverter
+.model u25 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, Ngspice Name: d_inverter
+.model u26 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, Ngspice Name: d_inverter
+.model u23 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, Ngspice Name: d_inverter
+.model u24 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, Ngspice Name: d_inverter
+.model u20 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, Ngspice Name: d_inverter
+.model u19 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, Ngspice Name: d_inverter
+.model u13 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, Ngspice Name: d_inverter
+.model u10 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, Ngspice Name: d_inverter
+.model u14 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, Ngspice Name: d_inverter
+.model u9 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, Ngspice Name: d_inverter
+.model u15 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, Ngspice Name: d_inverter
+.model u16 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, Ngspice Name: d_inverter
+.model u11 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, Ngspice Name: d_inverter
+.model u12 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+.tran 0e-00 0e-00 0e-00
+
+* Control Statements
+.control
+run
+print allv > plot_data_v.txt
+print alli > plot_data_i.txt
+.endc
+.end
diff --git a/library/SubcircuitLibrary/SN74HC42/SN74HC42.kicad_sch b/library/SubcircuitLibrary/SN74HC42/SN74HC42.kicad_sch
new file mode 100644
index 000000000..0c8ce4eb9
--- /dev/null
+++ b/library/SubcircuitLibrary/SN74HC42/SN74HC42.kicad_sch
@@ -0,0 +1,2243 @@
+(kicad_sch (version 20211123) (generator eeschema)
+
+ (uuid 2ebe176d-c90a-4b40-be6d-cfc37cb86d5e)
+
+ (paper "A2")
+
+ (lib_symbols
+ (symbol "eSim_Digital:d_inverter" (pin_names (offset 1.016)) (in_bom yes) (on_board yes)
+ (property "Reference" "U" (id 0) (at 0 -2.54 0)
+ (effects (font (size 1.524 1.524)))
+ )
+ (property "Value" "d_inverter" (id 1) (at 0 3.81 0)
+ (effects (font (size 1.524 1.524)))
+ )
+ (property "Footprint" "" (id 2) (at 1.27 -1.27 0)
+ (effects (font (size 1.524 1.524)))
+ )
+ (property "Datasheet" "" (id 3) (at 1.27 -1.27 0)
+ (effects (font (size 1.524 1.524)))
+ )
+ (symbol "d_inverter_0_1"
+ (polyline
+ (pts
+ (xy -2.54 1.27)
+ (xy -2.54 -1.27)
+ (xy 2.54 0)
+ (xy -2.54 1.27)
+ )
+ (stroke (width 0) (type default) (color 0 0 0 0))
+ (fill (type none))
+ )
+ )
+ (symbol "d_inverter_1_1"
+ (pin input line (at -7.62 0 0) (length 5.08)
+ (name "~" (effects (font (size 1.27 1.27))))
+ (number "1" (effects (font (size 1.27 1.27))))
+ )
+ (pin output inverted (at 7.62 0 180) (length 5.08)
+ (name "~" (effects (font (size 1.27 1.27))))
+ (number "2" (effects (font (size 1.27 1.27))))
+ )
+ )
+ )
+ (symbol "eSim_Miscellaneous:PORT" (pin_names (offset 1.016)) (in_bom yes) (on_board yes)
+ (property "Reference" "U" (id 0) (at 1.27 2.54 0)
+ (effects (font (size 0.762 0.762)))
+ )
+ (property "Value" "PORT" (id 1) (at 0 0 0)
+ (effects (font (size 0.762 0.762)))
+ )
+ (property "Footprint" "" (id 2) (at 0 0 0)
+ (effects (font (size 1.524 1.524)))
+ )
+ (property "Datasheet" "" (id 3) (at 0 0 0)
+ (effects (font (size 1.524 1.524)))
+ )
+ (symbol "PORT_0_1"
+ (rectangle (start -2.54 1.27) (end 2.54 -1.27)
+ (stroke (width 0) (type default) (color 0 0 0 0))
+ (fill (type none))
+ )
+ (arc (start 2.54 1.27) (mid 3.1355 0.5955) (end 3.81 0)
+ (stroke (width 0) (type default) (color 0 0 0 0))
+ (fill (type none))
+ )
+ (arc (start 3.81 0) (mid 3.1447 -0.6046) (end 2.54 -1.27)
+ (stroke (width 0) (type default) (color 0 0 0 0))
+ (fill (type none))
+ )
+ )
+ (symbol "PORT_1_1"
+ (pin bidirectional line (at 6.35 0 180) (length 2.54)
+ (name "~" (effects (font (size 0.762 0.762))))
+ (number "1" (effects (font (size 0.762 0.762))))
+ )
+ )
+ (symbol "PORT_2_1"
+ (pin bidirectional line (at 6.35 0 180) (length 2.54)
+ (name "~" (effects (font (size 0.762 0.762))))
+ (number "2" (effects (font (size 0.762 0.762))))
+ )
+ )
+ (symbol "PORT_3_1"
+ (pin bidirectional line (at 6.35 0 180) (length 2.54)
+ (name "~" (effects (font (size 0.762 0.762))))
+ (number "3" (effects (font (size 0.762 0.762))))
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+ )
+ (symbol "PORT_4_1"
+ (pin bidirectional line (at 6.35 0 180) (length 2.54)
+ (name "~" (effects (font (size 0.762 0.762))))
+ (number "4" (effects (font (size 0.762 0.762))))
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+ (symbol "PORT_5_1"
+ (pin bidirectional line (at 6.35 0 180) (length 2.54)
+ (name "~" (effects (font (size 0.762 0.762))))
+ (number "5" (effects (font (size 0.762 0.762))))
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+ (symbol "PORT_6_1"
+ (pin bidirectional line (at 6.35 0 180) (length 2.54)
+ (name "~" (effects (font (size 0.762 0.762))))
+ (number "6" (effects (font (size 0.762 0.762))))
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+ (symbol "PORT_7_1"
+ (pin bidirectional line (at 6.35 0 180) (length 2.54)
+ (name "~" (effects (font (size 0.762 0.762))))
+ (number "7" (effects (font (size 0.762 0.762))))
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+ (symbol "PORT_8_1"
+ (pin bidirectional line (at 6.35 0 180) (length 2.54)
+ (name "~" (effects (font (size 0.762 0.762))))
+ (number "8" (effects (font (size 0.762 0.762))))
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+ (name "~" (effects (font (size 0.762 0.762))))
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+ (pin bidirectional line (at 6.35 0 180) (length 2.54)
+ (name "~" (effects (font (size 0.762 0.762))))
+ (number "12" (effects (font (size 0.762 0.762))))
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+ (pin bidirectional line (at 6.35 0 180) (length 2.54)
+ (name "~" (effects (font (size 0.762 0.762))))
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+ (pin bidirectional line (at 6.35 0 180) (length 2.54)
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+ (symbol "PORT_15_1"
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+ (number "15" (effects (font (size 0.762 0.762))))
+ )
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+ (pin "26" (uuid 1807f748-8372-49e6-9179-aef43c3ed8b0))
+ )
+
+ (sheet_instances
+ (path "/" (page "1"))
+ )
+
+ (symbol_instances
+ (path "/c7b032d2-169b-410c-990b-8fe967c51105"
+ (reference "U1") (unit 1) (value "PORT") (footprint "")
+ )
+ (path "/44d98705-aae9-42bb-836b-efccd1878405"
+ (reference "U1") (unit 2) (value "PORT") (footprint "")
+ )
+ (path "/c590854a-0f3c-4b10-86c6-ac029c90f006"
+ (reference "U1") (unit 3) (value "PORT") (footprint "")
+ )
+ (path "/fdf2dd7c-8344-4565-a8f7-fad0b1db6f1a"
+ (reference "U1") (unit 4) (value "PORT") (footprint "")
+ )
+ (path "/de89a214-6815-4c75-b42c-73ff90eee9b0"
+ (reference "U1") (unit 5) (value "PORT") (footprint "")
+ )
+ (path "/2f3dc900-0234-40ff-9316-cf18d1a046fa"
+ (reference "U1") (unit 6) (value "PORT") (footprint "")
+ )
+ (path "/f8200310-6aef-4adf-bfe0-7f46c17950c2"
+ (reference "U1") (unit 7) (value "PORT") (footprint "")
+ )
+ (path "/d199479a-8481-44be-9fa4-a7df163181d3"
+ (reference "U1") (unit 8) (value "PORT") (footprint "")
+ )
+ (path "/086145ca-0f27-4992-8106-2fccef104061"
+ (reference "U1") (unit 9) (value "PORT") (footprint "")
+ )
+ (path "/32f53de2-51c1-4246-9b86-389688d0098c"
+ (reference "U1") (unit 10) (value "PORT") (footprint "")
+ )
+ (path "/bfa016e5-7816-41da-8b2b-ec09e50f9635"
+ (reference "U1") (unit 11) (value "PORT") (footprint "")
+ )
+ (path "/ab9c4b77-a2ee-428a-958d-2ffe2342ddc5"
+ (reference "U1") (unit 12) (value "PORT") (footprint "")
+ )
+ (path "/56e033a1-da0b-46e6-b6a2-d69510630f6a"
+ (reference "U1") (unit 13) (value "PORT") (footprint "")
+ )
+ (path "/f576bcfa-cfac-4c91-91c9-e20aedda640a"
+ (reference "U1") (unit 14) (value "PORT") (footprint "")
+ )
+ (path "/6347f8b3-c46d-43c4-baba-dbf08ba6a3d1"
+ (reference "U1") (unit 15) (value "PORT") (footprint "")
+ )
+ (path "/040573e0-309a-4b67-9d05-506e6bf91c77"
+ (reference "U1") (unit 16) (value "PORT") (footprint "")
+ )
+ (path "/cdcddca5-37a4-452f-adfc-ad542ff54bc4"
+ (reference "U9") (unit 1) (value "d_inverter") (footprint "")
+ )
+ (path "/65af963d-1068-4775-86a2-e2af9964f0ce"
+ (reference "U10") (unit 1) (value "d_inverter") (footprint "")
+ )
+ (path "/66f0c021-4d94-4a4e-9a1d-38c1fdf41ff1"
+ (reference "U11") (unit 1) (value "d_inverter") (footprint "")
+ )
+ (path "/77bee57a-15bf-42e6-9d7f-9eb8a14d8e37"
+ (reference "U12") (unit 1) (value "d_inverter") (footprint "")
+ )
+ (path "/03a4a3f3-531d-4a88-93af-d9541be5ee6e"
+ (reference "U13") (unit 1) (value "d_inverter") (footprint "")
+ )
+ (path "/6e4860f6-d191-438f-92f5-e3823ab69b94"
+ (reference "U14") (unit 1) (value "d_inverter") (footprint "")
+ )
+ (path "/372088c8-4c77-4f9b-bc5c-575e77cc5bd8"
+ (reference "U15") (unit 1) (value "d_inverter") (footprint "")
+ )
+ (path "/e40168cf-c67e-4444-91d6-dba10731344b"
+ (reference "U16") (unit 1) (value "d_inverter") (footprint "")
+ )
+ (path "/823251ff-315b-475a-91df-2690edb63c66"
+ (reference "U17") (unit 1) (value "d_inverter") (footprint "")
+ )
+ (path "/5848ac52-16e9-4b45-a6ae-05698d5c1186"
+ (reference "U18") (unit 1) (value "d_inverter") (footprint "")
+ )
+ (path "/666e6994-6288-4347-8dde-b129c11e3f1e"
+ (reference "U19") (unit 1) (value "d_inverter") (footprint "")
+ )
+ (path "/de71a58c-5168-438b-abea-f268e1489bfe"
+ (reference "U20") (unit 1) (value "d_inverter") (footprint "")
+ )
+ (path "/8d97b963-a89b-4960-bec9-5fbb73076ff4"
+ (reference "U21") (unit 1) (value "d_inverter") (footprint "")
+ )
+ (path "/0f7b0a96-f7d9-4474-84ac-d7386e3464e2"
+ (reference "U22") (unit 1) (value "d_inverter") (footprint "")
+ )
+ (path "/7596d8df-b002-4f29-8f38-9227d96f207d"
+ (reference "U23") (unit 1) (value "d_inverter") (footprint "")
+ )
+ (path "/6c95b85a-3199-416c-8422-c55124086f82"
+ (reference "U24") (unit 1) (value "d_inverter") (footprint "")
+ )
+ (path "/daadae79-f22b-4732-a787-0e80c9da38e3"
+ (reference "U25") (unit 1) (value "d_inverter") (footprint "")
+ )
+ (path "/2a0753f9-7fef-4771-bf9d-1f015a4eb88c"
+ (reference "U26") (unit 1) (value "d_inverter") (footprint "")
+ )
+ (path "/a07f589a-43e6-4fc8-84cd-fb657db8ce34"
+ (reference "X1") (unit 1) (value "4_and") (footprint "")
+ )
+ (path "/d80e665d-91a1-4880-83dd-307b37d62907"
+ (reference "X2") (unit 1) (value "4_and") (footprint "")
+ )
+ (path "/32f306fc-c9fc-457f-b728-bf8063732b58"
+ (reference "X3") (unit 1) (value "4_and") (footprint "")
+ )
+ (path "/ed48be08-56a9-43bc-b5c5-2530bf7b320b"
+ (reference "X4") (unit 1) (value "4_and") (footprint "")
+ )
+ (path "/5c8b2c43-039f-4ab6-979a-39a8df7847f5"
+ (reference "X5") (unit 1) (value "4_and") (footprint "")
+ )
+ (path "/034dded4-572b-4217-8857-98a7b7249ad1"
+ (reference "X6") (unit 1) (value "4_and") (footprint "")
+ )
+ (path "/85f5736d-17aa-4b45-91e5-e68473aff809"
+ (reference "X7") (unit 1) (value "4_and") (footprint "")
+ )
+ (path "/f7cc2934-2c40-40d3-a1b9-6b8cf3ed3c7f"
+ (reference "X8") (unit 1) (value "4_and") (footprint "")
+ )
+ (path "/38d7159a-4c3a-4217-a8d7-a1c060dfb3d9"
+ (reference "X9") (unit 1) (value "4_and") (footprint "")
+ )
+ (path "/9fbb6764-dc9b-4155-9b1e-f14ccffb7655"
+ (reference "X10") (unit 1) (value "4_and") (footprint "")
+ )
+ )
+)
diff --git a/library/SubcircuitLibrary/SN74HC42/SN74HC42.sub b/library/SubcircuitLibrary/SN74HC42/SN74HC42.sub
new file mode 100644
index 000000000..859ad6857
--- /dev/null
+++ b/library/SubcircuitLibrary/SN74HC42/SN74HC42.sub
@@ -0,0 +1,89 @@
+* Subcircuit SN74HC42
+.subckt SN74HC42 net-_u17-pad2_ net-_u18-pad2_ net-_u19-pad2_ net-_u20-pad2_ net-_u21-pad2_ net-_u22-pad2_ net-_u23-pad2_ unconnected-_u1-pad8_ net-_u24-pad2_ net-_u25-pad2_ net-_u26-pad2_ net-_u12-pad1_ net-_u11-pad1_ net-_u10-pad1_ net-_u9-pad1_ unconnected-_u1-pad16_
+.title kicad schematic
+.include 4_and.sub
+x1 net-_u13-pad1_ net-_u10-pad2_ net-_u11-pad2_ net-_u12-pad2_ net-_u17-pad1_ 4_and
+x3 net-_u13-pad1_ net-_u14-pad2_ net-_u11-pad2_ net-_u12-pad2_ net-_u19-pad1_ 4_and
+x2 net-_u13-pad2_ net-_u10-pad2_ net-_u11-pad2_ net-_u12-pad2_ net-_u18-pad1_ 4_and
+* u17 net-_u17-pad1_ net-_u17-pad2_ d_inverter
+* u18 net-_u18-pad1_ net-_u18-pad2_ d_inverter
+* u21 net-_u21-pad1_ net-_u21-pad2_ d_inverter
+* u22 net-_u22-pad1_ net-_u22-pad2_ d_inverter
+* u25 net-_u25-pad1_ net-_u25-pad2_ d_inverter
+* u26 net-_u26-pad1_ net-_u26-pad2_ d_inverter
+x10 net-_u13-pad2_ net-_u10-pad2_ net-_u11-pad2_ net-_u16-pad2_ net-_u26-pad1_ 4_and
+x9 net-_u13-pad1_ net-_u10-pad2_ net-_u11-pad2_ net-_u16-pad2_ net-_u25-pad1_ 4_and
+x8 net-_u13-pad2_ net-_u14-pad2_ net-_x5-pad3_ net-_u12-pad2_ net-_u24-pad1_ 4_and
+* u23 net-_u23-pad1_ net-_u23-pad2_ d_inverter
+* u24 net-_u24-pad1_ net-_u24-pad2_ d_inverter
+x4 net-_u13-pad2_ net-_u14-pad2_ net-_u11-pad2_ net-_u12-pad2_ net-_u20-pad1_ 4_and
+* u20 net-_u20-pad1_ net-_u20-pad2_ d_inverter
+* u19 net-_u19-pad1_ net-_u19-pad2_ d_inverter
+x6 net-_u13-pad2_ net-_u10-pad2_ net-_x5-pad3_ net-_u12-pad2_ net-_u22-pad1_ 4_and
+x7 net-_u13-pad1_ net-_u14-pad2_ net-_x5-pad3_ net-_u12-pad2_ net-_u23-pad1_ 4_and
+x5 net-_u13-pad1_ net-_u10-pad2_ net-_x5-pad3_ net-_u12-pad2_ net-_u21-pad1_ 4_and
+* u13 net-_u13-pad1_ net-_u13-pad2_ d_inverter
+* u10 net-_u10-pad1_ net-_u10-pad2_ d_inverter
+* u14 net-_u10-pad2_ net-_u14-pad2_ d_inverter
+* u9 net-_u9-pad1_ net-_u13-pad1_ d_inverter
+* u15 net-_u11-pad2_ net-_u11-pad2_ d_inverter
+* u16 net-_u12-pad2_ net-_u16-pad2_ d_inverter
+* u11 net-_u11-pad1_ net-_u11-pad2_ d_inverter
+* u12 net-_u12-pad1_ net-_u12-pad2_ d_inverter
+a1 net-_u17-pad1_ net-_u17-pad2_ u17
+a2 net-_u18-pad1_ net-_u18-pad2_ u18
+a3 net-_u21-pad1_ net-_u21-pad2_ u21
+a4 net-_u22-pad1_ net-_u22-pad2_ u22
+a5 net-_u25-pad1_ net-_u25-pad2_ u25
+a6 net-_u26-pad1_ net-_u26-pad2_ u26
+a7 net-_u23-pad1_ net-_u23-pad2_ u23
+a8 net-_u24-pad1_ net-_u24-pad2_ u24
+a9 net-_u20-pad1_ net-_u20-pad2_ u20
+a10 net-_u19-pad1_ net-_u19-pad2_ u19
+a11 net-_u13-pad1_ net-_u13-pad2_ u13
+a12 net-_u10-pad1_ net-_u10-pad2_ u10
+a13 net-_u10-pad2_ net-_u14-pad2_ u14
+a14 net-_u9-pad1_ net-_u13-pad1_ u9
+a15 net-_u11-pad2_ net-_u11-pad2_ u15
+a16 net-_u12-pad2_ net-_u16-pad2_ u16
+a17 net-_u11-pad1_ net-_u11-pad2_ u11
+a18 net-_u12-pad1_ net-_u12-pad2_ u12
+* Schematic Name: d_inverter, Ngspice Name: d_inverter
+.model u17 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, Ngspice Name: d_inverter
+.model u18 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, Ngspice Name: d_inverter
+.model u21 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, Ngspice Name: d_inverter
+.model u22 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, Ngspice Name: d_inverter
+.model u25 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, Ngspice Name: d_inverter
+.model u26 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, Ngspice Name: d_inverter
+.model u23 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, Ngspice Name: d_inverter
+.model u24 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, Ngspice Name: d_inverter
+.model u20 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, Ngspice Name: d_inverter
+.model u19 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, Ngspice Name: d_inverter
+.model u13 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, Ngspice Name: d_inverter
+.model u10 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, Ngspice Name: d_inverter
+.model u14 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, Ngspice Name: d_inverter
+.model u9 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, Ngspice Name: d_inverter
+.model u15 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, Ngspice Name: d_inverter
+.model u16 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, Ngspice Name: d_inverter
+.model u11 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, Ngspice Name: d_inverter
+.model u12 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Control Statements
+
+.ends SN74HC42
\ No newline at end of file
diff --git a/library/SubcircuitLibrary/SN74HC42/SN74HC42_Previous_Values.xml b/library/SubcircuitLibrary/SN74HC42/SN74HC42_Previous_Values.xml
new file mode 100644
index 000000000..f04b442a0
--- /dev/null
+++ b/library/SubcircuitLibrary/SN74HC42/SN74HC42_Previous_Values.xml
@@ -0,0 +1 @@
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diff --git a/library/SubcircuitLibrary/SN74HC42/_autosave-SN74HC42.sch b/library/SubcircuitLibrary/SN74HC42/_autosave-SN74HC42.sch
new file mode 100644
index 000000000..f4a0a4109
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+F 1 "4_and" H 14303 12150 60 0000 C CNN
+F 2 "" H 14250 11900 60 0000 C CNN
+F 3 "" H 14250 11900 60 0000 C CNN
+ 1 14250 11900
+ 1 0 0 -1
+$EndComp
+$EndSCHEMATC
diff --git a/library/SubcircuitLibrary/SN74HC42/analysis b/library/SubcircuitLibrary/SN74HC42/analysis
new file mode 100644
index 000000000..ebd5c0a94
--- /dev/null
+++ b/library/SubcircuitLibrary/SN74HC42/analysis
@@ -0,0 +1 @@
+.tran 0e-00 0e-00 0e-00
\ No newline at end of file
diff --git a/library/SubcircuitLibrary/SN74HC541/SN74HC541.cir b/library/SubcircuitLibrary/SN74HC541/SN74HC541.cir
new file mode 100644
index 000000000..47c285699
--- /dev/null
+++ b/library/SubcircuitLibrary/SN74HC541/SN74HC541.cir
@@ -0,0 +1,14 @@
+.title KiCad schematic
+U1 Net-_U10-Pad1_ Net-_U13-Pad1_ Net-_U14-Pad1_ Net-_U15-Pad1_ Net-_U16-Pad1_ Net-_U17-Pad1_ Net-_U18-Pad1_ Net-_U19-Pad1_ Net-_U20-Pad1_ unconnected-_U1-Pad10_ Net-_U20-Pad3_ Net-_U19-Pad3_ Net-_U18-Pad3_ Net-_U17-Pad3_ Net-_U16-Pad3_ Net-_U15-Pad3_ Net-_U14-Pad3_ Net-_U13-Pad3_ Net-_U11-Pad1_ unconnected-_U1-Pad20_ PORT
+U12 Net-_U10-Pad2_ Net-_U11-Pad2_ Net-_U12-Pad3_ d_and
+U10 Net-_U10-Pad1_ Net-_U10-Pad2_ d_inverter
+U11 Net-_U11-Pad1_ Net-_U11-Pad2_ d_inverter
+U16 Net-_U16-Pad1_ Net-_U12-Pad3_ Net-_U16-Pad3_ d_tristate
+U15 Net-_U15-Pad1_ Net-_U12-Pad3_ Net-_U15-Pad3_ d_tristate
+U13 Net-_U13-Pad1_ Net-_U12-Pad3_ Net-_U13-Pad3_ d_tristate
+U14 Net-_U14-Pad1_ Net-_U12-Pad3_ Net-_U14-Pad3_ d_tristate
+U17 Net-_U17-Pad1_ Net-_U12-Pad3_ Net-_U17-Pad3_ d_tristate
+U20 Net-_U20-Pad1_ Net-_U12-Pad3_ Net-_U20-Pad3_ d_tristate
+U19 Net-_U19-Pad1_ Net-_U12-Pad3_ Net-_U19-Pad3_ d_tristate
+U18 Net-_U18-Pad1_ Net-_U12-Pad3_ Net-_U18-Pad3_ d_tristate
+.end
diff --git a/library/SubcircuitLibrary/SN74HC541/SN74HC541.cir.out b/library/SubcircuitLibrary/SN74HC541/SN74HC541.cir.out
new file mode 100644
index 000000000..302f6b82d
--- /dev/null
+++ b/library/SubcircuitLibrary/SN74HC541/SN74HC541.cir.out
@@ -0,0 +1,56 @@
+.title kicad schematic
+
+* u1 net-_u10-pad1_ net-_u13-pad1_ net-_u14-pad1_ net-_u15-pad1_ net-_u16-pad1_ net-_u17-pad1_ net-_u18-pad1_ net-_u19-pad1_ net-_u20-pad1_ unconnected-_u1-pad10_ net-_u20-pad3_ net-_u19-pad3_ net-_u18-pad3_ net-_u17-pad3_ net-_u16-pad3_ net-_u15-pad3_ net-_u14-pad3_ net-_u13-pad3_ net-_u11-pad1_ unconnected-_u1-pad20_ port
+* u12 net-_u10-pad2_ net-_u11-pad2_ net-_u12-pad3_ d_and
+* u10 net-_u10-pad1_ net-_u10-pad2_ d_inverter
+* u11 net-_u11-pad1_ net-_u11-pad2_ d_inverter
+* u16 net-_u16-pad1_ net-_u12-pad3_ net-_u16-pad3_ d_tristate
+* u15 net-_u15-pad1_ net-_u12-pad3_ net-_u15-pad3_ d_tristate
+* u13 net-_u13-pad1_ net-_u12-pad3_ net-_u13-pad3_ d_tristate
+* u14 net-_u14-pad1_ net-_u12-pad3_ net-_u14-pad3_ d_tristate
+* u17 net-_u17-pad1_ net-_u12-pad3_ net-_u17-pad3_ d_tristate
+* u20 net-_u20-pad1_ net-_u12-pad3_ net-_u20-pad3_ d_tristate
+* u19 net-_u19-pad1_ net-_u12-pad3_ net-_u19-pad3_ d_tristate
+* u18 net-_u18-pad1_ net-_u12-pad3_ net-_u18-pad3_ d_tristate
+a1 [net-_u10-pad2_ net-_u11-pad2_ ] net-_u12-pad3_ u12
+a2 net-_u10-pad1_ net-_u10-pad2_ u10
+a3 net-_u11-pad1_ net-_u11-pad2_ u11
+a4 net-_u16-pad1_ net-_u12-pad3_ net-_u16-pad3_ u16
+a5 net-_u15-pad1_ net-_u12-pad3_ net-_u15-pad3_ u15
+a6 net-_u13-pad1_ net-_u12-pad3_ net-_u13-pad3_ u13
+a7 net-_u14-pad1_ net-_u12-pad3_ net-_u14-pad3_ u14
+a8 net-_u17-pad1_ net-_u12-pad3_ net-_u17-pad3_ u17
+a9 net-_u20-pad1_ net-_u12-pad3_ net-_u20-pad3_ u20
+a10 net-_u19-pad1_ net-_u12-pad3_ net-_u19-pad3_ u19
+a11 net-_u18-pad1_ net-_u12-pad3_ net-_u18-pad3_ u18
+* Schematic Name: d_and, Ngspice Name: d_and
+.model u12 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, Ngspice Name: d_inverter
+.model u10 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, Ngspice Name: d_inverter
+.model u11 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_tristate, Ngspice Name: d_tristate
+.model u16 d_tristate(delay=1.0e-9 input_load=1.0e-12 enable_load=1.0e-12 )
+* Schematic Name: d_tristate, Ngspice Name: d_tristate
+.model u15 d_tristate(delay=1.0e-9 input_load=1.0e-12 enable_load=1.0e-12 )
+* Schematic Name: d_tristate, Ngspice Name: d_tristate
+.model u13 d_tristate(delay=1.0e-9 input_load=1.0e-12 enable_load=1.0e-12 )
+* Schematic Name: d_tristate, Ngspice Name: d_tristate
+.model u14 d_tristate(delay=1.0e-9 input_load=1.0e-12 enable_load=1.0e-12 )
+* Schematic Name: d_tristate, Ngspice Name: d_tristate
+.model u17 d_tristate(delay=1.0e-9 input_load=1.0e-12 enable_load=1.0e-12 )
+* Schematic Name: d_tristate, Ngspice Name: d_tristate
+.model u20 d_tristate(delay=1.0e-9 input_load=1.0e-12 enable_load=1.0e-12 )
+* Schematic Name: d_tristate, Ngspice Name: d_tristate
+.model u19 d_tristate(delay=1.0e-9 input_load=1.0e-12 enable_load=1.0e-12 )
+* Schematic Name: d_tristate, Ngspice Name: d_tristate
+.model u18 d_tristate(delay=1.0e-9 input_load=1.0e-12 enable_load=1.0e-12 )
+.tran 0e-00 0e-00 0e-00
+
+* Control Statements
+.control
+run
+print allv > plot_data_v.txt
+print alli > plot_data_i.txt
+.endc
+.end
diff --git a/library/SubcircuitLibrary/SN74HC541/SN74HC541.kicad_sch b/library/SubcircuitLibrary/SN74HC541/SN74HC541.kicad_sch
new file mode 100644
index 000000000..d6c3c285f
--- /dev/null
+++ b/library/SubcircuitLibrary/SN74HC541/SN74HC541.kicad_sch
@@ -0,0 +1,1693 @@
+(kicad_sch (version 20211123) (generator eeschema)
+
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+ (reference "U12") (unit 1) (value "d_and") (footprint "")
+ )
+ (path "/f814fb79-5f9a-42e4-8336-dca9f9be5576"
+ (reference "U13") (unit 1) (value "d_tristate") (footprint "")
+ )
+ (path "/99d1f53d-1bae-495c-95d4-34df10ab3041"
+ (reference "U14") (unit 1) (value "d_tristate") (footprint "")
+ )
+ (path "/d69a406d-c7d2-4ff7-b9a7-e30c79b3000a"
+ (reference "U15") (unit 1) (value "d_tristate") (footprint "")
+ )
+ (path "/d4a02ae9-0757-4500-adb9-e76d9e8527ef"
+ (reference "U16") (unit 1) (value "d_tristate") (footprint "")
+ )
+ (path "/c2e3aa96-736d-4a21-ac0e-a00968b04d0f"
+ (reference "U17") (unit 1) (value "d_tristate") (footprint "")
+ )
+ (path "/a2420de4-2fe8-48a1-95c9-0f18ca2647c4"
+ (reference "U18") (unit 1) (value "d_tristate") (footprint "")
+ )
+ (path "/b464a4be-6238-4ffc-8f4b-e0973b92cd99"
+ (reference "U19") (unit 1) (value "d_tristate") (footprint "")
+ )
+ (path "/bdf0b392-f2a0-4017-86b7-03ba4f9eb8b8"
+ (reference "U20") (unit 1) (value "d_tristate") (footprint "")
+ )
+ )
+)
diff --git a/library/SubcircuitLibrary/SN74HC541/SN74HC541.sub b/library/SubcircuitLibrary/SN74HC541/SN74HC541.sub
new file mode 100644
index 000000000..1314eea32
--- /dev/null
+++ b/library/SubcircuitLibrary/SN74HC541/SN74HC541.sub
@@ -0,0 +1,50 @@
+* Subcircuit SN74HC541
+.subckt SN74HC541 net-_u10-pad1_ net-_u13-pad1_ net-_u14-pad1_ net-_u15-pad1_ net-_u16-pad1_ net-_u17-pad1_ net-_u18-pad1_ net-_u19-pad1_ net-_u20-pad1_ unconnected-_u1-pad10_ net-_u20-pad3_ net-_u19-pad3_ net-_u18-pad3_ net-_u17-pad3_ net-_u16-pad3_ net-_u15-pad3_ net-_u14-pad3_ net-_u13-pad3_ net-_u11-pad1_ unconnected-_u1-pad20_
+.title kicad schematic
+* u12 net-_u10-pad2_ net-_u11-pad2_ net-_u12-pad3_ d_and
+* u10 net-_u10-pad1_ net-_u10-pad2_ d_inverter
+* u11 net-_u11-pad1_ net-_u11-pad2_ d_inverter
+* u16 net-_u16-pad1_ net-_u12-pad3_ net-_u16-pad3_ d_tristate
+* u15 net-_u15-pad1_ net-_u12-pad3_ net-_u15-pad3_ d_tristate
+* u13 net-_u13-pad1_ net-_u12-pad3_ net-_u13-pad3_ d_tristate
+* u14 net-_u14-pad1_ net-_u12-pad3_ net-_u14-pad3_ d_tristate
+* u17 net-_u17-pad1_ net-_u12-pad3_ net-_u17-pad3_ d_tristate
+* u20 net-_u20-pad1_ net-_u12-pad3_ net-_u20-pad3_ d_tristate
+* u19 net-_u19-pad1_ net-_u12-pad3_ net-_u19-pad3_ d_tristate
+* u18 net-_u18-pad1_ net-_u12-pad3_ net-_u18-pad3_ d_tristate
+a1 [net-_u10-pad2_ net-_u11-pad2_ ] net-_u12-pad3_ u12
+a2 net-_u10-pad1_ net-_u10-pad2_ u10
+a3 net-_u11-pad1_ net-_u11-pad2_ u11
+a4 net-_u16-pad1_ net-_u12-pad3_ net-_u16-pad3_ u16
+a5 net-_u15-pad1_ net-_u12-pad3_ net-_u15-pad3_ u15
+a6 net-_u13-pad1_ net-_u12-pad3_ net-_u13-pad3_ u13
+a7 net-_u14-pad1_ net-_u12-pad3_ net-_u14-pad3_ u14
+a8 net-_u17-pad1_ net-_u12-pad3_ net-_u17-pad3_ u17
+a9 net-_u20-pad1_ net-_u12-pad3_ net-_u20-pad3_ u20
+a10 net-_u19-pad1_ net-_u12-pad3_ net-_u19-pad3_ u19
+a11 net-_u18-pad1_ net-_u12-pad3_ net-_u18-pad3_ u18
+* Schematic Name: d_and, Ngspice Name: d_and
+.model u12 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, Ngspice Name: d_inverter
+.model u10 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, Ngspice Name: d_inverter
+.model u11 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_tristate, Ngspice Name: d_tristate
+.model u16 d_tristate(delay=1.0e-9 input_load=1.0e-12 enable_load=1.0e-12 )
+* Schematic Name: d_tristate, Ngspice Name: d_tristate
+.model u15 d_tristate(delay=1.0e-9 input_load=1.0e-12 enable_load=1.0e-12 )
+* Schematic Name: d_tristate, Ngspice Name: d_tristate
+.model u13 d_tristate(delay=1.0e-9 input_load=1.0e-12 enable_load=1.0e-12 )
+* Schematic Name: d_tristate, Ngspice Name: d_tristate
+.model u14 d_tristate(delay=1.0e-9 input_load=1.0e-12 enable_load=1.0e-12 )
+* Schematic Name: d_tristate, Ngspice Name: d_tristate
+.model u17 d_tristate(delay=1.0e-9 input_load=1.0e-12 enable_load=1.0e-12 )
+* Schematic Name: d_tristate, Ngspice Name: d_tristate
+.model u20 d_tristate(delay=1.0e-9 input_load=1.0e-12 enable_load=1.0e-12 )
+* Schematic Name: d_tristate, Ngspice Name: d_tristate
+.model u19 d_tristate(delay=1.0e-9 input_load=1.0e-12 enable_load=1.0e-12 )
+* Schematic Name: d_tristate, Ngspice Name: d_tristate
+.model u18 d_tristate(delay=1.0e-9 input_load=1.0e-12 enable_load=1.0e-12 )
+* Control Statements
+
+.ends SN74HC541
\ No newline at end of file
diff --git a/library/SubcircuitLibrary/SN74HC541/SN74HC541_Previous_Values.xml b/library/SubcircuitLibrary/SN74HC541/SN74HC541_Previous_Values.xml
new file mode 100644
index 000000000..3e521ba77
--- /dev/null
+++ b/library/SubcircuitLibrary/SN74HC541/SN74HC541_Previous_Values.xml
@@ -0,0 +1 @@
+truefalsefalseHzHz0Volts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or Amperessecsecsecd_andd_inverterd_inverterd_tristated_tristated_tristated_tristated_tristated_tristated_tristated_tristate
\ No newline at end of file
diff --git a/library/SubcircuitLibrary/SN74HC541/_autosave-SN74HC541.sch b/library/SubcircuitLibrary/SN74HC541/_autosave-SN74HC541.sch
new file mode 100644
index 000000000..d0d719bae
--- /dev/null
+++ b/library/SubcircuitLibrary/SN74HC541/_autosave-SN74HC541.sch
@@ -0,0 +1,457 @@
+EESchema Schematic File Version 5
+EELAYER 36 0
+EELAYER END
+$Descr A2 23386 16535
+encoding utf-8
+Sheet 1 1
+Title ""
+Date ""
+Rev ""
+Comp ""
+Comment1 ""
+Comment2 ""
+Comment3 ""
+Comment4 ""
+Comment5 ""
+Comment6 ""
+Comment7 ""
+Comment8 ""
+Comment9 ""
+$EndDescr
+Connection ~ 12600 3400
+Connection ~ 12600 4500
+Connection ~ 12600 5550
+Connection ~ 12600 6600
+Connection ~ 12600 7650
+Connection ~ 12600 8750
+Connection ~ 12600 9800
+NoConn ~ 15400 11100
+NoConn ~ 15400 11400
+Wire Wire Line
+ 7900 2750 13300 2750
+Wire Wire Line
+ 7900 3800 13300 3800
+Wire Wire Line
+ 7900 4900 13300 4900
+Wire Wire Line
+ 7900 5950 13300 5950
+Wire Wire Line
+ 7900 7000 13300 7000
+Wire Wire Line
+ 7900 8050 13300 8050
+Wire Wire Line
+ 7900 9150 13300 9150
+Wire Wire Line
+ 7900 10200 13300 10200
+Wire Wire Line
+ 7900 11450 9850 11450
+Wire Wire Line
+ 7900 11550 9850 11550
+Wire Wire Line
+ 11350 11500 12600 11500
+Wire Wire Line
+ 12600 2350 13850 2350
+Wire Wire Line
+ 12600 3400 12600 2350
+Wire Wire Line
+ 12600 4500 12600 3400
+Wire Wire Line
+ 12600 5550 12600 4500
+Wire Wire Line
+ 12600 6600 12600 5550
+Wire Wire Line
+ 12600 7650 12600 6600
+Wire Wire Line
+ 12600 8750 12600 7650
+Wire Wire Line
+ 12600 9800 12600 8750
+Wire Wire Line
+ 12600 11500 12600 9800
+Wire Wire Line
+ 13850 2350 13850 2450
+Wire Wire Line
+ 13850 3400 12600 3400
+Wire Wire Line
+ 13850 3500 13850 3400
+Wire Wire Line
+ 13850 4500 12600 4500
+Wire Wire Line
+ 13850 4600 13850 4500
+Wire Wire Line
+ 13850 5550 12600 5550
+Wire Wire Line
+ 13850 5650 13850 5550
+Wire Wire Line
+ 13850 6600 12600 6600
+Wire Wire Line
+ 13850 6700 13850 6600
+Wire Wire Line
+ 13850 7650 12600 7650
+Wire Wire Line
+ 13850 7750 13850 7650
+Wire Wire Line
+ 13850 8750 12600 8750
+Wire Wire Line
+ 13850 8850 13850 8750
+Wire Wire Line
+ 13850 9800 12600 9800
+Wire Wire Line
+ 13850 9900 13850 9800
+Wire Wire Line
+ 14450 2750 15550 2750
+Wire Wire Line
+ 14450 3800 15550 3800
+Wire Wire Line
+ 14450 4900 15550 4900
+Wire Wire Line
+ 14450 5950 15550 5950
+Wire Wire Line
+ 14450 7000 15550 7000
+Wire Wire Line
+ 14450 8050 15550 8050
+Wire Wire Line
+ 14450 9150 15550 9150
+Wire Wire Line
+ 14450 10200 15550 10200
+$Comp
+L eSim_Miscellaneous:PORT U1
+U 2 1 00000000
+P 7650 2750
+F 0 "U1" H 7675 2950 30 0000 C CNN
+F 1 "PORT" H 7675 2850 30 0000 C CNN
+F 2 "" H 7650 2750 60 0000 C CNN
+F 3 "" H 7650 2750 60 0000 C CNN
+ 2 7650 2750
+ 1 0 0 -1
+$EndComp
+$Comp
+L eSim_Miscellaneous:PORT U1
+U 3 1 00000000
+P 7650 3800
+F 0 "U1" H 7675 4000 30 0000 C CNN
+F 1 "PORT" H 7675 3900 30 0000 C CNN
+F 2 "" H 7650 3800 60 0000 C CNN
+F 3 "" H 7650 3800 60 0000 C CNN
+ 3 7650 3800
+ 1 0 0 -1
+$EndComp
+$Comp
+L eSim_Miscellaneous:PORT U1
+U 4 1 00000000
+P 7650 4900
+F 0 "U1" H 7675 5100 30 0000 C CNN
+F 1 "PORT" H 7675 5000 30 0000 C CNN
+F 2 "" H 7650 4900 60 0000 C CNN
+F 3 "" H 7650 4900 60 0000 C CNN
+ 4 7650 4900
+ 1 0 0 -1
+$EndComp
+$Comp
+L eSim_Miscellaneous:PORT U1
+U 5 1 00000000
+P 7650 5950
+F 0 "U1" H 7675 6150 30 0000 C CNN
+F 1 "PORT" H 7675 6050 30 0000 C CNN
+F 2 "" H 7650 5950 60 0000 C CNN
+F 3 "" H 7650 5950 60 0000 C CNN
+ 5 7650 5950
+ 1 0 0 -1
+$EndComp
+$Comp
+L eSim_Miscellaneous:PORT U1
+U 6 1 00000000
+P 7650 7000
+F 0 "U1" H 7675 7200 30 0000 C CNN
+F 1 "PORT" H 7675 7100 30 0000 C CNN
+F 2 "" H 7650 7000 60 0000 C CNN
+F 3 "" H 7650 7000 60 0000 C CNN
+ 6 7650 7000
+ 1 0 0 -1
+$EndComp
+$Comp
+L eSim_Miscellaneous:PORT U1
+U 7 1 00000000
+P 7650 8050
+F 0 "U1" H 7675 8250 30 0000 C CNN
+F 1 "PORT" H 7675 8150 30 0000 C CNN
+F 2 "" H 7650 8050 60 0000 C CNN
+F 3 "" H 7650 8050 60 0000 C CNN
+ 7 7650 8050
+ 1 0 0 -1
+$EndComp
+$Comp
+L eSim_Miscellaneous:PORT U1
+U 8 1 00000000
+P 7650 9150
+F 0 "U1" H 7675 9350 30 0000 C CNN
+F 1 "PORT" H 7675 9250 30 0000 C CNN
+F 2 "" H 7650 9150 60 0000 C CNN
+F 3 "" H 7650 9150 60 0000 C CNN
+ 8 7650 9150
+ 1 0 0 -1
+$EndComp
+$Comp
+L eSim_Miscellaneous:PORT U1
+U 9 1 00000000
+P 7650 10200
+F 0 "U1" H 7675 10400 30 0000 C CNN
+F 1 "PORT" H 7675 10300 30 0000 C CNN
+F 2 "" H 7650 10200 60 0000 C CNN
+F 3 "" H 7650 10200 60 0000 C CNN
+ 9 7650 10200
+ 1 0 0 -1
+$EndComp
+$Comp
+L eSim_Miscellaneous:PORT U1
+U 1 1 00000000
+P 7650 11450
+F 0 "U1" H 7675 11650 30 0000 C CNN
+F 1 "PORT" H 7675 11550 30 0000 C CNN
+F 2 "" H 7650 11450 60 0000 C CNN
+F 3 "" H 7650 11450 60 0000 C CNN
+ 1 7650 11450
+ 1 0 0 -1
+$EndComp
+$Comp
+L eSim_Miscellaneous:PORT U1
+U 19 1 00000000
+P 7650 11550
+F 0 "U1" H 7675 11750 30 0000 C CNN
+F 1 "PORT" H 7675 11650 30 0000 C CNN
+F 2 "" H 7650 11550 60 0000 C CNN
+F 3 "" H 7650 11550 60 0000 C CNN
+ 19 7650 11550
+ 1 0 0 -1
+$EndComp
+$Comp
+L eSim_Miscellaneous:PORT U1
+U 10 1 00000000
+P 15150 11100
+F 0 "U1" H 15175 11300 30 0000 C CNN
+F 1 "PORT" H 15175 11200 30 0000 C CNN
+F 2 "" H 15150 11100 60 0000 C CNN
+F 3 "" H 15150 11100 60 0000 C CNN
+ 10 15150 11100
+ 1 0 0 -1
+$EndComp
+$Comp
+L eSim_Miscellaneous:PORT U1
+U 20 1 00000000
+P 15150 11400
+F 0 "U1" H 15175 11600 30 0000 C CNN
+F 1 "PORT" H 15175 11500 30 0000 C CNN
+F 2 "" H 15150 11400 60 0000 C CNN
+F 3 "" H 15150 11400 60 0000 C CNN
+ 20 15150 11400
+ 1 0 0 -1
+$EndComp
+$Comp
+L eSim_Miscellaneous:PORT U1
+U 18 1 00000000
+P 15800 2750
+F 0 "U1" H 15650 2725 30 0000 R CNN
+F 1 "PORT" H 15650 2825 30 0000 R CNN
+F 2 "" H 15800 2750 60 0000 C CNN
+F 3 "" H 15800 2750 60 0000 C CNN
+ 18 15800 2750
+ -1 0 0 1
+$EndComp
+$Comp
+L eSim_Miscellaneous:PORT U1
+U 17 1 00000000
+P 15800 3800
+F 0 "U1" H 15650 3775 30 0000 R CNN
+F 1 "PORT" H 15650 3875 30 0000 R CNN
+F 2 "" H 15800 3800 60 0000 C CNN
+F 3 "" H 15800 3800 60 0000 C CNN
+ 17 15800 3800
+ -1 0 0 1
+$EndComp
+$Comp
+L eSim_Miscellaneous:PORT U1
+U 16 1 00000000
+P 15800 4900
+F 0 "U1" H 15650 4875 30 0000 R CNN
+F 1 "PORT" H 15650 4975 30 0000 R CNN
+F 2 "" H 15800 4900 60 0000 C CNN
+F 3 "" H 15800 4900 60 0000 C CNN
+ 16 15800 4900
+ -1 0 0 1
+$EndComp
+$Comp
+L eSim_Miscellaneous:PORT U1
+U 15 1 00000000
+P 15800 5950
+F 0 "U1" H 15650 5925 30 0000 R CNN
+F 1 "PORT" H 15650 6025 30 0000 R CNN
+F 2 "" H 15800 5950 60 0000 C CNN
+F 3 "" H 15800 5950 60 0000 C CNN
+ 15 15800 5950
+ -1 0 0 1
+$EndComp
+$Comp
+L eSim_Miscellaneous:PORT U1
+U 14 1 00000000
+P 15800 7000
+F 0 "U1" H 15650 6975 30 0000 R CNN
+F 1 "PORT" H 15650 7075 30 0000 R CNN
+F 2 "" H 15800 7000 60 0000 C CNN
+F 3 "" H 15800 7000 60 0000 C CNN
+ 14 15800 7000
+ -1 0 0 1
+$EndComp
+$Comp
+L eSim_Miscellaneous:PORT U1
+U 13 1 00000000
+P 15800 8050
+F 0 "U1" H 15650 8025 30 0000 R CNN
+F 1 "PORT" H 15650 8125 30 0000 R CNN
+F 2 "" H 15800 8050 60 0000 C CNN
+F 3 "" H 15800 8050 60 0000 C CNN
+ 13 15800 8050
+ -1 0 0 1
+$EndComp
+$Comp
+L eSim_Miscellaneous:PORT U1
+U 12 1 00000000
+P 15800 9150
+F 0 "U1" H 15650 9125 30 0000 R CNN
+F 1 "PORT" H 15650 9225 30 0000 R CNN
+F 2 "" H 15800 9150 60 0000 C CNN
+F 3 "" H 15800 9150 60 0000 C CNN
+ 12 15800 9150
+ -1 0 0 1
+$EndComp
+$Comp
+L eSim_Miscellaneous:PORT U1
+U 11 1 00000000
+P 15800 10200
+F 0 "U1" H 15650 10175 30 0000 R CNN
+F 1 "PORT" H 15650 10275 30 0000 R CNN
+F 2 "" H 15800 10200 60 0000 C CNN
+F 3 "" H 15800 10200 60 0000 C CNN
+ 11 15800 10200
+ -1 0 0 1
+$EndComp
+$Comp
+L eSim_Digital:d_inverter U10
+U 1 1 00000000
+P 10150 11450
+F 0 "U10" H 10150 11700 60 0000 C CNN
+F 1 "d_inverter" H 10150 11550 60 0000 C CNN
+F 2 "" H 10200 11400 60 0000 C CNN
+F 3 "" H 10200 11400 60 0000 C CNN
+ 1 10150 11450
+ 1 0 0 -1
+$EndComp
+$Comp
+L eSim_Digital:d_inverter U11
+U 1 1 00000000
+P 10150 11550
+F 0 "U11" H 10150 11800 60 0000 C CNN
+F 1 "d_inverter" H 10150 11650 60 0000 C CNN
+F 2 "" H 10200 11500 60 0000 C CNN
+F 3 "" H 10200 11500 60 0000 C CNN
+ 1 10150 11550
+ 1 0 0 -1
+$EndComp
+$Comp
+L eSim_Digital:d_and U12
+U 1 1 00000000
+P 10900 11550
+F 0 "U12" H 10900 11900 60 0000 C CNN
+F 1 "d_and" H 10900 11750 60 0000 C CNN
+F 2 "" H 10900 11550 60 0000 C CNN
+F 3 "" H 10900 11550 60 0000 C CNN
+ 1 10900 11550
+ 1 0 0 -1
+$EndComp
+$Comp
+L eSim_Digital:d_tristate U13
+U 1 1 00000000
+P 13900 2400
+F 0 "U13" H 13875 3050 60 0000 C CNN
+F 1 "d_tristate" H 13875 3200 60 0000 C CNN
+F 2 "" H 13800 2750 60 0000 C CNN
+F 3 "" H 13800 2750 60 0000 C CNN
+ 1 13900 2400
+ 1 0 0 1
+$EndComp
+$Comp
+L eSim_Digital:d_tristate U14
+U 1 1 00000000
+P 13900 3450
+F 0 "U14" H 13875 4100 60 0000 C CNN
+F 1 "d_tristate" H 13875 4250 60 0000 C CNN
+F 2 "" H 13800 3800 60 0000 C CNN
+F 3 "" H 13800 3800 60 0000 C CNN
+ 1 13900 3450
+ 1 0 0 1
+$EndComp
+$Comp
+L eSim_Digital:d_tristate U15
+U 1 1 00000000
+P 13900 4550
+F 0 "U15" H 13875 5200 60 0000 C CNN
+F 1 "d_tristate" H 13875 5350 60 0000 C CNN
+F 2 "" H 13800 4900 60 0000 C CNN
+F 3 "" H 13800 4900 60 0000 C CNN
+ 1 13900 4550
+ 1 0 0 1
+$EndComp
+$Comp
+L eSim_Digital:d_tristate U16
+U 1 1 00000000
+P 13900 5600
+F 0 "U16" H 13875 6250 60 0000 C CNN
+F 1 "d_tristate" H 13875 6400 60 0000 C CNN
+F 2 "" H 13800 5950 60 0000 C CNN
+F 3 "" H 13800 5950 60 0000 C CNN
+ 1 13900 5600
+ 1 0 0 1
+$EndComp
+$Comp
+L eSim_Digital:d_tristate U17
+U 1 1 00000000
+P 13900 6650
+F 0 "U17" H 13875 7300 60 0000 C CNN
+F 1 "d_tristate" H 13875 7450 60 0000 C CNN
+F 2 "" H 13800 7000 60 0000 C CNN
+F 3 "" H 13800 7000 60 0000 C CNN
+ 1 13900 6650
+ 1 0 0 1
+$EndComp
+$Comp
+L eSim_Digital:d_tristate U18
+U 1 1 00000000
+P 13900 7700
+F 0 "U18" H 13875 8350 60 0000 C CNN
+F 1 "d_tristate" H 13875 8500 60 0000 C CNN
+F 2 "" H 13800 8050 60 0000 C CNN
+F 3 "" H 13800 8050 60 0000 C CNN
+ 1 13900 7700
+ 1 0 0 1
+$EndComp
+$Comp
+L eSim_Digital:d_tristate U19
+U 1 1 00000000
+P 13900 8800
+F 0 "U19" H 13875 9450 60 0000 C CNN
+F 1 "d_tristate" H 13875 9600 60 0000 C CNN
+F 2 "" H 13800 9150 60 0000 C CNN
+F 3 "" H 13800 9150 60 0000 C CNN
+ 1 13900 8800
+ 1 0 0 1
+$EndComp
+$Comp
+L eSim_Digital:d_tristate U20
+U 1 1 00000000
+P 13900 9850
+F 0 "U20" H 13875 10500 60 0000 C CNN
+F 1 "d_tristate" H 13875 10650 60 0000 C CNN
+F 2 "" H 13800 10200 60 0000 C CNN
+F 3 "" H 13800 10200 60 0000 C CNN
+ 1 13900 9850
+ 1 0 0 1
+$EndComp
+$EndSCHEMATC
diff --git a/library/SubcircuitLibrary/SN74HC541/analysis b/library/SubcircuitLibrary/SN74HC541/analysis
new file mode 100644
index 000000000..ebd5c0a94
--- /dev/null
+++ b/library/SubcircuitLibrary/SN74HC541/analysis
@@ -0,0 +1 @@
+.tran 0e-00 0e-00 0e-00
\ No newline at end of file