From e07e9d4f1e333878ea2867c679cbbe22bfc64a74 Mon Sep 17 00:00:00 2001 From: Sakshi Pandey Date: Sat, 24 Jan 2026 13:34:29 +0530 Subject: [PATCH 1/8] SN74AS20 as Quad 4 input NAND GATE --- .../SubcircuitLibrary/3_nor/3_nor-cache.lib | 146 - library/SubcircuitLibrary/3_nor/3_nor.cir | 20 - library/SubcircuitLibrary/3_nor/3_nor.cir.out | 32 - library/SubcircuitLibrary/3_nor/3_nor.pro | 73 - library/SubcircuitLibrary/3_nor/3_nor.sch | 332 - library/SubcircuitLibrary/3_nor/3_nor.sub | 26 - .../3_nor/3_nor_Previous_Values.xml | 1 - .../SubcircuitLibrary/3_nor/NMOS-180nm.lib | 13 - .../SubcircuitLibrary/3_nor/PMOS-180nm.lib | 11 - library/SubcircuitLibrary/3_nor/analysis | 1 - library/SubcircuitLibrary/4_nand/4_nand.cir | 11 + .../SubcircuitLibrary/4_nand/4_nand.cir.out | 44 + .../SubcircuitLibrary/4_nand/4_nand.kicad_sch | 1229 +++ library/SubcircuitLibrary/4_nand/4_nand.sub | 38 + .../4_nand/4_nand_Previous_Values.xml | 1 + library/SubcircuitLibrary/4_nand/D.lib | 2 + library/SubcircuitLibrary/4_nand/NPN.lib | 4 + library/SubcircuitLibrary/4_nand/analysis | 1 + .../4_nand/eSim_Subckt.kicad_sym | 6638 +++++++++++++++++ 19 files changed, 7968 insertions(+), 655 deletions(-) delete mode 100644 library/SubcircuitLibrary/3_nor/3_nor-cache.lib delete mode 100644 library/SubcircuitLibrary/3_nor/3_nor.cir delete mode 100644 library/SubcircuitLibrary/3_nor/3_nor.cir.out delete mode 100644 library/SubcircuitLibrary/3_nor/3_nor.pro delete mode 100644 library/SubcircuitLibrary/3_nor/3_nor.sch delete mode 100644 library/SubcircuitLibrary/3_nor/3_nor.sub delete mode 100644 library/SubcircuitLibrary/3_nor/3_nor_Previous_Values.xml delete mode 100644 library/SubcircuitLibrary/3_nor/NMOS-180nm.lib delete mode 100644 library/SubcircuitLibrary/3_nor/PMOS-180nm.lib delete mode 100644 library/SubcircuitLibrary/3_nor/analysis create mode 100644 library/SubcircuitLibrary/4_nand/4_nand.cir create mode 100644 library/SubcircuitLibrary/4_nand/4_nand.cir.out create mode 100644 library/SubcircuitLibrary/4_nand/4_nand.kicad_sch create mode 100644 library/SubcircuitLibrary/4_nand/4_nand.sub create mode 100644 library/SubcircuitLibrary/4_nand/4_nand_Previous_Values.xml create mode 100644 library/SubcircuitLibrary/4_nand/D.lib create mode 100644 library/SubcircuitLibrary/4_nand/NPN.lib create mode 100644 library/SubcircuitLibrary/4_nand/analysis create mode 100644 library/SubcircuitLibrary/4_nand/eSim_Subckt.kicad_sym diff --git a/library/SubcircuitLibrary/3_nor/3_nor-cache.lib b/library/SubcircuitLibrary/3_nor/3_nor-cache.lib deleted file mode 100644 index 4ba918afe..000000000 --- a/library/SubcircuitLibrary/3_nor/3_nor-cache.lib +++ /dev/null @@ -1,146 +0,0 @@ -EESchema-LIBRARY Version 2.3 -#encoding utf-8 -# -# PORT -# -DEF PORT U 0 40 Y Y 26 F N -F0 "U" 50 100 30 H V C CNN -F1 "PORT" 0 0 30 H V C CNN -F2 "" 0 0 60 H V C CNN -F3 "" 0 0 60 H V C CNN -DRAW -A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 -A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 -S -100 50 100 -50 0 1 0 N -X ~ 1 250 0 100 L 30 30 1 1 B -X ~ 2 250 0 100 L 30 30 2 1 B -X ~ 3 250 0 100 L 30 30 3 1 B -X ~ 4 250 0 100 L 30 30 4 1 B -X ~ 5 250 0 100 L 30 30 5 1 B -X ~ 6 250 0 100 L 30 30 6 1 B -X ~ 7 250 0 100 L 30 30 7 1 B -X ~ 8 250 0 100 L 30 30 8 1 B -X ~ 9 250 0 100 L 30 30 9 1 B -X ~ 10 250 0 100 L 30 30 10 1 B -X ~ 11 250 0 100 L 30 30 11 1 B -X ~ 12 250 0 100 L 30 30 12 1 B -X ~ 13 250 0 100 L 30 30 13 1 B -X ~ 14 250 0 100 L 30 30 14 1 B -X ~ 15 250 0 100 L 30 30 15 1 B -X ~ 16 250 0 100 L 30 30 16 1 B -X ~ 17 250 0 100 L 30 30 17 1 B -X ~ 18 250 0 100 L 30 30 18 1 B -X ~ 19 250 0 100 L 30 30 19 1 B -X ~ 20 250 0 100 L 30 30 20 1 B -X ~ 21 250 0 100 L 30 30 21 1 B -X ~ 22 250 0 100 L 30 30 22 1 B -X ~ 23 250 0 100 L 30 30 23 1 B -X ~ 24 250 0 100 L 30 30 24 1 B -X ~ 25 250 0 100 L 30 30 25 1 B -X ~ 26 250 0 100 L 30 30 26 1 B -ENDDRAW -ENDDEF -# -# adc_bridge_1 -# -DEF adc_bridge_1 U 0 40 Y Y 1 F N -F0 "U" 0 0 60 H V C CNN -F1 "adc_bridge_1" 0 150 60 H V C CNN -F2 "" 0 0 60 H V C CNN -F3 "" 0 0 60 H V C CNN -DRAW -S -400 200 350 -50 0 1 0 N -X IN1 1 -600 50 200 R 50 50 1 1 I -X OUT1 2 550 50 200 L 50 50 1 1 O -ENDDRAW -ENDDEF -# -# d_buffer -# -DEF d_buffer U 0 40 Y Y 1 F N -F0 "U" 0 -50 60 H V C CNN -F1 "d_buffer" 0 50 60 H V C CNN -F2 "" 0 0 60 H V C CNN -F3 "" 0 0 60 H V C CNN -DRAW -P 4 0 1 0 -300 200 -300 -200 450 0 -300 200 N -X IN 1 -500 0 200 R 50 50 1 1 I -X OUT 2 650 0 200 L 50 50 1 1 O -ENDDRAW -ENDDEF -# -# dac_bridge_3 -# -DEF dac_bridge_3 U 0 40 Y Y 1 F N -F0 "U" 0 0 60 H V C CNN -F1 "dac_bridge_3" 0 150 60 H V C CNN -F2 "" 0 0 60 H V C CNN -F3 "" 0 0 60 H V C CNN -DRAW -S -400 200 350 -200 0 1 0 N -X IN1 1 -600 50 200 R 50 50 1 1 I -X IN2 2 -600 -50 200 R 50 50 1 1 I -X IN3 3 -600 -150 200 R 50 50 1 1 I -X OUT1 4 550 50 200 L 50 50 1 1 O -X OUT2 5 550 -50 200 L 50 50 1 1 O -X OUT3 6 550 -150 200 L 50 50 1 1 O -ENDDRAW -ENDDEF -# -# eSim_MOS_N -# -DEF eSim_MOS_N M 0 0 Y N 1 F N -F0 "M" 0 -150 50 H V R CNN -F1 "eSim_MOS_N" 100 -50 50 H V R CNN -F2 "" 300 -300 29 H V C CNN -F3 "" 100 -200 60 H V C CNN -ALIAS mosfet_n -DRAW -C 150 -200 111 0 1 10 N -P 2 0 1 10 130 -290 130 -250 N -P 2 0 1 0 130 -270 200 -270 N -P 2 0 1 10 130 -220 130 -180 N -P 2 0 1 0 130 -200 200 -200 N -P 2 0 1 10 130 -150 130 -110 N -P 2 0 1 0 130 -130 200 -130 N -P 2 0 1 0 200 -300 200 -270 N -P 2 0 1 0 200 -130 200 -100 N -P 3 0 1 10 110 -275 110 -125 110 -125 N -P 3 0 1 0 200 -200 300 -200 300 -250 N -P 4 0 1 0 140 -200 180 -215 180 -185 140 -200 F -X D 1 200 0 100 D 50 50 1 1 P -X G 2 -100 -200 210 R 50 50 1 1 P -X S 3 200 -400 100 U 50 50 1 1 P -X B 4 300 -350 98 U 47 47 1 1 P -ENDDRAW -ENDDEF -# -# eSim_MOS_P -# -DEF eSim_MOS_P M 0 0 Y N 1 F N -F0 "M" -50 50 50 H V R CNN -F1 "eSim_MOS_P" 50 150 50 H V R CNN -F2 "" 250 100 29 H V C CNN -F3 "" 50 0 60 H V C CNN -ALIAS mosfet_p -DRAW -C 100 0 111 0 1 10 N -P 2 0 1 0 80 -70 150 -70 N -P 2 0 1 10 80 -50 80 -90 N -P 2 0 1 0 80 0 150 0 N -P 2 0 1 10 80 20 80 -20 N -P 2 0 1 0 80 70 150 70 N -P 2 0 1 10 80 90 80 50 N -P 2 0 1 0 150 -70 150 -100 N -P 2 0 1 0 150 100 150 70 N -P 3 0 1 10 60 75 60 -75 60 -75 N -P 3 0 1 0 150 0 250 0 250 -50 N -P 4 0 1 0 140 0 100 -15 100 15 140 0 F -X D 1 150 200 100 D 50 50 1 1 P -X G 2 -150 0 210 R 50 50 1 1 P -X S 3 150 -200 100 U 50 50 1 1 P -X B 4 250 -150 100 U 50 50 1 1 P -ENDDRAW -ENDDEF -# -#End Library diff --git a/library/SubcircuitLibrary/3_nor/3_nor.cir b/library/SubcircuitLibrary/3_nor/3_nor.cir deleted file mode 100644 index b8881701a..000000000 --- a/library/SubcircuitLibrary/3_nor/3_nor.cir +++ /dev/null @@ -1,20 +0,0 @@ -* C:\FOSSEE\eSim\library\SubcircuitLibrary\3_nor\3_nor.cir - -* EESchema Netlist Version 1.1 (Spice format) creation date: 06/13/25 12:25:06 - -* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N -* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 - -* Sheet Name: / -M1 Net-_M1-Pad1_ Net-_M1-Pad2_ Net-_M1-Pad3_ Net-_M1-Pad3_ mosfet_n -M5 Net-_M1-Pad1_ Net-_M3-Pad2_ Net-_M1-Pad3_ Net-_M1-Pad3_ mosfet_n -M6 Net-_M1-Pad1_ Net-_M4-Pad2_ Net-_M1-Pad3_ Net-_M1-Pad3_ mosfet_n -M2 Net-_M2-Pad1_ Net-_M1-Pad2_ Net-_M2-Pad3_ Net-_M2-Pad1_ eSim_MOS_P -M3 Net-_M2-Pad3_ Net-_M3-Pad2_ Net-_M3-Pad3_ Net-_M2-Pad1_ eSim_MOS_P -M4 Net-_M3-Pad3_ Net-_M4-Pad2_ Net-_M1-Pad1_ Net-_M2-Pad1_ eSim_MOS_P -U4 Net-_U3-Pad2_ Net-_U1-Pad6_ d_buffer -U3 Net-_M1-Pad1_ Net-_U3-Pad2_ adc_bridge_1 -U2 Net-_U1-Pad3_ Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_M1-Pad2_ Net-_M3-Pad2_ Net-_M4-Pad2_ dac_bridge_3 -U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_M2-Pad1_ Net-_M1-Pad3_ Net-_U1-Pad6_ PORT - -.end diff --git a/library/SubcircuitLibrary/3_nor/3_nor.cir.out b/library/SubcircuitLibrary/3_nor/3_nor.cir.out deleted file mode 100644 index 551422c51..000000000 --- a/library/SubcircuitLibrary/3_nor/3_nor.cir.out +++ /dev/null @@ -1,32 +0,0 @@ -* c:\fossee\esim\library\subcircuitlibrary\3_nor\3_nor.cir - -.include NMOS-180nm.lib -.include PMOS-180nm.lib -m1 net-_m1-pad1_ net-_m1-pad2_ net-_m1-pad3_ net-_m1-pad3_ CMOSN W=100u L=100u M=1 -m5 net-_m1-pad1_ net-_m3-pad2_ net-_m1-pad3_ net-_m1-pad3_ CMOSN W=100u L=100u M=1 -m6 net-_m1-pad1_ net-_m4-pad2_ net-_m1-pad3_ net-_m1-pad3_ CMOSN W=100u L=100u M=1 -m2 net-_m2-pad1_ net-_m1-pad2_ net-_m2-pad3_ net-_m2-pad1_ CMOSP W=100u L=100u M=1 -m3 net-_m2-pad3_ net-_m3-pad2_ net-_m3-pad3_ net-_m2-pad1_ CMOSP W=100u L=100u M=1 -m4 net-_m3-pad3_ net-_m4-pad2_ net-_m1-pad1_ net-_m2-pad1_ CMOSP W=100u L=100u M=1 -* u4 net-_u3-pad2_ net-_u1-pad6_ d_buffer -* u3 net-_m1-pad1_ net-_u3-pad2_ adc_bridge_1 -* u2 net-_u1-pad3_ net-_u1-pad1_ net-_u1-pad2_ net-_m1-pad2_ net-_m3-pad2_ net-_m4-pad2_ dac_bridge_3 -* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_m2-pad1_ net-_m1-pad3_ net-_u1-pad6_ port -a1 net-_u3-pad2_ net-_u1-pad6_ u4 -a2 [net-_m1-pad1_ ] [net-_u3-pad2_ ] u3 -a3 [net-_u1-pad3_ net-_u1-pad1_ net-_u1-pad2_ ] [net-_m1-pad2_ net-_m3-pad2_ net-_m4-pad2_ ] u2 -* Schematic Name: d_buffer, NgSpice Name: d_buffer -.model u4 d_buffer(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) -* Schematic Name: adc_bridge_1, NgSpice Name: adc_bridge -.model u3 adc_bridge(in_low=1.0 in_high=2.0 rise_delay=1.0e-9 fall_delay=1.0e-9 ) -* Schematic Name: dac_bridge_3, NgSpice Name: dac_bridge -.model u2 dac_bridge(out_low=0.0 out_high=5.0 out_undef=0.5 input_load=1.0e-12 t_rise=1.0e-9 t_fall=1.0e-9 ) -.tran 0e-00 0e-00 0e-00 - -* Control Statements -.control -run -print allv > plot_data_v.txt -print alli > plot_data_i.txt -.endc -.end diff --git a/library/SubcircuitLibrary/3_nor/3_nor.pro b/library/SubcircuitLibrary/3_nor/3_nor.pro deleted file mode 100644 index e27a398be..000000000 --- a/library/SubcircuitLibrary/3_nor/3_nor.pro +++ /dev/null @@ -1,73 +0,0 @@ -update=22/05/2015 07:44:53 -version=1 -last_client=kicad -[general] -version=1 -RootSch= -BoardNm= -[pcbnew] -version=1 -LastNetListRead= -UseCmpFile=1 -PadDrill=0.600000000000 -PadDrillOvalY=0.600000000000 -PadSizeH=1.500000000000 -PadSizeV=1.500000000000 -PcbTextSizeV=1.500000000000 -PcbTextSizeH=1.500000000000 -PcbTextThickness=0.300000000000 -ModuleTextSizeV=1.000000000000 -ModuleTextSizeH=1.000000000000 -ModuleTextSizeThickness=0.150000000000 -SolderMaskClearance=0.000000000000 -SolderMaskMinWidth=0.000000000000 -DrawSegmentWidth=0.200000000000 -BoardOutlineThickness=0.100000000000 -ModuleOutlineThickness=0.150000000000 -[cvpcb] -version=1 -NetIExt=net -[eeschema] -version=1 -LibDir= -[eeschema/libraries] -LibName1=adc-dac -LibName2=memory -LibName3=xilinx -LibName4=microcontrollers -LibName5=dsp -LibName6=microchip -LibName7=analog_switches -LibName8=motorola -LibName9=texas -LibName10=intel -LibName11=audio -LibName12=interface -LibName13=digital-audio -LibName14=philips -LibName15=display -LibName16=cypress -LibName17=siliconi -LibName18=opto -LibName19=atmel -LibName20=contrib -LibName21=power -LibName22=eSim_Plot -LibName23=transistors -LibName24=conn -LibName25=eSim_User -LibName26=regul -LibName27=74xx -LibName28=cmos4000 -LibName29=eSim_Analog -LibName30=eSim_Devices -LibName31=eSim_Digital -LibName32=eSim_Hybrid -LibName33=eSim_Miscellaneous -LibName34=eSim_Power -LibName35=eSim_Sources -LibName36=eSim_Subckt -LibName37=eSim_Nghdl -LibName38=eSim_Ngveri -LibName39=eSim_SKY130 -LibName40=eSim_SKY130_Subckts diff --git a/library/SubcircuitLibrary/3_nor/3_nor.sch b/library/SubcircuitLibrary/3_nor/3_nor.sch deleted file mode 100644 index fe1cae253..000000000 --- a/library/SubcircuitLibrary/3_nor/3_nor.sch +++ /dev/null @@ -1,332 +0,0 @@ -EESchema Schematic File Version 2 -LIBS:adc-dac -LIBS:memory -LIBS:xilinx -LIBS:microcontrollers -LIBS:dsp -LIBS:microchip -LIBS:analog_switches -LIBS:motorola -LIBS:texas -LIBS:intel -LIBS:audio -LIBS:interface -LIBS:digital-audio -LIBS:philips -LIBS:display -LIBS:cypress -LIBS:siliconi -LIBS:opto -LIBS:atmel -LIBS:contrib -LIBS:power -LIBS:eSim_Plot -LIBS:transistors -LIBS:conn -LIBS:eSim_User -LIBS:regul -LIBS:74xx -LIBS:cmos4000 -LIBS:eSim_Analog -LIBS:eSim_Devices -LIBS:eSim_Digital -LIBS:eSim_Hybrid -LIBS:eSim_Miscellaneous -LIBS:eSim_Power -LIBS:eSim_Sources -LIBS:eSim_Subckt -LIBS:eSim_Nghdl -LIBS:eSim_Ngveri -LIBS:eSim_SKY130 -LIBS:eSim_SKY130_Subckts -LIBS:3_nor-cache -LIBS:3_norgate-cache -EELAYER 25 0 -EELAYER END -$Descr A4 11693 8268 -encoding utf-8 -Sheet 1 1 -Title "" -Date "" -Rev "" -Comp "" -Comment1 "" -Comment2 "" -Comment3 "" -Comment4 "" -$EndDescr -Wire Wire Line - 3300 4650 3300 4450 -Wire Wire Line - 3300 1300 3300 4300 -$Comp -L mosfet_n M1 -U 1 1 684BC8E7 -P 4700 3600 -F 0 "M1" H 4700 3450 50 0000 R CNN -F 1 "mosfet_n" H 4800 3550 50 0000 R CNN -F 2 "" H 5000 3300 29 0000 C CNN -F 3 "" H 4800 3400 60 0000 C CNN - 1 4700 3600 - 1 0 0 -1 -$EndComp -$Comp -L mosfet_n M5 -U 1 1 684BC8E8 -P 6050 3600 -F 0 "M5" H 6050 3450 50 0000 R CNN -F 1 "mosfet_n" H 6150 3550 50 0000 R CNN -F 2 "" H 6350 3300 29 0000 C CNN -F 3 "" H 6150 3400 60 0000 C CNN - 1 6050 3600 - 1 0 0 -1 -$EndComp -$Comp -L mosfet_n M6 -U 1 1 684BC8E9 -P 7200 3650 -F 0 "M6" H 7200 3500 50 0000 R CNN -F 1 "mosfet_n" H 7300 3600 50 0000 R CNN -F 2 "" H 7500 3350 29 0000 C CNN -F 3 "" H 7300 3450 60 0000 C CNN - 1 7200 3650 - 1 0 0 -1 -$EndComp -$Comp -L eSim_MOS_P M2 -U 1 1 684BC8EA -P 5400 1300 -F 0 "M2" H 5350 1350 50 0000 R CNN -F 1 "eSim_MOS_P" H 5450 1450 50 0000 R CNN -F 2 "" H 5650 1400 29 0000 C CNN -F 3 "" H 5450 1300 60 0000 C CNN - 1 5400 1300 - 1 0 0 -1 -$EndComp -$Comp -L eSim_MOS_P M3 -U 1 1 684BC8EB -P 5400 1950 -F 0 "M3" H 5350 2000 50 0000 R CNN -F 1 "eSim_MOS_P" H 5450 2100 50 0000 R CNN -F 2 "" H 5650 2050 29 0000 C CNN -F 3 "" H 5450 1950 60 0000 C CNN - 1 5400 1950 - 1 0 0 -1 -$EndComp -$Comp -L eSim_MOS_P M4 -U 1 1 684BC8EC -P 5400 2600 -F 0 "M4" H 5350 2650 50 0000 R CNN -F 1 "eSim_MOS_P" H 5450 2750 50 0000 R CNN -F 2 "" H 5650 2700 29 0000 C CNN -F 3 "" H 5450 2600 60 0000 C CNN - 1 5400 2600 - 1 0 0 -1 -$EndComp -Wire Wire Line - 4900 3600 7400 3600 -Wire Wire Line - 7400 3600 7400 3650 -Connection ~ 6250 3600 -Wire Wire Line - 4900 4000 4900 4250 -Wire Wire Line - 4900 4250 7500 4250 -Wire Wire Line - 7400 4250 7400 4050 -Wire Wire Line - 6250 4000 6250 4250 -Connection ~ 6250 4250 -Wire Wire Line - 5000 3950 5000 4250 -Connection ~ 5000 4250 -Wire Wire Line - 6350 3950 6350 4500 -Connection ~ 6350 4250 -Wire Wire Line - 7500 4250 7500 4000 -Connection ~ 7400 4250 -Wire Wire Line - 5550 1500 5550 1750 -Wire Wire Line - 5550 2150 5550 2400 -Wire Wire Line - 5550 1100 5550 850 -Wire Wire Line - 5550 850 6500 850 -Wire Wire Line - 5650 1450 5950 1450 -Wire Wire Line - 5950 850 5950 2750 -Connection ~ 5950 850 -Wire Wire Line - 5950 2100 5650 2100 -Connection ~ 5950 1450 -Wire Wire Line - 5950 2750 5650 2750 -Connection ~ 5950 2100 -Wire Wire Line - 5550 2800 5550 3600 -Connection ~ 5550 3600 -Wire Wire Line - 3300 3800 4600 3800 -Wire Wire Line - 3300 1300 5250 1300 -Connection ~ 3300 3800 -Wire Wire Line - 3300 4450 5950 4450 -Wire Wire Line - 5950 4450 5950 3800 -Wire Wire Line - 3650 5050 7100 5050 -Wire Wire Line - 7100 5050 7100 3850 -Wire Wire Line - 4200 4450 4200 1950 -Wire Wire Line - 4200 1950 5250 1950 -Connection ~ 4200 4450 -Wire Wire Line - 5350 5050 5350 2800 -Wire Wire Line - 5350 2800 5100 2800 -Wire Wire Line - 5100 2800 5100 2600 -Wire Wire Line - 5100 2600 5250 2600 -Connection ~ 5350 5050 -Connection ~ 5550 3200 -$Comp -L d_buffer U4 -U 1 1 684BC8F1 -P 7800 3100 -F 0 "U4" H 7800 3050 60 0000 C CNN -F 1 "d_buffer" H 7800 3150 60 0000 C CNN -F 2 "" H 7800 3100 60 0000 C CNN -F 3 "" H 7800 3100 60 0000 C CNN - 1 7800 3100 - 1 0 0 -1 -$EndComp -$Comp -L adc_bridge_1 U3 -U 1 1 684BC8F2 -P 6400 3250 -F 0 "U3" H 6400 3250 60 0000 C CNN -F 1 "adc_bridge_1" H 6400 3400 60 0000 C CNN -F 2 "" H 6400 3250 60 0000 C CNN -F 3 "" H 6400 3250 60 0000 C CNN - 1 6400 3250 - 1 0 0 -1 -$EndComp -Wire Wire Line - 5550 3200 5800 3200 -Wire Wire Line - 6950 3200 6950 3100 -Wire Wire Line - 6950 3100 7300 3100 -Wire Wire Line - 8450 3100 8450 3550 -Wire Wire Line - 8450 3550 8550 3550 -$Comp -L dac_bridge_3 U2 -U 1 1 684BCCBA -P 2350 4600 -F 0 "U2" H 2350 4600 60 0000 C CNN -F 1 "dac_bridge_3" H 2350 4750 60 0000 C CNN -F 2 "" H 2350 4600 60 0000 C CNN -F 3 "" H 2350 4600 60 0000 C CNN - 1 2350 4600 - 1 0 0 -1 -$EndComp -Wire Wire Line - 2900 4550 3100 4550 -Wire Wire Line - 3100 4550 3100 4300 -Wire Wire Line - 3100 4300 3300 4300 -Wire Wire Line - 2900 4650 3300 4650 -Wire Wire Line - 2900 4750 3650 4750 -Wire Wire Line - 3650 4750 3650 5050 -$Comp -L PORT U1 -U 3 1 684BCFDE -P 1050 4500 -F 0 "U1" H 1100 4600 30 0000 C CNN -F 1 "PORT" H 1050 4500 30 0000 C CNN -F 2 "" H 1050 4500 60 0000 C CNN -F 3 "" H 1050 4500 60 0000 C CNN - 3 1050 4500 - 1 0 0 -1 -$EndComp -$Comp -L PORT U1 -U 1 1 684BD073 -P 950 4650 -F 0 "U1" H 1000 4750 30 0000 C CNN -F 1 "PORT" H 950 4650 30 0000 C CNN -F 2 "" H 950 4650 60 0000 C CNN -F 3 "" H 950 4650 60 0000 C CNN - 1 950 4650 - 1 0 0 -1 -$EndComp -$Comp -L PORT U1 -U 2 1 684BD0CA -P 950 4850 -F 0 "U1" H 1000 4950 30 0000 C CNN -F 1 "PORT" H 950 4850 30 0000 C CNN -F 2 "" H 950 4850 60 0000 C CNN -F 3 "" H 950 4850 60 0000 C CNN - 2 950 4850 - 1 0 0 -1 -$EndComp -Wire Wire Line - 1300 4500 1750 4500 -Wire Wire Line - 1750 4500 1750 4550 -Wire Wire Line - 1200 4650 1750 4650 -Wire Wire Line - 1200 4850 1200 4750 -Wire Wire Line - 1200 4750 1750 4750 -$Comp -L PORT U1 -U 4 1 684BD531 -P 6500 1100 -F 0 "U1" H 6550 1200 30 0000 C CNN -F 1 "PORT" H 6500 1100 30 0000 C CNN -F 2 "" H 6500 1100 60 0000 C CNN -F 3 "" H 6500 1100 60 0000 C CNN - 4 6500 1100 - 0 -1 -1 0 -$EndComp -$Comp -L PORT U1 -U 5 1 684BD700 -P 6600 4500 -F 0 "U1" H 6650 4600 30 0000 C CNN -F 1 "PORT" H 6600 4500 30 0000 C CNN -F 2 "" H 6600 4500 60 0000 C CNN -F 3 "" H 6600 4500 60 0000 C CNN - 5 6600 4500 - -1 0 0 1 -$EndComp -$Comp -L PORT U1 -U 6 1 684BDA88 -P 8800 3550 -F 0 "U1" H 8850 3650 30 0000 C CNN -F 1 "PORT" H 8800 3550 30 0000 C CNN -F 2 "" H 8800 3550 60 0000 C CNN -F 3 "" H 8800 3550 60 0000 C CNN - 6 8800 3550 - -1 0 0 1 -$EndComp -$EndSCHEMATC diff --git a/library/SubcircuitLibrary/3_nor/3_nor.sub b/library/SubcircuitLibrary/3_nor/3_nor.sub deleted file mode 100644 index 9bbbe57a5..000000000 --- a/library/SubcircuitLibrary/3_nor/3_nor.sub +++ /dev/null @@ -1,26 +0,0 @@ -* Subcircuit 3_nor -.subckt 3_nor net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_m2-pad1_ net-_m1-pad3_ net-_u1-pad6_ -* c:\fossee\esim\library\subcircuitlibrary\3_nor\3_nor.cir -.include NMOS-180nm.lib -.include PMOS-180nm.lib -m1 net-_m1-pad1_ net-_m1-pad2_ net-_m1-pad3_ net-_m1-pad3_ CMOSN W=100u L=100u M=1 -m5 net-_m1-pad1_ net-_m3-pad2_ net-_m1-pad3_ net-_m1-pad3_ CMOSN W=100u L=100u M=1 -m6 net-_m1-pad1_ net-_m4-pad2_ net-_m1-pad3_ net-_m1-pad3_ CMOSN W=100u L=100u M=1 -m2 net-_m2-pad1_ net-_m1-pad2_ net-_m2-pad3_ net-_m2-pad1_ CMOSP W=100u L=100u M=1 -m3 net-_m2-pad3_ net-_m3-pad2_ net-_m3-pad3_ net-_m2-pad1_ CMOSP W=100u L=100u M=1 -m4 net-_m3-pad3_ net-_m4-pad2_ net-_m1-pad1_ net-_m2-pad1_ CMOSP W=100u L=100u M=1 -* u4 net-_u3-pad2_ net-_u1-pad6_ d_buffer -* u3 net-_m1-pad1_ net-_u3-pad2_ adc_bridge_1 -* u2 net-_u1-pad3_ net-_u1-pad1_ net-_u1-pad2_ net-_m1-pad2_ net-_m3-pad2_ net-_m4-pad2_ dac_bridge_3 -a1 net-_u3-pad2_ net-_u1-pad6_ u4 -a2 [net-_m1-pad1_ ] [net-_u3-pad2_ ] u3 -a3 [net-_u1-pad3_ net-_u1-pad1_ net-_u1-pad2_ ] [net-_m1-pad2_ net-_m3-pad2_ net-_m4-pad2_ ] u2 -* Schematic Name: d_buffer, NgSpice Name: d_buffer -.model u4 d_buffer(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) -* Schematic Name: adc_bridge_1, NgSpice Name: adc_bridge -.model u3 adc_bridge(in_low=1.0 in_high=2.0 rise_delay=1.0e-9 fall_delay=1.0e-9 ) -* Schematic Name: dac_bridge_3, NgSpice Name: dac_bridge -.model u2 dac_bridge(out_low=0.0 out_high=5.0 out_undef=0.5 input_load=1.0e-12 t_rise=1.0e-9 t_fall=1.0e-9 ) -* Control Statements - -.ends 3_nor \ No newline at end of file diff --git a/library/SubcircuitLibrary/3_nor/3_nor_Previous_Values.xml b/library/SubcircuitLibrary/3_nor/3_nor_Previous_Values.xml deleted file mode 100644 index 2c30c1aab..000000000 --- a/library/SubcircuitLibrary/3_nor/3_nor_Previous_Values.xml +++ /dev/null @@ -1 +0,0 @@ -d_bufferadc_bridgedac_bridgeC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-180nm.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-180nm.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-180nm.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\PMOS-180nm.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\PMOS-180nm.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\PMOS-180nm.libtruefalsefalseHzHz0Volts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or Amperessecsecsec \ No newline at end of file diff --git a/library/SubcircuitLibrary/3_nor/NMOS-180nm.lib b/library/SubcircuitLibrary/3_nor/NMOS-180nm.lib deleted file mode 100644 index 51e9b1196..000000000 --- a/library/SubcircuitLibrary/3_nor/NMOS-180nm.lib +++ /dev/null @@ -1,13 +0,0 @@ -.model CMOSN NMOS (LEVEL=8 VERSION=3.2 TNOM=27 TOX=4.1E-9 XJ=1E-7 NCH=2.3549E17 VTH0=0.3823463 K1=0.5810697 -+ K2=4.774618E-3 K3=0.0431669 K3B=1.1498346 W0=1E-7 NLX=1.910552E-7 DVT0W=0 DVT1W=0 DVT2W=0 -+ DVT0=1.2894824 DVT1=0.3622063 DVT2=0.0713729 U0=280.633249 UA=-1.208537E-9 UB=2.158625E-18 -+ UC=5.342807E-11 VSAT=9.366802E4 A0=1.7593146 AGS=0.3939741 B0=-6.413949E-9 B1=-1E-7 KETA=-5.180424E-4 -+ A1=0 A2=1 RDSW=105.5517558 PRWG=0.5 PRWB=-0.1998871 WR=1 WINT=7.904732E-10 LINT=1.571424E-8 XL=0 -+ XW=-1E-8 DWG=1.297221E-9 DWB=1.479041E-9 VOFF=-0.0955434 NFACTOR=2.4358891 CIT=0 CDSC=2.4E-4 CDSCD=0 -+ CDSCB=0 ETA0=3.104851E-3 ETAB=-2.512384E-5 DSUB=0.0167075 PCLM=0.8073191 PDIBLC1=0.1666161 PDIBLC2=3.112892E-3 -+ PDIBLCB=-0.1 DROUT=0.7875618 PSCBE1=8E10 PSCBE2=9.213635E-10 PVAG=3.85243E-3 DELTA=0.01 RSH=6.7 MOBMOD=1 -+ PRT=0 UTE=-1.5 KT1=-0.11 KT1L=0 KT2=0.022 UA1=4.31E-9 UB1=-7.61E-18 UC1=-5.6E-11 AT=3.3E4 WL=0 WLN=1 -+ WW=0 WWN=1 WWL=0 LL=0 LLN=1 LW=0 LWN=1 LWL=0 CAPMOD=2 XPART=0.5 CGDO=7.08E-10 CGSO=7.08E-10 CGBO=1E-12 -+ CJ=9.68858E-4 PB=0.8 MJ=0.3864502 CJSW=2.512138E-10 PBSW=0.809286 MJSW=0.1060414 CJSWG=3.3E-10 PBSWG=0.809286 -+ MJSWG=0.1060414 CF=0 PVTH0=-1.192722E-3 PRDSW=-5 PK2=6.450505E-5 WKETA=-4.27294E-4 LKETA=-0.0104078 -+ PU0=6.3268729 PUA=2.226552E-11 PUB=0 PVSAT=969.1480157 PETA0=1E-4 PKETA=-1.049509E-3) diff --git a/library/SubcircuitLibrary/3_nor/PMOS-180nm.lib b/library/SubcircuitLibrary/3_nor/PMOS-180nm.lib deleted file mode 100644 index 032b5b95e..000000000 --- a/library/SubcircuitLibrary/3_nor/PMOS-180nm.lib +++ /dev/null @@ -1,11 +0,0 @@ -.model CMOSP PMOS (LEVEL=8 VERSION=3.2 TNOM=27 TOX=4.1E-9 XJ=1E-7 NCH=4.1589E17 VTH0=-0.3938813 K1=0.5479015 -+ K2=0.0360586 K3=0.0993095 K3B=5.7086622 W0=1E-6 NLX=1.313191E-7 DVT0W=0 DVT1W=0 DVT2W=0 DVT0=0.4911363 -+ DVT1=0.2227356 DVT2=0.1 U0=115.6852975 UA=1.505832E-9 UB=1E-21 UC=-1E-10 VSAT=1.329694E5 A0=1.7590478 -+ AGS=0.3641621 B0=3.427126E-7 B1=1.062928E-6 KETA=0.0134667 A1=0.6859506 A2=0.3506788 RDSW=168.5705677 -+ PRWG=0.5 PRWB=-0.4987371 WR=1 WINT=0 LINT=3.028832E-8 XL=0 XW=-1E-8 DWG=-2.349633E-8 DWB=-7.152486E-9 -+ VOFF=-0.0994037 NFACTOR=1.9424315 CIT=0 CDSC=2.4E-4 CDSCD=0 CDSCB=0 ETA0=0.0608072 ETAB=-0.0426148 -+ DSUB=0.7343015 PCLM=3.2579974 PDIBLC1=7.229527E-6 PDIBLC2=0.025389 PDIBLCB=-1E-3 DROUT=0 PSCBE1=1.454878E10 -+ PSCBE2=4.202027E-9 PVAG=15 DELTA=0.01 RSH=7.8 MOBMOD=1 PRT=0 UTE=-1.5 KT1=-0.11 KT1L=0 KT2=0.022 UA1=4.31E-9 -+ UB1=-7.61E-18 UC1=-5.6E-11 AT=3.3E4 WL=0 WLN=1 WW=0 WWN=1 WWL=0 LL=0 LLN=1 LW=0 LWN=1 LWL=0 CAPMOD=2 XPART=0.5 -+ CGDO=6.32E-10 CGSO=6.32E-10 CGBO=1E-12 CJ=1.172138E-3 PB=0.8421173 MJ=0.4109788 CJSW=2.242609E-10 PBSW=0.8 + MJSW=0.3752089 CJSWG=4.22E-10 PBSWG=0.8 MJSWG=0.3752089 CF=0 PVTH0=1.888482E-3 PRDSW=11.5315407 PK2=1.559399E-3 -+ WKETA=0.0319301 LKETA=2.955547E-3 PU0=-1.1105313 PUA=-4.62102E-11 PUB=1E-21 PVSAT=50 PETA0=1E-4 PKETA=-4.346368E-3) diff --git a/library/SubcircuitLibrary/3_nor/analysis b/library/SubcircuitLibrary/3_nor/analysis deleted file mode 100644 index ebd5c0a94..000000000 --- a/library/SubcircuitLibrary/3_nor/analysis +++ /dev/null @@ -1 +0,0 @@ -.tran 0e-00 0e-00 0e-00 \ No newline at end of file diff --git a/library/SubcircuitLibrary/4_nand/4_nand.cir b/library/SubcircuitLibrary/4_nand/4_nand.cir new file mode 100644 index 000000000..98494bdd8 --- /dev/null +++ b/library/SubcircuitLibrary/4_nand/4_nand.cir @@ -0,0 +1,11 @@ +.title KiCad schematic +U109 Net-_U107-Pad3_ Net-_U107-Pad3_ Net-_U109-Pad3_ d_nand +U106 Net-_U102-Pad3_ Net-_U103-Pad3_ Net-_U106-Pad3_ d_nand +U107 Net-_U104-Pad3_ Net-_U105-Pad3_ Net-_U107-Pad3_ d_nand +U108 Net-_U106-Pad3_ Net-_U106-Pad3_ Net-_U108-Pad3_ d_nand +U101 Net-_U104-Pad1_ Net-_U104-Pad2_ unconnected-_U101-Pad3_ Net-_U105-Pad1_ Net-_U105-Pad2_ Net-_U109-Pad3_ unconnected-_U101-Pad7_ Net-_U108-Pad3_ Net-_U102-Pad1_ Net-_U102-Pad2_ unconnected-_U101-Pad11_ Net-_U103-Pad1_ Net-_U103-Pad2_ unconnected-_U101-Pad14_ PORT +U105 Net-_U105-Pad1_ Net-_U105-Pad2_ Net-_U105-Pad3_ d_nand +U104 Net-_U104-Pad1_ Net-_U104-Pad2_ Net-_U104-Pad3_ d_nand +U102 Net-_U102-Pad1_ Net-_U102-Pad2_ Net-_U102-Pad3_ d_nand +U103 Net-_U103-Pad1_ Net-_U103-Pad2_ Net-_U103-Pad3_ d_nand +.end diff --git a/library/SubcircuitLibrary/4_nand/4_nand.cir.out b/library/SubcircuitLibrary/4_nand/4_nand.cir.out new file mode 100644 index 000000000..2d59c40a1 --- /dev/null +++ b/library/SubcircuitLibrary/4_nand/4_nand.cir.out @@ -0,0 +1,44 @@ +.title kicad schematic + +* u109 net-_u107-pad3_ net-_u107-pad3_ net-_u109-pad3_ d_nand +* u106 net-_u102-pad3_ net-_u103-pad3_ net-_u106-pad3_ d_nand +* u107 net-_u104-pad3_ net-_u105-pad3_ net-_u107-pad3_ d_nand +* u108 net-_u106-pad3_ net-_u106-pad3_ net-_u108-pad3_ d_nand +* u101 net-_u104-pad1_ net-_u104-pad2_ unconnected-_u101-pad3_ net-_u105-pad1_ net-_u105-pad2_ net-_u109-pad3_ unconnected-_u101-pad7_ net-_u108-pad3_ net-_u102-pad1_ net-_u102-pad2_ unconnected-_u101-pad11_ net-_u103-pad1_ net-_u103-pad2_ unconnected-_u101-pad14_ port +* u105 net-_u105-pad1_ net-_u105-pad2_ net-_u105-pad3_ d_nand +* u104 net-_u104-pad1_ net-_u104-pad2_ net-_u104-pad3_ d_nand +* u102 net-_u102-pad1_ net-_u102-pad2_ net-_u102-pad3_ d_nand +* u103 net-_u103-pad1_ net-_u103-pad2_ net-_u103-pad3_ d_nand +a1 [net-_u107-pad3_ net-_u107-pad3_ ] net-_u109-pad3_ u109 +a2 [net-_u102-pad3_ net-_u103-pad3_ ] net-_u106-pad3_ u106 +a3 [net-_u104-pad3_ net-_u105-pad3_ ] net-_u107-pad3_ u107 +a4 [net-_u106-pad3_ net-_u106-pad3_ ] net-_u108-pad3_ u108 +a5 [net-_u105-pad1_ net-_u105-pad2_ ] net-_u105-pad3_ u105 +a6 [net-_u104-pad1_ net-_u104-pad2_ ] net-_u104-pad3_ u104 +a7 [net-_u102-pad1_ net-_u102-pad2_ ] net-_u102-pad3_ u102 +a8 [net-_u103-pad1_ net-_u103-pad2_ ] net-_u103-pad3_ u103 +* Schematic Name: d_nand, Ngspice Name: d_nand +.model u109 d_nand(rise_delay=5n fall_delay=5n input_load=1p ) +* Schematic Name: d_nand, Ngspice Name: d_nand +.model u106 d_nand(rise_delay=5n fall_delay=5n input_load=1p ) +* Schematic Name: d_nand, Ngspice Name: d_nand +.model u107 d_nand(rise_delay=5n fall_delay=5n input_load=1p ) +* Schematic Name: d_nand, Ngspice Name: d_nand +.model u108 d_nand(rise_delay=5n fall_delay=5n input_load=1p ) +* Schematic Name: d_nand, Ngspice Name: d_nand +.model u105 d_nand(rise_delay=5n fall_delay=5n input_load=1p ) +* Schematic Name: d_nand, Ngspice Name: d_nand +.model u104 d_nand(rise_delay=5n fall_delay=5n input_load=1p ) +* Schematic Name: d_nand, Ngspice Name: d_nand +.model u102 d_nand(rise_delay=5n fall_delay=5n input_load=1p ) +* Schematic Name: d_nand, Ngspice Name: d_nand +.model u103 d_nand(rise_delay=5n fall_delay=5n input_load=1p ) +.tran 0.1e-03 10e-03 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/library/SubcircuitLibrary/4_nand/4_nand.kicad_sch b/library/SubcircuitLibrary/4_nand/4_nand.kicad_sch new file mode 100644 index 000000000..bdf9031a9 --- /dev/null +++ b/library/SubcircuitLibrary/4_nand/4_nand.kicad_sch @@ -0,0 +1,1229 @@ +(kicad_sch (version 20211123) (generator eeschema) + + (uuid 50040046-2680-423d-888e-06c84437a250) + + (paper "A4") + + (lib_symbols + (symbol "eSim_Digital:d_nand" (pin_names (offset 1.016)) (in_bom yes) (on_board yes) + (property "Reference" "U" (id 0) (at 0 0 0) + (effects (font (size 1.524 1.524))) + ) + (property "Value" "d_nand" (id 1) (at 1.27 2.54 0) + (effects (font (size 1.524 1.524))) + ) + (property "Footprint" "" (id 2) (at 0 0 0) + (effects (font (size 1.524 1.524))) + ) + (property "Datasheet" "" (id 3) (at 0 0 0) + (effects (font (size 1.524 1.524))) + ) + (symbol "d_nand_0_1" + (polyline + (pts + (xy 3.81 -1.27) + (xy -6.35 -1.27) + (xy -6.35 3.81) + (xy 3.81 3.81) + ) + (stroke (width 0) (type default) (color 0 0 0 0)) + (fill (type none)) + ) + (arc (start 3.81 -1.27) (mid 5.5897 -0.5171) (end 6.35 1.27) + (stroke (width 0) (type default) (color 0 0 0 0)) + (fill (type none)) + ) + (arc (start 6.35 1.27) (mid 5.5971 3.0497) (end 3.81 3.81) + (stroke (width 0) (type default) (color 0 0 0 0)) + (fill (type none)) + ) + ) + (symbol "d_nand_1_1" + (pin input line (at -11.43 2.54 0) (length 5.08) + (name "IN1" (effects (font (size 1.27 1.27)))) + (number "1" (effects (font (size 1.27 1.27)))) + ) + (pin input line (at -11.43 0 0) (length 5.08) + (name "IN2" (effects (font (size 1.27 1.27)))) + (number "2" (effects (font (size 1.27 1.27)))) + ) + (pin output inverted (at 11.43 1.27 180) (length 5.08) + (name "OUT" (effects (font (size 1.27 1.27)))) + (number "3" (effects (font (size 1.27 1.27)))) + ) + ) + ) + (symbol "eSim_Miscellaneous:PORT" (pin_names (offset 1.016)) (in_bom yes) (on_board yes) + (property "Reference" "U" (id 0) (at 1.27 2.54 0) + (effects (font (size 0.762 0.762))) + ) + (property "Value" "PORT" (id 1) (at 0 0 0) + (effects (font (size 0.762 0.762))) + ) + (property "Footprint" "" (id 2) (at 0 0 0) + (effects (font (size 1.524 1.524))) + ) + (property "Datasheet" "" (id 3) (at 0 0 0) + (effects (font (size 1.524 1.524))) + ) + (symbol "PORT_0_1" + (rectangle (start -2.54 1.27) (end 2.54 -1.27) + (stroke (width 0) (type default) (color 0 0 0 0)) + (fill (type none)) + ) + (arc (start 2.54 1.27) (mid 3.1355 0.5955) (end 3.81 0) + (stroke (width 0) (type default) (color 0 0 0 0)) + (fill (type none)) + ) + (arc (start 3.81 0) (mid 3.1447 -0.6046) (end 2.54 -1.27) + (stroke (width 0) (type default) (color 0 0 0 0)) + (fill (type none)) + ) + ) + (symbol "PORT_1_1" + (pin bidirectional line (at 6.35 0 180) (length 2.54) + (name "~" (effects (font (size 0.762 0.762)))) + (number "1" (effects (font (size 0.762 0.762)))) + ) + ) + (symbol "PORT_2_1" + (pin bidirectional line (at 6.35 0 180) (length 2.54) + (name "~" (effects (font (size 0.762 0.762)))) + (number "2" (effects (font (size 0.762 0.762)))) + ) + ) + (symbol "PORT_3_1" + (pin bidirectional line (at 6.35 0 180) (length 2.54) + (name "~" (effects (font (size 0.762 0.762)))) + (number "3" (effects (font (size 0.762 0.762)))) + ) + ) + (symbol "PORT_4_1" + (pin bidirectional line (at 6.35 0 180) (length 2.54) + (name "~" (effects (font (size 0.762 0.762)))) + (number "4" (effects (font (size 0.762 0.762)))) + ) + ) + (symbol "PORT_5_1" + (pin bidirectional line (at 6.35 0 180) (length 2.54) + (name "~" (effects (font (size 0.762 0.762)))) + (number "5" (effects (font (size 0.762 0.762)))) + ) + ) + (symbol "PORT_6_1" + (pin bidirectional line (at 6.35 0 180) (length 2.54) + (name "~" (effects (font (size 0.762 0.762)))) + (number "6" (effects (font (size 0.762 0.762)))) + ) + ) + (symbol "PORT_7_1" + (pin bidirectional line (at 6.35 0 180) (length 2.54) + (name "~" (effects (font (size 0.762 0.762)))) + (number "7" (effects (font (size 0.762 0.762)))) + ) + ) + (symbol "PORT_8_1" + (pin bidirectional line (at 6.35 0 180) (length 2.54) + (name "~" (effects (font (size 0.762 0.762)))) + (number "8" (effects (font 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(uuid d12d60a8-331a-451c-9480-3478e18aaa59)) + (pin "10" (uuid 005a2373-5110-4768-b7ae-71196087e918)) + (pin "11" (uuid fc548095-d9a6-4117-80c9-67b1868b324d)) + (pin "12" (uuid 6a23a1bd-83ab-420d-9207-b94f4f00d758)) + (pin "13" (uuid a070cb50-8b5c-4ad3-8618-9c5a154954d3)) + (pin "14" (uuid f455d47f-8455-4fea-b2d0-3b068f743b95)) + (pin "15" (uuid 27cfb10e-f552-4eb5-b2eb-8cbde950186a)) + (pin "16" (uuid bb4493aa-4c7a-490e-9468-60507c31c3da)) + (pin "17" (uuid 2a43df2c-6f76-4a93-ac3f-7cd57d6d8bcc)) + (pin "18" (uuid f20df342-4ebe-4f08-8a3b-965dc8200844)) + (pin "19" (uuid 4b602eb3-3425-4b09-9d68-67d644e0d1f1)) + (pin "20" (uuid 1f1f018c-b030-4e25-adf3-a4889d71cb88)) + (pin "21" (uuid a11071d8-2693-42bb-94e5-d13554beaf99)) + (pin "22" (uuid cbdca8d1-9073-4aec-afba-b28b6fc2e6c4)) + (pin "23" (uuid 0c7a6f62-5e5f-431c-b571-83b4d74ca5c1)) + (pin "24" (uuid d6bf551d-e784-49ac-8619-dbc7b28b8bc3)) + (pin "25" (uuid 3b4f204c-c14e-47bd-9bf1-0df35df8dc14)) + (pin "26" (uuid 4d4c75d2-b9c9-42b6-a88b-7d2bf902fdf1)) + ) + + (sheet_instances + (path "/" (page "1")) + ) + + (symbol_instances + (path "/8e6c1888-7e7a-49f1-b752-39ff852dd961" + (reference "U101") (unit 1) (value "PORT") (footprint "") + ) + (path "/996ca00d-8080-444b-9d65-ec93d5f43cf9" + (reference "U101") (unit 2) (value "PORT") (footprint "") + ) + (path "/e544c5fd-8eb5-48b3-b5cb-053baeb9a621" + (reference "U101") (unit 3) (value "PORT") (footprint "") + ) + (path "/84cc49ca-19e4-47a7-9336-f8fb937861b1" + (reference "U101") (unit 4) (value "PORT") (footprint "") + ) + (path "/e7a881f3-469e-4107-87be-6eb96219fce8" + (reference "U101") (unit 5) (value "PORT") (footprint "") + ) + (path "/643b1ef4-7e55-4712-b609-6cd363005e90" + (reference "U101") (unit 6) (value "PORT") (footprint "") + ) + (path "/c7dddf59-cef7-4efc-b2c8-69fd0f456a32" + (reference "U101") (unit 7) (value "PORT") (footprint "") + ) + (path "/afd1ad5d-60ac-432b-86be-59a089d3510c" + (reference "U101") (unit 8) (value "PORT") (footprint "") + ) + (path "/670a723f-f6f2-47f2-8017-97e6d3c43a8d" + (reference "U101") (unit 9) (value "PORT") (footprint "") + ) + (path "/1a1e9d64-96dd-4fc5-9158-77a500f71dc7" + (reference "U101") (unit 10) (value "PORT") (footprint "") + ) + (path "/bd0cd8cd-cbf6-448b-9b53-e3f14ed78c28" + (reference "U101") (unit 11) (value "PORT") (footprint "") + ) + (path "/d795a0f1-0ebc-49ab-b27a-554a6eeb394f" + (reference "U101") (unit 12) (value "PORT") (footprint "") + ) + (path "/cbe467ae-6ff1-4fbd-8edc-3e58755524af" + (reference "U101") (unit 13) (value "PORT") (footprint "") + ) + (path "/3d01f60e-d2f3-4299-8822-6a6828794f7d" + (reference "U101") (unit 14) (value "PORT") (footprint "") + ) + (path "/53c58957-ca72-46ec-a71a-82271ad110bc" + (reference "U102") (unit 1) (value "d_nand") (footprint "") + ) + (path "/c67ac81a-0c0f-4240-9bbd-2a371e76e5bb" + (reference "U103") (unit 1) (value "d_nand") (footprint "") + ) + (path "/a30ba25d-38ee-4dd6-b3dc-6bf8802f5d4f" + (reference "U104") (unit 1) (value "d_nand") (footprint "") + ) + (path "/a6ee2d4e-46d5-4440-90d4-7fbf4a20f192" + (reference "U105") (unit 1) (value "d_nand") (footprint "") + ) + (path "/1f87b528-b9e5-4106-958b-02af87736682" + (reference "U106") (unit 1) (value "d_nand") (footprint "") + ) + (path "/e06e6a4f-9724-44d9-abc2-37fff9bc2f20" + (reference "U107") (unit 1) (value "d_nand") (footprint "") + ) + (path "/c1dc7879-d11c-4646-bd25-e64b9e226d7f" + (reference "U108") (unit 1) (value "d_nand") (footprint "") + ) + (path "/0b67ede1-b696-43b4-a00d-a6443ab1c385" + (reference "U109") (unit 1) (value "d_nand") (footprint "") + ) + ) +) diff --git a/library/SubcircuitLibrary/4_nand/4_nand.sub b/library/SubcircuitLibrary/4_nand/4_nand.sub new file mode 100644 index 000000000..58ba5bc09 --- /dev/null +++ b/library/SubcircuitLibrary/4_nand/4_nand.sub @@ -0,0 +1,38 @@ +* Subcircuit 4_nand +.subckt 4_nand net-_u104-pad1_ net-_u104-pad2_ unconnected-_u101-pad3_ net-_u105-pad1_ net-_u105-pad2_ net-_u109-pad3_ unconnected-_u101-pad7_ net-_u108-pad3_ net-_u102-pad1_ net-_u102-pad2_ unconnected-_u101-pad11_ net-_u103-pad1_ net-_u103-pad2_ unconnected-_u101-pad14_ +.title kicad schematic +* u109 net-_u107-pad3_ net-_u107-pad3_ net-_u109-pad3_ d_nand +* u106 net-_u102-pad3_ net-_u103-pad3_ net-_u106-pad3_ d_nand +* u107 net-_u104-pad3_ net-_u105-pad3_ net-_u107-pad3_ d_nand +* u108 net-_u106-pad3_ net-_u106-pad3_ net-_u108-pad3_ d_nand +* u105 net-_u105-pad1_ net-_u105-pad2_ net-_u105-pad3_ d_nand +* u104 net-_u104-pad1_ net-_u104-pad2_ net-_u104-pad3_ d_nand +* u102 net-_u102-pad1_ net-_u102-pad2_ net-_u102-pad3_ d_nand +* u103 net-_u103-pad1_ net-_u103-pad2_ net-_u103-pad3_ d_nand +a1 [net-_u107-pad3_ net-_u107-pad3_ ] net-_u109-pad3_ u109 +a2 [net-_u102-pad3_ net-_u103-pad3_ ] net-_u106-pad3_ u106 +a3 [net-_u104-pad3_ net-_u105-pad3_ ] net-_u107-pad3_ u107 +a4 [net-_u106-pad3_ net-_u106-pad3_ ] net-_u108-pad3_ u108 +a5 [net-_u105-pad1_ net-_u105-pad2_ ] net-_u105-pad3_ u105 +a6 [net-_u104-pad1_ net-_u104-pad2_ ] net-_u104-pad3_ u104 +a7 [net-_u102-pad1_ net-_u102-pad2_ ] net-_u102-pad3_ u102 +a8 [net-_u103-pad1_ net-_u103-pad2_ ] net-_u103-pad3_ u103 +* Schematic Name: d_nand, Ngspice Name: d_nand +.model u109 d_nand(rise_delay=5n fall_delay=5n input_load=1p ) +* Schematic Name: d_nand, Ngspice Name: d_nand +.model u106 d_nand(rise_delay=5n fall_delay=5n input_load=1p ) +* Schematic Name: d_nand, Ngspice Name: d_nand +.model u107 d_nand(rise_delay=5n fall_delay=5n input_load=1p ) +* Schematic Name: d_nand, Ngspice Name: d_nand +.model u108 d_nand(rise_delay=5n fall_delay=5n input_load=1p ) +* Schematic Name: d_nand, Ngspice Name: d_nand +.model u105 d_nand(rise_delay=5n fall_delay=5n input_load=1p ) +* Schematic Name: d_nand, Ngspice Name: d_nand +.model u104 d_nand(rise_delay=5n fall_delay=5n input_load=1p ) +* Schematic Name: d_nand, Ngspice Name: d_nand +.model u102 d_nand(rise_delay=5n fall_delay=5n input_load=1p ) +* Schematic Name: d_nand, Ngspice Name: d_nand +.model u103 d_nand(rise_delay=5n fall_delay=5n input_load=1p ) +* Control Statements + +.ends 4_nand \ No newline at end of file diff --git a/library/SubcircuitLibrary/4_nand/4_nand_Previous_Values.xml b/library/SubcircuitLibrary/4_nand/4_nand_Previous_Values.xml new file mode 100644 index 000000000..0ce194f18 --- /dev/null +++ b/library/SubcircuitLibrary/4_nand/4_nand_Previous_Values.xml @@ -0,0 +1 @@ +dc5d_nand5n5n1pd_nand5n5n1pd_nand5n5n1pd_nand5n5n1pd_nand5n5n1pd_nand5n5n1pd_nand5n5n1pd_nand5n5n1ptruefalsefalseHzHz0Volts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or Amperes00.110secmsms \ No newline at end of file diff --git a/library/SubcircuitLibrary/4_nand/D.lib b/library/SubcircuitLibrary/4_nand/D.lib new file mode 100644 index 000000000..f53bf3e03 --- /dev/null +++ b/library/SubcircuitLibrary/4_nand/D.lib @@ -0,0 +1,2 @@ +.model 1N4148 D(is=2.495E-09 rs=4.755E-01 n=1.679E+00 tt=3.030E-09 cjo=1.700E-12 vj=1 m=1.959E-01 bv=1.000E+02 ibv=1.000E-04) + diff --git a/library/SubcircuitLibrary/4_nand/NPN.lib b/library/SubcircuitLibrary/4_nand/NPN.lib new file mode 100644 index 000000000..be5f3073a --- /dev/null +++ b/library/SubcircuitLibrary/4_nand/NPN.lib @@ -0,0 +1,4 @@ +.model Q2N2222 NPN( Is=14.34f Xti=3 Eg=1.11 Vaf=74.03 Bf=400 Ne=1.307 ++ Ise=14.34f Ikf=0.2847 Xtb=1.5 Br=6.092 Nc=2 Isc=0 Ikr=0 Rc=1 Cjc=7.306p ++ Mjc=0.3416 Vjc=0.75 Fc=0.5 Cje=22.01p Mje=0.377 Vje=0.75 Tr=46.91n Tf=411.1p ++ Itf=0.6 Vtf=1.7 Xtf=3 Rb=10) diff --git a/library/SubcircuitLibrary/4_nand/analysis b/library/SubcircuitLibrary/4_nand/analysis new file mode 100644 index 000000000..89dfa722c --- /dev/null +++ b/library/SubcircuitLibrary/4_nand/analysis @@ -0,0 +1 @@ +.tran 0.1e-03 10e-03 0e-00 \ No newline at end of file diff --git a/library/SubcircuitLibrary/4_nand/eSim_Subckt.kicad_sym b/library/SubcircuitLibrary/4_nand/eSim_Subckt.kicad_sym new file mode 100644 index 000000000..26a39f1be --- /dev/null +++ b/library/SubcircuitLibrary/4_nand/eSim_Subckt.kicad_sym @@ -0,0 +1,6638 @@ +(kicad_symbol_lib (version 20211014) (generator kicad_symbol_editor) + (symbol "10bitDAC" (pin_names (offset 1.016)) (in_bom yes) (on_board yes) + (property "Reference" "X" (id 0) (at 0 1.27 0) + (effects (font (size 1.524 1.524))) + ) + (property "Value" "10bitDAC" (id 1) (at -1.27 -1.27 0) + (effects (font (size 1.524 1.524))) + ) + (property "Footprint" "" (id 2) (at 0 1.27 0) + (effects (font (size 1.524 1.524)) hide) + ) + (property "Datasheet" "" (id 3) (at 0 1.27 0) + (effects (font (size 1.524 1.524)) hide) + ) + (symbol "10bitDAC_0_1" + (rectangle (start -12.7 12.7) (end 10.16 -15.24) + (stroke (width 0) (type default) (color 0 0 0 0)) + (fill (type none)) + ) + ) + (symbol "10bitDAC_1_1" + (pin input line (at -17.78 -12.7 0) (length 5.08) + (name "D0" (effects (font (size 1.27 1.27)))) + (number "1" (effects (font (size 1.27 1.27)))) + ) + (pin input line (at -17.78 10.16 0) (length 5.08) + (name "D9" (effects (font (size 1.27 1.27)))) + (number "10" (effects (font (size 1.27 1.27)))) + ) + (pin output line (at 15.24 8.89 180) (length 5.08) + (name "AnalogOut" (effects (font (size 1.27 1.27)))) + (number "11" (effects (font (size 1.27 1.27)))) + ) + (pin input line (at -17.78 -10.16 0) (length 5.08) + (name "D1" (effects (font (size 1.27 1.27)))) + (number "2" (effects (font (size 1.27 1.27)))) + ) + (pin input line (at -17.78 -7.62 0) (length 5.08) + (name "D2" (effects (font (size 1.27 1.27)))) + (number "3" (effects (font (size 1.27 1.27)))) + ) + (pin input line (at -17.78 -5.08 0) (length 5.08) + (name "D3" (effects (font (size 1.27 1.27)))) + (number "4" (effects (font (size 1.27 1.27)))) + ) + (pin input line (at -17.78 -2.54 0) (length 5.08) + (name "D4" (effects (font (size 1.27 1.27)))) + (number "5" (effects (font (size 1.27 1.27)))) + ) + (pin input line (at -17.78 0 0) (length 5.08) + (name "D5" (effects (font (size 1.27 1.27)))) + (number "6" (effects (font (size 1.27 1.27)))) + ) + (pin input line (at -17.78 2.54 0) (length 5.08) + (name "D6" (effects (font (size 1.27 1.27)))) + (number "7" (effects (font (size 1.27 1.27)))) + ) + (pin input line (at -17.78 5.08 0) (length 5.08) + (name "D7" (effects (font (size 1.27 1.27)))) + (number "8" (effects (font (size 1.27 1.27)))) + ) + (pin input line (at -17.78 7.62 0) (length 5.08) + (name "D8" (effects (font (size 1.27 1.27)))) + (number "9" (effects (font (size 1.27 1.27)))) + ) + ) + ) + (symbol "2BITMUL" (pin_names (offset 1.016)) (in_bom yes) (on_board yes) + (property "Reference" "X" (id 0) (at 0 0 0) + (effects (font (size 1.524 1.524))) + ) + (property "Value" "2BITMUL" (id 1) (at 0 0 0) + (effects (font (size 1.524 1.524))) + ) + (property "Footprint" "" (id 2) (at 0 0 0) + (effects (font (size 1.524 1.524)) hide) + ) + (property "Datasheet" "" (id 3) (at 0 0 0) + (effects (font (size 1.524 1.524)) hide) + ) + (symbol "2BITMUL_0_1" + (rectangle (start -7.62 10.16) (end 7.62 -10.16) + (stroke (width 0) (type default) (color 0 0 0 0)) + (fill (type none)) + ) + ) + (symbol "2BITMUL_1_1" + (pin input line (at -12.7 7.62 0) (length 5.08) + (name "A0" (effects (font (size 1.27 1.27)))) + (number "1" (effects (font (size 1.27 1.27)))) + ) + (pin input line (at -12.7 3.81 0) (length 5.08) + (name "A1" (effects (font (size 1.27 1.27)))) + (number "2" (effects (font (size 1.27 1.27)))) + ) + (pin input line (at -12.7 -1.27 0) (length 5.08) + (name "B0" (effects (font (size 1.27 1.27)))) + (number "3" (effects (font (size 1.27 1.27)))) + ) + (pin input line (at -12.7 -6.35 0) (length 5.08) + (name "B1" (effects (font (size 1.27 1.27)))) + (number "4" (effects (font (size 1.27 1.27)))) + ) + (pin output line (at 12.7 6.35 180) (length 5.08) + (name "M0" (effects (font (size 1.27 1.27)))) + (number "5" (effects (font (size 1.27 1.27)))) + ) + (pin output line (at 12.7 2.54 180) (length 5.08) + (name "M1" (effects (font (size 1.27 1.27)))) + (number "6" (effects (font (size 1.27 1.27)))) + ) + (pin output line (at 12.7 -1.27 180) (length 5.08) + (name "M2" (effects (font (size 1.27 1.27)))) + (number "7" (effects (font (size 1.27 1.27)))) + ) + (pin output line (at 12.7 -6.35 180) (length 5.08) + (name "M3" (effects (font (size 1.27 1.27)))) + (number "8" (effects (font (size 1.27 1.27)))) + ) + ) + ) + (symbol "3_and" (pin_names (offset 1.016)) (in_bom yes) (on_board yes) + (property "Reference" "X" (id 0) (at 2.54 -1.27 0) + (effects (font (size 1.524 1.524))) + ) + (property "Value" "3_and" (id 1) (at 3.81 3.81 0) + (effects (font (size 1.524 1.524))) + ) + (property "Footprint" "" (id 2) (at 0 0 0) + (effects (font (size 1.524 1.524))) + ) + (property "Datasheet" "" (id 3) (at 0 0 0) + (effects (font (size 1.524 1.524))) + ) + (symbol "3_and_0_1" + (polyline + (pts + (xy -3.81 5.08) + (xy 5.08 5.08) + ) + (stroke (width 0) (type default) (color 0 0 0 0)) + (fill (type none)) + ) + (polyline + (pts + (xy -3.81 5.08) + (xy -3.81 -2.54) + (xy 5.08 -2.54) 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1.27)))) + ) + (pin input line (at -3.81 -6.35 90) (length 5.08) + (name "~" (effects (font (size 1.27 1.27)))) + (number "2" (effects (font (size 1.27 1.27)))) + ) + (pin input line (at 8.89 0 180) (length 5.08) + (name "~" (effects (font (size 1.27 1.27)))) + (number "3" (effects (font (size 1.27 1.27)))) + ) + (pin output line (at 3.81 -6.35 90) (length 5.08) + (name "~" (effects (font (size 1.27 1.27)))) + (number "4" (effects (font (size 1.27 1.27)))) + ) + ) + ) +) From 2f7a91b81fccc64136e556ae50befc6e9eeadc75 Mon Sep 17 00:00:00 2001 From: Sakshi Pandey Date: Sat, 24 Jan 2026 13:35:38 +0530 Subject: [PATCH 2/8] SN74LS27 as 3 input NOR GATE --- library/SubcircuitLibrary/3_nor/3_nor.cir | 57 + library/SubcircuitLibrary/3_nor/3_nor.cir.out | 68 + .../SubcircuitLibrary/3_nor/3_nor.kicad_sch | 14 + library/SubcircuitLibrary/3_nor/3_nor.sub | 62 + .../3_nor/3_nor_Previous_Values.xml | 1 + library/SubcircuitLibrary/3_nor/D.lib | 2 + library/SubcircuitLibrary/3_nor/NPN.lib | 4 + .../3_nor/_autosave-3_nor.kicad_sch | 4889 ++++++++++++ .../3_nor/_autosave-3_nor.sch | 1713 ++++ library/SubcircuitLibrary/3_nor/analysis | 1 + .../3_nor/eSim_Subckt.kicad_sym | 6888 +++++++++++++++++ 11 files changed, 13699 insertions(+) create mode 100644 library/SubcircuitLibrary/3_nor/3_nor.cir create mode 100644 library/SubcircuitLibrary/3_nor/3_nor.cir.out create mode 100644 library/SubcircuitLibrary/3_nor/3_nor.kicad_sch create mode 100644 library/SubcircuitLibrary/3_nor/3_nor.sub create mode 100644 library/SubcircuitLibrary/3_nor/3_nor_Previous_Values.xml create mode 100644 library/SubcircuitLibrary/3_nor/D.lib create mode 100644 library/SubcircuitLibrary/3_nor/NPN.lib create mode 100644 library/SubcircuitLibrary/3_nor/_autosave-3_nor.kicad_sch create mode 100644 library/SubcircuitLibrary/3_nor/_autosave-3_nor.sch create mode 100644 library/SubcircuitLibrary/3_nor/analysis create mode 100644 library/SubcircuitLibrary/3_nor/eSim_Subckt.kicad_sym diff --git a/library/SubcircuitLibrary/3_nor/3_nor.cir b/library/SubcircuitLibrary/3_nor/3_nor.cir new file mode 100644 index 000000000..5f2fa706b --- /dev/null +++ b/library/SubcircuitLibrary/3_nor/3_nor.cir @@ -0,0 +1,57 @@ +.title KiCad schematic +R112 Net-_QN116-Pad1_ Net-_R113-Pad1_ 130 +U101 Net-_D101-Pad2_ Net-_D102-Pad2_ Net-_D105-Pad2_ Net-_D106-Pad2_ Net-_D107-Pad2_ Net-_D108-Pad2_ Net-_D109-Pad1_ Net-_D112-Pad2_ Net-_D109-Pad2_ Net-_D110-Pad2_ Net-_D111-Pad2_ Net-_D104-Pad2_ Net-_D103-Pad2_ Net-_R113-Pad1_ PORT +QN113 Net-_QN112-Pad1_ Net-_QN109-Pad1_ Net-_QN112-Pad3_ npn +R110 Net-_QN112-Pad1_ Net-_R113-Pad1_ 1.6K +QN111 Net-_QN111-Pad1_ Net-_QN111-Pad2_ Net-_D107-Pad2_ npn +QN110 Net-_QN110-Pad1_ Net-_QN110-Pad2_ Net-_D106-Pad2_ npn +R108 Net-_R113-Pad1_ Net-_QN110-Pad2_ 4K +QN115 Net-_D108-Pad2_ Net-_QN112-Pad3_ Net-_D109-Pad1_ npn +D108 Net-_D108-Pad1_ Net-_D108-Pad2_ diode +D109 Net-_D109-Pad1_ Net-_D109-Pad2_ diode +R109 Net-_R113-Pad1_ Net-_QN111-Pad2_ 4K +QN116 Net-_QN116-Pad1_ Net-_QN112-Pad1_ Net-_D108-Pad1_ npn +QN112 Net-_QN112-Pad1_ Net-_QN111-Pad1_ Net-_QN112-Pad3_ npn +R111 Net-_D109-Pad1_ Net-_QN112-Pad3_ 1K +QN114 Net-_QN112-Pad1_ Net-_QN110-Pad1_ Net-_QN112-Pad3_ npn +R105 Net-_D109-Pad1_ Net-_QN104-Pad3_ 1K +R106 Net-_QN108-Pad1_ Net-_R113-Pad1_ 130 +QN109 Net-_QN109-Pad1_ Net-_QN109-Pad2_ Net-_D105-Pad2_ npn +R107 Net-_R113-Pad1_ Net-_QN109-Pad2_ 4K +D105 Net-_D109-Pad1_ Net-_D105-Pad2_ diode +D104 Net-_D104-Pad1_ Net-_D104-Pad2_ diode +QN108 Net-_QN108-Pad1_ Net-_QN104-Pad1_ Net-_D104-Pad1_ npn +R104 Net-_QN104-Pad1_ Net-_R113-Pad1_ 1.6K +QN105 Net-_QN104-Pad1_ Net-_QN101-Pad1_ Net-_QN104-Pad3_ npn +D106 Net-_D109-Pad1_ Net-_D106-Pad2_ diode +D107 Net-_D109-Pad1_ Net-_D107-Pad2_ diode +QN106 Net-_QN104-Pad1_ Net-_QN102-Pad1_ Net-_QN104-Pad3_ npn +QN107 Net-_D104-Pad2_ Net-_QN104-Pad3_ Net-_D109-Pad1_ npn +D110 Net-_D109-Pad1_ Net-_D110-Pad2_ diode +QN118 Net-_QN118-Pad1_ Net-_QN118-Pad2_ Net-_D110-Pad2_ npn +R113 Net-_R113-Pad1_ Net-_QN117-Pad2_ 4K +R114 Net-_R113-Pad1_ Net-_QN118-Pad2_ 4K +QN117 Net-_QN117-Pad1_ Net-_QN117-Pad2_ Net-_D109-Pad2_ npn +QN121 Net-_QN120-Pad1_ Net-_QN117-Pad1_ Net-_QN121-Pad3_ npn +R115 Net-_R113-Pad1_ Net-_QN119-Pad2_ 4K +D111 Net-_D109-Pad1_ Net-_D111-Pad2_ diode +QN119 Net-_QN119-Pad1_ Net-_QN119-Pad2_ Net-_D111-Pad2_ npn +QN120 Net-_QN120-Pad1_ Net-_QN119-Pad1_ Net-_QN121-Pad3_ npn +QN122 Net-_QN120-Pad1_ Net-_QN118-Pad1_ Net-_QN121-Pad3_ npn +R117 Net-_D109-Pad1_ Net-_QN121-Pad3_ 1K +R118 Net-_QN124-Pad1_ Net-_R113-Pad1_ 130 +QN124 Net-_QN124-Pad1_ Net-_QN120-Pad1_ Net-_D112-Pad1_ npn +D112 Net-_D112-Pad1_ Net-_D112-Pad2_ diode +R116 Net-_QN120-Pad1_ Net-_R113-Pad1_ 1.6K +QN123 Net-_D112-Pad2_ Net-_QN121-Pad3_ Net-_D109-Pad1_ npn +R102 Net-_R113-Pad1_ Net-_QN102-Pad2_ 4K +QN102 Net-_QN102-Pad1_ Net-_QN102-Pad2_ Net-_D102-Pad2_ npn +R103 Net-_R113-Pad1_ Net-_QN103-Pad2_ 4K +D102 Net-_D109-Pad1_ Net-_D102-Pad2_ diode +QN103 Net-_QN103-Pad1_ Net-_QN103-Pad2_ Net-_D103-Pad2_ npn +D103 Net-_D109-Pad1_ Net-_D103-Pad2_ diode +QN104 Net-_QN104-Pad1_ Net-_QN103-Pad1_ Net-_QN104-Pad3_ npn +D101 Net-_D109-Pad1_ Net-_D101-Pad2_ diode +R101 Net-_R113-Pad1_ Net-_QN101-Pad2_ 4K +QN101 Net-_QN101-Pad1_ Net-_QN101-Pad2_ Net-_D101-Pad2_ npn +.end diff --git a/library/SubcircuitLibrary/3_nor/3_nor.cir.out b/library/SubcircuitLibrary/3_nor/3_nor.cir.out new file mode 100644 index 000000000..8abe2dd6f --- /dev/null +++ b/library/SubcircuitLibrary/3_nor/3_nor.cir.out @@ -0,0 +1,68 @@ +.title kicad schematic + +.include NPN.lib +.include D.lib +r112 net-_qn116-pad1_ net-_r113-pad1_ 130 +* u101 net-_d101-pad2_ net-_d102-pad2_ net-_d105-pad2_ net-_d106-pad2_ net-_d107-pad2_ net-_d108-pad2_ net-_d109-pad1_ net-_d112-pad2_ net-_d109-pad2_ net-_d110-pad2_ net-_d111-pad2_ net-_d104-pad2_ net-_d103-pad2_ net-_r113-pad1_ port +qn113 net-_qn112-pad1_ net-_qn109-pad1_ net-_qn112-pad3_ Q2N2222 +r110 net-_qn112-pad1_ net-_r113-pad1_ 1.6k +qn111 net-_qn111-pad1_ net-_qn111-pad2_ net-_d107-pad2_ Q2N2222 +qn110 net-_qn110-pad1_ net-_qn110-pad2_ net-_d106-pad2_ Q2N2222 +r108 net-_r113-pad1_ net-_qn110-pad2_ 4k +qn115 net-_d108-pad2_ net-_qn112-pad3_ net-_d109-pad1_ Q2N2222 +d108 net-_d108-pad1_ net-_d108-pad2_ 1N4148 +d109 net-_d109-pad1_ net-_d109-pad2_ 1N4148 +r109 net-_r113-pad1_ net-_qn111-pad2_ 4k +qn116 net-_qn116-pad1_ net-_qn112-pad1_ net-_d108-pad1_ Q2N2222 +qn112 net-_qn112-pad1_ net-_qn111-pad1_ net-_qn112-pad3_ Q2N2222 +r111 net-_d109-pad1_ net-_qn112-pad3_ 1k +qn114 net-_qn112-pad1_ net-_qn110-pad1_ net-_qn112-pad3_ Q2N2222 +r105 net-_d109-pad1_ net-_qn104-pad3_ 1k +r106 net-_qn108-pad1_ net-_r113-pad1_ 130 +qn109 net-_qn109-pad1_ net-_qn109-pad2_ net-_d105-pad2_ Q2N2222 +r107 net-_r113-pad1_ net-_qn109-pad2_ 4k +d105 net-_d109-pad1_ net-_d105-pad2_ 1N4148 +d104 net-_d104-pad1_ net-_d104-pad2_ 1N4148 +qn108 net-_qn108-pad1_ net-_qn104-pad1_ net-_d104-pad1_ Q2N2222 +r104 net-_qn104-pad1_ net-_r113-pad1_ 1.6k +qn105 net-_qn104-pad1_ net-_qn101-pad1_ net-_qn104-pad3_ Q2N2222 +d106 net-_d109-pad1_ net-_d106-pad2_ 1N4148 +d107 net-_d109-pad1_ net-_d107-pad2_ 1N4148 +qn106 net-_qn104-pad1_ net-_qn102-pad1_ net-_qn104-pad3_ Q2N2222 +qn107 net-_d104-pad2_ net-_qn104-pad3_ net-_d109-pad1_ Q2N2222 +d110 net-_d109-pad1_ net-_d110-pad2_ 1N4148 +qn118 net-_qn118-pad1_ net-_qn118-pad2_ net-_d110-pad2_ Q2N2222 +r113 net-_r113-pad1_ net-_qn117-pad2_ 4k +r114 net-_r113-pad1_ net-_qn118-pad2_ 4k +qn117 net-_qn117-pad1_ net-_qn117-pad2_ net-_d109-pad2_ Q2N2222 +qn121 net-_qn120-pad1_ net-_qn117-pad1_ net-_qn121-pad3_ Q2N2222 +r115 net-_r113-pad1_ net-_qn119-pad2_ 4k +d111 net-_d109-pad1_ net-_d111-pad2_ 1N4148 +qn119 net-_qn119-pad1_ net-_qn119-pad2_ net-_d111-pad2_ Q2N2222 +qn120 net-_qn120-pad1_ net-_qn119-pad1_ net-_qn121-pad3_ Q2N2222 +qn122 net-_qn120-pad1_ net-_qn118-pad1_ net-_qn121-pad3_ Q2N2222 +r117 net-_d109-pad1_ net-_qn121-pad3_ 1k +r118 net-_qn124-pad1_ net-_r113-pad1_ 130 +qn124 net-_qn124-pad1_ net-_qn120-pad1_ net-_d112-pad1_ Q2N2222 +d112 net-_d112-pad1_ net-_d112-pad2_ 1N4148 +r116 net-_qn120-pad1_ net-_r113-pad1_ 1.6k +qn123 net-_d112-pad2_ net-_qn121-pad3_ net-_d109-pad1_ Q2N2222 +r102 net-_r113-pad1_ net-_qn102-pad2_ 4k +qn102 net-_qn102-pad1_ net-_qn102-pad2_ net-_d102-pad2_ Q2N2222 +r103 net-_r113-pad1_ net-_qn103-pad2_ 4k +d102 net-_d109-pad1_ net-_d102-pad2_ 1N4148 +qn103 net-_qn103-pad1_ net-_qn103-pad2_ net-_d103-pad2_ Q2N2222 +d103 net-_d109-pad1_ net-_d103-pad2_ 1N4148 +qn104 net-_qn104-pad1_ net-_qn103-pad1_ net-_qn104-pad3_ Q2N2222 +d101 net-_d109-pad1_ net-_d101-pad2_ 1N4148 +r101 net-_r113-pad1_ net-_qn101-pad2_ 4k +qn101 net-_qn101-pad1_ net-_qn101-pad2_ net-_d101-pad2_ Q2N2222 +.tran 0.1e-06 50e-06 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/library/SubcircuitLibrary/3_nor/3_nor.kicad_sch b/library/SubcircuitLibrary/3_nor/3_nor.kicad_sch new file mode 100644 index 000000000..a495dd9fd --- /dev/null +++ b/library/SubcircuitLibrary/3_nor/3_nor.kicad_sch @@ -0,0 +1,14 @@ +(kicad_sch (version 20211123) (generator eeschema) + + (uuid 5b1e0762-71a5-4ce2-aa7b-b3983e129f2e) + + (paper "A4") + + (lib_symbols + ) + + + (sheet_instances + (path "/" (page "1")) + ) +) diff --git a/library/SubcircuitLibrary/3_nor/3_nor.sub b/library/SubcircuitLibrary/3_nor/3_nor.sub new file mode 100644 index 000000000..525349d9a --- /dev/null +++ b/library/SubcircuitLibrary/3_nor/3_nor.sub @@ -0,0 +1,62 @@ +* Subcircuit 3_nor +.subckt 3_nor net-_d101-pad2_ net-_d102-pad2_ net-_d105-pad2_ net-_d106-pad2_ net-_d107-pad2_ net-_d108-pad2_ net-_d109-pad1_ net-_d112-pad2_ net-_d109-pad2_ net-_d110-pad2_ net-_d111-pad2_ net-_d104-pad2_ net-_d103-pad2_ net-_r113-pad1_ +.title kicad schematic +.include NPN.lib +.include D.lib +r112 net-_qn116-pad1_ net-_r113-pad1_ 130 +qn113 net-_qn112-pad1_ net-_qn109-pad1_ net-_qn112-pad3_ Q2N2222 +r110 net-_qn112-pad1_ net-_r113-pad1_ 1.6k +qn111 net-_qn111-pad1_ net-_qn111-pad2_ net-_d107-pad2_ Q2N2222 +qn110 net-_qn110-pad1_ net-_qn110-pad2_ net-_d106-pad2_ Q2N2222 +r108 net-_r113-pad1_ net-_qn110-pad2_ 4k +qn115 net-_d108-pad2_ net-_qn112-pad3_ net-_d109-pad1_ Q2N2222 +d108 net-_d108-pad1_ net-_d108-pad2_ 1N4148 +d109 net-_d109-pad1_ net-_d109-pad2_ 1N4148 +r109 net-_r113-pad1_ net-_qn111-pad2_ 4k +qn116 net-_qn116-pad1_ net-_qn112-pad1_ net-_d108-pad1_ Q2N2222 +qn112 net-_qn112-pad1_ net-_qn111-pad1_ net-_qn112-pad3_ Q2N2222 +r111 net-_d109-pad1_ net-_qn112-pad3_ 1k +qn114 net-_qn112-pad1_ net-_qn110-pad1_ net-_qn112-pad3_ Q2N2222 +r105 net-_d109-pad1_ net-_qn104-pad3_ 1k +r106 net-_qn108-pad1_ net-_r113-pad1_ 130 +qn109 net-_qn109-pad1_ net-_qn109-pad2_ net-_d105-pad2_ Q2N2222 +r107 net-_r113-pad1_ net-_qn109-pad2_ 4k +d105 net-_d109-pad1_ net-_d105-pad2_ 1N4148 +d104 net-_d104-pad1_ net-_d104-pad2_ 1N4148 +qn108 net-_qn108-pad1_ net-_qn104-pad1_ net-_d104-pad1_ Q2N2222 +r104 net-_qn104-pad1_ net-_r113-pad1_ 1.6k +qn105 net-_qn104-pad1_ net-_qn101-pad1_ net-_qn104-pad3_ Q2N2222 +d106 net-_d109-pad1_ net-_d106-pad2_ 1N4148 +d107 net-_d109-pad1_ net-_d107-pad2_ 1N4148 +qn106 net-_qn104-pad1_ net-_qn102-pad1_ net-_qn104-pad3_ Q2N2222 +qn107 net-_d104-pad2_ net-_qn104-pad3_ net-_d109-pad1_ Q2N2222 +d110 net-_d109-pad1_ net-_d110-pad2_ 1N4148 +qn118 net-_qn118-pad1_ net-_qn118-pad2_ net-_d110-pad2_ Q2N2222 +r113 net-_r113-pad1_ net-_qn117-pad2_ 4k +r114 net-_r113-pad1_ net-_qn118-pad2_ 4k +qn117 net-_qn117-pad1_ net-_qn117-pad2_ net-_d109-pad2_ Q2N2222 +qn121 net-_qn120-pad1_ net-_qn117-pad1_ net-_qn121-pad3_ Q2N2222 +r115 net-_r113-pad1_ net-_qn119-pad2_ 4k +d111 net-_d109-pad1_ net-_d111-pad2_ 1N4148 +qn119 net-_qn119-pad1_ net-_qn119-pad2_ net-_d111-pad2_ Q2N2222 +qn120 net-_qn120-pad1_ net-_qn119-pad1_ net-_qn121-pad3_ Q2N2222 +qn122 net-_qn120-pad1_ net-_qn118-pad1_ net-_qn121-pad3_ Q2N2222 +r117 net-_d109-pad1_ net-_qn121-pad3_ 1k +r118 net-_qn124-pad1_ net-_r113-pad1_ 130 +qn124 net-_qn124-pad1_ net-_qn120-pad1_ net-_d112-pad1_ Q2N2222 +d112 net-_d112-pad1_ net-_d112-pad2_ 1N4148 +r116 net-_qn120-pad1_ net-_r113-pad1_ 1.6k +qn123 net-_d112-pad2_ net-_qn121-pad3_ net-_d109-pad1_ Q2N2222 +r102 net-_r113-pad1_ net-_qn102-pad2_ 4k +qn102 net-_qn102-pad1_ net-_qn102-pad2_ net-_d102-pad2_ Q2N2222 +r103 net-_r113-pad1_ net-_qn103-pad2_ 4k +d102 net-_d109-pad1_ net-_d102-pad2_ 1N4148 +qn103 net-_qn103-pad1_ net-_qn103-pad2_ net-_d103-pad2_ Q2N2222 +d103 net-_d109-pad1_ net-_d103-pad2_ 1N4148 +qn104 net-_qn104-pad1_ net-_qn103-pad1_ net-_qn104-pad3_ Q2N2222 +d101 net-_d109-pad1_ net-_d101-pad2_ 1N4148 +r101 net-_r113-pad1_ net-_qn101-pad2_ 4k +qn101 net-_qn101-pad1_ net-_qn101-pad2_ net-_d101-pad2_ Q2N2222 +* Control Statements + +.ends 3_nor \ No newline at end of file diff --git a/library/SubcircuitLibrary/3_nor/3_nor_Previous_Values.xml b/library/SubcircuitLibrary/3_nor/3_nor_Previous_Values.xml new file mode 100644 index 000000000..95c51d4b7 --- /dev/null +++ b/library/SubcircuitLibrary/3_nor/3_nor_Previous_Values.xml @@ -0,0 +1 @@ +C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.libC:\FOSSEE\eSim\library\deviceModelLibrary\Diode\D.libC:\FOSSEE\eSim\library\deviceModelLibrary\Diode\D.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.libC:\FOSSEE\eSim\library\deviceModelLibrary\Diode\D.libC:\FOSSEE\eSim\library\deviceModelLibrary\Diode\D.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.libC:\FOSSEE\eSim\library\deviceModelLibrary\Diode\D.libC:\FOSSEE\eSim\library\deviceModelLibrary\Diode\D.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.libC:\FOSSEE\eSim\library\deviceModelLibrary\Diode\D.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.libC:\FOSSEE\eSim\library\deviceModelLibrary\Diode\D.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.libC:\FOSSEE\eSim\library\deviceModelLibrary\Diode\D.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.libC:\FOSSEE\eSim\library\deviceModelLibrary\Diode\D.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.libC:\FOSSEE\eSim\library\deviceModelLibrary\Diode\D.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.libC:\FOSSEE\eSim\library\deviceModelLibrary\Diode\D.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.libtruefalsefalseHzHz0Volts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or Amperes00.150secusus \ No newline at end of file diff --git a/library/SubcircuitLibrary/3_nor/D.lib b/library/SubcircuitLibrary/3_nor/D.lib new file mode 100644 index 000000000..f53bf3e03 --- /dev/null +++ b/library/SubcircuitLibrary/3_nor/D.lib @@ -0,0 +1,2 @@ +.model 1N4148 D(is=2.495E-09 rs=4.755E-01 n=1.679E+00 tt=3.030E-09 cjo=1.700E-12 vj=1 m=1.959E-01 bv=1.000E+02 ibv=1.000E-04) + diff --git a/library/SubcircuitLibrary/3_nor/NPN.lib b/library/SubcircuitLibrary/3_nor/NPN.lib new file mode 100644 index 000000000..be5f3073a --- /dev/null +++ b/library/SubcircuitLibrary/3_nor/NPN.lib @@ -0,0 +1,4 @@ +.model Q2N2222 NPN( Is=14.34f Xti=3 Eg=1.11 Vaf=74.03 Bf=400 Ne=1.307 ++ Ise=14.34f Ikf=0.2847 Xtb=1.5 Br=6.092 Nc=2 Isc=0 Ikr=0 Rc=1 Cjc=7.306p ++ Mjc=0.3416 Vjc=0.75 Fc=0.5 Cje=22.01p Mje=0.377 Vje=0.75 Tr=46.91n Tf=411.1p ++ Itf=0.6 Vtf=1.7 Xtf=3 Rb=10) diff --git a/library/SubcircuitLibrary/3_nor/_autosave-3_nor.kicad_sch b/library/SubcircuitLibrary/3_nor/_autosave-3_nor.kicad_sch new file mode 100644 index 000000000..9eb4f1fab --- /dev/null +++ b/library/SubcircuitLibrary/3_nor/_autosave-3_nor.kicad_sch @@ -0,0 +1,4889 @@ +(kicad_sch (version 20211123) (generator eeschema) + + (uuid ee2972f1-1e05-453d-822f-214bedddf339) + + (paper "A3") + + (lib_symbols + (symbol "LTspice_sym:diode" (pin_numbers hide) (pin_names (offset 0.0254) hide) (in_bom yes) (on_board yes) + (property "Reference" "D" (id 0) (at 1.905 0 0) + (effects (font (size 1.27 1.27)) (justify left)) + ) + (property "Value" "diode" (id 1) (at 1.905 -5.08 0) + (effects (font (size 1.27 1.27)) (justify left)) + ) + (property "Footprint" "" (id 2) (at 0 0 0) + (effects (font (size 1.27 1.27)) hide) + ) + (property "Datasheet" "" (id 3) (at 0 0 0) + (effects (font (size 1.27 1.27)) hide) + ) + (property "Field5" "D" (id 5) (at 1.905 -5.08 0) + (effects (font (size 1.27 1.27)) (justify left) hide) + ) + (property "ki_fp_filters" "D_*" (id 4) (at 0 0 0) + (effects (font (size 1.27 1.27)) hide) + ) + (symbol "diode_0_0" + (polyline + (pts + (xy 0 -3.4798) + (xy 2.54 -3.4798) + ) + (stroke (width 0) (type default) (color 0 0 0 0)) + (fill (type none)) + ) + (polyline + (pts + (xy 0 -1.5748) + (xy 1.27 -3.4798) + ) + (stroke (width 0) (type default) (color 0 0 0 0)) + (fill (type none)) + ) + (polyline + (pts + (xy 0 -1.5748) + (xy 2.54 -1.5748) + ) + (stroke (width 0) (type default) (color 0 0 0 0)) + (fill (type none)) + ) + (polyline + (pts + (xy 1.27 -3.4798) + (xy 1.27 -5.08) + ) + (stroke (width 0) (type default) (color 0 0 0 0)) + (fill (type none)) + ) + (polyline + (pts + (xy 1.27 0) + (xy 1.27 -1.5748) + ) + (stroke (width 0) (type default) (color 0 0 0 0)) + (fill (type none)) + ) + (polyline + (pts + (xy 2.54 -1.5748) + (xy 1.27 -3.4798) + ) + (stroke (width 0) (type default) (color 0 0 0 0)) + (fill (type none)) + ) + ) + (symbol "diode_1_1" + (pin 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1.27)))) + ) + (pin input line (at -3.81 -6.35 90) (length 5.08) + (name "~" (effects (font (size 1.27 1.27)))) + (number "2" (effects (font (size 1.27 1.27)))) + ) + (pin input line (at 8.89 0 180) (length 5.08) + (name "~" (effects (font (size 1.27 1.27)))) + (number "3" (effects (font (size 1.27 1.27)))) + ) + (pin output line (at 3.81 -6.35 90) (length 5.08) + (name "~" (effects (font (size 1.27 1.27)))) + (number "4" (effects (font (size 1.27 1.27)))) + ) + ) + ) +) From 928e92040d667414d749560f4b37ed1330e2be41 Mon Sep 17 00:00:00 2001 From: Sakshi Pandey Date: Sat, 24 Jan 2026 13:37:40 +0530 Subject: [PATCH 3/8] SN74157 as Quad 2:1 MUX --- library/SubcircuitLibrary/2x1_mux/2x1_mux.cir | 19 + .../SubcircuitLibrary/2x1_mux/2x1_mux.cir.out | 53 + .../2x1_mux/2x1_mux.kicad_prl | 75 + .../2x1_mux/2x1_mux.kicad_pro | 294 + .../2x1_mux/2x1_mux.kicad_sch | 1820 +++++ library/SubcircuitLibrary/2x1_mux/2x1_mux.sub | 47 + .../2x1_mux/2x1_mux_Previous_Values.xml | 1 + .../SubcircuitLibrary/2x1_mux/3_and-cache.lib | 61 + library/SubcircuitLibrary/2x1_mux/3_and.cir | 13 + .../SubcircuitLibrary/2x1_mux/3_and.cir.out | 20 + library/SubcircuitLibrary/2x1_mux/3_and.pro | 43 + library/SubcircuitLibrary/2x1_mux/3_and.sch | 130 + library/SubcircuitLibrary/2x1_mux/3_and.sub | 14 + .../2x1_mux/3_and_Previous_Values.xml | 1 + .../2x1_mux/_autosave-2x1_mux.sch | 529 ++ library/SubcircuitLibrary/2x1_mux/analysis | 1 + .../2x1_mux/eSim_Subckt.kicad_sym | 7120 +++++++++++++++++ 17 files changed, 10241 insertions(+) create mode 100644 library/SubcircuitLibrary/2x1_mux/2x1_mux.cir create mode 100644 library/SubcircuitLibrary/2x1_mux/2x1_mux.cir.out create mode 100644 library/SubcircuitLibrary/2x1_mux/2x1_mux.kicad_prl create mode 100644 library/SubcircuitLibrary/2x1_mux/2x1_mux.kicad_pro create mode 100644 library/SubcircuitLibrary/2x1_mux/2x1_mux.kicad_sch create mode 100644 library/SubcircuitLibrary/2x1_mux/2x1_mux.sub create mode 100644 library/SubcircuitLibrary/2x1_mux/2x1_mux_Previous_Values.xml create mode 100644 library/SubcircuitLibrary/2x1_mux/3_and-cache.lib create mode 100644 library/SubcircuitLibrary/2x1_mux/3_and.cir create mode 100644 library/SubcircuitLibrary/2x1_mux/3_and.cir.out create mode 100644 library/SubcircuitLibrary/2x1_mux/3_and.pro create mode 100644 library/SubcircuitLibrary/2x1_mux/3_and.sch create mode 100644 library/SubcircuitLibrary/2x1_mux/3_and.sub create mode 100644 library/SubcircuitLibrary/2x1_mux/3_and_Previous_Values.xml create mode 100644 library/SubcircuitLibrary/2x1_mux/_autosave-2x1_mux.sch create mode 100644 library/SubcircuitLibrary/2x1_mux/analysis create mode 100644 library/SubcircuitLibrary/2x1_mux/eSim_Subckt.kicad_sym diff --git a/library/SubcircuitLibrary/2x1_mux/2x1_mux.cir b/library/SubcircuitLibrary/2x1_mux/2x1_mux.cir new file mode 100644 index 000000000..fb99f793a --- /dev/null +++ b/library/SubcircuitLibrary/2x1_mux/2x1_mux.cir @@ -0,0 +1,19 @@ +.title KiCad schematic +U101 Net-_U101-Pad1_ Net-_U101-Pad2_ Net-_U101-Pad3_ Net-_U101-Pad4_ Net-_U101-Pad5_ Net-_U101-Pad6_ Net-_U101-Pad7_ unconnected-_U101-Pad8_ Net-_U101-Pad9_ Net-_U101-Pad10_ Net-_U101-Pad11_ Net-_U101-Pad12_ Net-_U101-Pad13_ Net-_U101-Pad14_ Net-_U101-Pad15_ unconnected-_U101-Pad16_ PORT +U102 Net-_U101-Pad15_ Net-_U102-Pad2_ d_inverter +U103 Net-_U101-Pad1_ Net-_U103-Pad2_ d_inverter +U104 Net-_U102-Pad2_ Net-_U104-Pad2_ d_buffer +U105 Net-_U103-Pad2_ Net-_U105-Pad2_ d_inverter +U106 Net-_U106-Pad1_ Net-_U106-Pad2_ Net-_U101-Pad12_ d_or +X108 Net-_U101-Pad13_ Net-_U105-Pad2_ Net-_U104-Pad2_ Net-_U106-Pad2_ 3_and +X107 Net-_U101-Pad14_ Net-_U103-Pad2_ Net-_U104-Pad2_ Net-_U106-Pad1_ 3_and +X106 Net-_U101-Pad10_ Net-_U105-Pad2_ Net-_U104-Pad2_ Net-_U107-Pad2_ 3_and +X104 Net-_U101-Pad6_ Net-_U105-Pad2_ Net-_U104-Pad2_ Net-_U108-Pad2_ 3_and +X105 Net-_U101-Pad11_ Net-_U103-Pad2_ Net-_U104-Pad2_ Net-_U107-Pad1_ 3_and +U107 Net-_U107-Pad1_ Net-_U107-Pad2_ Net-_U101-Pad9_ d_or +U108 Net-_U108-Pad1_ Net-_U108-Pad2_ Net-_U101-Pad7_ d_or +U109 Net-_U109-Pad1_ Net-_U109-Pad2_ Net-_U101-Pad4_ d_or +X101 Net-_U101-Pad2_ Net-_U103-Pad2_ Net-_U104-Pad2_ Net-_U109-Pad1_ 3_and +X102 Net-_U101-Pad3_ Net-_U105-Pad2_ Net-_U104-Pad2_ Net-_U109-Pad2_ 3_and +X103 Net-_U101-Pad5_ Net-_U103-Pad2_ Net-_U104-Pad2_ Net-_U108-Pad1_ 3_and +.end diff --git a/library/SubcircuitLibrary/2x1_mux/2x1_mux.cir.out b/library/SubcircuitLibrary/2x1_mux/2x1_mux.cir.out new file mode 100644 index 000000000..a2952d5ed --- /dev/null +++ b/library/SubcircuitLibrary/2x1_mux/2x1_mux.cir.out @@ -0,0 +1,53 @@ +.title kicad schematic + +.include 3_and.sub +* u101 net-_u101-pad1_ net-_u101-pad2_ net-_u101-pad3_ net-_u101-pad4_ net-_u101-pad5_ net-_u101-pad6_ net-_u101-pad7_ unconnected-_u101-pad8_ net-_u101-pad9_ net-_u101-pad10_ net-_u101-pad11_ net-_u101-pad12_ net-_u101-pad13_ net-_u101-pad14_ net-_u101-pad15_ unconnected-_u101-pad16_ port +* u102 net-_u101-pad15_ net-_u102-pad2_ d_inverter +* u103 net-_u101-pad1_ net-_u103-pad2_ d_inverter +* u104 net-_u102-pad2_ net-_u104-pad2_ d_buffer +* u105 net-_u103-pad2_ net-_u105-pad2_ d_inverter +* u106 net-_u106-pad1_ net-_u106-pad2_ net-_u101-pad12_ d_or +x108 net-_u101-pad13_ net-_u105-pad2_ net-_u104-pad2_ net-_u106-pad2_ 3_and +x107 net-_u101-pad14_ net-_u103-pad2_ net-_u104-pad2_ net-_u106-pad1_ 3_and +x106 net-_u101-pad10_ net-_u105-pad2_ net-_u104-pad2_ net-_u107-pad2_ 3_and +x104 net-_u101-pad6_ net-_u105-pad2_ net-_u104-pad2_ net-_u108-pad2_ 3_and +x105 net-_u101-pad11_ net-_u103-pad2_ net-_u104-pad2_ net-_u107-pad1_ 3_and +* u107 net-_u107-pad1_ net-_u107-pad2_ net-_u101-pad9_ d_or +* u108 net-_u108-pad1_ net-_u108-pad2_ net-_u101-pad7_ d_or +* u109 net-_u109-pad1_ net-_u109-pad2_ net-_u101-pad4_ d_or +x101 net-_u101-pad2_ net-_u103-pad2_ net-_u104-pad2_ net-_u109-pad1_ 3_and +x102 net-_u101-pad3_ net-_u105-pad2_ net-_u104-pad2_ net-_u109-pad2_ 3_and +x103 net-_u101-pad5_ net-_u103-pad2_ net-_u104-pad2_ net-_u108-pad1_ 3_and +a1 net-_u101-pad15_ net-_u102-pad2_ u102 +a2 net-_u101-pad1_ net-_u103-pad2_ u103 +a3 net-_u102-pad2_ net-_u104-pad2_ u104 +a4 net-_u103-pad2_ net-_u105-pad2_ u105 +a5 [net-_u106-pad1_ net-_u106-pad2_ ] net-_u101-pad12_ u106 +a6 [net-_u107-pad1_ net-_u107-pad2_ ] net-_u101-pad9_ u107 +a7 [net-_u108-pad1_ net-_u108-pad2_ ] net-_u101-pad7_ u108 +a8 [net-_u109-pad1_ net-_u109-pad2_ ] net-_u101-pad4_ u109 +* Schematic Name: d_inverter, Ngspice Name: d_inverter +.model u102 d_inverter(rise_delay=1n fall_delay=0.7n input_load=1.0e-12 ) +* Schematic Name: d_inverter, Ngspice Name: d_inverter +.model u103 d_inverter(rise_delay=1n fall_delay=0.7n input_load=1.0e-12 ) +* Schematic Name: d_buffer, Ngspice Name: d_buffer +.model u104 d_buffer(rise_delay=2n fall_delay=2n input_load=1.0e-12 ) +* Schematic Name: d_inverter, Ngspice Name: d_inverter +.model u105 d_inverter(rise_delay=1n fall_delay=0.7n input_load=1.0e-12 ) +* Schematic Name: d_or, Ngspice Name: d_or +.model u106 d_or(rise_delay=1.5n fall_delay=1.2n input_load=1.0e-12 ) +* Schematic Name: d_or, Ngspice Name: d_or +.model u107 d_or(rise_delay=1.5n fall_delay=1.2n input_load=1.0e-12 ) +* Schematic Name: d_or, Ngspice Name: d_or +.model u108 d_or(rise_delay=1.5n fall_delay=1.2n input_load=1.0e-12 ) +* Schematic Name: d_or, Ngspice Name: d_or +.model u109 d_or(rise_delay=1.5n fall_delay=1.2n input_load=1.0e-12 ) +.tran 0.1e-09 100e-09 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/library/SubcircuitLibrary/2x1_mux/2x1_mux.kicad_prl b/library/SubcircuitLibrary/2x1_mux/2x1_mux.kicad_prl new file mode 100644 index 000000000..49081a81e --- /dev/null +++ b/library/SubcircuitLibrary/2x1_mux/2x1_mux.kicad_prl @@ -0,0 +1,75 @@ +{ + "board": { + "active_layer": 0, + "active_layer_preset": "", + "auto_track_width": true, + "hidden_nets": [], + "high_contrast_mode": 0, + "net_color_mode": 1, + "opacity": { + "pads": 1.0, + "tracks": 1.0, + "vias": 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"X108") (unit 1) (value "3_and") (footprint "") + ) + ) +) diff --git a/library/SubcircuitLibrary/2x1_mux/2x1_mux.sub b/library/SubcircuitLibrary/2x1_mux/2x1_mux.sub new file mode 100644 index 000000000..836d7cab8 --- /dev/null +++ b/library/SubcircuitLibrary/2x1_mux/2x1_mux.sub @@ -0,0 +1,47 @@ +* Subcircuit 2x1_mux +.subckt 2x1_mux net-_u101-pad1_ net-_u101-pad2_ net-_u101-pad3_ net-_u101-pad4_ net-_u101-pad5_ net-_u101-pad6_ net-_u101-pad7_ unconnected-_u101-pad8_ net-_u101-pad9_ net-_u101-pad10_ net-_u101-pad11_ net-_u101-pad12_ net-_u101-pad13_ net-_u101-pad14_ net-_u101-pad15_ unconnected-_u101-pad16_ +.title kicad schematic +.include 3_and.sub +* u102 net-_u101-pad15_ net-_u102-pad2_ d_inverter +* u103 net-_u101-pad1_ net-_u103-pad2_ d_inverter +* u104 net-_u102-pad2_ net-_u104-pad2_ d_buffer +* u105 net-_u103-pad2_ net-_u105-pad2_ d_inverter +* u106 net-_u106-pad1_ net-_u106-pad2_ net-_u101-pad12_ d_or +x108 net-_u101-pad13_ net-_u105-pad2_ net-_u104-pad2_ net-_u106-pad2_ 3_and +x107 net-_u101-pad14_ net-_u103-pad2_ net-_u104-pad2_ net-_u106-pad1_ 3_and +x106 net-_u101-pad10_ net-_u105-pad2_ net-_u104-pad2_ net-_u107-pad2_ 3_and +x104 net-_u101-pad6_ net-_u105-pad2_ net-_u104-pad2_ net-_u108-pad2_ 3_and +x105 net-_u101-pad11_ net-_u103-pad2_ net-_u104-pad2_ net-_u107-pad1_ 3_and +* u107 net-_u107-pad1_ net-_u107-pad2_ net-_u101-pad9_ d_or +* u108 net-_u108-pad1_ net-_u108-pad2_ net-_u101-pad7_ d_or +* u109 net-_u109-pad1_ net-_u109-pad2_ net-_u101-pad4_ d_or +x101 net-_u101-pad2_ net-_u103-pad2_ net-_u104-pad2_ net-_u109-pad1_ 3_and +x102 net-_u101-pad3_ net-_u105-pad2_ net-_u104-pad2_ net-_u109-pad2_ 3_and +x103 net-_u101-pad5_ net-_u103-pad2_ net-_u104-pad2_ net-_u108-pad1_ 3_and +a1 net-_u101-pad15_ net-_u102-pad2_ u102 +a2 net-_u101-pad1_ net-_u103-pad2_ u103 +a3 net-_u102-pad2_ net-_u104-pad2_ u104 +a4 net-_u103-pad2_ net-_u105-pad2_ u105 +a5 [net-_u106-pad1_ net-_u106-pad2_ ] net-_u101-pad12_ u106 +a6 [net-_u107-pad1_ net-_u107-pad2_ ] net-_u101-pad9_ u107 +a7 [net-_u108-pad1_ net-_u108-pad2_ ] net-_u101-pad7_ u108 +a8 [net-_u109-pad1_ net-_u109-pad2_ ] net-_u101-pad4_ u109 +* Schematic Name: d_inverter, Ngspice Name: d_inverter +.model u102 d_inverter(rise_delay=1n fall_delay=0.7n input_load=1.0e-12 ) +* Schematic Name: d_inverter, Ngspice Name: d_inverter +.model u103 d_inverter(rise_delay=1n fall_delay=0.7n input_load=1.0e-12 ) +* Schematic Name: d_buffer, Ngspice Name: d_buffer +.model u104 d_buffer(rise_delay=2n fall_delay=2n input_load=1.0e-12 ) +* Schematic Name: d_inverter, Ngspice Name: d_inverter +.model u105 d_inverter(rise_delay=1n fall_delay=0.7n input_load=1.0e-12 ) +* Schematic Name: d_or, Ngspice Name: d_or +.model u106 d_or(rise_delay=1.5n fall_delay=1.2n input_load=1.0e-12 ) +* Schematic Name: d_or, Ngspice Name: d_or +.model u107 d_or(rise_delay=1.5n fall_delay=1.2n input_load=1.0e-12 ) +* Schematic Name: d_or, Ngspice Name: d_or +.model u108 d_or(rise_delay=1.5n fall_delay=1.2n input_load=1.0e-12 ) +* Schematic Name: d_or, Ngspice Name: d_or +.model u109 d_or(rise_delay=1.5n fall_delay=1.2n input_load=1.0e-12 ) +* Control Statements + +.ends 2x1_mux \ No newline at end of file diff --git a/library/SubcircuitLibrary/2x1_mux/2x1_mux_Previous_Values.xml b/library/SubcircuitLibrary/2x1_mux/2x1_mux_Previous_Values.xml new file mode 100644 index 000000000..e04d3a9aa --- /dev/null +++ b/library/SubcircuitLibrary/2x1_mux/2x1_mux_Previous_Values.xml @@ -0,0 +1 @@ +d_inverter1n0.7nd_inverter1n0.7nd_buffer2n2nd_inverter1n0.7nd_or1.5n1.2nd_or1.5n1.2nd_or1.5n1.2nd_or1.5n1.2nC:\FOSSEE\eSim\library\SubcircuitLibrary\3_andC:\FOSSEE\eSim\library\SubcircuitLibrary\3_andC:\FOSSEE\eSim\library\SubcircuitLibrary\3_andC:\FOSSEE\eSim\library\SubcircuitLibrary\3_andC:\FOSSEE\eSim\library\SubcircuitLibrary\3_andC:\FOSSEE\eSim\library\SubcircuitLibrary\3_andC:\FOSSEE\eSim\library\SubcircuitLibrary\3_andC:\FOSSEE\eSim\library\SubcircuitLibrary\3_andtruefalsefalseHzHz0Volts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or Amperes00.1100secnsns \ No newline at end of file diff --git a/library/SubcircuitLibrary/2x1_mux/3_and-cache.lib b/library/SubcircuitLibrary/2x1_mux/3_and-cache.lib new file mode 100644 index 000000000..af0586415 --- /dev/null +++ b/library/SubcircuitLibrary/2x1_mux/3_and-cache.lib @@ -0,0 +1,61 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# PORT +# +DEF PORT U 0 40 Y Y 26 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +X ~ 9 250 0 100 L 30 30 9 1 B +X ~ 10 250 0 100 L 30 30 10 1 B +X ~ 11 250 0 100 L 30 30 11 1 B +X ~ 12 250 0 100 L 30 30 12 1 B +X ~ 13 250 0 100 L 30 30 13 1 B +X ~ 14 250 0 100 L 30 30 14 1 B +X ~ 15 250 0 100 L 30 30 15 1 B +X ~ 16 250 0 100 L 30 30 16 1 B +X ~ 17 250 0 100 L 30 30 17 1 B +X ~ 18 250 0 100 L 30 30 18 1 B +X ~ 19 250 0 100 L 30 30 19 1 B +X ~ 20 250 0 100 L 30 30 20 1 B +X ~ 21 250 0 100 L 30 30 21 1 B +X ~ 22 250 0 100 L 30 30 22 1 B +X ~ 23 250 0 100 L 30 30 23 1 B +X ~ 24 250 0 100 L 30 30 24 1 B +X ~ 25 250 0 100 L 30 30 25 1 B +X ~ 26 250 0 100 L 30 30 26 1 B +ENDDRAW +ENDDEF +# +# d_and +# +DEF d_and U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_and" 50 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 149 50 100 -894 0 0 1 0 N 150 -50 250 50 +A 150 49 100 6 900 0 1 0 N 250 50 150 150 +P 4 0 1 0 150 -50 -250 -50 -250 150 150 150 N +X IN1 1 -450 100 200 R 50 50 1 1 I +X IN2 2 -450 0 200 R 50 50 1 1 I +X OUT 3 450 50 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +#End Library diff --git a/library/SubcircuitLibrary/2x1_mux/3_and.cir b/library/SubcircuitLibrary/2x1_mux/3_and.cir new file mode 100644 index 000000000..ba296cf01 --- /dev/null +++ b/library/SubcircuitLibrary/2x1_mux/3_and.cir @@ -0,0 +1,13 @@ +* C:\Users\malli\eSim\src\SubcircuitLibrary\3_and\3_and.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: 03/26/19 18:42:57 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +U2 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U2-Pad3_ d_and +U3 Net-_U2-Pad3_ Net-_U1-Pad3_ Net-_U1-Pad4_ d_and +U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ PORT + +.end diff --git a/library/SubcircuitLibrary/2x1_mux/3_and.cir.out b/library/SubcircuitLibrary/2x1_mux/3_and.cir.out new file mode 100644 index 000000000..d7cf79a07 --- /dev/null +++ b/library/SubcircuitLibrary/2x1_mux/3_and.cir.out @@ -0,0 +1,20 @@ +* c:\users\malli\esim\src\subcircuitlibrary\3_and\3_and.cir + +* u2 net-_u1-pad1_ net-_u1-pad2_ net-_u2-pad3_ d_and +* u3 net-_u2-pad3_ net-_u1-pad3_ net-_u1-pad4_ d_and +* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ port +a1 [net-_u1-pad1_ net-_u1-pad2_ ] net-_u2-pad3_ u2 +a2 [net-_u2-pad3_ net-_u1-pad3_ ] net-_u1-pad4_ u3 +* Schematic Name: d_and, NgSpice Name: d_and +.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u3 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +.tran 0e-00 0e-00 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/library/SubcircuitLibrary/2x1_mux/3_and.pro b/library/SubcircuitLibrary/2x1_mux/3_and.pro new file mode 100644 index 000000000..00597a5ad --- /dev/null +++ b/library/SubcircuitLibrary/2x1_mux/3_and.pro @@ -0,0 +1,43 @@ +update=05/31/19 15:26:09 +version=1 +last_client=eeschema +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir=../../../kicadSchematicLibrary +[eeschema/libraries] +LibName1=eSim_Analog +LibName2=eSim_Devices +LibName3=eSim_Digital +LibName4=eSim_Hybrid +LibName5=eSim_Miscellaneous +LibName6=eSim_Plot +LibName7=eSim_Power +LibName8=eSim_User +LibName9=eSim_Sources +LibName10=eSim_Subckt diff --git a/library/SubcircuitLibrary/2x1_mux/3_and.sch b/library/SubcircuitLibrary/2x1_mux/3_and.sch new file mode 100644 index 000000000..d6ac89f95 --- /dev/null +++ b/library/SubcircuitLibrary/2x1_mux/3_and.sch @@ -0,0 +1,130 @@ +EESchema Schematic File Version 2 +LIBS:power +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:valves +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Plot +LIBS:eSim_Power +LIBS:eSim_PSpice +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:eSim_User +LIBS:3_and-cache +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L d_and U2 +U 1 1 5C9A24D8 +P 4250 2700 +F 0 "U2" H 4250 2700 60 0000 C CNN +F 1 "d_and" H 4300 2800 60 0000 C CNN +F 2 "" H 4250 2700 60 0000 C CNN +F 3 "" H 4250 2700 60 0000 C CNN + 1 4250 2700 + 1 0 0 -1 +$EndComp +$Comp +L d_and U3 +U 1 1 5C9A2538 +P 5150 2900 +F 0 "U3" H 5150 2900 60 0000 C CNN +F 1 "d_and" H 5200 3000 60 0000 C CNN +F 2 "" H 5150 2900 60 0000 C CNN +F 3 "" H 5150 2900 60 0000 C CNN + 1 5150 2900 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 1 1 5C9A259A +P 3050 2600 +F 0 "U1" H 3100 2700 30 0000 C CNN +F 1 "PORT" H 3050 2600 30 0000 C CNN +F 2 "" H 3050 2600 60 0000 C CNN +F 3 "" H 3050 2600 60 0000 C CNN + 1 3050 2600 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 2 1 5C9A25D9 +P 3050 2800 +F 0 "U1" H 3100 2900 30 0000 C CNN +F 1 "PORT" H 3050 2800 30 0000 C CNN +F 2 "" H 3050 2800 60 0000 C CNN +F 3 "" H 3050 2800 60 0000 C CNN + 2 3050 2800 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 3 1 5C9A260A +P 3050 3100 +F 0 "U1" H 3100 3200 30 0000 C CNN +F 1 "PORT" H 3050 3100 30 0000 C CNN +F 2 "" H 3050 3100 60 0000 C CNN +F 3 "" H 3050 3100 60 0000 C CNN + 3 3050 3100 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 4 1 5C9A2637 +P 6900 2850 +F 0 "U1" H 6950 2950 30 0000 C CNN +F 1 "PORT" H 6900 2850 30 0000 C CNN +F 2 "" H 6900 2850 60 0000 C CNN +F 3 "" H 6900 2850 60 0000 C CNN + 4 6900 2850 + -1 0 0 1 +$EndComp +Wire Wire Line + 4700 2650 4700 2800 +Wire Wire Line + 5600 2850 6650 2850 +Wire Wire Line + 3800 2600 3300 2600 +Wire Wire Line + 3800 2700 3300 2700 +Wire Wire Line + 3300 2700 3300 2800 +Wire Wire Line + 3300 3100 4700 3100 +Wire Wire Line + 4700 3100 4700 2900 +Text Notes 3500 2600 0 60 ~ 12 +in1 +Text Notes 3450 2800 0 60 ~ 12 +in2\n +Text Notes 3500 3100 0 60 ~ 12 +in3 +Text Notes 6100 2850 0 60 ~ 12 +out +$EndSCHEMATC diff --git a/library/SubcircuitLibrary/2x1_mux/3_and.sub b/library/SubcircuitLibrary/2x1_mux/3_and.sub new file mode 100644 index 000000000..3d9120bb6 --- /dev/null +++ b/library/SubcircuitLibrary/2x1_mux/3_and.sub @@ -0,0 +1,14 @@ +* Subcircuit 3_and +.subckt 3_and net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ +* c:\users\malli\esim\src\subcircuitlibrary\3_and\3_and.cir +* u2 net-_u1-pad1_ net-_u1-pad2_ net-_u2-pad3_ d_and +* u3 net-_u2-pad3_ net-_u1-pad3_ net-_u1-pad4_ d_and +a1 [net-_u1-pad1_ net-_u1-pad2_ ] net-_u2-pad3_ u2 +a2 [net-_u2-pad3_ net-_u1-pad3_ ] net-_u1-pad4_ u3 +* Schematic Name: d_and, NgSpice Name: d_and +.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u3 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Control Statements + +.ends 3_and \ No newline at end of file diff --git a/library/SubcircuitLibrary/2x1_mux/3_and_Previous_Values.xml b/library/SubcircuitLibrary/2x1_mux/3_and_Previous_Values.xml new file mode 100644 index 000000000..abc5faaae --- /dev/null +++ b/library/SubcircuitLibrary/2x1_mux/3_and_Previous_Values.xml @@ -0,0 +1 @@ +d_andd_andtruefalsefalseHzHz0Volts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesSecSecSec \ No newline at end of file diff --git a/library/SubcircuitLibrary/2x1_mux/_autosave-2x1_mux.sch b/library/SubcircuitLibrary/2x1_mux/_autosave-2x1_mux.sch new file mode 100644 index 000000000..13fe5d8fa --- /dev/null +++ b/library/SubcircuitLibrary/2x1_mux/_autosave-2x1_mux.sch @@ -0,0 +1,529 @@ +EESchema Schematic File Version 5 +EELAYER 36 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +Comment5 "" +Comment6 "" +Comment7 "" +Comment8 "" +Comment9 "" +$EndDescr +Connection ~ 2350 2850 +Connection ~ 2350 4100 +Connection ~ 2350 5550 +Connection ~ 2350 6550 +Connection ~ 3150 3450 +Connection ~ 3150 4800 +Connection ~ 3150 6400 +Connection ~ 3350 2300 +Connection ~ 3350 2950 +Connection ~ 3350 3550 +Connection ~ 3350 4200 +Connection ~ 3350 4900 +Connection ~ 3350 5650 +Connection ~ 3350 6500 +NoConn ~ 9000 3050 +NoConn ~ 9050 2000 +Wire Wire Line + 750 6250 750 6300 +Wire Wire Line + 800 5450 3750 5450 +Wire Wire Line + 900 3350 3750 3350 +Wire Wire Line + 1000 2700 1000 2750 +Wire Wire Line + 1050 1350 3750 1350 +Wire Wire Line + 1200 6550 1550 6550 +Wire Wire Line + 1250 7100 1400 7100 +Wire Wire Line + 2000 7100 2100 7100 +Wire Wire Line + 2150 6550 2350 6550 +Wire Wire Line + 2350 1450 2350 2850 +Wire Wire Line + 2350 2850 2350 4100 +Wire Wire Line + 2350 4100 2350 5550 +Wire Wire Line + 2350 5550 2350 6550 +Wire Wire Line + 2350 5550 3750 5550 +Wire Wire Line + 2350 6550 2550 6550 +Wire Wire Line + 3150 2200 3150 3450 +Wire Wire Line + 3150 3450 3150 4800 +Wire Wire Line + 3150 3450 3750 3450 +Wire Wire Line + 3150 4800 3150 6400 +Wire Wire Line + 3150 4800 3750 4800 +Wire Wire Line + 3150 6400 3150 6550 +Wire Wire Line + 3150 6400 3750 6400 +Wire Wire Line + 3350 1550 3350 2300 +Wire Wire Line + 3350 2300 3350 2950 +Wire Wire Line + 3350 2300 3750 2300 +Wire Wire Line + 3350 2950 3350 3550 +Wire Wire Line + 3350 2950 3750 2950 +Wire Wire Line + 3350 3550 3350 4200 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1.27)))) + ) + (pin input line (at -3.81 -6.35 90) (length 5.08) + (name "~" (effects (font (size 1.27 1.27)))) + (number "2" (effects (font (size 1.27 1.27)))) + ) + (pin input line (at 8.89 0 180) (length 5.08) + (name "~" (effects (font (size 1.27 1.27)))) + (number "3" (effects (font (size 1.27 1.27)))) + ) + (pin output line (at 3.81 -6.35 90) (length 5.08) + (name "~" (effects (font (size 1.27 1.27)))) + (number "4" (effects (font (size 1.27 1.27)))) + ) + ) + ) +) From 3da98edb4827100fa396af1e6e4e07b3c4157917 Mon Sep 17 00:00:00 2001 From: Sakshi Pandey Date: Sat, 24 Jan 2026 13:43:34 +0530 Subject: [PATCH 4/8] SN74HC04 is a Hex Inverter --- .../SubcircuitLibrary/hex_inv/NMOS-180nm.lib | 13 + .../SubcircuitLibrary/hex_inv/PMOS-180nm.lib | 11 + library/SubcircuitLibrary/hex_inv/analysis | 1 + .../hex_inv/eSim_Subckt.kicad_sym | 7264 +++++++++++++++++ library/SubcircuitLibrary/hex_inv/hex_inv.cir | 21 + .../SubcircuitLibrary/hex_inv/hex_inv.cir.out | 84 + .../hex_inv/hex_inv.kicad_sch | 1421 ++++ library/SubcircuitLibrary/hex_inv/hex_inv.sub | 78 + .../hex_inv/hex_inv_Previous_Values.xml | 1 + 9 files changed, 8894 insertions(+) create mode 100644 library/SubcircuitLibrary/hex_inv/NMOS-180nm.lib create mode 100644 library/SubcircuitLibrary/hex_inv/PMOS-180nm.lib create mode 100644 library/SubcircuitLibrary/hex_inv/analysis create mode 100644 library/SubcircuitLibrary/hex_inv/eSim_Subckt.kicad_sym create mode 100644 library/SubcircuitLibrary/hex_inv/hex_inv.cir create mode 100644 library/SubcircuitLibrary/hex_inv/hex_inv.cir.out create mode 100644 library/SubcircuitLibrary/hex_inv/hex_inv.kicad_sch create mode 100644 library/SubcircuitLibrary/hex_inv/hex_inv.sub create mode 100644 library/SubcircuitLibrary/hex_inv/hex_inv_Previous_Values.xml diff --git a/library/SubcircuitLibrary/hex_inv/NMOS-180nm.lib b/library/SubcircuitLibrary/hex_inv/NMOS-180nm.lib new file mode 100644 index 000000000..51e9b1196 --- /dev/null +++ b/library/SubcircuitLibrary/hex_inv/NMOS-180nm.lib @@ -0,0 +1,13 @@ +.model CMOSN NMOS (LEVEL=8 VERSION=3.2 TNOM=27 TOX=4.1E-9 XJ=1E-7 NCH=2.3549E17 VTH0=0.3823463 K1=0.5810697 ++ K2=4.774618E-3 K3=0.0431669 K3B=1.1498346 W0=1E-7 NLX=1.910552E-7 DVT0W=0 DVT1W=0 DVT2W=0 ++ DVT0=1.2894824 DVT1=0.3622063 DVT2=0.0713729 U0=280.633249 UA=-1.208537E-9 UB=2.158625E-18 ++ UC=5.342807E-11 VSAT=9.366802E4 A0=1.7593146 AGS=0.3939741 B0=-6.413949E-9 B1=-1E-7 KETA=-5.180424E-4 ++ A1=0 A2=1 RDSW=105.5517558 PRWG=0.5 PRWB=-0.1998871 WR=1 WINT=7.904732E-10 LINT=1.571424E-8 XL=0 ++ XW=-1E-8 DWG=1.297221E-9 DWB=1.479041E-9 VOFF=-0.0955434 NFACTOR=2.4358891 CIT=0 CDSC=2.4E-4 CDSCD=0 ++ CDSCB=0 ETA0=3.104851E-3 ETAB=-2.512384E-5 DSUB=0.0167075 PCLM=0.8073191 PDIBLC1=0.1666161 PDIBLC2=3.112892E-3 ++ PDIBLCB=-0.1 DROUT=0.7875618 PSCBE1=8E10 PSCBE2=9.213635E-10 PVAG=3.85243E-3 DELTA=0.01 RSH=6.7 MOBMOD=1 ++ PRT=0 UTE=-1.5 KT1=-0.11 KT1L=0 KT2=0.022 UA1=4.31E-9 UB1=-7.61E-18 UC1=-5.6E-11 AT=3.3E4 WL=0 WLN=1 ++ WW=0 WWN=1 WWL=0 LL=0 LLN=1 LW=0 LWN=1 LWL=0 CAPMOD=2 XPART=0.5 CGDO=7.08E-10 CGSO=7.08E-10 CGBO=1E-12 ++ CJ=9.68858E-4 PB=0.8 MJ=0.3864502 CJSW=2.512138E-10 PBSW=0.809286 MJSW=0.1060414 CJSWG=3.3E-10 PBSWG=0.809286 ++ MJSWG=0.1060414 CF=0 PVTH0=-1.192722E-3 PRDSW=-5 PK2=6.450505E-5 WKETA=-4.27294E-4 LKETA=-0.0104078 ++ PU0=6.3268729 PUA=2.226552E-11 PUB=0 PVSAT=969.1480157 PETA0=1E-4 PKETA=-1.049509E-3) diff --git a/library/SubcircuitLibrary/hex_inv/PMOS-180nm.lib b/library/SubcircuitLibrary/hex_inv/PMOS-180nm.lib new file mode 100644 index 000000000..032b5b95e --- /dev/null +++ b/library/SubcircuitLibrary/hex_inv/PMOS-180nm.lib @@ -0,0 +1,11 @@ +.model CMOSP PMOS (LEVEL=8 VERSION=3.2 TNOM=27 TOX=4.1E-9 XJ=1E-7 NCH=4.1589E17 VTH0=-0.3938813 K1=0.5479015 ++ K2=0.0360586 K3=0.0993095 K3B=5.7086622 W0=1E-6 NLX=1.313191E-7 DVT0W=0 DVT1W=0 DVT2W=0 DVT0=0.4911363 ++ DVT1=0.2227356 DVT2=0.1 U0=115.6852975 UA=1.505832E-9 UB=1E-21 UC=-1E-10 VSAT=1.329694E5 A0=1.7590478 ++ AGS=0.3641621 B0=3.427126E-7 B1=1.062928E-6 KETA=0.0134667 A1=0.6859506 A2=0.3506788 RDSW=168.5705677 ++ PRWG=0.5 PRWB=-0.4987371 WR=1 WINT=0 LINT=3.028832E-8 XL=0 XW=-1E-8 DWG=-2.349633E-8 DWB=-7.152486E-9 ++ VOFF=-0.0994037 NFACTOR=1.9424315 CIT=0 CDSC=2.4E-4 CDSCD=0 CDSCB=0 ETA0=0.0608072 ETAB=-0.0426148 ++ DSUB=0.7343015 PCLM=3.2579974 PDIBLC1=7.229527E-6 PDIBLC2=0.025389 PDIBLCB=-1E-3 DROUT=0 PSCBE1=1.454878E10 ++ PSCBE2=4.202027E-9 PVAG=15 DELTA=0.01 RSH=7.8 MOBMOD=1 PRT=0 UTE=-1.5 KT1=-0.11 KT1L=0 KT2=0.022 UA1=4.31E-9 ++ UB1=-7.61E-18 UC1=-5.6E-11 AT=3.3E4 WL=0 WLN=1 WW=0 WWN=1 WWL=0 LL=0 LLN=1 LW=0 LWN=1 LWL=0 CAPMOD=2 XPART=0.5 ++ CGDO=6.32E-10 CGSO=6.32E-10 CGBO=1E-12 CJ=1.172138E-3 PB=0.8421173 MJ=0.4109788 CJSW=2.242609E-10 PBSW=0.8 + MJSW=0.3752089 CJSWG=4.22E-10 PBSWG=0.8 MJSWG=0.3752089 CF=0 PVTH0=1.888482E-3 PRDSW=11.5315407 PK2=1.559399E-3 ++ WKETA=0.0319301 LKETA=2.955547E-3 PU0=-1.1105313 PUA=-4.62102E-11 PUB=1E-21 PVSAT=50 PETA0=1E-4 PKETA=-4.346368E-3) diff --git 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Net-_U111-Pad2_ Net-_U101-Pad6_ d_buffer +U117 Net-_U108-Pad2_ Net-_U101-Pad8_ d_buffer +U110 Net-_U110-Pad1_ Net-_U110-Pad2_ d_inverter +U108 Net-_U108-Pad1_ Net-_U108-Pad2_ d_inverter +U113 Net-_U113-Pad1_ Net-_U113-Pad2_ d_inverter +U111 Net-_U111-Pad1_ Net-_U111-Pad2_ d_inverter +U116 Net-_U113-Pad2_ Net-_U101-Pad2_ d_buffer +U119 Net-_U110-Pad2_ Net-_U101-Pad4_ d_buffer +U115 Net-_U112-Pad2_ Net-_U101-Pad10_ d_buffer +U118 Net-_U109-Pad2_ Net-_U101-Pad12_ d_buffer +U112 Net-_U112-Pad1_ Net-_U112-Pad2_ d_inverter +U109 Net-_U109-Pad1_ Net-_U109-Pad2_ d_inverter +U107 Net-_U101-Pad3_ Net-_U110-Pad1_ d_buffer +U106 Net-_U101-Pad1_ Net-_U113-Pad1_ d_buffer +U102 Net-_U101-Pad5_ Net-_U111-Pad1_ d_buffer +U103 Net-_U101-Pad11_ Net-_U112-Pad1_ d_buffer +U105 Net-_U101-Pad13_ Net-_U109-Pad1_ d_buffer +U104 Net-_U101-Pad9_ Net-_U108-Pad1_ d_buffer +.end diff --git a/library/SubcircuitLibrary/hex_inv/hex_inv.cir.out b/library/SubcircuitLibrary/hex_inv/hex_inv.cir.out new file mode 100644 index 000000000..3f64475b9 --- /dev/null +++ b/library/SubcircuitLibrary/hex_inv/hex_inv.cir.out @@ -0,0 +1,84 @@ +.title kicad schematic + +* u101 net-_u101-pad1_ net-_u101-pad2_ net-_u101-pad3_ net-_u101-pad4_ net-_u101-pad5_ net-_u101-pad6_ unconnected-_u101-pad7_ net-_u101-pad8_ net-_u101-pad9_ net-_u101-pad10_ net-_u101-pad11_ net-_u101-pad12_ net-_u101-pad13_ unconnected-_u101-pad14_ port +* u114 net-_u111-pad2_ net-_u101-pad6_ d_buffer +* u117 net-_u108-pad2_ net-_u101-pad8_ d_buffer +* u110 net-_u110-pad1_ net-_u110-pad2_ d_inverter +* u108 net-_u108-pad1_ net-_u108-pad2_ d_inverter +* u113 net-_u113-pad1_ net-_u113-pad2_ d_inverter +* u111 net-_u111-pad1_ net-_u111-pad2_ d_inverter +* u116 net-_u113-pad2_ net-_u101-pad2_ d_buffer +* u119 net-_u110-pad2_ net-_u101-pad4_ d_buffer +* u115 net-_u112-pad2_ net-_u101-pad10_ d_buffer +* u118 net-_u109-pad2_ net-_u101-pad12_ d_buffer +* u112 net-_u112-pad1_ net-_u112-pad2_ d_inverter +* u109 net-_u109-pad1_ net-_u109-pad2_ d_inverter +* u107 net-_u101-pad3_ net-_u110-pad1_ d_buffer +* u106 net-_u101-pad1_ net-_u113-pad1_ d_buffer +* u102 net-_u101-pad5_ net-_u111-pad1_ d_buffer +* u103 net-_u101-pad11_ net-_u112-pad1_ d_buffer +* u105 net-_u101-pad13_ net-_u109-pad1_ d_buffer +* u104 net-_u101-pad9_ net-_u108-pad1_ d_buffer +a1 net-_u111-pad2_ net-_u101-pad6_ u114 +a2 net-_u108-pad2_ net-_u101-pad8_ u117 +a3 net-_u110-pad1_ net-_u110-pad2_ u110 +a4 net-_u108-pad1_ net-_u108-pad2_ u108 +a5 net-_u113-pad1_ net-_u113-pad2_ u113 +a6 net-_u111-pad1_ net-_u111-pad2_ u111 +a7 net-_u113-pad2_ net-_u101-pad2_ u116 +a8 net-_u110-pad2_ net-_u101-pad4_ u119 +a9 net-_u112-pad2_ net-_u101-pad10_ u115 +a10 net-_u109-pad2_ net-_u101-pad12_ u118 +a11 net-_u112-pad1_ net-_u112-pad2_ u112 +a12 net-_u109-pad1_ net-_u109-pad2_ u109 +a13 net-_u101-pad3_ net-_u110-pad1_ u107 +a14 net-_u101-pad1_ net-_u113-pad1_ u106 +a15 net-_u101-pad5_ net-_u111-pad1_ u102 +a16 net-_u101-pad11_ net-_u112-pad1_ u103 +a17 net-_u101-pad13_ net-_u109-pad1_ u105 +a18 net-_u101-pad9_ net-_u108-pad1_ u104 +* Schematic Name: d_buffer, Ngspice Name: d_buffer +.model u114 d_buffer(rise_delay=1n fall_delay=1n input_load=1.0e-12 ) +* Schematic Name: d_buffer, Ngspice Name: d_buffer +.model u117 d_buffer(rise_delay=1n fall_delay=1n input_load=1.0e-12 ) +* Schematic Name: d_inverter, Ngspice Name: d_inverter +.model u110 d_inverter(rise_delay=1n fall_delay=1n input_load=1.0e-12 ) +* Schematic Name: d_inverter, Ngspice Name: d_inverter +.model u108 d_inverter(rise_delay=1n fall_delay=1n input_load=1.0e-12 ) +* Schematic Name: d_inverter, Ngspice Name: d_inverter +.model u113 d_inverter(rise_delay=1n fall_delay=1n input_load=1.0e-12 ) +* Schematic Name: d_inverter, Ngspice Name: d_inverter +.model u111 d_inverter(rise_delay=1n fall_delay=1n input_load=1.0e-12 ) +* Schematic Name: d_buffer, Ngspice Name: d_buffer +.model u116 d_buffer(rise_delay=1n fall_delay=1n input_load=1.0e-12 ) +* Schematic Name: d_buffer, Ngspice Name: d_buffer +.model u119 d_buffer(rise_delay=1n fall_delay=1n input_load=1.0e-12 ) +* Schematic Name: d_buffer, Ngspice Name: d_buffer +.model u115 d_buffer(rise_delay=1n fall_delay=1n input_load=1.0e-12 ) +* Schematic Name: d_buffer, Ngspice Name: d_buffer +.model u118 d_buffer(rise_delay=1n fall_delay=1n input_load=1.0e-12 ) +* Schematic Name: d_inverter, Ngspice Name: d_inverter +.model u112 d_inverter(rise_delay=1n fall_delay=1n input_load=1.0e-12 ) +* Schematic Name: d_inverter, Ngspice Name: d_inverter +.model u109 d_inverter(rise_delay=1n fall_delay=1n input_load=1.0e-12 ) +* Schematic Name: d_buffer, Ngspice Name: d_buffer +.model u107 d_buffer(rise_delay=1n fall_delay=1n input_load=1.0e-12 ) +* Schematic Name: d_buffer, Ngspice Name: d_buffer +.model u106 d_buffer(rise_delay=1n fall_delay=1n input_load=1.0e-12 ) +* Schematic Name: d_buffer, Ngspice Name: d_buffer +.model u102 d_buffer(rise_delay=1n fall_delay=1n input_load=1.0e-12 ) +* Schematic Name: d_buffer, Ngspice Name: d_buffer +.model u103 d_buffer(rise_delay=1n fall_delay=1n input_load=1.0e-12 ) +* Schematic Name: d_buffer, Ngspice Name: d_buffer +.model u105 d_buffer(rise_delay=1n fall_delay=1n input_load=1.0e-12 ) +* Schematic Name: d_buffer, Ngspice Name: d_buffer +.model u104 d_buffer(rise_delay=1n fall_delay=1n input_load=1.0e-12 ) +.tran 1e-09 100e-09 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/library/SubcircuitLibrary/hex_inv/hex_inv.kicad_sch b/library/SubcircuitLibrary/hex_inv/hex_inv.kicad_sch new file mode 100644 index 000000000..9bacba88c --- /dev/null +++ b/library/SubcircuitLibrary/hex_inv/hex_inv.kicad_sch @@ -0,0 +1,1421 @@ +(kicad_sch (version 20211123) (generator eeschema) + + (uuid 993ed63d-12c9-4a43-94d5-e3a205bfca9b) + + (paper "A4") + + (lib_symbols + (symbol "eSim_Digital:d_buffer" (pin_names (offset 1.016)) (in_bom yes) (on_board yes) + (property "Reference" "U" (id 0) (at 0 -1.27 0) + (effects (font (size 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1) (value "d_buffer") (footprint "") + ) + (path "/b76defdf-c440-439a-ba37-fc95c16077c0" + (reference "U104") (unit 1) (value "d_buffer") (footprint "") + ) + (path "/4a63a4f1-f77e-4ce7-bc5e-7e6eeec9c6bc" + (reference "U105") (unit 1) (value "d_buffer") (footprint "") + ) + (path "/1240d03b-ad87-4df1-90cc-93145ca2bfaa" + (reference "U106") (unit 1) (value "d_buffer") (footprint "") + ) + (path "/b226b13b-a971-401f-afb9-8604d4f7fda5" + (reference "U107") (unit 1) (value "d_buffer") (footprint "") + ) + (path "/9308f48c-a7fc-4bf7-acb4-3c076757b1a9" + (reference "U108") (unit 1) (value "d_inverter") (footprint "") + ) + (path "/97058ffa-b28f-484d-b369-e2583113214b" + (reference "U109") (unit 1) (value "d_inverter") (footprint "") + ) + (path "/bb0ffd0c-b731-49f5-8b13-b474f8f32196" + (reference "U110") (unit 1) (value "d_inverter") (footprint "") + ) + (path "/65e388d4-7292-456f-8c32-523bbbe6caf3" + (reference "U111") (unit 1) (value "d_inverter") (footprint "") + ) + (path "/e636c5c9-9272-41b7-be1a-e99a7f810f44" + (reference "U112") (unit 1) (value "d_inverter") (footprint "") + ) + (path "/d26557a6-f4f6-4475-bf69-9bb4449f032b" + (reference "U113") (unit 1) (value "d_inverter") (footprint "") + ) + (path "/a2790de9-1ecf-42d2-96e6-e7b6eaeab062" + (reference "U114") (unit 1) (value "d_buffer") (footprint "") + ) + (path "/9663f0c5-cbf0-4aed-b322-f558b455718c" + (reference "U115") (unit 1) (value "d_buffer") (footprint "") + ) + (path "/35d6343f-a69f-4f7e-a7a5-94c19c576e3e" + (reference "U116") (unit 1) (value "d_buffer") (footprint "") + ) + (path "/19a516e5-b4e4-4df9-b147-8267799e4914" + (reference "U117") (unit 1) (value "d_buffer") (footprint "") + ) + (path "/01c215c7-e285-4e6d-a883-512e4171212c" + (reference "U118") (unit 1) (value "d_buffer") (footprint "") + ) + (path "/77b4b4d4-05ed-49a8-b975-45208fc1d5f6" + (reference "U119") (unit 1) (value "d_buffer") (footprint "") + ) + ) +) diff --git a/library/SubcircuitLibrary/hex_inv/hex_inv.sub b/library/SubcircuitLibrary/hex_inv/hex_inv.sub new file mode 100644 index 000000000..a61b484af --- /dev/null +++ b/library/SubcircuitLibrary/hex_inv/hex_inv.sub @@ -0,0 +1,78 @@ +* Subcircuit hex_inv +.subckt hex_inv net-_u101-pad1_ net-_u101-pad2_ net-_u101-pad3_ net-_u101-pad4_ net-_u101-pad5_ net-_u101-pad6_ unconnected-_u101-pad7_ net-_u101-pad8_ net-_u101-pad9_ net-_u101-pad10_ net-_u101-pad11_ net-_u101-pad12_ net-_u101-pad13_ unconnected-_u101-pad14_ +.title kicad schematic +* u114 net-_u111-pad2_ net-_u101-pad6_ d_buffer +* u117 net-_u108-pad2_ net-_u101-pad8_ d_buffer +* u110 net-_u110-pad1_ net-_u110-pad2_ d_inverter +* u108 net-_u108-pad1_ net-_u108-pad2_ d_inverter +* u113 net-_u113-pad1_ net-_u113-pad2_ d_inverter +* u111 net-_u111-pad1_ net-_u111-pad2_ d_inverter +* u116 net-_u113-pad2_ net-_u101-pad2_ d_buffer +* u119 net-_u110-pad2_ net-_u101-pad4_ d_buffer +* u115 net-_u112-pad2_ net-_u101-pad10_ d_buffer +* u118 net-_u109-pad2_ net-_u101-pad12_ d_buffer +* u112 net-_u112-pad1_ net-_u112-pad2_ d_inverter +* u109 net-_u109-pad1_ net-_u109-pad2_ d_inverter +* u107 net-_u101-pad3_ net-_u110-pad1_ d_buffer +* u106 net-_u101-pad1_ net-_u113-pad1_ d_buffer +* u102 net-_u101-pad5_ net-_u111-pad1_ d_buffer +* u103 net-_u101-pad11_ net-_u112-pad1_ d_buffer +* u105 net-_u101-pad13_ net-_u109-pad1_ d_buffer +* u104 net-_u101-pad9_ net-_u108-pad1_ d_buffer +a1 net-_u111-pad2_ net-_u101-pad6_ u114 +a2 net-_u108-pad2_ net-_u101-pad8_ u117 +a3 net-_u110-pad1_ net-_u110-pad2_ u110 +a4 net-_u108-pad1_ net-_u108-pad2_ u108 +a5 net-_u113-pad1_ net-_u113-pad2_ u113 +a6 net-_u111-pad1_ net-_u111-pad2_ u111 +a7 net-_u113-pad2_ net-_u101-pad2_ u116 +a8 net-_u110-pad2_ net-_u101-pad4_ u119 +a9 net-_u112-pad2_ net-_u101-pad10_ u115 +a10 net-_u109-pad2_ net-_u101-pad12_ u118 +a11 net-_u112-pad1_ net-_u112-pad2_ u112 +a12 net-_u109-pad1_ net-_u109-pad2_ u109 +a13 net-_u101-pad3_ net-_u110-pad1_ u107 +a14 net-_u101-pad1_ net-_u113-pad1_ u106 +a15 net-_u101-pad5_ net-_u111-pad1_ u102 +a16 net-_u101-pad11_ net-_u112-pad1_ u103 +a17 net-_u101-pad13_ net-_u109-pad1_ u105 +a18 net-_u101-pad9_ net-_u108-pad1_ u104 +* Schematic Name: d_buffer, Ngspice Name: d_buffer +.model u114 d_buffer(rise_delay=1n fall_delay=1n input_load=1.0e-12 ) +* Schematic Name: d_buffer, Ngspice Name: d_buffer +.model u117 d_buffer(rise_delay=1n fall_delay=1n input_load=1.0e-12 ) +* Schematic Name: d_inverter, Ngspice Name: d_inverter +.model u110 d_inverter(rise_delay=1n fall_delay=1n input_load=1.0e-12 ) +* Schematic Name: d_inverter, Ngspice Name: d_inverter +.model u108 d_inverter(rise_delay=1n fall_delay=1n input_load=1.0e-12 ) +* Schematic Name: d_inverter, Ngspice Name: d_inverter +.model u113 d_inverter(rise_delay=1n fall_delay=1n input_load=1.0e-12 ) +* Schematic Name: d_inverter, Ngspice Name: d_inverter +.model u111 d_inverter(rise_delay=1n fall_delay=1n input_load=1.0e-12 ) +* Schematic Name: d_buffer, Ngspice Name: d_buffer +.model u116 d_buffer(rise_delay=1n fall_delay=1n input_load=1.0e-12 ) +* Schematic Name: d_buffer, Ngspice Name: d_buffer +.model u119 d_buffer(rise_delay=1n fall_delay=1n input_load=1.0e-12 ) +* Schematic Name: d_buffer, Ngspice Name: d_buffer +.model u115 d_buffer(rise_delay=1n fall_delay=1n input_load=1.0e-12 ) +* Schematic Name: d_buffer, Ngspice Name: d_buffer +.model u118 d_buffer(rise_delay=1n fall_delay=1n input_load=1.0e-12 ) +* Schematic Name: d_inverter, Ngspice Name: d_inverter +.model u112 d_inverter(rise_delay=1n fall_delay=1n input_load=1.0e-12 ) +* Schematic Name: d_inverter, Ngspice Name: d_inverter +.model u109 d_inverter(rise_delay=1n fall_delay=1n input_load=1.0e-12 ) +* Schematic Name: d_buffer, Ngspice Name: d_buffer +.model u107 d_buffer(rise_delay=1n fall_delay=1n input_load=1.0e-12 ) +* Schematic Name: d_buffer, Ngspice Name: d_buffer +.model u106 d_buffer(rise_delay=1n fall_delay=1n input_load=1.0e-12 ) +* Schematic Name: d_buffer, Ngspice Name: d_buffer +.model u102 d_buffer(rise_delay=1n fall_delay=1n input_load=1.0e-12 ) +* Schematic Name: d_buffer, Ngspice Name: d_buffer +.model u103 d_buffer(rise_delay=1n fall_delay=1n input_load=1.0e-12 ) +* Schematic Name: d_buffer, Ngspice Name: d_buffer +.model u105 d_buffer(rise_delay=1n fall_delay=1n input_load=1.0e-12 ) +* Schematic Name: d_buffer, Ngspice Name: d_buffer +.model u104 d_buffer(rise_delay=1n fall_delay=1n input_load=1.0e-12 ) +* Control Statements + +.ends hex_inv \ No newline at end of file diff --git a/library/SubcircuitLibrary/hex_inv/hex_inv_Previous_Values.xml b/library/SubcircuitLibrary/hex_inv/hex_inv_Previous_Values.xml new file mode 100644 index 000000000..f1bbd38bf --- /dev/null +++ b/library/SubcircuitLibrary/hex_inv/hex_inv_Previous_Values.xml @@ -0,0 +1 @@ +d_inverter1n1nd_inverter1n1nd_buffer1n1nd_buffer1n1nd_buffer1n1nd_buffer1n1nd_buffer1n1nd_buffer1n1nd_inverter1n1nd_inverter1n1nd_inverter1n1nd_inverter1n1nd_buffer1n1nd_buffer1n1nd_buffer1n1nd_buffer1n1nd_buffer1n1nd_buffer1n1nd_inverter2n2nd_inverter2n2nd_inverter2n2nd_inverter2n2nd_inverter2n2nd_inverter2n2ntruefalsefalseHzHz0Volts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or Amperes01100secnsns \ No newline at end of file From 94d9b7706193ce40e23422b60f66c908811a9373 Mon Sep 17 00:00:00 2001 From: Sakshi Pandey Date: Sat, 24 Jan 2026 13:44:57 +0530 Subject: [PATCH 5/8] LF356 is an op-amp --- library/SubcircuitLibrary/LF356/D.lib | 2 + library/SubcircuitLibrary/LF356/LF356.cir | 47 + library/SubcircuitLibrary/LF356/LF356.cir.out | 60 + .../SubcircuitLibrary/LF356/LF356.kicad_sch | 3109 +++++++ library/SubcircuitLibrary/LF356/LF356.sub | 54 + .../LF356/LF356_Previous_Values.xml | 1 + library/SubcircuitLibrary/LF356/NPN.lib | 4 + library/SubcircuitLibrary/LF356/PJF.lib | 5 + library/SubcircuitLibrary/LF356/PNP.lib | 4 + .../LF356/_autosave-LF356.sch | 1080 +++ library/SubcircuitLibrary/LF356/analysis | 1 + .../LF356/eSim_Subckt.kicad_sym | 7132 +++++++++++++++++ 12 files changed, 11499 insertions(+) create mode 100644 library/SubcircuitLibrary/LF356/D.lib create mode 100644 library/SubcircuitLibrary/LF356/LF356.cir create mode 100644 library/SubcircuitLibrary/LF356/LF356.cir.out create mode 100644 library/SubcircuitLibrary/LF356/LF356.kicad_sch create mode 100644 library/SubcircuitLibrary/LF356/LF356.sub create mode 100644 library/SubcircuitLibrary/LF356/LF356_Previous_Values.xml create mode 100644 library/SubcircuitLibrary/LF356/NPN.lib create mode 100644 library/SubcircuitLibrary/LF356/PJF.lib create mode 100644 library/SubcircuitLibrary/LF356/PNP.lib create mode 100644 library/SubcircuitLibrary/LF356/_autosave-LF356.sch create mode 100644 library/SubcircuitLibrary/LF356/analysis create mode 100644 library/SubcircuitLibrary/LF356/eSim_Subckt.kicad_sym diff --git a/library/SubcircuitLibrary/LF356/D.lib b/library/SubcircuitLibrary/LF356/D.lib new file mode 100644 index 000000000..f53bf3e03 --- /dev/null +++ b/library/SubcircuitLibrary/LF356/D.lib @@ -0,0 +1,2 @@ +.model 1N4148 D(is=2.495E-09 rs=4.755E-01 n=1.679E+00 tt=3.030E-09 cjo=1.700E-12 vj=1 m=1.959E-01 bv=1.000E+02 ibv=1.000E-04) + diff --git a/library/SubcircuitLibrary/LF356/LF356.cir b/library/SubcircuitLibrary/LF356/LF356.cir new file mode 100644 index 000000000..3c655f19a --- /dev/null +++ b/library/SubcircuitLibrary/LF356/LF356.cir @@ -0,0 +1,47 @@ +.title KiCad schematic +D105 Net-_D105-Pad1_ Net-_D103-Pad2_ diode +QN109 Net-_J111-Pad3_ Net-_D104-Pad1_ Net-_C101-Pad2_ npn +D104 Net-_D104-Pad1_ Net-_C101-Pad2_ diode +J109 Net-_J107-Pad2_ Net-_J107-Pad2_ Net-_D102-Pad1_ jfet_p +QN106 Net-_J105-Pad2_ Net-_C102-Pad2_ Net-_QN105-Pad2_ npn +D103 Net-_D103-Pad1_ Net-_D103-Pad2_ diode +QN108 Net-_J105-Pad2_ Net-_C102-Pad1_ Net-_D103-Pad1_ npn +QP104 Net-_J107-Pad2_ Net-_J107-Pad2_ Net-_J105-Pad2_ pnp +D101 Net-_D101-Pad1_ Net-_C101-Pad2_ diode +J110 Net-_D103-Pad2_ Net-_D103-Pad2_ Net-_D104-Pad1_ jfet_p +QN107 Net-_D103-Pad2_ Net-_D102-Pad1_ Net-_C101-Pad2_ npn +D102 Net-_D102-Pad1_ Net-_C101-Pad2_ diode +QP102 Net-_J101-Pad1_ Net-_J107-Pad2_ Net-_J105-Pad2_ pnp +QP103 Net-_J107-Pad1_ Net-_J107-Pad2_ Net-_J105-Pad2_ pnp +J108 Net-_J107-Pad2_ Net-_J107-Pad2_ Net-_D101-Pad1_ jfet_p +J107 Net-_J107-Pad1_ Net-_J107-Pad2_ Net-_C102-Pad1_ jfet_p +U101 Net-_J106-Pad1_ Net-_J103-Pad2_ Net-_J101-Pad2_ Net-_C101-Pad2_ Net-_J105-Pad1_ Net-_D105-Pad1_ Net-_J105-Pad2_ unconnected-_U101-Pad8_ PORT +C102 Net-_C102-Pad1_ Net-_C102-Pad2_ 10p +QP101 Net-_C101-Pad2_ Net-_QN105-Pad1_ Net-_C102-Pad2_ pnp +J105 Net-_J105-Pad1_ Net-_J105-Pad2_ Net-_C102-Pad2_ jfet_p +J106 Net-_J106-Pad1_ Net-_J105-Pad2_ Net-_J106-Pad3_ jfet_p +C101 Net-_C101-Pad1_ Net-_C101-Pad2_ 10p +R101 Net-_C101-Pad2_ Net-_QN101-Pad3_ 1K +QN103 Net-_J105-Pad2_ Net-_QN102-Pad3_ Net-_QN103-Pad3_ npn +QN105 Net-_QN105-Pad1_ Net-_QN105-Pad2_ Net-_QN105-Pad3_ npn +QN102 Net-_J105-Pad2_ Net-_J106-Pad3_ Net-_QN102-Pad3_ npn +QN101 Net-_J101-Pad1_ Net-_QN101-Pad2_ Net-_QN101-Pad3_ npn +J101 Net-_J101-Pad1_ Net-_J101-Pad2_ Net-_C102-Pad2_ jfet_p +J103 Net-_J101-Pad1_ Net-_J103-Pad2_ Net-_C101-Pad1_ jfet_p +J102 Net-_C102-Pad2_ Net-_C102-Pad2_ Net-_C101-Pad2_ jfet_p +J104 Net-_C101-Pad1_ Net-_C101-Pad1_ Net-_C101-Pad2_ jfet_p +R105 Net-_C101-Pad2_ Net-_QN105-Pad2_ 5K +R104 Net-_QN105-Pad3_ Net-_QN101-Pad2_ 30 +QN104 Net-_QN101-Pad2_ Net-_D101-Pad1_ Net-_C101-Pad2_ npn +R102 Net-_C101-Pad2_ Net-_QN102-Pad3_ 5K +R103 Net-_QN101-Pad2_ Net-_QN103-Pad3_ 30 +QN113 Net-_C102-Pad1_ Net-_D106-Pad1_ Net-_D105-Pad1_ npn +QN110 Net-_J105-Pad2_ Net-_D103-Pad1_ Net-_J111-Pad1_ npn +D106 Net-_D106-Pad1_ Net-_C102-Pad1_ diode +R106 Net-_C101-Pad2_ Net-_QN111-Pad3_ 3K +R107 Net-_C101-Pad2_ Net-_QN112-Pad3_ 50 +J111 Net-_J111-Pad1_ Net-_D103-Pad2_ Net-_J111-Pad3_ jfet_p +R108 Net-_D105-Pad1_ Net-_D106-Pad1_ 25 +QN112 Net-_D106-Pad1_ Net-_QN111-Pad3_ Net-_QN112-Pad3_ npn +QN111 Net-_J105-Pad2_ Net-_J111-Pad3_ Net-_QN111-Pad3_ npn +.end diff --git a/library/SubcircuitLibrary/LF356/LF356.cir.out b/library/SubcircuitLibrary/LF356/LF356.cir.out new file mode 100644 index 000000000..ec18c24ab --- /dev/null +++ b/library/SubcircuitLibrary/LF356/LF356.cir.out @@ -0,0 +1,60 @@ +.title kicad schematic + +.include NPN.lib +.include D.lib +.include PNP.lib +.include PJF.lib +d105 net-_d105-pad1_ net-_d103-pad2_ 1N4148 +qn109 net-_j111-pad3_ net-_d104-pad1_ net-_c101-pad2_ Q2N2222 +d104 net-_d104-pad1_ net-_c101-pad2_ 1N4148 +j109 net-_j107-pad2_ net-_j107-pad2_ net-_d102-pad1_ J2N3820 +qn106 net-_j105-pad2_ net-_c102-pad2_ net-_qn105-pad2_ Q2N2222 +d103 net-_d103-pad1_ net-_d103-pad2_ 1N4148 +qn108 net-_j105-pad2_ net-_c102-pad1_ net-_d103-pad1_ Q2N2222 +qp104 net-_j107-pad2_ net-_j107-pad2_ net-_j105-pad2_ Q2N2907A +d101 net-_d101-pad1_ net-_c101-pad2_ 1N4148 +j110 net-_d103-pad2_ net-_d103-pad2_ net-_d104-pad1_ J2N3820 +qn107 net-_d103-pad2_ net-_d102-pad1_ net-_c101-pad2_ Q2N2222 +d102 net-_d102-pad1_ net-_c101-pad2_ 1N4148 +qp102 net-_j101-pad1_ net-_j107-pad2_ net-_j105-pad2_ Q2N2907A +qp103 net-_j107-pad1_ net-_j107-pad2_ net-_j105-pad2_ Q2N2907A +j108 net-_j107-pad2_ net-_j107-pad2_ net-_d101-pad1_ J2N3820 +j107 net-_j107-pad1_ net-_j107-pad2_ net-_c102-pad1_ J2N3820 +* u101 net-_j106-pad1_ net-_j103-pad2_ net-_j101-pad2_ net-_c101-pad2_ net-_j105-pad1_ net-_d105-pad1_ net-_j105-pad2_ unconnected-_u101-pad8_ port +c102 net-_c102-pad1_ net-_c102-pad2_ 10p +qp101 net-_c101-pad2_ net-_qn105-pad1_ net-_c102-pad2_ Q2N2907A +j105 net-_j105-pad1_ net-_j105-pad2_ net-_c102-pad2_ J2N3820 +j106 net-_j106-pad1_ net-_j105-pad2_ net-_j106-pad3_ J2N3820 +c101 net-_c101-pad1_ net-_c101-pad2_ 10p +r101 net-_c101-pad2_ net-_qn101-pad3_ 1k +qn103 net-_j105-pad2_ net-_qn102-pad3_ net-_qn103-pad3_ Q2N2222 +qn105 net-_qn105-pad1_ net-_qn105-pad2_ net-_qn105-pad3_ Q2N2222 +qn102 net-_j105-pad2_ net-_j106-pad3_ net-_qn102-pad3_ Q2N2222 +qn101 net-_j101-pad1_ net-_qn101-pad2_ net-_qn101-pad3_ Q2N2222 +j101 net-_j101-pad1_ net-_j101-pad2_ net-_c102-pad2_ J2N3820 +j103 net-_j101-pad1_ net-_j103-pad2_ net-_c101-pad1_ J2N3820 +j102 net-_c102-pad2_ net-_c102-pad2_ net-_c101-pad2_ J2N3820 +j104 net-_c101-pad1_ net-_c101-pad1_ net-_c101-pad2_ J2N3820 +r105 net-_c101-pad2_ net-_qn105-pad2_ 5k +r104 net-_qn105-pad3_ net-_qn101-pad2_ 30 +qn104 net-_qn101-pad2_ net-_d101-pad1_ net-_c101-pad2_ Q2N2222 +r102 net-_c101-pad2_ net-_qn102-pad3_ 5k +r103 net-_qn101-pad2_ net-_qn103-pad3_ 30 +qn113 net-_c102-pad1_ net-_d106-pad1_ net-_d105-pad1_ Q2N2222 +qn110 net-_j105-pad2_ net-_d103-pad1_ net-_j111-pad1_ Q2N2222 +d106 net-_d106-pad1_ net-_c102-pad1_ 1N4148 +r106 net-_c101-pad2_ net-_qn111-pad3_ 3k +r107 net-_c101-pad2_ net-_qn112-pad3_ 50 +j111 net-_j111-pad1_ net-_d103-pad2_ net-_j111-pad3_ J2N3820 +r108 net-_d105-pad1_ net-_d106-pad1_ 25 +qn112 net-_d106-pad1_ net-_qn111-pad3_ net-_qn112-pad3_ Q2N2222 +qn111 net-_j105-pad2_ net-_j111-pad3_ net-_qn111-pad3_ Q2N2222 +.tran 1e-12 10e-09 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/library/SubcircuitLibrary/LF356/LF356.kicad_sch b/library/SubcircuitLibrary/LF356/LF356.kicad_sch new file mode 100644 index 000000000..3121ca9ea --- /dev/null +++ b/library/SubcircuitLibrary/LF356/LF356.kicad_sch @@ -0,0 +1,3109 @@ +(kicad_sch (version 20211123) (generator eeschema) + + (uuid 359a080f-5abd-4507-a2da-d76cee43cdc1) + + (paper "A4") + + (lib_symbols + (symbol "LTspice_sym:diode" (pin_numbers hide) (pin_names (offset 0.0254) hide) (in_bom yes) (on_board yes) + (property "Reference" "D" (id 0) (at 1.905 0 0) + (effects (font (size 1.27 1.27)) (justify left)) + ) + (property "Value" "diode" (id 1) (at 1.905 -5.08 0) + (effects (font (size 1.27 1.27)) (justify left)) + ) + (property "Footprint" "" (id 2) (at 0 0 0) + (effects (font (size 1.27 1.27)) hide) + ) + (property "Datasheet" "" (id 3) (at 0 0 0) + (effects (font (size 1.27 1.27)) hide) + ) + (property "Field5" "D" (id 4) (at 1.905 -5.08 0) + (effects (font (size 1.27 1.27)) (justify left) hide) + ) + (property "ki_fp_filters" "D_*" (id 5) (at 0 0 0) + (effects (font (size 1.27 1.27)) hide) + ) + (symbol "diode_0_0" + (polyline + (pts + (xy 0 -3.4798) + (xy 2.54 -3.4798) + ) + (stroke (width 0) (type default) (color 0 0 0 0)) + (fill (type none)) + ) + (polyline + (pts + (xy 0 -1.5748) + (xy 1.27 -3.4798) + ) + (stroke (width 0) (type default) (color 0 0 0 0)) + (fill (type none)) + ) + (polyline + (pts + (xy 0 -1.5748) + (xy 2.54 -1.5748) + ) + (stroke (width 0) (type default) (color 0 0 0 0)) + (fill (type none)) + ) + (polyline + (pts + (xy 1.27 -3.4798) + (xy 1.27 -5.08) + ) + (stroke (width 0) (type default) (color 0 0 0 0)) + (fill (type none)) + ) + (polyline + (pts + (xy 1.27 0) + (xy 1.27 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"/23adae5a-fbfe-4550-9a6d-f6147036d806" + (reference "QN112") (unit 1) (value "npn") (footprint "") + ) + (path "/efcd1be3-a4ea-40b2-999c-e590dd4a25fe" + (reference "QN113") (unit 1) (value "npn") (footprint "") + ) + (path "/88abbfeb-f6b4-499a-a3ec-75216795c88f" + (reference "QP101") (unit 1) (value "pnp") (footprint "") + ) + (path "/c239ac18-b791-45be-84ac-d4f8509d19ca" + (reference "QP102") (unit 1) (value "pnp") (footprint "") + ) + (path "/3f0a3324-d89c-464c-87ab-cea24640dfad" + (reference "QP103") (unit 1) (value "pnp") (footprint "") + ) + (path "/1980d92f-2af3-410e-b049-58d06ed65694" + (reference "QP104") (unit 1) (value "pnp") (footprint "") + ) + (path "/655740ba-aeac-4b47-b9a4-c0b1b5042b08" + (reference "R101") (unit 1) (value "1K") (footprint "") + ) + (path "/090f2453-c41b-449b-94ff-0d23ad38717f" + (reference "R102") (unit 1) (value "5K") (footprint "") + ) + (path "/abe1ec7b-45cd-4880-8003-5c3558cc74a0" + (reference "R103") (unit 1) (value "30") (footprint "") + ) + (path "/d967dacd-12e1-4429-842c-89bccca5e41a" + (reference "R104") (unit 1) (value "30") (footprint "") + ) + (path "/b25560d5-9367-4344-99be-005bb0c4fa20" + (reference "R105") (unit 1) (value "5K") (footprint "") + ) + (path "/5a3804e5-d0b1-4412-af94-4664509de32f" + (reference "R106") (unit 1) (value "3K") (footprint "") + ) + (path "/b830d647-fc54-439a-9e54-39a4a67d5c58" + (reference "R107") (unit 1) (value "50") (footprint "") + ) + (path "/399bb66d-e771-4dfd-bb06-a7a697696868" + (reference "R108") (unit 1) (value "25") (footprint "") + ) + (path "/e0b49922-597a-481c-8f70-ea1ef40439db" + (reference "U101") (unit 1) (value "PORT") (footprint "") + ) + (path "/b240aba4-ce26-4029-88a4-4a60bddb4f65" + (reference "U101") (unit 2) (value "PORT") (footprint "") + ) + (path "/d22466bb-1088-44b0-8dc3-19e6b2f036ef" + (reference "U101") (unit 3) (value "PORT") (footprint "") + ) + (path "/8fd882dd-1c96-42fa-ba53-ab55320b049b" + (reference "U101") (unit 4) (value "PORT") (footprint "") + ) + (path "/1bb5e0a9-a27e-4cf0-8c20-608f4bbb5e8c" + (reference "U101") (unit 5) (value "PORT") (footprint "") + ) + (path "/25474f93-7098-4509-b381-fa91af699085" + (reference "U101") (unit 6) (value "PORT") (footprint "") + ) + (path "/0870ea13-e34e-4572-86b9-a1775d568777" + (reference "U101") (unit 7) (value "PORT") (footprint "") + ) + (path "/c0c6410f-1bb8-40f3-b077-99af1e530607" + (reference "U101") (unit 8) (value "PORT") (footprint "") + ) + ) +) diff --git a/library/SubcircuitLibrary/LF356/LF356.sub b/library/SubcircuitLibrary/LF356/LF356.sub new file mode 100644 index 000000000..d2fd63744 --- /dev/null +++ b/library/SubcircuitLibrary/LF356/LF356.sub @@ -0,0 +1,54 @@ +* Subcircuit LF356 +.subckt LF356 net-_j106-pad1_ net-_j103-pad2_ net-_j101-pad2_ net-_c101-pad2_ net-_j105-pad1_ net-_d105-pad1_ net-_j105-pad2_ unconnected-_u101-pad8_ +.title kicad schematic +.include NPN.lib +.include D.lib +.include PNP.lib +.include PJF.lib +d105 net-_d105-pad1_ net-_d103-pad2_ 1N4148 +qn109 net-_j111-pad3_ net-_d104-pad1_ net-_c101-pad2_ Q2N2222 +d104 net-_d104-pad1_ net-_c101-pad2_ 1N4148 +j109 net-_j107-pad2_ net-_j107-pad2_ net-_d102-pad1_ J2N3820 +qn106 net-_j105-pad2_ net-_c102-pad2_ net-_qn105-pad2_ Q2N2222 +d103 net-_d103-pad1_ net-_d103-pad2_ 1N4148 +qn108 net-_j105-pad2_ net-_c102-pad1_ net-_d103-pad1_ Q2N2222 +qp104 net-_j107-pad2_ net-_j107-pad2_ net-_j105-pad2_ Q2N2907A +d101 net-_d101-pad1_ net-_c101-pad2_ 1N4148 +j110 net-_d103-pad2_ net-_d103-pad2_ net-_d104-pad1_ J2N3820 +qn107 net-_d103-pad2_ net-_d102-pad1_ net-_c101-pad2_ Q2N2222 +d102 net-_d102-pad1_ net-_c101-pad2_ 1N4148 +qp102 net-_j101-pad1_ net-_j107-pad2_ net-_j105-pad2_ Q2N2907A +qp103 net-_j107-pad1_ net-_j107-pad2_ net-_j105-pad2_ Q2N2907A +j108 net-_j107-pad2_ net-_j107-pad2_ net-_d101-pad1_ J2N3820 +j107 net-_j107-pad1_ net-_j107-pad2_ net-_c102-pad1_ J2N3820 +c102 net-_c102-pad1_ net-_c102-pad2_ 10p +qp101 net-_c101-pad2_ net-_qn105-pad1_ net-_c102-pad2_ Q2N2907A +j105 net-_j105-pad1_ net-_j105-pad2_ net-_c102-pad2_ J2N3820 +j106 net-_j106-pad1_ net-_j105-pad2_ net-_j106-pad3_ J2N3820 +c101 net-_c101-pad1_ net-_c101-pad2_ 10p +r101 net-_c101-pad2_ net-_qn101-pad3_ 1k +qn103 net-_j105-pad2_ net-_qn102-pad3_ net-_qn103-pad3_ Q2N2222 +qn105 net-_qn105-pad1_ net-_qn105-pad2_ net-_qn105-pad3_ Q2N2222 +qn102 net-_j105-pad2_ net-_j106-pad3_ net-_qn102-pad3_ Q2N2222 +qn101 net-_j101-pad1_ net-_qn101-pad2_ net-_qn101-pad3_ Q2N2222 +j101 net-_j101-pad1_ net-_j101-pad2_ net-_c102-pad2_ J2N3820 +j103 net-_j101-pad1_ net-_j103-pad2_ net-_c101-pad1_ J2N3820 +j102 net-_c102-pad2_ net-_c102-pad2_ net-_c101-pad2_ J2N3820 +j104 net-_c101-pad1_ net-_c101-pad1_ net-_c101-pad2_ J2N3820 +r105 net-_c101-pad2_ net-_qn105-pad2_ 5k +r104 net-_qn105-pad3_ net-_qn101-pad2_ 30 +qn104 net-_qn101-pad2_ net-_d101-pad1_ net-_c101-pad2_ Q2N2222 +r102 net-_c101-pad2_ net-_qn102-pad3_ 5k +r103 net-_qn101-pad2_ net-_qn103-pad3_ 30 +qn113 net-_c102-pad1_ net-_d106-pad1_ net-_d105-pad1_ Q2N2222 +qn110 net-_j105-pad2_ net-_d103-pad1_ net-_j111-pad1_ Q2N2222 +d106 net-_d106-pad1_ net-_c102-pad1_ 1N4148 +r106 net-_c101-pad2_ net-_qn111-pad3_ 3k +r107 net-_c101-pad2_ net-_qn112-pad3_ 50 +j111 net-_j111-pad1_ net-_d103-pad2_ net-_j111-pad3_ J2N3820 +r108 net-_d105-pad1_ net-_d106-pad1_ 25 +qn112 net-_d106-pad1_ net-_qn111-pad3_ net-_qn112-pad3_ Q2N2222 +qn111 net-_j105-pad2_ net-_j111-pad3_ net-_qn111-pad3_ Q2N2222 +* Control Statements + +.ends LF356 \ No newline at end of file diff --git a/library/SubcircuitLibrary/LF356/LF356_Previous_Values.xml b/library/SubcircuitLibrary/LF356/LF356_Previous_Values.xml new file mode 100644 index 000000000..6bfcc4fac --- /dev/null +++ b/library/SubcircuitLibrary/LF356/LF356_Previous_Values.xml @@ -0,0 +1 @@ +C:\FOSSEE\eSim\library\deviceModelLibrary\Diode\D.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.libC:\FOSSEE\eSim\library\deviceModelLibrary\Diode\D.libC:\FOSSEE\eSim\library\deviceModelLibrary\JFET\PJF.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.libC:\FOSSEE\eSim\library\deviceModelLibrary\Diode\D.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.libC:\FOSSEE\eSim\library\deviceModelLibrary\Diode\D.libC:\FOSSEE\eSim\library\deviceModelLibrary\JFET\PJF.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.libC:\FOSSEE\eSim\library\deviceModelLibrary\Diode\D.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.libC:\FOSSEE\eSim\library\deviceModelLibrary\JFET\PJF.libC:\FOSSEE\eSim\library\deviceModelLibrary\JFET\PJF.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.libC:\FOSSEE\eSim\library\deviceModelLibrary\JFET\PJF.libC:\FOSSEE\eSim\library\deviceModelLibrary\JFET\PJF.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.libC:\FOSSEE\eSim\library\deviceModelLibrary\JFET\PJF.libC:\FOSSEE\eSim\library\deviceModelLibrary\JFET\PJF.libC:\FOSSEE\eSim\library\deviceModelLibrary\JFET\PJF.libC:\FOSSEE\eSim\library\deviceModelLibrary\JFET\PJF.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.libC:\FOSSEE\eSim\library\deviceModelLibrary\Diode\D.libC:\FOSSEE\eSim\library\deviceModelLibrary\JFET\PJF.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.libtruefalsefalseHzHz0Volts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or Amperes0110secpsns \ No newline at end of file diff --git a/library/SubcircuitLibrary/LF356/NPN.lib b/library/SubcircuitLibrary/LF356/NPN.lib new file mode 100644 index 000000000..be5f3073a --- /dev/null +++ b/library/SubcircuitLibrary/LF356/NPN.lib @@ -0,0 +1,4 @@ +.model Q2N2222 NPN( Is=14.34f Xti=3 Eg=1.11 Vaf=74.03 Bf=400 Ne=1.307 ++ Ise=14.34f Ikf=0.2847 Xtb=1.5 Br=6.092 Nc=2 Isc=0 Ikr=0 Rc=1 Cjc=7.306p ++ Mjc=0.3416 Vjc=0.75 Fc=0.5 Cje=22.01p Mje=0.377 Vje=0.75 Tr=46.91n Tf=411.1p ++ Itf=0.6 Vtf=1.7 Xtf=3 Rb=10) diff --git a/library/SubcircuitLibrary/LF356/PJF.lib b/library/SubcircuitLibrary/LF356/PJF.lib new file mode 100644 index 000000000..5589571d1 --- /dev/null +++ b/library/SubcircuitLibrary/LF356/PJF.lib @@ -0,0 +1,5 @@ +.model J2N3820 PJF(Beta=1.304m Betatce=-.5 Rd=1 Rs=1 Lambda=2.25m Vto=-3 ++ Vtotc=-2.5m Is=33.57f Isr=322.4f N=1 Nr=2 Xti=3 Alpha=311.7u ++ Vk=243.6 Cgd=1.6p M=.3622 Pb=1 Fc=.5 Cgs=2.414p Kf=9.882E-18 ++ Af=1) + diff --git a/library/SubcircuitLibrary/LF356/PNP.lib b/library/SubcircuitLibrary/LF356/PNP.lib new file mode 100644 index 000000000..7edda0eab --- /dev/null +++ b/library/SubcircuitLibrary/LF356/PNP.lib @@ -0,0 +1,4 @@ +.model Q2N2907A PNP(Is=650.6E-18 Xti=3 Eg=1.11 Vaf=115.7 Bf=231.7 Ne=1.829 ++ Ise=54.81f Ikf=1.079 Xtb=1.5 Br=3.563 Nc=2 Isc=0 Ikr=0 Rc=.715 ++ Cjc=14.76p Mjc=.5383 Vjc=.75 Fc=.5 Cje=19.82p Mje=.3357 Vje=.75 ++ Tr=111.3n Tf=603.7p Itf=.65 Vtf=5 Xtf=1.7 Rb=10) diff --git a/library/SubcircuitLibrary/LF356/_autosave-LF356.sch b/library/SubcircuitLibrary/LF356/_autosave-LF356.sch new file mode 100644 index 000000000..8d814a240 --- /dev/null +++ b/library/SubcircuitLibrary/LF356/_autosave-LF356.sch @@ -0,0 +1,1080 @@ +EESchema Schematic File Version 5 +EELAYER 36 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +Comment5 "" +Comment6 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1.27)))) + ) + (pin input line (at -3.81 -6.35 90) (length 5.08) + (name "~" (effects (font (size 1.27 1.27)))) + (number "2" (effects (font (size 1.27 1.27)))) + ) + (pin input line (at 8.89 0 180) (length 5.08) + (name "~" (effects (font (size 1.27 1.27)))) + (number "3" (effects (font (size 1.27 1.27)))) + ) + (pin output line (at 3.81 -6.35 90) (length 5.08) + (name "~" (effects (font (size 1.27 1.27)))) + (number "4" (effects (font (size 1.27 1.27)))) + ) + ) + ) +) From 909a718ca30c0600cfb7265fcc34eb4f17e621bc Mon Sep 17 00:00:00 2001 From: Sakshi Pandey Date: Sat, 24 Jan 2026 13:47:14 +0530 Subject: [PATCH 6/8] CD4075 is 3 input OR GATE --- library/SubcircuitLibrary/3_or/3_or.cir | 27 + library/SubcircuitLibrary/3_or/3_or.cir.out | 108 + library/SubcircuitLibrary/3_or/3_or.kicad_sch | 1703 +++++ library/SubcircuitLibrary/3_or/3_or.sub | 102 + .../3_or/3_or_Previous_Values.xml | 1 + .../3_or/3_or_gate.kicad_prl | 75 + .../3_or/3_or_gate.kicad_pro | 294 + .../3_or/3_or_gate.kicad_sch | 340 + library/SubcircuitLibrary/3_or/NMOS-180nm.lib | 13 + library/SubcircuitLibrary/3_or/NMOS-5um.lib | 5 + library/SubcircuitLibrary/3_or/PMOS-180nm.lib | 11 + library/SubcircuitLibrary/3_or/PMOS-5um.lib | 5 + library/SubcircuitLibrary/3_or/analysis | 1 + .../3_or/eSim_Subckt.kicad_sym | 6806 +++++++++++++++++ 14 files changed, 9491 insertions(+) create mode 100644 library/SubcircuitLibrary/3_or/3_or.cir create mode 100644 library/SubcircuitLibrary/3_or/3_or.cir.out create mode 100644 library/SubcircuitLibrary/3_or/3_or.kicad_sch create mode 100644 library/SubcircuitLibrary/3_or/3_or.sub create mode 100644 library/SubcircuitLibrary/3_or/3_or_Previous_Values.xml create mode 100644 library/SubcircuitLibrary/3_or/3_or_gate.kicad_prl create mode 100644 library/SubcircuitLibrary/3_or/3_or_gate.kicad_pro create mode 100644 library/SubcircuitLibrary/3_or/3_or_gate.kicad_sch create mode 100644 library/SubcircuitLibrary/3_or/NMOS-180nm.lib create mode 100644 library/SubcircuitLibrary/3_or/NMOS-5um.lib create mode 100644 library/SubcircuitLibrary/3_or/PMOS-180nm.lib create mode 100644 library/SubcircuitLibrary/3_or/PMOS-5um.lib create mode 100644 library/SubcircuitLibrary/3_or/analysis create mode 100644 library/SubcircuitLibrary/3_or/eSim_Subckt.kicad_sym diff --git a/library/SubcircuitLibrary/3_or/3_or.cir b/library/SubcircuitLibrary/3_or/3_or.cir new file mode 100644 index 000000000..ab4c07e45 --- /dev/null +++ b/library/SubcircuitLibrary/3_or/3_or.cir @@ -0,0 +1,27 @@ +.title KiCad schematic +U112 Net-_U104-Pad2_ Net-_U106-Pad2_ Net-_U112-Pad3_ d_nand +U106 Net-_U101-Pad4_ Net-_U106-Pad2_ d_inverter +U109 Net-_U101-Pad12_ Net-_U109-Pad2_ d_inverter +U101 Net-_U101-Pad1_ Net-_U101-Pad2_ Net-_U101-Pad3_ Net-_U101-Pad4_ Net-_U101-Pad5_ Net-_U101-Pad6_ unconnected-_U101-Pad7_ Net-_U101-Pad8_ Net-_U101-Pad9_ Net-_U101-Pad10_ Net-_U101-Pad11_ Net-_U101-Pad12_ Net-_U101-Pad13_ unconnected-_U101-Pad14_ PORT +U110 Net-_U101-Pad13_ Net-_U110-Pad2_ d_inverter +U107 Net-_U101-Pad5_ Net-_U107-Pad2_ d_inverter +U108 Net-_U101-Pad11_ Net-_U108-Pad2_ d_inverter +U113 Net-_U108-Pad2_ Net-_U109-Pad2_ Net-_U113-Pad3_ d_nand +U103 Net-_U101-Pad2_ Net-_U103-Pad2_ d_inverter +U102 Net-_U101-Pad1_ Net-_U102-Pad2_ d_inverter +U114 Net-_U111-Pad3_ Net-_U111-Pad3_ Net-_U114-Pad3_ d_nand +U111 Net-_U102-Pad2_ Net-_U103-Pad2_ Net-_U111-Pad3_ d_nand +U104 Net-_U101-Pad3_ Net-_U104-Pad2_ d_inverter +U105 Net-_U101-Pad8_ Net-_U105-Pad2_ d_inverter +U115 Net-_U112-Pad3_ Net-_U112-Pad3_ Net-_U115-Pad3_ d_nand +U119 Net-_U116-Pad3_ Net-_U110-Pad2_ Net-_U119-Pad3_ d_nand +U116 Net-_U113-Pad3_ Net-_U113-Pad3_ Net-_U116-Pad3_ d_nand +U125 Net-_U122-Pad2_ Net-_U101-Pad10_ d_inverter +U122 Net-_U119-Pad3_ Net-_U122-Pad2_ d_inverter +U121 Net-_U118-Pad3_ Net-_U121-Pad2_ d_inverter +U118 Net-_U115-Pad3_ Net-_U107-Pad2_ Net-_U118-Pad3_ d_nand +U117 Net-_U114-Pad3_ Net-_U105-Pad2_ Net-_U117-Pad3_ d_nand +U124 Net-_U121-Pad2_ Net-_U101-Pad6_ d_inverter +U123 Net-_U120-Pad2_ Net-_U101-Pad9_ d_inverter +U120 Net-_U117-Pad3_ Net-_U120-Pad2_ d_inverter +.end diff --git a/library/SubcircuitLibrary/3_or/3_or.cir.out b/library/SubcircuitLibrary/3_or/3_or.cir.out new file mode 100644 index 000000000..df6bda055 --- /dev/null +++ b/library/SubcircuitLibrary/3_or/3_or.cir.out @@ -0,0 +1,108 @@ +.title kicad schematic + +* u112 net-_u104-pad2_ net-_u106-pad2_ net-_u112-pad3_ d_nand +* u106 net-_u101-pad4_ net-_u106-pad2_ d_inverter +* u109 net-_u101-pad12_ net-_u109-pad2_ d_inverter +* u101 net-_u101-pad1_ net-_u101-pad2_ net-_u101-pad3_ net-_u101-pad4_ net-_u101-pad5_ net-_u101-pad6_ unconnected-_u101-pad7_ net-_u101-pad8_ net-_u101-pad9_ net-_u101-pad10_ net-_u101-pad11_ net-_u101-pad12_ net-_u101-pad13_ unconnected-_u101-pad14_ port +* u110 net-_u101-pad13_ net-_u110-pad2_ d_inverter +* u107 net-_u101-pad5_ net-_u107-pad2_ d_inverter +* u108 net-_u101-pad11_ net-_u108-pad2_ d_inverter +* u113 net-_u108-pad2_ net-_u109-pad2_ net-_u113-pad3_ d_nand +* u103 net-_u101-pad2_ net-_u103-pad2_ d_inverter +* u102 net-_u101-pad1_ net-_u102-pad2_ d_inverter +* u114 net-_u111-pad3_ net-_u111-pad3_ net-_u114-pad3_ d_nand +* u111 net-_u102-pad2_ net-_u103-pad2_ net-_u111-pad3_ d_nand +* u104 net-_u101-pad3_ net-_u104-pad2_ d_inverter +* u105 net-_u101-pad8_ net-_u105-pad2_ d_inverter +* u115 net-_u112-pad3_ net-_u112-pad3_ net-_u115-pad3_ d_nand +* u119 net-_u116-pad3_ net-_u110-pad2_ net-_u119-pad3_ d_nand +* u116 net-_u113-pad3_ net-_u113-pad3_ net-_u116-pad3_ d_nand +* u125 net-_u122-pad2_ net-_u101-pad10_ d_inverter +* u122 net-_u119-pad3_ net-_u122-pad2_ d_inverter +* u121 net-_u118-pad3_ net-_u121-pad2_ d_inverter +* u118 net-_u115-pad3_ net-_u107-pad2_ net-_u118-pad3_ d_nand +* u117 net-_u114-pad3_ net-_u105-pad2_ net-_u117-pad3_ d_nand +* u124 net-_u121-pad2_ net-_u101-pad6_ d_inverter +* u123 net-_u120-pad2_ net-_u101-pad9_ d_inverter +* u120 net-_u117-pad3_ net-_u120-pad2_ d_inverter +a1 [net-_u104-pad2_ net-_u106-pad2_ ] net-_u112-pad3_ u112 +a2 net-_u101-pad4_ net-_u106-pad2_ u106 +a3 net-_u101-pad12_ net-_u109-pad2_ u109 +a4 net-_u101-pad13_ net-_u110-pad2_ u110 +a5 net-_u101-pad5_ net-_u107-pad2_ u107 +a6 net-_u101-pad11_ net-_u108-pad2_ u108 +a7 [net-_u108-pad2_ net-_u109-pad2_ ] net-_u113-pad3_ u113 +a8 net-_u101-pad2_ net-_u103-pad2_ u103 +a9 net-_u101-pad1_ net-_u102-pad2_ u102 +a10 [net-_u111-pad3_ net-_u111-pad3_ ] net-_u114-pad3_ u114 +a11 [net-_u102-pad2_ net-_u103-pad2_ ] net-_u111-pad3_ u111 +a12 net-_u101-pad3_ net-_u104-pad2_ u104 +a13 net-_u101-pad8_ net-_u105-pad2_ u105 +a14 [net-_u112-pad3_ net-_u112-pad3_ ] net-_u115-pad3_ u115 +a15 [net-_u116-pad3_ net-_u110-pad2_ ] net-_u119-pad3_ u119 +a16 [net-_u113-pad3_ net-_u113-pad3_ ] net-_u116-pad3_ u116 +a17 net-_u122-pad2_ net-_u101-pad10_ u125 +a18 net-_u119-pad3_ net-_u122-pad2_ u122 +a19 net-_u118-pad3_ net-_u121-pad2_ u121 +a20 [net-_u115-pad3_ net-_u107-pad2_ ] net-_u118-pad3_ u118 +a21 [net-_u114-pad3_ net-_u105-pad2_ ] net-_u117-pad3_ u117 +a22 net-_u121-pad2_ net-_u101-pad6_ u124 +a23 net-_u120-pad2_ net-_u101-pad9_ u123 +a24 net-_u117-pad3_ net-_u120-pad2_ u120 +* Schematic Name: d_nand, Ngspice Name: d_nand +.model u112 d_nand(rise_delay=5n fall_delay=5n input_load=1.0e-12 ) +* Schematic Name: d_inverter, Ngspice Name: d_inverter +.model u106 d_inverter(rise_delay=5n fall_delay=5n input_load=1.0e-12 ) +* Schematic Name: d_inverter, Ngspice Name: d_inverter +.model u109 d_inverter(rise_delay=5n fall_delay=5n input_load=1.0e-12 ) +* Schematic Name: d_inverter, Ngspice Name: d_inverter +.model u110 d_inverter(rise_delay=5n fall_delay=5n input_load=1.0e-12 ) +* Schematic Name: d_inverter, Ngspice Name: d_inverter +.model u107 d_inverter(rise_delay=5n fall_delay=5n input_load=1.0e-12 ) +* Schematic Name: d_inverter, Ngspice Name: d_inverter +.model u108 d_inverter(rise_delay=5n fall_delay=5n input_load=1.0e-12 ) +* Schematic Name: d_nand, Ngspice Name: d_nand +.model u113 d_nand(rise_delay=5n fall_delay=5n input_load=1.0e-12 ) +* Schematic Name: d_inverter, Ngspice Name: d_inverter +.model u103 d_inverter(rise_delay=5n fall_delay=5n input_load=1.0e-12 ) +* Schematic Name: d_inverter, Ngspice Name: d_inverter +.model u102 d_inverter(rise_delay=5n fall_delay=5n input_load=1.0e-12 ) +* Schematic Name: d_nand, Ngspice Name: d_nand +.model u114 d_nand(rise_delay=5n fall_delay=5n input_load=1.0e-12 ) +* Schematic Name: d_nand, Ngspice Name: d_nand +.model u111 d_nand(rise_delay=5n fall_delay=5n input_load=1.0e-12 ) +* Schematic Name: d_inverter, Ngspice Name: d_inverter +.model u104 d_inverter(rise_delay=5n fall_delay=5n input_load=1.0e-12 ) +* Schematic Name: d_inverter, Ngspice Name: d_inverter +.model u105 d_inverter(rise_delay=5n fall_delay=5n input_load=1.0e-12 ) +* Schematic Name: d_nand, Ngspice Name: d_nand +.model u115 d_nand(rise_delay=5n fall_delay=5n input_load=1.0e-12 ) +* Schematic Name: d_nand, Ngspice Name: d_nand +.model u119 d_nand(rise_delay=5n fall_delay=5n input_load=1.0e-12 ) +* Schematic Name: d_nand, Ngspice Name: d_nand +.model u116 d_nand(rise_delay=5n fall_delay=5n input_load=1.0e-12 ) +* Schematic Name: d_inverter, Ngspice Name: d_inverter +.model u125 d_inverter(rise_delay=5n fall_delay=5n input_load=1.0e-12 ) +* Schematic Name: d_inverter, Ngspice Name: d_inverter +.model u122 d_inverter(rise_delay=5n fall_delay=5n input_load=1.0e-12 ) +* Schematic Name: d_inverter, Ngspice Name: d_inverter +.model u121 d_inverter(rise_delay=5n fall_delay=5n input_load=1.0e-12 ) +* Schematic Name: d_nand, Ngspice Name: d_nand +.model u118 d_nand(rise_delay=5n fall_delay=5n input_load=1.0e-12 ) +* Schematic Name: d_nand, Ngspice Name: d_nand +.model u117 d_nand(rise_delay=5n fall_delay=5n input_load=1.0e-12 ) +* Schematic Name: d_inverter, Ngspice Name: d_inverter +.model u124 d_inverter(rise_delay=5n fall_delay=5n input_load=1.0e-12 ) +* Schematic Name: d_inverter, Ngspice Name: d_inverter +.model u123 d_inverter(rise_delay=5n fall_delay=5n input_load=1.0e-12 ) +* Schematic Name: d_inverter, Ngspice Name: d_inverter +.model u120 d_inverter(rise_delay=5n fall_delay=5n input_load=1.0e-12 ) +.tran 1e-09 100e-09 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/library/SubcircuitLibrary/3_or/3_or.kicad_sch b/library/SubcircuitLibrary/3_or/3_or.kicad_sch new file mode 100644 index 000000000..405d79323 --- /dev/null +++ b/library/SubcircuitLibrary/3_or/3_or.kicad_sch @@ -0,0 +1,1703 @@ +(kicad_sch (version 20211123) (generator eeschema) + + (uuid f0a2e0f0-48f6-4aa6-a5ad-23eec30288fd) + + (paper "A4") + + (lib_symbols + (symbol "eSim_Digital:d_inverter" (pin_names (offset 1.016)) (in_bom yes) (on_board yes) + (property "Reference" "U" (id 0) (at 0 -2.54 0) + (effects (font (size 1.524 1.524))) + ) + (property "Value" "d_inverter" (id 1) (at 0 3.81 0) + (effects (font (size 1.524 1.524))) + ) + (property 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(value "d_inverter") (footprint "") + ) + (path "/fad8f04e-d01c-4ef5-8138-8f4a59f44297" + (reference "U106") (unit 1) (value "d_inverter") (footprint "") + ) + (path "/345df87f-82d8-45f0-a2fe-fd05b09d37a1" + (reference "U107") (unit 1) (value "d_inverter") (footprint "") + ) + (path "/619e94d3-6d8f-47d2-80d0-414c142085fe" + (reference "U108") (unit 1) (value "d_inverter") (footprint "") + ) + (path "/38c22a5a-7426-4d8c-bf5d-58ef9050f17a" + (reference "U109") (unit 1) (value "d_inverter") (footprint "") + ) + (path "/ead9eede-4d15-4e87-a4db-277f5d58ad96" + (reference "U110") (unit 1) (value "d_inverter") (footprint "") + ) + (path "/abd89148-89a6-479e-bc30-d7f5c36a916a" + (reference "U111") (unit 1) (value "d_nand") (footprint "") + ) + (path "/6e42155f-b792-48fe-8959-5e64dbd9bae8" + (reference "U112") (unit 1) (value "d_nand") (footprint "") + ) + (path "/56c73fff-2e1f-4888-b322-f275af52606a" + (reference "U113") (unit 1) (value "d_nand") (footprint "") + ) + (path "/10861f48-6341-4cda-9acf-afadfbce4853" + (reference "U114") (unit 1) (value "d_nand") (footprint "") + ) + (path "/45bef100-3b8a-46d6-87bf-36860d89bcde" + (reference "U115") (unit 1) (value "d_nand") (footprint "") + ) + (path "/cdc2100f-2282-429a-b3d7-f0729b6f6eb9" + (reference "U116") (unit 1) (value "d_nand") (footprint "") + ) + (path "/a60dd54d-2c20-4ab1-869d-84864ba78bdf" + (reference "U117") (unit 1) (value "d_nand") (footprint "") + ) + (path "/50ee90cd-b609-45be-8652-9c8dc8366bbf" + (reference "U118") (unit 1) (value "d_nand") (footprint "") + ) + (path "/7264414f-408f-43c7-81c0-37dd5ff94a5b" + (reference "U119") (unit 1) (value "d_nand") (footprint "") + ) + (path "/d0d7aac7-e7d2-428f-ac27-5bb4c5a92466" + (reference "U120") (unit 1) (value "d_inverter") (footprint "") + ) + (path "/1513d772-a4ac-4963-8fd5-be2aa621e74b" + (reference "U121") (unit 1) (value "d_inverter") (footprint "") + ) + (path "/4dd863ce-b7f1-4200-bc45-b174edb1ac92" + (reference "U122") (unit 1) (value "d_inverter") (footprint "") + ) + (path "/e681427b-d2fe-4328-9307-b1643091a505" + (reference "U123") (unit 1) (value "d_inverter") (footprint "") + ) + (path "/03ef26b4-2046-4211-b828-d8ffbfcd1015" + (reference "U124") (unit 1) (value "d_inverter") (footprint "") + ) + (path "/ac3abb3f-dd5a-45d9-9547-2b5f76c27838" + (reference "U125") (unit 1) (value "d_inverter") (footprint "") + ) + ) +) diff --git a/library/SubcircuitLibrary/3_or/3_or.sub b/library/SubcircuitLibrary/3_or/3_or.sub new file mode 100644 index 000000000..73b9a602d --- /dev/null +++ b/library/SubcircuitLibrary/3_or/3_or.sub @@ -0,0 +1,102 @@ +* Subcircuit 3_or +.subckt 3_or net-_u101-pad1_ net-_u101-pad2_ net-_u101-pad3_ net-_u101-pad4_ net-_u101-pad5_ net-_u101-pad6_ unconnected-_u101-pad7_ net-_u101-pad8_ net-_u101-pad9_ net-_u101-pad10_ net-_u101-pad11_ net-_u101-pad12_ net-_u101-pad13_ unconnected-_u101-pad14_ +.title kicad schematic +* u112 net-_u104-pad2_ net-_u106-pad2_ net-_u112-pad3_ d_nand +* u106 net-_u101-pad4_ net-_u106-pad2_ d_inverter +* u109 net-_u101-pad12_ net-_u109-pad2_ d_inverter +* u110 net-_u101-pad13_ net-_u110-pad2_ d_inverter +* u107 net-_u101-pad5_ net-_u107-pad2_ d_inverter +* u108 net-_u101-pad11_ net-_u108-pad2_ d_inverter +* u113 net-_u108-pad2_ net-_u109-pad2_ net-_u113-pad3_ d_nand +* u103 net-_u101-pad2_ net-_u103-pad2_ d_inverter +* u102 net-_u101-pad1_ net-_u102-pad2_ d_inverter +* u114 net-_u111-pad3_ net-_u111-pad3_ net-_u114-pad3_ d_nand +* u111 net-_u102-pad2_ net-_u103-pad2_ net-_u111-pad3_ d_nand +* u104 net-_u101-pad3_ net-_u104-pad2_ d_inverter +* u105 net-_u101-pad8_ net-_u105-pad2_ d_inverter +* u115 net-_u112-pad3_ net-_u112-pad3_ net-_u115-pad3_ d_nand +* u119 net-_u116-pad3_ net-_u110-pad2_ net-_u119-pad3_ d_nand +* u116 net-_u113-pad3_ net-_u113-pad3_ net-_u116-pad3_ d_nand +* u125 net-_u122-pad2_ net-_u101-pad10_ d_inverter +* u122 net-_u119-pad3_ net-_u122-pad2_ d_inverter +* u121 net-_u118-pad3_ net-_u121-pad2_ d_inverter +* u118 net-_u115-pad3_ net-_u107-pad2_ net-_u118-pad3_ d_nand +* u117 net-_u114-pad3_ net-_u105-pad2_ net-_u117-pad3_ d_nand +* u124 net-_u121-pad2_ net-_u101-pad6_ d_inverter +* u123 net-_u120-pad2_ net-_u101-pad9_ d_inverter +* u120 net-_u117-pad3_ net-_u120-pad2_ d_inverter +a1 [net-_u104-pad2_ net-_u106-pad2_ ] net-_u112-pad3_ u112 +a2 net-_u101-pad4_ net-_u106-pad2_ u106 +a3 net-_u101-pad12_ net-_u109-pad2_ u109 +a4 net-_u101-pad13_ net-_u110-pad2_ u110 +a5 net-_u101-pad5_ net-_u107-pad2_ u107 +a6 net-_u101-pad11_ net-_u108-pad2_ u108 +a7 [net-_u108-pad2_ net-_u109-pad2_ ] net-_u113-pad3_ u113 +a8 net-_u101-pad2_ net-_u103-pad2_ u103 +a9 net-_u101-pad1_ net-_u102-pad2_ u102 +a10 [net-_u111-pad3_ net-_u111-pad3_ ] net-_u114-pad3_ u114 +a11 [net-_u102-pad2_ net-_u103-pad2_ ] net-_u111-pad3_ u111 +a12 net-_u101-pad3_ net-_u104-pad2_ u104 +a13 net-_u101-pad8_ net-_u105-pad2_ u105 +a14 [net-_u112-pad3_ net-_u112-pad3_ ] net-_u115-pad3_ u115 +a15 [net-_u116-pad3_ net-_u110-pad2_ ] net-_u119-pad3_ u119 +a16 [net-_u113-pad3_ net-_u113-pad3_ ] net-_u116-pad3_ u116 +a17 net-_u122-pad2_ net-_u101-pad10_ u125 +a18 net-_u119-pad3_ net-_u122-pad2_ u122 +a19 net-_u118-pad3_ net-_u121-pad2_ u121 +a20 [net-_u115-pad3_ net-_u107-pad2_ ] net-_u118-pad3_ u118 +a21 [net-_u114-pad3_ net-_u105-pad2_ ] net-_u117-pad3_ u117 +a22 net-_u121-pad2_ net-_u101-pad6_ u124 +a23 net-_u120-pad2_ net-_u101-pad9_ u123 +a24 net-_u117-pad3_ net-_u120-pad2_ u120 +* Schematic Name: d_nand, Ngspice Name: d_nand +.model u112 d_nand(rise_delay=5n fall_delay=5n input_load=1.0e-12 ) +* Schematic Name: d_inverter, Ngspice Name: d_inverter +.model u106 d_inverter(rise_delay=5n fall_delay=5n input_load=1.0e-12 ) +* Schematic Name: d_inverter, Ngspice Name: d_inverter +.model u109 d_inverter(rise_delay=5n fall_delay=5n input_load=1.0e-12 ) +* Schematic Name: d_inverter, Ngspice Name: d_inverter +.model u110 d_inverter(rise_delay=5n fall_delay=5n input_load=1.0e-12 ) +* Schematic Name: d_inverter, Ngspice Name: d_inverter +.model u107 d_inverter(rise_delay=5n fall_delay=5n input_load=1.0e-12 ) +* Schematic Name: d_inverter, Ngspice Name: d_inverter +.model u108 d_inverter(rise_delay=5n fall_delay=5n input_load=1.0e-12 ) +* Schematic Name: d_nand, Ngspice Name: d_nand +.model u113 d_nand(rise_delay=5n fall_delay=5n input_load=1.0e-12 ) +* Schematic Name: d_inverter, Ngspice Name: d_inverter +.model u103 d_inverter(rise_delay=5n fall_delay=5n input_load=1.0e-12 ) +* Schematic Name: d_inverter, Ngspice Name: d_inverter +.model u102 d_inverter(rise_delay=5n fall_delay=5n input_load=1.0e-12 ) +* Schematic Name: d_nand, Ngspice Name: d_nand +.model u114 d_nand(rise_delay=5n fall_delay=5n input_load=1.0e-12 ) +* Schematic Name: d_nand, Ngspice Name: d_nand +.model u111 d_nand(rise_delay=5n fall_delay=5n input_load=1.0e-12 ) +* Schematic Name: d_inverter, Ngspice Name: d_inverter +.model u104 d_inverter(rise_delay=5n fall_delay=5n input_load=1.0e-12 ) +* Schematic Name: d_inverter, Ngspice Name: d_inverter +.model u105 d_inverter(rise_delay=5n fall_delay=5n input_load=1.0e-12 ) +* Schematic Name: d_nand, Ngspice Name: d_nand +.model u115 d_nand(rise_delay=5n fall_delay=5n input_load=1.0e-12 ) +* Schematic Name: d_nand, Ngspice Name: d_nand +.model u119 d_nand(rise_delay=5n fall_delay=5n input_load=1.0e-12 ) +* Schematic Name: d_nand, Ngspice Name: d_nand +.model u116 d_nand(rise_delay=5n fall_delay=5n input_load=1.0e-12 ) +* Schematic Name: d_inverter, Ngspice Name: d_inverter +.model u125 d_inverter(rise_delay=5n fall_delay=5n input_load=1.0e-12 ) +* Schematic Name: d_inverter, Ngspice Name: d_inverter +.model u122 d_inverter(rise_delay=5n fall_delay=5n input_load=1.0e-12 ) +* Schematic Name: d_inverter, Ngspice Name: d_inverter +.model u121 d_inverter(rise_delay=5n fall_delay=5n input_load=1.0e-12 ) +* Schematic Name: d_nand, Ngspice Name: d_nand +.model u118 d_nand(rise_delay=5n fall_delay=5n input_load=1.0e-12 ) +* Schematic Name: d_nand, Ngspice Name: d_nand +.model u117 d_nand(rise_delay=5n fall_delay=5n input_load=1.0e-12 ) +* Schematic Name: d_inverter, Ngspice Name: d_inverter +.model u124 d_inverter(rise_delay=5n fall_delay=5n input_load=1.0e-12 ) +* Schematic Name: d_inverter, Ngspice Name: d_inverter +.model u123 d_inverter(rise_delay=5n fall_delay=5n input_load=1.0e-12 ) +* Schematic Name: d_inverter, Ngspice Name: d_inverter +.model u120 d_inverter(rise_delay=5n fall_delay=5n input_load=1.0e-12 ) +* Control Statements + +.ends 3_or \ No newline at end of file diff --git a/library/SubcircuitLibrary/3_or/3_or_Previous_Values.xml b/library/SubcircuitLibrary/3_or/3_or_Previous_Values.xml new file mode 100644 index 000000000..a92667c09 --- /dev/null +++ b/library/SubcircuitLibrary/3_or/3_or_Previous_Values.xml @@ -0,0 +1 @@ +5d_nand5n5nd_nand5n5nd_inverter5n5nd_inverter5n5nd_nand5n5nd_inverter5n5nd_inverter5n5nd_inverter5n5nd_inverter5n5nd_nand5n5nd_inverter5n5nd_nand5n5nd_inverter5n5nd_nand5n5nd_nand5n5nd_nand5n5nd_inverter5n5nd_inverter5n5nd_inverter5n5nd_inverter5n5nd_nand5n5nd_nand5n5nd_nand5n5nd_inverter5n5nd_inverter5n5nd_nand5n5nd_inverter5n5ntruefalsefalseHzHz0Volts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or Amperes01100secnsns \ No newline at end of file diff --git a/library/SubcircuitLibrary/3_or/3_or_gate.kicad_prl b/library/SubcircuitLibrary/3_or/3_or_gate.kicad_prl new file mode 100644 index 000000000..93cb54f55 --- /dev/null +++ b/library/SubcircuitLibrary/3_or/3_or_gate.kicad_prl @@ -0,0 +1,75 @@ +{ + "board": { + "active_layer": 0, + "active_layer_preset": "", + "auto_track_width": true, + "hidden_nets": [], + "high_contrast_mode": 0, + "net_color_mode": 1, + "opacity": { + "pads": 1.0, + "tracks": 1.0, + "vias": 1.0, + "zones": 0.6 + }, + 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(unit 1) (value "d_inverter") (footprint "") + ) + ) +) diff --git a/library/SubcircuitLibrary/3_or/NMOS-180nm.lib b/library/SubcircuitLibrary/3_or/NMOS-180nm.lib new file mode 100644 index 000000000..51e9b1196 --- /dev/null +++ b/library/SubcircuitLibrary/3_or/NMOS-180nm.lib @@ -0,0 +1,13 @@ +.model CMOSN NMOS (LEVEL=8 VERSION=3.2 TNOM=27 TOX=4.1E-9 XJ=1E-7 NCH=2.3549E17 VTH0=0.3823463 K1=0.5810697 ++ K2=4.774618E-3 K3=0.0431669 K3B=1.1498346 W0=1E-7 NLX=1.910552E-7 DVT0W=0 DVT1W=0 DVT2W=0 ++ DVT0=1.2894824 DVT1=0.3622063 DVT2=0.0713729 U0=280.633249 UA=-1.208537E-9 UB=2.158625E-18 ++ UC=5.342807E-11 VSAT=9.366802E4 A0=1.7593146 AGS=0.3939741 B0=-6.413949E-9 B1=-1E-7 KETA=-5.180424E-4 ++ A1=0 A2=1 RDSW=105.5517558 PRWG=0.5 PRWB=-0.1998871 WR=1 WINT=7.904732E-10 LINT=1.571424E-8 XL=0 ++ XW=-1E-8 DWG=1.297221E-9 DWB=1.479041E-9 VOFF=-0.0955434 NFACTOR=2.4358891 CIT=0 CDSC=2.4E-4 CDSCD=0 ++ CDSCB=0 ETA0=3.104851E-3 ETAB=-2.512384E-5 DSUB=0.0167075 PCLM=0.8073191 PDIBLC1=0.1666161 PDIBLC2=3.112892E-3 ++ PDIBLCB=-0.1 DROUT=0.7875618 PSCBE1=8E10 PSCBE2=9.213635E-10 PVAG=3.85243E-3 DELTA=0.01 RSH=6.7 MOBMOD=1 ++ PRT=0 UTE=-1.5 KT1=-0.11 KT1L=0 KT2=0.022 UA1=4.31E-9 UB1=-7.61E-18 UC1=-5.6E-11 AT=3.3E4 WL=0 WLN=1 ++ WW=0 WWN=1 WWL=0 LL=0 LLN=1 LW=0 LWN=1 LWL=0 CAPMOD=2 XPART=0.5 CGDO=7.08E-10 CGSO=7.08E-10 CGBO=1E-12 ++ CJ=9.68858E-4 PB=0.8 MJ=0.3864502 CJSW=2.512138E-10 PBSW=0.809286 MJSW=0.1060414 CJSWG=3.3E-10 PBSWG=0.809286 ++ MJSWG=0.1060414 CF=0 PVTH0=-1.192722E-3 PRDSW=-5 PK2=6.450505E-5 WKETA=-4.27294E-4 LKETA=-0.0104078 ++ PU0=6.3268729 PUA=2.226552E-11 PUB=0 PVSAT=969.1480157 PETA0=1E-4 PKETA=-1.049509E-3) diff --git a/library/SubcircuitLibrary/3_or/NMOS-5um.lib b/library/SubcircuitLibrary/3_or/NMOS-5um.lib new file mode 100644 index 000000000..a237e1fe3 --- /dev/null +++ b/library/SubcircuitLibrary/3_or/NMOS-5um.lib @@ -0,0 +1,5 @@ +* 5um technology + +.model mos_n NMOS( Cgso=0.4n Tox=85n Vto=1 phi=0.7 ++ Level=1 ++ Mj=.5 UO=750 Cgdo=0.4n Gamma=1.4 LAMBDA=0.01 LD=0.7u JS=1u CJ=0.4m CJSW=0.8n MJSW=0.5 PB=0.7 CGBO=0.2n ) diff --git a/library/SubcircuitLibrary/3_or/PMOS-180nm.lib b/library/SubcircuitLibrary/3_or/PMOS-180nm.lib new file mode 100644 index 000000000..032b5b95e --- /dev/null +++ b/library/SubcircuitLibrary/3_or/PMOS-180nm.lib @@ -0,0 +1,11 @@ +.model CMOSP PMOS (LEVEL=8 VERSION=3.2 TNOM=27 TOX=4.1E-9 XJ=1E-7 NCH=4.1589E17 VTH0=-0.3938813 K1=0.5479015 ++ K2=0.0360586 K3=0.0993095 K3B=5.7086622 W0=1E-6 NLX=1.313191E-7 DVT0W=0 DVT1W=0 DVT2W=0 DVT0=0.4911363 ++ DVT1=0.2227356 DVT2=0.1 U0=115.6852975 UA=1.505832E-9 UB=1E-21 UC=-1E-10 VSAT=1.329694E5 A0=1.7590478 ++ AGS=0.3641621 B0=3.427126E-7 B1=1.062928E-6 KETA=0.0134667 A1=0.6859506 A2=0.3506788 RDSW=168.5705677 ++ PRWG=0.5 PRWB=-0.4987371 WR=1 WINT=0 LINT=3.028832E-8 XL=0 XW=-1E-8 DWG=-2.349633E-8 DWB=-7.152486E-9 ++ VOFF=-0.0994037 NFACTOR=1.9424315 CIT=0 CDSC=2.4E-4 CDSCD=0 CDSCB=0 ETA0=0.0608072 ETAB=-0.0426148 ++ DSUB=0.7343015 PCLM=3.2579974 PDIBLC1=7.229527E-6 PDIBLC2=0.025389 PDIBLCB=-1E-3 DROUT=0 PSCBE1=1.454878E10 ++ PSCBE2=4.202027E-9 PVAG=15 DELTA=0.01 RSH=7.8 MOBMOD=1 PRT=0 UTE=-1.5 KT1=-0.11 KT1L=0 KT2=0.022 UA1=4.31E-9 ++ UB1=-7.61E-18 UC1=-5.6E-11 AT=3.3E4 WL=0 WLN=1 WW=0 WWN=1 WWL=0 LL=0 LLN=1 LW=0 LWN=1 LWL=0 CAPMOD=2 XPART=0.5 ++ CGDO=6.32E-10 CGSO=6.32E-10 CGBO=1E-12 CJ=1.172138E-3 PB=0.8421173 MJ=0.4109788 CJSW=2.242609E-10 PBSW=0.8 + MJSW=0.3752089 CJSWG=4.22E-10 PBSWG=0.8 MJSWG=0.3752089 CF=0 PVTH0=1.888482E-3 PRDSW=11.5315407 PK2=1.559399E-3 ++ WKETA=0.0319301 LKETA=2.955547E-3 PU0=-1.1105313 PUA=-4.62102E-11 PUB=1E-21 PVSAT=50 PETA0=1E-4 PKETA=-4.346368E-3) diff --git a/library/SubcircuitLibrary/3_or/PMOS-5um.lib b/library/SubcircuitLibrary/3_or/PMOS-5um.lib new file mode 100644 index 000000000..9c3ed9760 --- /dev/null +++ b/library/SubcircuitLibrary/3_or/PMOS-5um.lib @@ -0,0 +1,5 @@ +*5um technology + +.model mos_p PMOS( Cgso=0.4n Tox=85n Vto=-1 phi=0.65 ++ Level=1 ++ Mj=.5 UO=250 Cgdo=0.4n Gamma=0.65 LAMBDA=0.03 LD=0.6u JS=1u CJ=0.18m CJSW=0.6n MJSW=0.5 PB=0.7 CGBO=0.2n ) diff --git a/library/SubcircuitLibrary/3_or/analysis b/library/SubcircuitLibrary/3_or/analysis new file mode 100644 index 000000000..e299e97d9 --- /dev/null +++ b/library/SubcircuitLibrary/3_or/analysis @@ -0,0 +1 @@ +.tran 1e-09 100e-09 0e-00 \ No newline at end of file diff --git a/library/SubcircuitLibrary/3_or/eSim_Subckt.kicad_sym b/library/SubcircuitLibrary/3_or/eSim_Subckt.kicad_sym new file mode 100644 index 000000000..28bd9e520 --- /dev/null +++ b/library/SubcircuitLibrary/3_or/eSim_Subckt.kicad_sym @@ -0,0 +1,6806 @@ +(kicad_symbol_lib (version 20211014) (generator kicad_symbol_editor) + (symbol "10bitDAC" (pin_names (offset 1.016)) (in_bom yes) (on_board yes) + (property "Reference" "X" (id 0) (at 0 1.27 0) + (effects (font (size 1.524 1.524))) + ) + (property "Value" "10bitDAC" (id 1) (at -1.27 -1.27 0) + (effects (font (size 1.524 1.524))) + ) + (property "Footprint" "" (id 2) (at 0 1.27 0) + (effects (font (size 1.524 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1.27)))) + ) + (pin input line (at -3.81 -6.35 90) (length 5.08) + (name "~" (effects (font (size 1.27 1.27)))) + (number "2" (effects (font (size 1.27 1.27)))) + ) + (pin input line (at 8.89 0 180) (length 5.08) + (name "~" (effects (font (size 1.27 1.27)))) + (number "3" (effects (font (size 1.27 1.27)))) + ) + (pin output line (at 3.81 -6.35 90) (length 5.08) + (name "~" (effects (font (size 1.27 1.27)))) + (number "4" (effects (font (size 1.27 1.27)))) + ) + ) + ) +) From aab23ea4d8c7da11c0283736edfc4c0f67ebc746 Mon Sep 17 00:00:00 2001 From: Sakshi Pandey Date: Sat, 24 Jan 2026 13:49:37 +0530 Subject: [PATCH 7/8] SN74LVC1G386 is a 3 input XOR GATE --- .../SubcircuitLibrary/3_xor/3_and-cache.lib | 61 + library/SubcircuitLibrary/3_xor/3_and.cir | 13 + library/SubcircuitLibrary/3_xor/3_and.cir.out | 20 + library/SubcircuitLibrary/3_xor/3_and.pro | 43 + library/SubcircuitLibrary/3_xor/3_and.sch | 130 + library/SubcircuitLibrary/3_xor/3_and.sub | 14 + .../3_xor/3_and_Previous_Values.xml | 1 + library/SubcircuitLibrary/3_xor/3_xor.cir | 19 + library/SubcircuitLibrary/3_xor/3_xor.cir.out | 65 + .../SubcircuitLibrary/3_xor/3_xor.kicad_prl | 75 + .../SubcircuitLibrary/3_xor/3_xor.kicad_pro | 294 + .../SubcircuitLibrary/3_xor/3_xor.kicad_sch | 1177 +++ library/SubcircuitLibrary/3_xor/3_xor.sub | 59 + .../3_xor/3_xor_Previous_Values.xml | 1 + .../3_xor/_autosave-3_xor.sch | 333 + library/SubcircuitLibrary/3_xor/analysis | 1 + .../3_xor/eSim_Subckt.kicad_sym | 7191 +++++++++++++++++ 17 files changed, 9497 insertions(+) create mode 100644 library/SubcircuitLibrary/3_xor/3_and-cache.lib create mode 100644 library/SubcircuitLibrary/3_xor/3_and.cir create mode 100644 library/SubcircuitLibrary/3_xor/3_and.cir.out create mode 100644 library/SubcircuitLibrary/3_xor/3_and.pro create mode 100644 library/SubcircuitLibrary/3_xor/3_and.sch create mode 100644 library/SubcircuitLibrary/3_xor/3_and.sub create mode 100644 library/SubcircuitLibrary/3_xor/3_and_Previous_Values.xml create mode 100644 library/SubcircuitLibrary/3_xor/3_xor.cir create mode 100644 library/SubcircuitLibrary/3_xor/3_xor.cir.out create mode 100644 library/SubcircuitLibrary/3_xor/3_xor.kicad_prl create mode 100644 library/SubcircuitLibrary/3_xor/3_xor.kicad_pro create mode 100644 library/SubcircuitLibrary/3_xor/3_xor.kicad_sch create mode 100644 library/SubcircuitLibrary/3_xor/3_xor.sub create mode 100644 library/SubcircuitLibrary/3_xor/3_xor_Previous_Values.xml create mode 100644 library/SubcircuitLibrary/3_xor/_autosave-3_xor.sch create mode 100644 library/SubcircuitLibrary/3_xor/analysis create mode 100644 library/SubcircuitLibrary/3_xor/eSim_Subckt.kicad_sym diff --git a/library/SubcircuitLibrary/3_xor/3_and-cache.lib b/library/SubcircuitLibrary/3_xor/3_and-cache.lib new file mode 100644 index 000000000..af0586415 --- /dev/null +++ b/library/SubcircuitLibrary/3_xor/3_and-cache.lib @@ -0,0 +1,61 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# PORT +# +DEF PORT U 0 40 Y Y 26 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +X ~ 9 250 0 100 L 30 30 9 1 B +X ~ 10 250 0 100 L 30 30 10 1 B +X ~ 11 250 0 100 L 30 30 11 1 B +X ~ 12 250 0 100 L 30 30 12 1 B +X ~ 13 250 0 100 L 30 30 13 1 B +X ~ 14 250 0 100 L 30 30 14 1 B +X ~ 15 250 0 100 L 30 30 15 1 B +X ~ 16 250 0 100 L 30 30 16 1 B +X ~ 17 250 0 100 L 30 30 17 1 B +X ~ 18 250 0 100 L 30 30 18 1 B +X ~ 19 250 0 100 L 30 30 19 1 B +X ~ 20 250 0 100 L 30 30 20 1 B +X ~ 21 250 0 100 L 30 30 21 1 B +X ~ 22 250 0 100 L 30 30 22 1 B +X ~ 23 250 0 100 L 30 30 23 1 B +X ~ 24 250 0 100 L 30 30 24 1 B +X ~ 25 250 0 100 L 30 30 25 1 B +X ~ 26 250 0 100 L 30 30 26 1 B +ENDDRAW +ENDDEF +# +# d_and +# +DEF d_and U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_and" 50 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 149 50 100 -894 0 0 1 0 N 150 -50 250 50 +A 150 49 100 6 900 0 1 0 N 250 50 150 150 +P 4 0 1 0 150 -50 -250 -50 -250 150 150 150 N +X IN1 1 -450 100 200 R 50 50 1 1 I +X IN2 2 -450 0 200 R 50 50 1 1 I +X OUT 3 450 50 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +#End Library diff --git a/library/SubcircuitLibrary/3_xor/3_and.cir b/library/SubcircuitLibrary/3_xor/3_and.cir new file mode 100644 index 000000000..ba296cf01 --- /dev/null +++ b/library/SubcircuitLibrary/3_xor/3_and.cir @@ -0,0 +1,13 @@ +* C:\Users\malli\eSim\src\SubcircuitLibrary\3_and\3_and.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: 03/26/19 18:42:57 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +U2 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U2-Pad3_ d_and +U3 Net-_U2-Pad3_ Net-_U1-Pad3_ Net-_U1-Pad4_ d_and +U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ PORT + +.end diff --git a/library/SubcircuitLibrary/3_xor/3_and.cir.out b/library/SubcircuitLibrary/3_xor/3_and.cir.out new file mode 100644 index 000000000..d7cf79a07 --- /dev/null +++ b/library/SubcircuitLibrary/3_xor/3_and.cir.out @@ -0,0 +1,20 @@ +* c:\users\malli\esim\src\subcircuitlibrary\3_and\3_and.cir + +* u2 net-_u1-pad1_ net-_u1-pad2_ net-_u2-pad3_ d_and +* u3 net-_u2-pad3_ net-_u1-pad3_ net-_u1-pad4_ d_and +* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ port +a1 [net-_u1-pad1_ net-_u1-pad2_ ] net-_u2-pad3_ u2 +a2 [net-_u2-pad3_ net-_u1-pad3_ ] net-_u1-pad4_ u3 +* Schematic Name: d_and, NgSpice Name: d_and +.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u3 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +.tran 0e-00 0e-00 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/library/SubcircuitLibrary/3_xor/3_and.pro b/library/SubcircuitLibrary/3_xor/3_and.pro new file mode 100644 index 000000000..00597a5ad --- /dev/null +++ b/library/SubcircuitLibrary/3_xor/3_and.pro @@ -0,0 +1,43 @@ +update=05/31/19 15:26:09 +version=1 +last_client=eeschema +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir=../../../kicadSchematicLibrary +[eeschema/libraries] +LibName1=eSim_Analog +LibName2=eSim_Devices +LibName3=eSim_Digital +LibName4=eSim_Hybrid +LibName5=eSim_Miscellaneous +LibName6=eSim_Plot +LibName7=eSim_Power +LibName8=eSim_User +LibName9=eSim_Sources +LibName10=eSim_Subckt diff --git a/library/SubcircuitLibrary/3_xor/3_and.sch b/library/SubcircuitLibrary/3_xor/3_and.sch new file mode 100644 index 000000000..d6ac89f95 --- /dev/null +++ b/library/SubcircuitLibrary/3_xor/3_and.sch @@ -0,0 +1,130 @@ +EESchema Schematic File Version 2 +LIBS:power +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:valves +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Plot +LIBS:eSim_Power +LIBS:eSim_PSpice +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:eSim_User +LIBS:3_and-cache +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L d_and U2 +U 1 1 5C9A24D8 +P 4250 2700 +F 0 "U2" H 4250 2700 60 0000 C CNN +F 1 "d_and" H 4300 2800 60 0000 C CNN +F 2 "" H 4250 2700 60 0000 C CNN +F 3 "" H 4250 2700 60 0000 C CNN + 1 4250 2700 + 1 0 0 -1 +$EndComp +$Comp +L d_and U3 +U 1 1 5C9A2538 +P 5150 2900 +F 0 "U3" H 5150 2900 60 0000 C CNN +F 1 "d_and" H 5200 3000 60 0000 C CNN +F 2 "" H 5150 2900 60 0000 C CNN +F 3 "" H 5150 2900 60 0000 C CNN + 1 5150 2900 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 1 1 5C9A259A +P 3050 2600 +F 0 "U1" H 3100 2700 30 0000 C CNN +F 1 "PORT" H 3050 2600 30 0000 C CNN +F 2 "" H 3050 2600 60 0000 C CNN +F 3 "" H 3050 2600 60 0000 C CNN + 1 3050 2600 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 2 1 5C9A25D9 +P 3050 2800 +F 0 "U1" H 3100 2900 30 0000 C CNN +F 1 "PORT" H 3050 2800 30 0000 C CNN +F 2 "" H 3050 2800 60 0000 C CNN +F 3 "" H 3050 2800 60 0000 C CNN + 2 3050 2800 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 3 1 5C9A260A +P 3050 3100 +F 0 "U1" H 3100 3200 30 0000 C CNN +F 1 "PORT" H 3050 3100 30 0000 C CNN +F 2 "" H 3050 3100 60 0000 C CNN +F 3 "" H 3050 3100 60 0000 C CNN + 3 3050 3100 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 4 1 5C9A2637 +P 6900 2850 +F 0 "U1" H 6950 2950 30 0000 C CNN +F 1 "PORT" H 6900 2850 30 0000 C CNN +F 2 "" H 6900 2850 60 0000 C CNN +F 3 "" H 6900 2850 60 0000 C CNN + 4 6900 2850 + -1 0 0 1 +$EndComp +Wire Wire Line + 4700 2650 4700 2800 +Wire Wire Line + 5600 2850 6650 2850 +Wire Wire Line + 3800 2600 3300 2600 +Wire Wire Line + 3800 2700 3300 2700 +Wire Wire Line + 3300 2700 3300 2800 +Wire Wire Line + 3300 3100 4700 3100 +Wire Wire Line + 4700 3100 4700 2900 +Text Notes 3500 2600 0 60 ~ 12 +in1 +Text Notes 3450 2800 0 60 ~ 12 +in2\n +Text Notes 3500 3100 0 60 ~ 12 +in3 +Text Notes 6100 2850 0 60 ~ 12 +out +$EndSCHEMATC diff --git a/library/SubcircuitLibrary/3_xor/3_and.sub b/library/SubcircuitLibrary/3_xor/3_and.sub new file mode 100644 index 000000000..3d9120bb6 --- /dev/null +++ b/library/SubcircuitLibrary/3_xor/3_and.sub @@ -0,0 +1,14 @@ +* Subcircuit 3_and +.subckt 3_and net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ +* c:\users\malli\esim\src\subcircuitlibrary\3_and\3_and.cir +* u2 net-_u1-pad1_ net-_u1-pad2_ net-_u2-pad3_ d_and +* u3 net-_u2-pad3_ net-_u1-pad3_ net-_u1-pad4_ d_and +a1 [net-_u1-pad1_ net-_u1-pad2_ ] net-_u2-pad3_ u2 +a2 [net-_u2-pad3_ net-_u1-pad3_ ] net-_u1-pad4_ u3 +* Schematic Name: d_and, NgSpice Name: d_and +.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u3 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Control Statements + +.ends 3_and \ No newline at end of file diff --git a/library/SubcircuitLibrary/3_xor/3_and_Previous_Values.xml b/library/SubcircuitLibrary/3_xor/3_and_Previous_Values.xml new file mode 100644 index 000000000..abc5faaae --- /dev/null +++ b/library/SubcircuitLibrary/3_xor/3_and_Previous_Values.xml @@ -0,0 +1 @@ +d_andd_andtruefalsefalseHzHz0Volts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesSecSecSec \ No newline at end of file diff --git a/library/SubcircuitLibrary/3_xor/3_xor.cir b/library/SubcircuitLibrary/3_xor/3_xor.cir new file mode 100644 index 000000000..3a9267924 --- /dev/null +++ b/library/SubcircuitLibrary/3_xor/3_xor.cir @@ -0,0 +1,19 @@ +.title KiCad schematic +X104 Net-_U102-Pad2_ Net-_U106-Pad2_ Net-_U105-Pad2_ Net-_U109-Pad1_ 3_and +U109 Net-_U109-Pad1_ Net-_U109-Pad2_ Net-_U109-Pad3_ d_nor +U111 Net-_U109-Pad3_ Net-_U112-Pad2_ d_inverter +U108 Net-_U108-Pad1_ Net-_U108-Pad2_ Net-_U108-Pad3_ d_nor +U110 Net-_U108-Pad3_ Net-_U112-Pad1_ d_inverter +U113 Net-_U113-Pad1_ Net-_U101-Pad4_ d_inverter +U112 Net-_U112-Pad1_ Net-_U112-Pad2_ Net-_U113-Pad1_ d_nor +U101 Net-_U101-Pad1_ Net-_U101-Pad2_ Net-_U101-Pad3_ Net-_U101-Pad4_ PORT +X103 Net-_U106-Pad2_ Net-_U107-Pad2_ Net-_U103-Pad2_ Net-_U108-Pad1_ 3_and +U106 Net-_U104-Pad2_ Net-_U106-Pad2_ d_inverter +X101 Net-_U104-Pad2_ Net-_U107-Pad2_ Net-_U105-Pad2_ Net-_U108-Pad2_ 3_and +U107 Net-_U102-Pad2_ Net-_U107-Pad2_ d_inverter +X102 Net-_U103-Pad2_ Net-_U102-Pad2_ Net-_U104-Pad2_ Net-_U109-Pad2_ 3_and +U102 Net-_U101-Pad2_ Net-_U102-Pad2_ d_buffer +U104 Net-_U101-Pad1_ Net-_U104-Pad2_ d_buffer +U103 Net-_U101-Pad3_ Net-_U103-Pad2_ d_buffer +U105 Net-_U103-Pad2_ Net-_U105-Pad2_ d_inverter +.end diff --git a/library/SubcircuitLibrary/3_xor/3_xor.cir.out b/library/SubcircuitLibrary/3_xor/3_xor.cir.out new file mode 100644 index 000000000..0d54f6e05 --- /dev/null +++ b/library/SubcircuitLibrary/3_xor/3_xor.cir.out @@ -0,0 +1,65 @@ +.title kicad schematic + +.include 3_and.sub +x104 net-_u102-pad2_ net-_u106-pad2_ net-_u105-pad2_ net-_u109-pad1_ 3_and +* u109 net-_u109-pad1_ net-_u109-pad2_ net-_u109-pad3_ d_nor +* u111 net-_u109-pad3_ net-_u112-pad2_ d_inverter +* u108 net-_u108-pad1_ net-_u108-pad2_ net-_u108-pad3_ d_nor +* u110 net-_u108-pad3_ net-_u112-pad1_ d_inverter +* u113 net-_u113-pad1_ net-_u101-pad4_ d_inverter +* u112 net-_u112-pad1_ net-_u112-pad2_ net-_u113-pad1_ d_nor +* u101 net-_u101-pad1_ net-_u101-pad2_ net-_u101-pad3_ net-_u101-pad4_ port +x103 net-_u106-pad2_ net-_u107-pad2_ net-_u103-pad2_ net-_u108-pad1_ 3_and +* u106 net-_u104-pad2_ net-_u106-pad2_ d_inverter +x101 net-_u104-pad2_ net-_u107-pad2_ net-_u105-pad2_ net-_u108-pad2_ 3_and +* u107 net-_u102-pad2_ net-_u107-pad2_ d_inverter +x102 net-_u103-pad2_ net-_u102-pad2_ net-_u104-pad2_ net-_u109-pad2_ 3_and +* u102 net-_u101-pad2_ net-_u102-pad2_ d_buffer +* u104 net-_u101-pad1_ net-_u104-pad2_ d_buffer +* u103 net-_u101-pad3_ net-_u103-pad2_ d_buffer +* u105 net-_u103-pad2_ net-_u105-pad2_ d_inverter +a1 [net-_u109-pad1_ net-_u109-pad2_ ] net-_u109-pad3_ u109 +a2 net-_u109-pad3_ net-_u112-pad2_ u111 +a3 [net-_u108-pad1_ net-_u108-pad2_ ] net-_u108-pad3_ u108 +a4 net-_u108-pad3_ net-_u112-pad1_ u110 +a5 net-_u113-pad1_ net-_u101-pad4_ u113 +a6 [net-_u112-pad1_ net-_u112-pad2_ ] net-_u113-pad1_ u112 +a7 net-_u104-pad2_ net-_u106-pad2_ u106 +a8 net-_u102-pad2_ net-_u107-pad2_ u107 +a9 net-_u101-pad2_ net-_u102-pad2_ u102 +a10 net-_u101-pad1_ net-_u104-pad2_ u104 +a11 net-_u101-pad3_ net-_u103-pad2_ u103 +a12 net-_u103-pad2_ net-_u105-pad2_ u105 +* Schematic Name: d_nor, Ngspice Name: d_nor +.model u109 d_nor(rise_delay=5n fall_delay=5n input_load=1.0e-12 ) +* Schematic Name: d_inverter, Ngspice Name: d_inverter +.model u111 d_inverter(rise_delay=2n fall_delay=2n input_load=1.0e-12 ) +* Schematic Name: d_nor, Ngspice Name: d_nor +.model u108 d_nor(rise_delay=5n fall_delay=5n input_load=1.0e-12 ) +* Schematic Name: d_inverter, Ngspice Name: d_inverter +.model u110 d_inverter(rise_delay=2n fall_delay=2n input_load=1.0e-12 ) +* Schematic Name: d_inverter, Ngspice Name: d_inverter +.model u113 d_inverter(rise_delay=2n fall_delay=2n input_load=1.0e-12 ) +* Schematic Name: d_nor, Ngspice Name: d_nor +.model u112 d_nor(rise_delay=5n fall_delay=5n input_load=1.0e-12 ) +* Schematic Name: d_inverter, Ngspice Name: d_inverter +.model u106 d_inverter(rise_delay=2n fall_delay=2n input_load=1.0e-12 ) +* Schematic Name: d_inverter, Ngspice Name: d_inverter +.model u107 d_inverter(rise_delay=2n fall_delay=2n input_load=1.0e-12 ) +* Schematic Name: d_buffer, Ngspice Name: d_buffer +.model u102 d_buffer(rise_delay=2n fall_delay=2n input_load=1.0e-12 ) +* Schematic Name: d_buffer, Ngspice Name: d_buffer +.model u104 d_buffer(rise_delay=2n fall_delay=2n input_load=1.0e-12 ) +* Schematic Name: d_buffer, Ngspice Name: d_buffer +.model u103 d_buffer(rise_delay=2n fall_delay=2n input_load=1.0e-12 ) +* Schematic Name: d_inverter, Ngspice Name: d_inverter +.model u105 d_inverter(rise_delay=5n fall_delay=5n input_load=1.0e-12 ) +.tran 0.1e-09 80e-09 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/library/SubcircuitLibrary/3_xor/3_xor.kicad_prl b/library/SubcircuitLibrary/3_xor/3_xor.kicad_prl new file mode 100644 index 000000000..973879fbc --- /dev/null +++ b/library/SubcircuitLibrary/3_xor/3_xor.kicad_prl @@ -0,0 +1,75 @@ +{ + "board": { + "active_layer": 0, + "active_layer_preset": "", + "auto_track_width": true, + "hidden_nets": [], + "high_contrast_mode": 0, + "net_color_mode": 1, + "opacity": { + "pads": 1.0, + "tracks": 1.0, + "vias": 1.0, + "zones": 0.6 + }, + "ratsnest_display_mode": 0, + "selection_filter": { + "dimensions": true, + "footprints": true, + "graphics": true, + "keepouts": true, + "lockedItems": true, + "otherItems": true, + "pads": true, + "text": true, + "tracks": true, + "vias": true, + "zones": true + }, + "visible_items": [ + 0, + 1, + 2, + 3, + 4, + 5, + 8, + 9, + 10, + 11, + 12, + 13, + 14, + 15, + 16, + 17, + 18, + 19, + 20, + 21, + 22, + 23, + 24, + 25, + 26, + 27, + 28, + 29, + 30, + 32, + 33, + 34, + 35, + 36 + ], + "visible_layers": "fffffff_ffffffff", + "zone_display_mode": 0 + }, + "meta": { + "filename": "3_xor.kicad_prl", + "version": 3 + }, + "project": { + "files": [] + } +} diff --git a/library/SubcircuitLibrary/3_xor/3_xor.kicad_pro b/library/SubcircuitLibrary/3_xor/3_xor.kicad_pro new file mode 100644 index 000000000..c4c50fecb --- /dev/null +++ b/library/SubcircuitLibrary/3_xor/3_xor.kicad_pro @@ -0,0 +1,294 @@ +{ + "board": { + "layer_presets": [] + }, + "boards": [], + "cvpcb": { + "equivalence_files": [] + }, + "erc": { + "erc_exclusions": [], + "meta": { + "version": 0 + }, + "pin_map": [ + [ + 0, + 0, + 0, + 0, + 0, + 0, + 1, + 0, + 0, + 0, + 0, + 2 + ], + [ + 0, + 2, + 0, + 1, + 0, + 0, + 1, + 0, + 2, + 2, + 2, + 2 + ], + [ + 0, + 0, + 0, + 0, + 0, + 0, + 1, + 0, + 1, + 0, + 1, + 2 + ], + [ + 0, + 1, + 0, + 0, + 0, + 0, + 1, + 1, + 2, + 1, + 1, + 2 + ], + [ + 0, + 0, + 0, + 0, + 0, + 0, + 1, + 0, + 0, + 0, + 0, + 2 + ], + [ + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 2 + ], + [ + 1, + 1, + 1, + 1, + 1, + 0, + 1, + 1, + 1, + 1, + 1, + 2 + ], + [ + 0, + 0, + 0, + 1, + 0, + 0, + 1, + 0, + 0, + 0, + 0, + 2 + ], + [ + 0, + 2, + 1, + 2, + 0, + 0, + 1, + 0, + 2, + 2, + 2, + 2 + ], + [ + 0, + 2, + 0, + 1, + 0, + 0, + 1, + 0, + 2, + 0, + 0, + 2 + ], + [ + 0, + 2, + 1, + 1, + 0, + 0, + 1, + 0, + 2, + 0, + 0, + 2 + ], + [ + 2, + 2, + 2, + 2, + 2, + 2, + 2, + 2, + 2, + 2, + 2, + 2 + ] + ], + "rule_severities": { + "bus_definition_conflict": "error", + "bus_entry_needed": "error", + "bus_label_syntax": "error", + "bus_to_bus_conflict": "error", + "bus_to_net_conflict": "error", + "different_unit_footprint": "error", + "different_unit_net": "error", + "duplicate_reference": "error", + "duplicate_sheet_names": "error", + "extra_units": "error", + "global_label_dangling": "warning", + "hier_label_mismatch": "error", + "label_dangling": "error", + "lib_symbol_issues": "warning", + "multiple_net_names": "warning", + "net_not_bus_member": "warning", + "no_connect_connected": "warning", + "no_connect_dangling": "warning", + "pin_not_connected": "error", + "pin_not_driven": "error", + "pin_to_pin": "warning", + "power_pin_not_driven": "error", + "similar_labels": "warning", + "unannotated": "error", + "unit_value_mismatch": "error", + "unresolved_variable": "error", + "wire_dangling": "error" + } + }, + "libraries": { + "pinned_footprint_libs": [], + "pinned_symbol_libs": [] + }, + "meta": { + "filename": "3_xor.kicad_pro", + "version": 1 + }, + "net_settings": { + "classes": [ + { + "bus_width": 12.0, + "clearance": 0.2, + "diff_pair_gap": 0.25, + "diff_pair_via_gap": 0.25, + "diff_pair_width": 0.2, + "line_style": 0, + "microvia_diameter": 0.3, + "microvia_drill": 0.1, + "name": "Default", + "pcb_color": "rgba(0, 0, 0, 0.000)", + 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a/library/SubcircuitLibrary/3_xor/3_xor.sub b/library/SubcircuitLibrary/3_xor/3_xor.sub new file mode 100644 index 000000000..f432cac48 --- /dev/null +++ b/library/SubcircuitLibrary/3_xor/3_xor.sub @@ -0,0 +1,59 @@ +* Subcircuit 3_xor +.subckt 3_xor net-_u101-pad1_ net-_u101-pad2_ net-_u101-pad3_ net-_u101-pad4_ +.title kicad schematic +.include 3_and.sub +x104 net-_u102-pad2_ net-_u106-pad2_ net-_u105-pad2_ net-_u109-pad1_ 3_and +* u109 net-_u109-pad1_ net-_u109-pad2_ net-_u109-pad3_ d_nor +* u111 net-_u109-pad3_ net-_u112-pad2_ d_inverter +* u108 net-_u108-pad1_ net-_u108-pad2_ net-_u108-pad3_ d_nor +* u110 net-_u108-pad3_ net-_u112-pad1_ d_inverter +* u113 net-_u113-pad1_ net-_u101-pad4_ d_inverter +* u112 net-_u112-pad1_ net-_u112-pad2_ net-_u113-pad1_ d_nor +x103 net-_u106-pad2_ net-_u107-pad2_ net-_u103-pad2_ net-_u108-pad1_ 3_and +* u106 net-_u104-pad2_ net-_u106-pad2_ d_inverter +x101 net-_u104-pad2_ net-_u107-pad2_ net-_u105-pad2_ net-_u108-pad2_ 3_and +* u107 net-_u102-pad2_ net-_u107-pad2_ d_inverter +x102 net-_u103-pad2_ net-_u102-pad2_ net-_u104-pad2_ net-_u109-pad2_ 3_and +* u102 net-_u101-pad2_ net-_u102-pad2_ d_buffer +* u104 net-_u101-pad1_ net-_u104-pad2_ d_buffer +* u103 net-_u101-pad3_ net-_u103-pad2_ d_buffer +* u105 net-_u103-pad2_ net-_u105-pad2_ d_inverter +a1 [net-_u109-pad1_ net-_u109-pad2_ ] net-_u109-pad3_ u109 +a2 net-_u109-pad3_ net-_u112-pad2_ u111 +a3 [net-_u108-pad1_ net-_u108-pad2_ ] net-_u108-pad3_ u108 +a4 net-_u108-pad3_ net-_u112-pad1_ u110 +a5 net-_u113-pad1_ net-_u101-pad4_ u113 +a6 [net-_u112-pad1_ net-_u112-pad2_ ] net-_u113-pad1_ u112 +a7 net-_u104-pad2_ net-_u106-pad2_ u106 +a8 net-_u102-pad2_ net-_u107-pad2_ u107 +a9 net-_u101-pad2_ net-_u102-pad2_ u102 +a10 net-_u101-pad1_ net-_u104-pad2_ u104 +a11 net-_u101-pad3_ net-_u103-pad2_ u103 +a12 net-_u103-pad2_ net-_u105-pad2_ u105 +* Schematic Name: d_nor, Ngspice Name: d_nor +.model u109 d_nor(rise_delay=5n fall_delay=5n input_load=1.0e-12 ) +* Schematic Name: d_inverter, Ngspice Name: d_inverter +.model u111 d_inverter(rise_delay=2n fall_delay=2n input_load=1.0e-12 ) +* Schematic Name: d_nor, Ngspice Name: d_nor +.model u108 d_nor(rise_delay=5n fall_delay=5n input_load=1.0e-12 ) +* Schematic Name: d_inverter, Ngspice Name: d_inverter +.model u110 d_inverter(rise_delay=2n fall_delay=2n input_load=1.0e-12 ) +* Schematic Name: d_inverter, Ngspice Name: d_inverter +.model u113 d_inverter(rise_delay=2n fall_delay=2n input_load=1.0e-12 ) +* Schematic Name: d_nor, Ngspice Name: d_nor +.model u112 d_nor(rise_delay=5n fall_delay=5n input_load=1.0e-12 ) +* Schematic Name: d_inverter, Ngspice Name: d_inverter +.model u106 d_inverter(rise_delay=2n fall_delay=2n input_load=1.0e-12 ) +* Schematic Name: d_inverter, Ngspice Name: d_inverter +.model u107 d_inverter(rise_delay=2n fall_delay=2n input_load=1.0e-12 ) +* Schematic Name: d_buffer, Ngspice Name: d_buffer +.model u102 d_buffer(rise_delay=2n fall_delay=2n input_load=1.0e-12 ) +* Schematic Name: d_buffer, Ngspice Name: d_buffer +.model u104 d_buffer(rise_delay=2n fall_delay=2n input_load=1.0e-12 ) +* Schematic Name: d_buffer, Ngspice Name: d_buffer +.model u103 d_buffer(rise_delay=2n fall_delay=2n input_load=1.0e-12 ) +* Schematic Name: d_inverter, Ngspice Name: d_inverter +.model u105 d_inverter(rise_delay=5n fall_delay=5n input_load=1.0e-12 ) +* Control Statements + +.ends 3_xor \ No newline at end of file diff --git a/library/SubcircuitLibrary/3_xor/3_xor_Previous_Values.xml b/library/SubcircuitLibrary/3_xor/3_xor_Previous_Values.xml new file mode 100644 index 000000000..220289f56 --- /dev/null +++ b/library/SubcircuitLibrary/3_xor/3_xor_Previous_Values.xml @@ -0,0 +1 @@ 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850 1650 60 0000 C CNN + 1 850 1650 + 1 0 0 -1 +$EndComp +$Comp +L eSim_Miscellaneous:PORT U101 +U 3 1 00000000 +P 850 4000 +F 0 "U101" H 875 4200 30 0000 C CNN +F 1 "PORT" H 875 4100 30 0000 C CNN +F 2 "" H 850 4000 60 0000 C CNN +F 3 "" H 850 4000 60 0000 C CNN + 3 850 4000 + 1 0 0 -1 +$EndComp +$Comp +L eSim_Miscellaneous:PORT U101 +U 4 1 00000000 +P 11150 3050 +F 0 "U101" H 11000 3025 30 0000 R CNN +F 1 "PORT" H 11000 3125 30 0000 R CNN +F 2 "" H 11150 3050 60 0000 C CNN +F 3 "" H 11150 3050 60 0000 C CNN + 4 11150 3050 + -1 0 0 1 +$EndComp +$Comp +L eSim_Digital:d_inverter U105 +U 1 1 00000000 +P 3200 4000 +F 0 "U105" H 3200 4250 60 0000 C CNN +F 1 "d_inverter" H 3200 4100 60 0000 C CNN +F 2 "" H 3250 3950 60 0000 C CNN +F 3 "" H 3250 3950 60 0000 C CNN + 1 3200 4000 + 1 0 0 -1 +$EndComp +$Comp +L eSim_Digital:d_inverter U106 +U 1 1 00000000 +P 3350 1650 +F 0 "U106" H 3350 1900 60 0000 C CNN +F 1 "d_inverter" H 3350 1750 60 0000 C CNN +F 2 "" H 3400 1600 60 0000 C CNN +F 3 "" H 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1.27)))) + ) + (pin input line (at -3.81 -6.35 90) (length 5.08) + (name "~" (effects (font (size 1.27 1.27)))) + (number "2" (effects (font (size 1.27 1.27)))) + ) + (pin input line (at 8.89 0 180) (length 5.08) + (name "~" (effects (font (size 1.27 1.27)))) + (number "3" (effects (font (size 1.27 1.27)))) + ) + (pin output line (at 3.81 -6.35 90) (length 5.08) + (name "~" (effects (font (size 1.27 1.27)))) + (number "4" (effects (font (size 1.27 1.27)))) + ) + ) + ) +) From 3c89a6b96a25365db10c3e48bba70d2fd7eccecf Mon Sep 17 00:00:00 2001 From: Sakshi Pandey Date: Sat, 24 Jan 2026 13:52:14 +0530 Subject: [PATCH 8/8] CD4075B is a 4 stage Serial Input/Parallel Output --- library/SubcircuitLibrary/sipo/analysis | 1 + .../sipo/eSim_Subckt.kicad_sym | 7000 +++++++++++++++++ library/SubcircuitLibrary/sipo/sipo.cir | 39 + library/SubcircuitLibrary/sipo/sipo.cir.out | 156 + library/SubcircuitLibrary/sipo/sipo.kicad_prl | 75 + library/SubcircuitLibrary/sipo/sipo.kicad_pro | 294 + library/SubcircuitLibrary/sipo/sipo.kicad_sch | 2273 ++++++ library/SubcircuitLibrary/sipo/sipo.sub | 150 + .../sipo/sipo_Previous_Values.xml | 1 + 9 files changed, 9989 insertions(+) create mode 100644 library/SubcircuitLibrary/sipo/analysis create mode 100644 library/SubcircuitLibrary/sipo/eSim_Subckt.kicad_sym create mode 100644 library/SubcircuitLibrary/sipo/sipo.cir create mode 100644 library/SubcircuitLibrary/sipo/sipo.cir.out create mode 100644 library/SubcircuitLibrary/sipo/sipo.kicad_prl create mode 100644 library/SubcircuitLibrary/sipo/sipo.kicad_pro create mode 100644 library/SubcircuitLibrary/sipo/sipo.kicad_sch create mode 100644 library/SubcircuitLibrary/sipo/sipo.sub create mode 100644 library/SubcircuitLibrary/sipo/sipo_Previous_Values.xml diff --git a/library/SubcircuitLibrary/sipo/analysis b/library/SubcircuitLibrary/sipo/analysis new file mode 100644 index 000000000..a13ac59ea --- /dev/null +++ b/library/SubcircuitLibrary/sipo/analysis @@ -0,0 +1 @@ +.tran 0.1e-09 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unconnected-_U101-Pad16_ PORT +U103 Net-_U101-Pad9_ Net-_U103-Pad2_ d_inverter +U102 Net-_U101-Pad7_ Net-_U102-Pad2_ d_inverter +U107 Net-_U103-Pad2_ Net-_U107-Pad2_ d_inverter +U110 Net-_U106-Pad2_ Net-_U110-Pad2_ d_inverter +U106 Net-_U102-Pad2_ Net-_U106-Pad2_ d_inverter +U104 Net-_U101-Pad6_ Net-_U104-Pad2_ d_inverter +U118 Net-_U113-Pad5_ Net-_U107-Pad2_ Net-_U104-Pad2_ Net-_U123-Pad1_ Net-_U118-Pad5_ dbar_ff +U122 Net-_U122-Pad1_ Net-_U101-Pad4_ d_inverter +U123 Net-_U123-Pad1_ Net-_U122-Pad1_ d_inverter +U117 Net-_U117-Pad1_ Net-_U116-Pad1_ d_inverter +U113 Net-_U110-Pad2_ Net-_U107-Pad2_ Net-_U104-Pad2_ Net-_U117-Pad1_ Net-_U113-Pad5_ dbar_ff +U116 Net-_U116-Pad1_ Net-_U101-Pad5_ d_inverter +U124 Net-_U118-Pad5_ Net-_U107-Pad2_ Net-_U104-Pad2_ Net-_U129-Pad1_ Net-_U124-Pad5_ dbar_ff +U129 Net-_U129-Pad1_ Net-_U128-Pad1_ d_inverter +U134 Net-_U134-Pad1_ Net-_U101-Pad10_ d_inverter +U135 Net-_U135-Pad1_ Net-_U134-Pad1_ d_inverter +U130 Net-_U124-Pad5_ Net-_U107-Pad2_ Net-_U104-Pad2_ Net-_U135-Pad1_ unconnected-_U130-Pad5_ dbar_ff +U128 Net-_U128-Pad1_ Net-_U101-Pad3_ d_inverter +U114 Net-_U111-Pad2_ Net-_U114-Pad2_ d_inverter +U109 Net-_U101-Pad14_ Net-_U109-Pad2_ d_inverter +U105 Net-_U101-Pad15_ Net-_U105-Pad2_ d_inverter +U111 Net-_U105-Pad2_ Net-_U111-Pad2_ d_inverter +U112 Net-_U108-Pad2_ Net-_U112-Pad2_ d_inverter +U108 Net-_U101-Pad1_ Net-_U108-Pad2_ d_inverter +U115 Net-_U114-Pad2_ Net-_U112-Pad2_ Net-_U109-Pad2_ Net-_U120-Pad1_ Net-_U115-Pad5_ dbar_ff +U120 Net-_U120-Pad1_ Net-_U119-Pad1_ d_inverter +U119 Net-_U119-Pad1_ Net-_U101-Pad13_ d_inverter +U126 Net-_U126-Pad1_ Net-_U125-Pad1_ d_inverter +U121 Net-_U115-Pad5_ Net-_U112-Pad2_ Net-_U109-Pad2_ Net-_U126-Pad1_ Net-_U121-Pad5_ dbar_ff +U125 Net-_U125-Pad1_ Net-_U101-Pad12_ d_inverter +U132 Net-_U132-Pad1_ Net-_U131-Pad1_ d_inverter +U131 Net-_U131-Pad1_ Net-_U101-Pad11_ d_inverter +U127 Net-_U121-Pad5_ Net-_U112-Pad2_ Net-_U109-Pad2_ Net-_U132-Pad1_ Net-_U127-Pad5_ dbar_ff +U137 Net-_U137-Pad1_ Net-_U136-Pad1_ d_inverter +U136 Net-_U136-Pad1_ Net-_U101-Pad2_ d_inverter +U133 Net-_U127-Pad5_ Net-_U112-Pad2_ Net-_U109-Pad2_ Net-_U137-Pad1_ unconnected-_U133-Pad5_ dbar_ff +.end diff --git a/library/SubcircuitLibrary/sipo/sipo.cir.out b/library/SubcircuitLibrary/sipo/sipo.cir.out new file mode 100644 index 000000000..46e3757d3 --- /dev/null +++ b/library/SubcircuitLibrary/sipo/sipo.cir.out @@ -0,0 +1,156 @@ +.title kicad schematic + +* u101 net-_u101-pad1_ net-_u101-pad2_ net-_u101-pad3_ net-_u101-pad4_ net-_u101-pad5_ net-_u101-pad6_ net-_u101-pad7_ unconnected-_u101-pad8_ net-_u101-pad9_ net-_u101-pad10_ net-_u101-pad11_ net-_u101-pad12_ net-_u101-pad13_ net-_u101-pad14_ net-_u101-pad15_ unconnected-_u101-pad16_ port +* u103 net-_u101-pad9_ net-_u103-pad2_ d_inverter +* u102 net-_u101-pad7_ net-_u102-pad2_ d_inverter +* u107 net-_u103-pad2_ net-_u107-pad2_ d_inverter +* u110 net-_u106-pad2_ net-_u110-pad2_ d_inverter +* u106 net-_u102-pad2_ net-_u106-pad2_ d_inverter +* u104 net-_u101-pad6_ net-_u104-pad2_ d_inverter +* u118 net-_u113-pad5_ net-_u107-pad2_ net-_u104-pad2_ net-_u123-pad1_ net-_u118-pad5_ dbar_ff +* u122 net-_u122-pad1_ net-_u101-pad4_ d_inverter +* u123 net-_u123-pad1_ net-_u122-pad1_ d_inverter +* u117 net-_u117-pad1_ net-_u116-pad1_ d_inverter +* u113 net-_u110-pad2_ net-_u107-pad2_ net-_u104-pad2_ net-_u117-pad1_ net-_u113-pad5_ dbar_ff +* u116 net-_u116-pad1_ net-_u101-pad5_ d_inverter +* u124 net-_u118-pad5_ net-_u107-pad2_ net-_u104-pad2_ net-_u129-pad1_ net-_u124-pad5_ dbar_ff +* u129 net-_u129-pad1_ net-_u128-pad1_ d_inverter +* u134 net-_u134-pad1_ net-_u101-pad10_ d_inverter +* u135 net-_u135-pad1_ net-_u134-pad1_ d_inverter +* u130 net-_u124-pad5_ net-_u107-pad2_ net-_u104-pad2_ net-_u135-pad1_ unconnected-_u130-pad5_ dbar_ff +* u128 net-_u128-pad1_ net-_u101-pad3_ d_inverter +* u114 net-_u111-pad2_ net-_u114-pad2_ d_inverter +* u109 net-_u101-pad14_ net-_u109-pad2_ d_inverter +* u105 net-_u101-pad15_ net-_u105-pad2_ d_inverter +* u111 net-_u105-pad2_ net-_u111-pad2_ d_inverter +* u112 net-_u108-pad2_ net-_u112-pad2_ d_inverter +* u108 net-_u101-pad1_ net-_u108-pad2_ d_inverter +* u115 net-_u114-pad2_ net-_u112-pad2_ net-_u109-pad2_ net-_u120-pad1_ net-_u115-pad5_ dbar_ff +* u120 net-_u120-pad1_ net-_u119-pad1_ d_inverter +* u119 net-_u119-pad1_ net-_u101-pad13_ d_inverter +* u126 net-_u126-pad1_ net-_u125-pad1_ d_inverter +* u121 net-_u115-pad5_ net-_u112-pad2_ net-_u109-pad2_ net-_u126-pad1_ net-_u121-pad5_ dbar_ff +* u125 net-_u125-pad1_ net-_u101-pad12_ d_inverter +* u132 net-_u132-pad1_ net-_u131-pad1_ d_inverter +* u131 net-_u131-pad1_ net-_u101-pad11_ d_inverter +* u127 net-_u121-pad5_ net-_u112-pad2_ net-_u109-pad2_ net-_u132-pad1_ net-_u127-pad5_ dbar_ff +* u137 net-_u137-pad1_ net-_u136-pad1_ d_inverter +* u136 net-_u136-pad1_ net-_u101-pad2_ d_inverter +* u133 net-_u127-pad5_ net-_u112-pad2_ net-_u109-pad2_ net-_u137-pad1_ unconnected-_u133-pad5_ dbar_ff +a1 net-_u101-pad9_ net-_u103-pad2_ u103 +a2 net-_u101-pad7_ net-_u102-pad2_ u102 +a3 net-_u103-pad2_ net-_u107-pad2_ u107 +a4 net-_u106-pad2_ net-_u110-pad2_ u110 +a5 net-_u102-pad2_ net-_u106-pad2_ u106 +a6 net-_u101-pad6_ net-_u104-pad2_ u104 +a7 [net-_u113-pad5_ ] [net-_u107-pad2_ ] [net-_u104-pad2_ ] [net-_u123-pad1_ ] [net-_u118-pad5_ ] u118 +a8 net-_u122-pad1_ net-_u101-pad4_ u122 +a9 net-_u123-pad1_ net-_u122-pad1_ u123 +a10 net-_u117-pad1_ net-_u116-pad1_ u117 +a11 [net-_u110-pad2_ ] [net-_u107-pad2_ ] [net-_u104-pad2_ ] [net-_u117-pad1_ ] [net-_u113-pad5_ ] u113 +a12 net-_u116-pad1_ net-_u101-pad5_ u116 +a13 [net-_u118-pad5_ ] [net-_u107-pad2_ ] [net-_u104-pad2_ ] [net-_u129-pad1_ ] [net-_u124-pad5_ ] u124 +a14 net-_u129-pad1_ net-_u128-pad1_ u129 +a15 net-_u134-pad1_ net-_u101-pad10_ u134 +a16 net-_u135-pad1_ net-_u134-pad1_ u135 +a17 [net-_u124-pad5_ ] [net-_u107-pad2_ ] [net-_u104-pad2_ ] [net-_u135-pad1_ ] [unconnected-_u130-pad5_ ] u130 +a18 net-_u128-pad1_ net-_u101-pad3_ u128 +a19 net-_u111-pad2_ net-_u114-pad2_ u114 +a20 net-_u101-pad14_ net-_u109-pad2_ u109 +a21 net-_u101-pad15_ net-_u105-pad2_ u105 +a22 net-_u105-pad2_ net-_u111-pad2_ u111 +a23 net-_u108-pad2_ net-_u112-pad2_ u112 +a24 net-_u101-pad1_ net-_u108-pad2_ u108 +a25 [net-_u114-pad2_ ] [net-_u112-pad2_ ] [net-_u109-pad2_ ] [net-_u120-pad1_ ] [net-_u115-pad5_ ] u115 +a26 net-_u120-pad1_ net-_u119-pad1_ u120 +a27 net-_u119-pad1_ net-_u101-pad13_ u119 +a28 net-_u126-pad1_ net-_u125-pad1_ u126 +a29 [net-_u115-pad5_ ] [net-_u112-pad2_ ] [net-_u109-pad2_ ] [net-_u126-pad1_ ] [net-_u121-pad5_ ] u121 +a30 net-_u125-pad1_ net-_u101-pad12_ u125 +a31 net-_u132-pad1_ net-_u131-pad1_ u132 +a32 net-_u131-pad1_ net-_u101-pad11_ u131 +a33 [net-_u121-pad5_ ] [net-_u112-pad2_ ] [net-_u109-pad2_ ] [net-_u132-pad1_ ] [net-_u127-pad5_ ] u127 +a34 net-_u137-pad1_ net-_u136-pad1_ u137 +a35 net-_u136-pad1_ net-_u101-pad2_ u136 +a36 [net-_u127-pad5_ ] [net-_u112-pad2_ ] [net-_u109-pad2_ ] [net-_u137-pad1_ ] [unconnected-_u133-pad5_ ] u133 +* Schematic Name: d_inverter, Ngspice Name: d_inverter +.model u103 d_inverter(rise_delay=5n fall_delay=5n input_load=1.0e-12 ) +* Schematic Name: d_inverter, Ngspice Name: d_inverter +.model u102 d_inverter(rise_delay=5n fall_delay=5n input_load=1.0e-12 ) +* Schematic Name: d_inverter, Ngspice Name: d_inverter +.model u107 d_inverter(rise_delay=5n fall_delay=5n input_load=1.0e-12 ) +* Schematic Name: d_inverter, Ngspice Name: d_inverter +.model u110 d_inverter(rise_delay=5n fall_delay=5n input_load=1.0e-12 ) +* Schematic Name: d_inverter, Ngspice Name: d_inverter +.model u106 d_inverter(rise_delay=5n fall_delay=5n input_load=1.0e-12 ) +* Schematic Name: d_inverter, Ngspice Name: d_inverter +.model u104 d_inverter(rise_delay=5n fall_delay=5n input_load=1.0e-12 ) +* Schematic Name: dbar_ff, Ngspice Name: dbar_ff +.model u118 dbar_ff(rise_delay=10n fall_delay=10n10n input_load=1.0e-12 instance_id=1 ) +* Schematic Name: d_inverter, Ngspice Name: d_inverter +.model u122 d_inverter(rise_delay=5n fall_delay=5n input_load=1.0e-12 ) +* Schematic Name: d_inverter, Ngspice Name: d_inverter +.model u123 d_inverter(rise_delay=5n fall_delay=5n input_load=1.0e-12 ) +* Schematic Name: d_inverter, Ngspice Name: d_inverter +.model u117 d_inverter(rise_delay=5n fall_delay=5n input_load=1.0e-12 ) +* Schematic Name: dbar_ff, Ngspice Name: dbar_ff +.model u113 dbar_ff(rise_delay=10n fall_delay=10n input_load=1.0e-12 instance_id=1 ) +* Schematic Name: d_inverter, Ngspice Name: d_inverter +.model u116 d_inverter(rise_delay=5n fall_delay=5n input_load=1.0e-12 ) +* Schematic Name: dbar_ff, Ngspice Name: dbar_ff +.model u124 dbar_ff(rise_delay=10n fall_delay=10n input_load=1.0e-12 instance_id=1 ) +* Schematic Name: d_inverter, Ngspice Name: d_inverter +.model u129 d_inverter(rise_delay=5n fall_delay=5n input_load=1.0e-12 ) +* Schematic Name: d_inverter, Ngspice Name: d_inverter +.model u134 d_inverter(rise_delay=5n fall_delay=5n input_load=1.0e-12 ) +* Schematic Name: d_inverter, Ngspice Name: d_inverter +.model u135 d_inverter(rise_delay=5n fall_delay=5n input_load=1.0e-12 ) +* Schematic Name: dbar_ff, Ngspice Name: dbar_ff +.model u130 dbar_ff(rise_delay=10n fall_delay=10n input_load=1.0e-12 instance_id=1 ) +* Schematic Name: d_inverter, Ngspice Name: d_inverter +.model u128 d_inverter(rise_delay=5n fall_delay=5n input_load=1.0e-12 ) +* Schematic Name: d_inverter, Ngspice Name: d_inverter +.model u114 d_inverter(rise_delay=5n fall_delay=5n input_load=1.0e-12 ) +* Schematic Name: d_inverter, Ngspice Name: d_inverter +.model u109 d_inverter(rise_delay=5n fall_delay=5n input_load=1.0e-12 ) +* Schematic Name: d_inverter, Ngspice Name: d_inverter +.model u105 d_inverter(rise_delay=5n fall_delay=5n input_load=1.0e-12 ) +* Schematic Name: d_inverter, Ngspice Name: d_inverter +.model u111 d_inverter(rise_delay=5n fall_delay=5n input_load=1.0e-12 ) +* Schematic Name: d_inverter, Ngspice Name: d_inverter +.model u112 d_inverter(rise_delay=5n fall_delay=5n input_load=1.0e-12 ) +* Schematic Name: d_inverter, Ngspice Name: d_inverter +.model u108 d_inverter(rise_delay=5n fall_delay=5n input_load=1.0e-12 ) +* Schematic Name: dbar_ff, Ngspice Name: dbar_ff +.model u115 dbar_ff(rise_delay=10n fall_delay=10n input_load=1.0e-12 instance_id=1 ) +* Schematic Name: d_inverter, Ngspice Name: d_inverter +.model u120 d_inverter(rise_delay=5n fall_delay=5n input_load=1.0e-12 ) +* Schematic Name: d_inverter, Ngspice Name: d_inverter +.model u119 d_inverter(rise_delay=5n fall_delay=5n input_load=1.0e-12 ) +* Schematic Name: d_inverter, Ngspice Name: d_inverter +.model u126 d_inverter(rise_delay=5n fall_delay=5n input_load=1.0e-12 ) +* Schematic Name: dbar_ff, Ngspice Name: dbar_ff +.model u121 dbar_ff(rise_delay=10n fall_delay=10n input_load=1.0e-12 instance_id=1 ) +* Schematic Name: d_inverter, Ngspice Name: d_inverter +.model u125 d_inverter(rise_delay=5n fall_delay=5n input_load=1.0e-12 ) +* Schematic Name: d_inverter, Ngspice Name: d_inverter +.model u132 d_inverter(rise_delay=5n fall_delay=5n input_load=1.0e-12 ) +* Schematic Name: d_inverter, Ngspice Name: d_inverter +.model u131 d_inverter(rise_delay=5n fall_delay=5n input_load=1.0e-12 ) +* Schematic Name: dbar_ff, Ngspice Name: dbar_ff +.model u127 dbar_ff(rise_delay=10n fall_delay=10n input_load=1.0e-12 instance_id=1 ) +* Schematic Name: d_inverter, Ngspice Name: d_inverter +.model u137 d_inverter(rise_delay=5n fall_delay=5n input_load=1.0e-12 ) +* Schematic Name: d_inverter, Ngspice Name: d_inverter +.model u136 d_inverter(rise_delay=5n fall_delay=5n input_load=1.0e-12 ) +* Schematic Name: dbar_ff, Ngspice Name: dbar_ff +.model u133 dbar_ff(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 instance_id=1 ) +.tran 0.1e-09 50e-09 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/library/SubcircuitLibrary/sipo/sipo.kicad_prl b/library/SubcircuitLibrary/sipo/sipo.kicad_prl new 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(unit 1) (value "dbar_ff") (footprint "") + ) + (path "/8d189f82-bcac-479d-b75d-cd5024b8aafe" + (reference "U119") (unit 1) (value "d_inverter") (footprint "") + ) + (path "/5d2f0b32-dcdd-44ac-960f-b74da7c0bf4c" + (reference "U120") (unit 1) (value "d_inverter") (footprint "") + ) + (path "/f5b09dd8-9fcb-4474-b4f4-57addcc769fd" + (reference "U121") (unit 1) (value "dbar_ff") (footprint "") + ) + (path "/04e48444-ec35-4c31-9ca9-9ec178da4c68" + (reference "U122") (unit 1) (value "d_inverter") (footprint "") + ) + (path "/5a1253af-8c9c-46f5-8c65-6f3eef47fae9" + (reference "U123") (unit 1) (value "d_inverter") (footprint "") + ) + (path "/a9e11617-6e94-4091-89d7-0af6914209d3" + (reference "U124") (unit 1) (value "dbar_ff") (footprint "") + ) + (path "/4aec70cc-4863-44ce-9549-7dbe1cc282d3" + (reference "U125") (unit 1) (value "d_inverter") (footprint "") + ) + (path "/1e96bfc6-4e0c-4eea-82ba-c73baa41d0b4" + (reference "U126") (unit 1) (value "d_inverter") (footprint "") + ) + (path "/749ee769-e933-4f54-b638-cee96d92ee79" + (reference "U127") (unit 1) (value "dbar_ff") (footprint "") + ) + (path "/dfe9de5e-baac-4f35-bc4b-43fcd1a77df4" + (reference "U128") (unit 1) (value "d_inverter") (footprint "") + ) + (path "/872e3a50-46f9-4c67-8b85-3af9152269cb" + (reference "U129") (unit 1) (value "d_inverter") (footprint "") + ) + (path "/6476593f-cb9a-425b-8e78-d80cff92ee70" + (reference "U130") (unit 1) (value "dbar_ff") (footprint "") + ) + (path "/7300958d-528a-425e-964b-0b1bd945a0a7" + (reference "U131") (unit 1) (value "d_inverter") (footprint "") + ) + (path "/f5afee9c-8d67-47b9-8f06-746aa45ced6e" + (reference "U132") (unit 1) (value "d_inverter") (footprint "") + ) + (path "/c7b217a6-a82b-41bd-a2d5-0262ba8d4925" + (reference "U133") (unit 1) (value "dbar_ff") (footprint "") + ) + (path "/279e8981-94e1-4463-b759-9ab7745dadce" + (reference "U134") (unit 1) (value "d_inverter") (footprint "") + ) + (path "/8f5b6762-8098-4b80-bc99-cd36f4e43772" + (reference "U135") (unit 1) (value "d_inverter") (footprint "") + ) + (path "/f98094d4-3ccb-4c69-aede-19776172a963" + (reference "U136") (unit 1) (value "d_inverter") (footprint "") + ) + (path "/92932450-5abd-43dd-a624-0d7b302657be" + (reference "U137") (unit 1) (value "d_inverter") (footprint "") + ) + ) +) diff --git a/library/SubcircuitLibrary/sipo/sipo.sub b/library/SubcircuitLibrary/sipo/sipo.sub new file mode 100644 index 000000000..f27b28c30 --- /dev/null +++ b/library/SubcircuitLibrary/sipo/sipo.sub @@ -0,0 +1,150 @@ +* Subcircuit sipo +.subckt sipo net-_u101-pad1_ net-_u101-pad2_ net-_u101-pad3_ net-_u101-pad4_ net-_u101-pad5_ net-_u101-pad6_ net-_u101-pad7_ unconnected-_u101-pad8_ net-_u101-pad9_ net-_u101-pad10_ net-_u101-pad11_ net-_u101-pad12_ net-_u101-pad13_ net-_u101-pad14_ net-_u101-pad15_ unconnected-_u101-pad16_ +.title kicad schematic +* u103 net-_u101-pad9_ net-_u103-pad2_ d_inverter +* u102 net-_u101-pad7_ net-_u102-pad2_ d_inverter +* u107 net-_u103-pad2_ net-_u107-pad2_ d_inverter +* u110 net-_u106-pad2_ net-_u110-pad2_ d_inverter +* u106 net-_u102-pad2_ net-_u106-pad2_ d_inverter +* u104 net-_u101-pad6_ net-_u104-pad2_ d_inverter +* u118 net-_u113-pad5_ net-_u107-pad2_ net-_u104-pad2_ net-_u123-pad1_ net-_u118-pad5_ dbar_ff +* u122 net-_u122-pad1_ net-_u101-pad4_ d_inverter +* u123 net-_u123-pad1_ net-_u122-pad1_ d_inverter +* u117 net-_u117-pad1_ net-_u116-pad1_ d_inverter +* u113 net-_u110-pad2_ net-_u107-pad2_ net-_u104-pad2_ net-_u117-pad1_ net-_u113-pad5_ dbar_ff +* u116 net-_u116-pad1_ net-_u101-pad5_ d_inverter +* u124 net-_u118-pad5_ net-_u107-pad2_ net-_u104-pad2_ net-_u129-pad1_ net-_u124-pad5_ dbar_ff +* u129 net-_u129-pad1_ net-_u128-pad1_ d_inverter +* u134 net-_u134-pad1_ net-_u101-pad10_ d_inverter +* u135 net-_u135-pad1_ net-_u134-pad1_ d_inverter +* u130 net-_u124-pad5_ net-_u107-pad2_ net-_u104-pad2_ net-_u135-pad1_ unconnected-_u130-pad5_ dbar_ff +* u128 net-_u128-pad1_ net-_u101-pad3_ d_inverter +* u114 net-_u111-pad2_ net-_u114-pad2_ d_inverter +* u109 net-_u101-pad14_ net-_u109-pad2_ d_inverter +* u105 net-_u101-pad15_ net-_u105-pad2_ d_inverter +* u111 net-_u105-pad2_ net-_u111-pad2_ d_inverter +* u112 net-_u108-pad2_ net-_u112-pad2_ d_inverter +* u108 net-_u101-pad1_ net-_u108-pad2_ d_inverter +* u115 net-_u114-pad2_ net-_u112-pad2_ net-_u109-pad2_ net-_u120-pad1_ net-_u115-pad5_ dbar_ff +* u120 net-_u120-pad1_ net-_u119-pad1_ d_inverter +* u119 net-_u119-pad1_ net-_u101-pad13_ d_inverter +* u126 net-_u126-pad1_ net-_u125-pad1_ d_inverter +* u121 net-_u115-pad5_ net-_u112-pad2_ net-_u109-pad2_ net-_u126-pad1_ net-_u121-pad5_ dbar_ff +* u125 net-_u125-pad1_ net-_u101-pad12_ d_inverter +* u132 net-_u132-pad1_ net-_u131-pad1_ d_inverter +* u131 net-_u131-pad1_ net-_u101-pad11_ d_inverter +* u127 net-_u121-pad5_ net-_u112-pad2_ net-_u109-pad2_ net-_u132-pad1_ net-_u127-pad5_ dbar_ff +* u137 net-_u137-pad1_ net-_u136-pad1_ d_inverter +* u136 net-_u136-pad1_ net-_u101-pad2_ d_inverter +* u133 net-_u127-pad5_ net-_u112-pad2_ net-_u109-pad2_ net-_u137-pad1_ unconnected-_u133-pad5_ dbar_ff +a1 net-_u101-pad9_ net-_u103-pad2_ u103 +a2 net-_u101-pad7_ net-_u102-pad2_ u102 +a3 net-_u103-pad2_ net-_u107-pad2_ u107 +a4 net-_u106-pad2_ net-_u110-pad2_ u110 +a5 net-_u102-pad2_ net-_u106-pad2_ u106 +a6 net-_u101-pad6_ net-_u104-pad2_ u104 +a7 [net-_u113-pad5_ ] [net-_u107-pad2_ ] [net-_u104-pad2_ ] [net-_u123-pad1_ ] [net-_u118-pad5_ ] u118 +a8 net-_u122-pad1_ net-_u101-pad4_ u122 +a9 net-_u123-pad1_ net-_u122-pad1_ u123 +a10 net-_u117-pad1_ net-_u116-pad1_ u117 +a11 [net-_u110-pad2_ ] [net-_u107-pad2_ ] [net-_u104-pad2_ ] [net-_u117-pad1_ ] [net-_u113-pad5_ ] u113 +a12 net-_u116-pad1_ net-_u101-pad5_ u116 +a13 [net-_u118-pad5_ ] [net-_u107-pad2_ ] [net-_u104-pad2_ ] [net-_u129-pad1_ ] [net-_u124-pad5_ ] u124 +a14 net-_u129-pad1_ net-_u128-pad1_ u129 +a15 net-_u134-pad1_ net-_u101-pad10_ u134 +a16 net-_u135-pad1_ net-_u134-pad1_ u135 +a17 [net-_u124-pad5_ ] [net-_u107-pad2_ ] [net-_u104-pad2_ ] [net-_u135-pad1_ ] [unconnected-_u130-pad5_ ] u130 +a18 net-_u128-pad1_ net-_u101-pad3_ u128 +a19 net-_u111-pad2_ net-_u114-pad2_ u114 +a20 net-_u101-pad14_ net-_u109-pad2_ u109 +a21 net-_u101-pad15_ net-_u105-pad2_ u105 +a22 net-_u105-pad2_ net-_u111-pad2_ u111 +a23 net-_u108-pad2_ net-_u112-pad2_ u112 +a24 net-_u101-pad1_ net-_u108-pad2_ u108 +a25 [net-_u114-pad2_ ] [net-_u112-pad2_ ] [net-_u109-pad2_ ] [net-_u120-pad1_ ] [net-_u115-pad5_ ] u115 +a26 net-_u120-pad1_ net-_u119-pad1_ u120 +a27 net-_u119-pad1_ net-_u101-pad13_ u119 +a28 net-_u126-pad1_ net-_u125-pad1_ u126 +a29 [net-_u115-pad5_ ] [net-_u112-pad2_ ] [net-_u109-pad2_ ] [net-_u126-pad1_ ] [net-_u121-pad5_ ] u121 +a30 net-_u125-pad1_ net-_u101-pad12_ u125 +a31 net-_u132-pad1_ net-_u131-pad1_ u132 +a32 net-_u131-pad1_ net-_u101-pad11_ u131 +a33 [net-_u121-pad5_ ] [net-_u112-pad2_ ] [net-_u109-pad2_ ] [net-_u132-pad1_ ] [net-_u127-pad5_ ] u127 +a34 net-_u137-pad1_ net-_u136-pad1_ u137 +a35 net-_u136-pad1_ net-_u101-pad2_ u136 +a36 [net-_u127-pad5_ ] [net-_u112-pad2_ ] [net-_u109-pad2_ ] [net-_u137-pad1_ ] [unconnected-_u133-pad5_ ] u133 +* Schematic Name: d_inverter, Ngspice Name: d_inverter +.model u103 d_inverter(rise_delay=5n fall_delay=5n input_load=1.0e-12 ) +* Schematic Name: d_inverter, Ngspice Name: d_inverter +.model u102 d_inverter(rise_delay=5n fall_delay=5n input_load=1.0e-12 ) +* Schematic Name: d_inverter, Ngspice Name: d_inverter +.model u107 d_inverter(rise_delay=5n fall_delay=5n input_load=1.0e-12 ) +* Schematic Name: d_inverter, Ngspice Name: d_inverter +.model u110 d_inverter(rise_delay=5n fall_delay=5n input_load=1.0e-12 ) +* Schematic Name: d_inverter, Ngspice Name: d_inverter +.model u106 d_inverter(rise_delay=5n fall_delay=5n input_load=1.0e-12 ) +* Schematic Name: d_inverter, Ngspice Name: d_inverter +.model u104 d_inverter(rise_delay=5n fall_delay=5n input_load=1.0e-12 ) +* Schematic Name: dbar_ff, Ngspice Name: dbar_ff +.model u118 dbar_ff(rise_delay=10n fall_delay=10n10n input_load=1.0e-12 instance_id=1 ) +* Schematic Name: d_inverter, Ngspice Name: d_inverter +.model u122 d_inverter(rise_delay=5n fall_delay=5n input_load=1.0e-12 ) +* Schematic Name: d_inverter, Ngspice Name: d_inverter +.model u123 d_inverter(rise_delay=5n fall_delay=5n input_load=1.0e-12 ) +* Schematic Name: d_inverter, Ngspice Name: d_inverter +.model u117 d_inverter(rise_delay=5n fall_delay=5n input_load=1.0e-12 ) +* Schematic Name: dbar_ff, Ngspice Name: dbar_ff +.model u113 dbar_ff(rise_delay=10n fall_delay=10n input_load=1.0e-12 instance_id=1 ) +* Schematic Name: d_inverter, Ngspice Name: d_inverter +.model u116 d_inverter(rise_delay=5n fall_delay=5n input_load=1.0e-12 ) +* Schematic Name: dbar_ff, Ngspice Name: dbar_ff +.model u124 dbar_ff(rise_delay=10n fall_delay=10n input_load=1.0e-12 instance_id=1 ) +* Schematic Name: d_inverter, Ngspice Name: d_inverter +.model u129 d_inverter(rise_delay=5n fall_delay=5n input_load=1.0e-12 ) +* Schematic Name: d_inverter, Ngspice Name: d_inverter +.model u134 d_inverter(rise_delay=5n fall_delay=5n input_load=1.0e-12 ) +* Schematic Name: d_inverter, Ngspice Name: d_inverter +.model u135 d_inverter(rise_delay=5n fall_delay=5n input_load=1.0e-12 ) +* Schematic Name: dbar_ff, Ngspice Name: dbar_ff +.model u130 dbar_ff(rise_delay=10n fall_delay=10n input_load=1.0e-12 instance_id=1 ) +* Schematic Name: d_inverter, Ngspice Name: d_inverter +.model u128 d_inverter(rise_delay=5n fall_delay=5n input_load=1.0e-12 ) +* Schematic Name: d_inverter, Ngspice Name: d_inverter +.model u114 d_inverter(rise_delay=5n fall_delay=5n input_load=1.0e-12 ) +* Schematic Name: d_inverter, Ngspice Name: d_inverter +.model u109 d_inverter(rise_delay=5n fall_delay=5n input_load=1.0e-12 ) +* Schematic Name: d_inverter, Ngspice Name: d_inverter +.model u105 d_inverter(rise_delay=5n fall_delay=5n input_load=1.0e-12 ) +* Schematic Name: d_inverter, Ngspice Name: d_inverter +.model u111 d_inverter(rise_delay=5n fall_delay=5n input_load=1.0e-12 ) +* Schematic Name: d_inverter, Ngspice Name: d_inverter +.model u112 d_inverter(rise_delay=5n fall_delay=5n input_load=1.0e-12 ) +* Schematic Name: d_inverter, Ngspice Name: d_inverter +.model u108 d_inverter(rise_delay=5n fall_delay=5n input_load=1.0e-12 ) +* Schematic Name: dbar_ff, Ngspice Name: dbar_ff +.model u115 dbar_ff(rise_delay=10n fall_delay=10n input_load=1.0e-12 instance_id=1 ) +* Schematic Name: d_inverter, Ngspice Name: d_inverter +.model u120 d_inverter(rise_delay=5n fall_delay=5n input_load=1.0e-12 ) +* Schematic Name: d_inverter, Ngspice Name: d_inverter +.model u119 d_inverter(rise_delay=5n fall_delay=5n input_load=1.0e-12 ) +* Schematic Name: d_inverter, Ngspice Name: d_inverter +.model u126 d_inverter(rise_delay=5n fall_delay=5n input_load=1.0e-12 ) +* Schematic Name: dbar_ff, Ngspice Name: dbar_ff +.model u121 dbar_ff(rise_delay=10n fall_delay=10n input_load=1.0e-12 instance_id=1 ) +* Schematic Name: d_inverter, Ngspice Name: d_inverter +.model u125 d_inverter(rise_delay=5n fall_delay=5n input_load=1.0e-12 ) +* Schematic Name: d_inverter, Ngspice Name: d_inverter +.model u132 d_inverter(rise_delay=5n fall_delay=5n input_load=1.0e-12 ) +* Schematic Name: d_inverter, Ngspice Name: d_inverter +.model u131 d_inverter(rise_delay=5n fall_delay=5n input_load=1.0e-12 ) +* Schematic Name: dbar_ff, Ngspice Name: dbar_ff +.model u127 dbar_ff(rise_delay=10n fall_delay=10n input_load=1.0e-12 instance_id=1 ) +* Schematic Name: d_inverter, Ngspice Name: d_inverter +.model u137 d_inverter(rise_delay=5n fall_delay=5n input_load=1.0e-12 ) +* Schematic Name: d_inverter, Ngspice Name: d_inverter +.model u136 d_inverter(rise_delay=5n fall_delay=5n input_load=1.0e-12 ) +* Schematic Name: dbar_ff, Ngspice Name: dbar_ff +.model u133 dbar_ff(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 instance_id=1 ) +* Control Statements + +.ends sipo \ No newline at end of file diff --git a/library/SubcircuitLibrary/sipo/sipo_Previous_Values.xml b/library/SubcircuitLibrary/sipo/sipo_Previous_Values.xml new file mode 100644 index 000000000..07e5092d8 --- /dev/null +++ b/library/SubcircuitLibrary/sipo/sipo_Previous_Values.xml @@ -0,0 +1 @@ +d_inverter5n5nd_inverter5n5nd_inverter5n5nd_inverter5n5nd_inverter5n5nd_inverter5n5ndbar_ff6n6n5pd_inverter5n5ndbar_ff100n100n10pd_inverter5n5nd_inverter5n5nd_inverter5n5nd_inverter5n5ndbar_ff100n100n10pd_inverter5n5nd_inverter5n5ndbar_ff100n100n10pd_inverter5n5ndbar_ff6n6n5pd_inverter5n5ndbar_ff6n6n5pdbar_ff6n6n5pd_inverter5n5nd_inverter5n5nd_inverter5n5nd_inverter5n5nd_ff10n10nd_inverter5n5nd_inverter5n5nd_ff10n10nd_inverter5n5nd_ff10n10nd_ff10n10nd_inverter5n5nd_ff10n10nd_inverter5n5nd_inverter5n5nd_ff10n10nd_inverter5n5nd_inverter5n5nd_inverter5n5nd_inverter5n5nd_ff10n10nd_ff10n10nd_inverter5n5nd_inverter5n5nd_inverter5n5nd_inverter5n5nd_ff3n3nd_ff3n3nd_ff3n3nd_inverter5n5nd_ff3n3nd_inverter5n5nd_ff3n3nd_ff3n3nd_inverter5n5nd_ff3n3nd_inverter5n5nd_ff3n3ndbar_ff10n10n10ndbar_ff10n10ndbar_ff10n10ndbar_ff10n10ndbar_ff10n10ndbar_ff10n10ndbar_ff10n10ndbar_fftruefalsefalseHzHz0Volts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or Amperes00.150secnsns \ No newline at end of file