chipflow-training/Makefile at main · ChipFlow/chipflow-training · GitHub

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.PHONY: init # Init local environemnt
init:
	uv sync

.PHONY: clean # Clean/delete the builds

define soc_target
.PHONY: $(1) # Build RTLIL for the design
$(strip $(1))/pins.lock:
	@CHIPFLOW_ROOT=$(strip $(1)) PYTHONPATH=$PYTHONPATH:${PWD} uv run chipflow pin lock

$(1): $(strip $(1))/pins.lock
	@CHIPFLOW_ROOT=$(strip $(1)) PYTHONPATH=$PYTHONPATH:${PWD} uv run chipflow silicon prepare

.PHONY: $(1)-submit # Submit RTLIL for build
$(1)-submit: $(1)
	@CHIPFLOW_ROOT=$(strip $(1)) PYTHONPATH=$PYTHONPATH:${PWD} uv run chipflow silicon submit

.PHONY: $(1)-submit-wait # Submit RTLIL for build
$(1)-submit-wait: $(1)
	@CHIPFLOW_ROOT=$(strip $(1)) PYTHONPATH=$PYTHONPATH:${PWD} uv run chipflow silicon submit --wait

.PHONY: $(1)-clean # clean the design
$(1)-clean:
	rm -fr $(strip $(1))/build

.PHONY: $(1)-lint
$(1)-lint:
	cd $(strip $(1))/design && uv run --group lint pycodestyle --config=../../.pycodestyle .

clean: $(1)-clean
endef

$(eval $(call soc_target, upcounter))