Fix docstring formatting and update URLs to .com domain

- Fix RST formatting in docstrings for IOModelOptions, IOModel,
  DriverModel, and simulatable_interface
- Use double backticks for inline code references
- Move orphaned docstring inside simulatable_interface function
- Update all build.chipflow.org URLs to build.chipflow.com
- Fix test assertions for new URL

🤖 Generated with [Claude Code](https://claude.com/claude-code)

Co-Authored-By: Claude Opus 4.5 <noreply@anthropic.com>

Author: robtaylor

CLAUDE.md

@@ -136,6 +136,6 @@ chipflow-lib is a Python library for working with the ChipFlow platform, enablin
 - `CHIPFLOW_ROOT`: Project root directory (auto-detected if not set)
 - `CHIPFLOW_API_KEY`: API key for cloud builder authentication
 - `CHIPFLOW_API_KEY_SECRET`: Deprecated, use `CHIPFLOW_API_KEY` instead
-- `CHIPFLOW_API_ORIGIN`: Cloud builder URL (default: https://build.chipflow.org)
+- `CHIPFLOW_API_ORIGIN`: Cloud builder URL (default: https://build.chipflow.com)
 - `CHIPFLOW_BACKEND_VERSION`: Developer override for backend version
 - `CHIPFLOW_SUBMISSION_NAME`: Override submission name (default: git commit hash)

chipflow/auth.py

@@ -254,7 +254,7 @@ def get_api_key(api_origin: str | None = None, interactive: bool = True, force_l
         AuthenticationError: If all authentication methods fail
     """
     if api_origin is None:
-        api_origin = os.environ.get("CHIPFLOW_API_ORIGIN", "https://build.chipflow.org")
+        api_origin = os.environ.get("CHIPFLOW_API_ORIGIN", "https://build.chipflow.com")
 
     # Method 1: Check environment variable
     api_key = os.environ.get("CHIPFLOW_API_KEY")

chipflow/auth_command.py

@@ -56,7 +56,7 @@ def _login(self, force=False):
         """Perform login/authentication."""
         import os
 
-        api_origin = os.environ.get("CHIPFLOW_API_ORIGIN", "https://build.chipflow.org")
+        api_origin = os.environ.get("CHIPFLOW_API_ORIGIN", "https://build.chipflow.com")
 
         print(f"🔐 Authenticating with ChipFlow API ({api_origin})...")
 

chipflow/platform/io/iosignature.py

@@ -56,19 +56,20 @@ class IOModelOptions(TypedDict):
     Attributes:
         invert: Polarity inversion. If the value is a simple :class:`bool`, it specifies inversion for
             the entire port. If the value is an iterable of :class:`bool`, the iterable must have the
-            same length as the width of :py:`io`, and the inversion is specified for individual wires.
+            same length as the width of ``io``, and the inversion is specified for individual wires.
         individual_oe: controls whether each output wire is associated with an individual Output Enable bit
             or if a single OE bit will be used for entire port. The default value is False (indicating that a
             single OE bit controls the entire port).
-        power_domain: The name of the I/O power domain. NB there is only one of these, so IO with multiple power domains must be split up.
-
-        clock_domain: the name of the I/O's clock domain (see `Amaranth.ClockDomain`). NB there is only one of these, so IO with multiple clocks must be split up.
+        power_domain: The name of the I/O power domain. NB there is only one of these, so IO with
+            multiple power domains must be split up.
+        clock_domain: the name of the I/O's clock domain (see ``amaranth.hdl.ClockDomain``). NB there
+            is only one of these, so IO with multiple clocks must be split up.
         buffer_in: Should the IO pad have an input buffer?
         buffer_out: Should the IO pad have an output buffer?
-        sky130_drive_mode: Drive mode for output buffer on sky130
-        trip_point: Trip Point configutation for input buffer
-        init: The value for the initial values of the port
-        init_oe: The value for the initial values of the output enable(s) of the port
+        sky130_drive_mode: Drive mode for output buffer on sky130.
+        trip_point: Trip Point configuration for input buffer.
+        init: The value for the initial values of the port.
+        init_oe: The value for the initial values of the output enable(s) of the port.
     """
 
     invert: NotRequired[bool|Tuple[bool, ...]]
@@ -85,11 +86,11 @@ class IOModelOptions(TypedDict):
 @pydantic.config.with_config(ConfigDict(arbitrary_types_allowed=True))  # type: ignore[reportCallIssue]
 class IOModel(IOModelOptions):
     """
-    Setting for IO Ports (see also base class `IOModelOptions`)
+    Setting for IO Ports (see also base class :class:`IOModelOptions`).
 
     Attributes:
-        direction: `io.Direction.Input`, `io.Direction.Output` or `io.Direction.Bidir`
-        width: width of port, default is 1
+        direction: ``io.Direction.Input``, ``io.Direction.Output`` or ``io.Direction.Bidir``.
+        width: Width of port, default is 1.
     """
 
     width: int

chipflow/platform/io/signatures.py

@@ -84,15 +84,15 @@ class Data(TypedDict, Generic[_T_DataClass]):
 
 class DriverModel(TypedDict):
     """
-    Options for `SoftwareDriverSignature`
+    Options for :class:`SoftwareDriverSignature`.
 
     Attributes:
-        component: The `wiring.Component` that this is the signature for.
-        regs_struct: The name of the C struct that represents the registers of this component
-        h_files: Header files for the driver
-        c_files: C files for the driver
-        regs_bus: The bus of this `Component` which contains its control registers
-        include_dirs: any extra include directories needed by the driver
+        component: The ``wiring.Component`` that this is the signature for.
+        regs_struct: The name of the C struct that represents the registers of this component.
+        h_files: Header files for the driver.
+        c_files: C files for the driver.
+        regs_bus: The bus of this ``Component`` which contains its control registers.
+        include_dirs: Any extra include directories needed by the driver.
     """
     # we just extrat the info we need, don't actually serialise a `wiring.Component`...
     component: Annotated[
@@ -125,13 +125,21 @@ def _unpack_dict(d: dict) -> str:
     params = [ f"{k}={repr(v)}" for k,v in d.items()]
     return ', '.join(params)
 
-"""
-Attributes:
-    __chipflow_parameters__: list of tuples (name, value).
-        It is expected that a model that takes parameters is implmemted as a template, with the parameters in the order
-        given.
-"""
+
 def simulatable_interface(base="com.chipflow.chipflow"):
+    """
+    Decorator for creating simulatable interface signatures.
+
+    The decorated class will have a ``__chipflow_parameters__`` method that returns
+    a list of tuples (name, value). It is expected that a model that takes parameters
+    is implemented as a template, with the parameters in the order given.
+
+    Args:
+        base: Base UID string for the interface (default: "com.chipflow.chipflow").
+
+    Returns:
+        A decorator function that adds chipflow annotation support to a class.
+    """
     def decorate(klass):
         assert _VALID_UID(base)
         dec = amaranth_annotate(SimInterface, SIM_ANNOTATION_SCHEMA)

chipflow/platform/silicon_step.py

@@ -121,7 +121,7 @@ def submit(self, rtlil_path, args):
             --wait: Wait until build has completed. Use '-v' to increase level of verbosity
             --log-file <file>: Log full debug output to file
         """
-        chipflow_api_origin = os.environ.get("CHIPFLOW_API_ORIGIN", "https://build.chipflow.org")
+        chipflow_api_origin = os.environ.get("CHIPFLOW_API_ORIGIN", "https://build.chipflow.com")
 
         if not args.dry_run:
             # Get API key using the new authentication helper

docs/UNFINISHED_IDEAS.md

@@ -8,7 +8,7 @@ These may be implemented in the future or serve as inspiration for documentation
 ### Environment Variables (REAL - should be documented)
 - `CHIPFLOW_ROOT`: Root directory of your project (must contain chipflow.toml)
 - `CHIPFLOW_API_KEY`: API key for ChipFlow cloud services
-- `CHIPFLOW_API_ENDPOINT`: Custom API endpoint (defaults to https://build.chipflow.org)
+- `CHIPFLOW_API_ENDPOINT`: Custom API endpoint (defaults to https://build.chipflow.com)
 - `CHIPFLOW_DEBUG`: Enable debug logging (set to "1")
 
 **Action**: Add environment variable reference to chipflow-commands.rst or chipflow-toml-guide.rst

docs/getting-started.rst

@@ -100,7 +100,7 @@ Method 2: Manual API key (Alternative)
 
 If you prefer to manually manage your API key:
 
-1. Go to https://build.chipflow.org/ and log in with your GitHub account
+1. Go to https://build.chipflow.com/ and log in with your GitHub account
 2. Click on the 'User' menu, then on 'Create/Refresh API Key'
 3. Your new API key will appear at the top
 
@@ -179,7 +179,7 @@ This should return something like:
 
    INFO:chipflow.steps.silicon:Submitting c23dab6-dirty for project chipflow-examples-minimal
    INFO:chipflow.steps.silicon:Submitted design: {'build_id': '3f51a69c-b3e3-4fd3-88fd-52826ac5e5dd'}
-   Design submitted successfully! Build URL: https://build-staging.chipflow.org//build/3f51a69c-b3e3-4fd3-88fd-52826ac5e5dd
+   Design submitted successfully! Build URL: https://build.chipflow.com/build/3f51a69c-b3e3-4fd3-88fd-52826ac5e5dd
 
 Your design will now start building: pictures and logs of the build are
 available at build URL that is returned, once it is complete.

tests/test_silicon_submit.py

@@ -50,7 +50,7 @@ def test_browser_prompt_yes(self, mock_subprocess, mock_isatty, mock_input, mock
             config.chipflow.silicon = True
             config.chipflow.project_name = 'test_project'
             step = SiliconStep(config)
-            step._build_url = "https://build.chipflow.org/build/test123"
+            step._build_url = "https://build.chipflow.com/build/test123"
             step.platform._ports = {}
 
             # Mock the submit method dependencies
@@ -74,7 +74,7 @@ def test_browser_prompt_yes(self, mock_subprocess, mock_isatty, mock_input, mock
                                 step.submit('/tmp/test.il', args)
 
                                 # Verify webbrowser.open was called
-                                mock_webbrowser.assert_called_once_with("https://build.chipflow.org/build/test123")
+                                mock_webbrowser.assert_called_once_with("https://build.chipflow.com/build/test123")
                                 mock_exit.assert_called_once_with(0)
 
     @mock.patch('chipflow.packaging.load_pinlock')
@@ -99,7 +99,7 @@ def test_browser_prompt_no(self, mock_subprocess, mock_isatty, mock_input, mock_
             config.chipflow.silicon = True
             config.chipflow.project_name = 'test_project'
             step = SiliconStep(config)
-            step._build_url = "https://build.chipflow.org/build/test123"
+            step._build_url = "https://build.chipflow.com/build/test123"
             step.platform._ports = {}
 
             # Mock the submit method dependencies
@@ -146,7 +146,7 @@ def test_browser_prompt_not_tty(self, mock_subprocess, mock_isatty, mock_input,
             config.chipflow.silicon = True
             config.chipflow.project_name = 'test_project'
             step = SiliconStep(config)
-            step._build_url = "https://build.chipflow.org/build/test123"
+            step._build_url = "https://build.chipflow.com/build/test123"
             step.platform._ports = {}
 
             # Mock the submit method dependencies